Semiconductor equipment

Abstract

The present invention provides a semiconductor device in which the voltage resistance of the edge portion can be higher than that of the active portion. [Solution] The semiconductor device has an active region 10 and a termination structure 30. It comprises a first semiconductor layer 3 of a first conductivity type and a second semiconductor layer 2 of a first conductivity type, provided on the front surface of a semiconductor substrate 1 of a first conductivity type. The active region 10 is provided with a first parallel pn structure 51 in which a first column region 52 of a first conductivity type and a second column region 53 of a second conductivity type are repeatedly and alternately arranged, and the termination structure 30 is provided with a second parallel pn structure 54 in which a third column region 55 of a first conductivity type and a fourth column region 56 of a second conductivity type are repeatedly and alternately arranged. The column length of the second parallel pn structure 54 is longer than the column length of the first parallel pn structure 51.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, the thickness of the parallel pn layer in the active part is made thinner than the pn layer in the pressure-resistant structure part, and the parallel pn layer and n + Between the drain layer and the n-drift region, n- + By inserting an intermediate drain layer, superjunction semiconductor devices with high L-load avalanche withstand capability (breakdown withstand capability) and high reliability are known (see, for example, Patent Document 1 below). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 4843843 [Overview of the project] [Problems that the invention aims to solve]

[0004] Conventional semiconductor devices have faced the challenge of making the withstand voltage of the edge portion higher than that of the active portion. This disclosure aims to provide a semiconductor device that can achieve a withstand voltage of the edge portion higher than that of the active portion. [Means for solving the problem]

[0005] To solve the above-mentioned problems and achieve the objectives of this disclosure, the semiconductor device according to this disclosure has the following features. The semiconductor device includes an active region and a termination structure disposed outside the active region and surrounding the periphery of the active region. It comprises a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the front surface of a semiconductor substrate of a first conductivity type, and a second semiconductor layer of a first conductivity type having a lower impurity concentration than the first semiconductor layer, provided on the upper surface of the first semiconductor layer. The active region includes a first parallel pn structure in which a first column region of a first conductivity type and a second column region of a second conductivity type provided in the second semiconductor layer are repeatedly and alternately arranged in a direction parallel to the front surface, a first semiconductor region of a second conductivity type provided on the surface layer of the first parallel pn structure of the active region, a second semiconductor region of a first conductivity type selectively provided on the surface layer of the first semiconductor region of the active region, and a gate electrode provided via a gate insulating film in contact with a part of the first semiconductor region and a part of the second semiconductor region. The terminal structure comprises a second parallel pn structure in which a third column region of a first conductivity type and a fourth column region of a second conductivity type, provided within the second semiconductor layer, are repeatedly and alternately arranged in a direction parallel to the front surface. The column length of the second parallel pn structure is longer than the column length of the first parallel pn structure.

[0006] According to the disclosure described above, the column length of the second parallel pn layer in the edge-terminating region is longer than the column length of the first parallel pn layer in the active region. This makes it possible to raise the breakdown voltage of the edge-terminating region to a higher level than that of the active region. Because the avalanche current when an avalanche occurs is shared by the active region, which has a larger area, the breakdown of the silicon carbide semiconductor device can be suppressed. [Effects of the Invention]

[0007] The semiconductor device according to this disclosure has the effect of making the withstand voltage of the edge portion higher than the withstand voltage of the active portion. [Brief explanation of the drawing]

[0008] [Figure 1]This is a cross-sectional view taken along line X-X' in Figure 3, showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 2] This is a cross-sectional view taken along the line Y-Y' in Figure 3, showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 3] This is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 4] Figure 3 shows a cross-sectional view taken along line X-X' (part 1) illustrating another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 5] This is a cross-sectional view (part 2) taken along line X-X' in Figure 3, showing another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 6] This is a cross-sectional view taken along line X-X' in Figure 7, showing the structure of a conventional silicon carbide semiconductor device. [Figure 7] This is a top view showing the structure of a conventional silicon carbide semiconductor device. [Modes for carrying out the invention]

[0009] <Summary of the embodiments of this disclosure> To solve the above-mentioned problems and achieve the objectives of this disclosure, the semiconductor device according to this disclosure has the following features. The semiconductor device includes an active region and a termination structure disposed outside the active region and surrounding the periphery of the active region. It comprises a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the front surface of a semiconductor substrate of a first conductivity type, and a second semiconductor layer of a first conductivity type having a lower impurity concentration than the first semiconductor layer, provided on the upper surface of the first semiconductor layer. The active region includes a first parallel pn structure in which a first column region of a first conductivity type and a second column region of a second conductivity type provided in the second semiconductor layer are repeatedly and alternately arranged in a direction parallel to the front surface, a first semiconductor region of a second conductivity type provided on the surface layer of the first parallel pn structure of the active region, a second semiconductor region of a first conductivity type selectively provided on the surface layer of the first semiconductor region of the active region, and a gate electrode provided via a gate insulating film in contact with a part of the first semiconductor region and a part of the second semiconductor region. The terminal structure comprises a second parallel pn structure in which a third column region of a first conductivity type and a fourth column region of a second conductivity type, provided within the second semiconductor layer, are repeatedly and alternately arranged in a direction parallel to the front surface. The column length of the second parallel pn structure is longer than the column length of the first parallel pn structure.

[0010] According to the disclosure described above, the column length of the second parallel pn layer in the edge-terminating region is longer than the column length of the first parallel pn layer in the active region. This makes it possible to raise the breakdown voltage of the edge-terminating region to a higher level than that of the active region. Because the avalanche current when an avalanche occurs is shared by the active region, which has a larger area, the breakdown of the silicon carbide semiconductor device can be suppressed.

[0011] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the second parallel pn structure is longer on the semiconductor substrate side than the first parallel pn structure.

[0012] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the first column region and the third column region have a lower impurity concentration than the first semiconductor layer.

[0013] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the first column region and the third column region have a higher impurity concentration than the first semiconductor layer.

[0014] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the disclosure described above, the first semiconductor layer is composed of a first semiconductor layer provided on the front surface of the semiconductor substrate and a second semiconductor layer provided on the first semiconductor layer, the first semiconductor layer has a lower impurity concentration than the semiconductor substrate and a higher impurity concentration than the first column region and the third column region, and the second semiconductor layer has a lower impurity concentration than the semiconductor substrate and a lower impurity concentration than the first column region and the third column region.

[0015] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the fourth column region is provided at the boundary between the active region and the termination structure.

[0016] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the third column region and the fourth column region are not exposed on the surface of the second semiconductor layer opposite to the semiconductor substrate.

[0017] <Knowledge forming the basis of this disclosure> Conventionally, semiconductor devices with a superjunction (SJ) structure are known, in which the drift layer is a parallel pn layer in which n-type and p-type regions are alternately and repeatedly arranged adjacent to each other in a direction parallel to the main surface of the substrate. The n-type and p-type regions constituting the parallel pn layer extend in a stripe-like manner parallel to the main surface of the semiconductor substrate (semiconductor chip). The n-type and p-type regions constituting the parallel pn layer are provided almost uniformly over almost the entire semiconductor substrate, from the active region in the center of the semiconductor substrate (center of the chip) to the edge of the semiconductor substrate (edge ​​of the chip).

[0018] Regarding the structure of a conventional silicon carbide semiconductor device with an SJ structure, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, an MOS-type field effect transistor with an insulated gate composed of a three-layer structure of metal-oxide-semiconductor) will be used as an example for explanation. FIG. 6 is a cross-sectional view taken along the line X-X' of FIG. 7 showing the structure of a conventional silicon carbide semiconductor device. FIG. 7 is a top view showing the structure of a conventional silicon carbide semiconductor device.

[0019] The conventional silicon carbide semiconductor device 150 shown in FIGS. 6 and 7 has a general trench gate structure in the active region 110 of a semiconductor substrate (semiconductor chip) 140 made of silicon carbide, and is a vertical MOSFET with an SJ structure in which the n-type drift layer 102 is a parallel pn layer 151. The semiconductor substrate 140 has a rectangular planar shape. The active region 110 has a substantially rectangular planar shape and is provided at the center of the semiconductor substrate 140 (the center of the chip). The periphery of the active region 110 is surrounded by an edge termination region 130.

[0020] The semiconductor substrate 140 is formed by laminating an n-type buffer layer 103 and an n-type epitaxial layer 142 that becomes the n-type drift layer 102 on an n-type starting substrate 141 made of silicon carbide. The main surface on the side of the n-type epitaxial layer 142 of the semiconductor substrate 140 is defined as the front surface, and the main surface on the side of the n-type starting substrate 141 which is the n-type drain region 101 is defined as the back surface. The n-type epitaxial layer 142 is the portion that becomes the n-type drift layer (drift region) 102 and includes the parallel pn layer 151.

[0021] n ++ On the front surface side (the surface on the side of the n-type drift layer 102) of the n-type starting substrate 141, a MOS gate structure composed of a p-type base region 104, an n-type source region 105, a gate trench 107, a gate insulating film 108, and a gate electrode 109 is provided. In the n-type drift layer 102, a p + ​​​​​​​​​​A type region 111 is selectively provided. In the gate trench 107 on the edge terminal region 130 side of the active region 110, p + The mold region 111 extends from the side wall on the edge termination region 130 side of the gate trench 107 to the JTE structure 132, which will be described later. + Type region 112 is p + It is provided on the mold region 111 and is exposed on the surface of the semiconductor substrate 140.

[0022] The edge termination region 130 has a junction termination extension (JTE) structure 132 as a pressure-resistant structure, and n + A channel stopper region 134 and a JTE structure 132 are located around the active region 110.

[0023] n + The channel stopper region 134 is located outside (towards the chip edge) of the JTE structure 132, away from the JTE structure 132, and reaches the edge of the semiconductor substrate 140. + The channel stopper region 134 extends along the edge of the semiconductor substrate 140 and surrounds the JTE structure 132.

[0024] The parallel pn layer 151 is uniformly provided across almost the entire semiconductor substrate 140, from the active region 110 to the edge termination region 130. The parallel pn layer 151 has an SJ structure in which n-type regions 152 and p-type regions 153 are alternately and repeatedly arranged adjacently in a first direction X parallel to the front surface of the semiconductor substrate 140. The n-type region 152 and p-type region 153 of the parallel pn layer 151 extend in a stripe-like manner in a second direction Y parallel to the front surface of the semiconductor substrate 140 and perpendicular to the first direction X.

[0025] The n-type region 152 and p-type region 153 of the parallel pn layer 151 are directly beneath the JTE structure 132 (n ++ It is arranged from the drain region 101 side to almost the entire edge termination region 130. The parallel pn layer 151 is in contact with the JTE structure 132 and is in contact with the JTE structure 132. +The channel stopper region 134 does not reach the front surface of the semiconductor substrate 140.

[0026] The n-type region 152 and p-type region 153 of the parallel pn layer 151 are arranged at equal intervals across approximately the entire semiconductor substrate 140, from the active region 110 to the edge termination region 130. The carrier concentration (impurity concentration) and width (width in the first direction X) of the n-type region 152 and p-type region 153 of the parallel pn layer 151 are set so that a charge balance is achieved between adjacent n-type region 152 and p-type region 153 of the parallel pn layer 151.

[0027] A charge balance means that the charge amount, expressed as the product of the carrier concentration and width in the n-type region 152, and the charge amount, expressed as the product of the carrier concentration and width in the p-type region 153, are approximately the same within a range that includes tolerances due to process variations.

[0028] As shown in Figure 6, in the conventional silicon carbide semiconductor device 150, the active region 110 and the edge termination region 130 use an SJ structure in which the n-type region 152 and p-type region 153 of the parallel pn layer 151 have the same column length. In the SJ structure, the depletion layer extends laterally across the parallel pn layer 151 which is aligned perpendicular to the semiconductor substrate 140, so the depletion layer thickness is equal to the column length of the SJ structure.

[0029] In conventional silicon carbide semiconductor devices 150, when an avalanche occurs, the avalanche current can be shared by causing the avalanche to occur in the large active region 110, thereby suppressing the breakdown of the silicon carbide semiconductor device 150. For this reason, the breakdown voltage of the edge termination region 130 is made higher than that of the active region 110.

[0030] However, in the SJ structure, the pressure resistance is mainly determined by the column length of the SJ structure. Therefore, when the column lengths of the SJ structure are the same in the active region 110 and the edge-terminal region 130, there is a challenge in making the pressure resistance of the edge-terminal region 130 higher than that of the active region 110.

[0031] A preferred embodiment of the silicon carbide semiconductor device according to this disclosure, which solves the problems of the conventional silicon carbide semiconductor devices described above, will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, layers or regions prefixed with n or p mean that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p mean that they have a higher and lower impurity concentration than layers or regions without them, respectively. In the following description of embodiments and attached drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. It is preferable to include up to 5% in the description of the same or equivalent components to account for manufacturing variations.

[0032] (Embodiment) The structure of a silicon carbide semiconductor device according to the embodiment will be explained using a MOSFET as an example. Figure 1 is a cross-sectional view taken along the line X-X' in Figure 3, showing the structure of a silicon carbide semiconductor device according to the embodiment. Figure 2 is a cross-sectional view taken along the line Y-Y' in Figure 3, showing the structure of a silicon carbide semiconductor device according to the embodiment. Figure 3 is a top view showing the structure of a silicon carbide semiconductor device according to the embodiment. In Figure 3, the number of n-type regions (first and second first conductivity type regions) 52, 55 and p-type regions (first and second second conductivity type regions) 53, 56 of the first and second parallel pn layers 51, 54 is simplified, which differs from Figures 1 and 2.

[0033] The silicon carbide semiconductor device 50 according to this embodiment is a vertical MOSFET with an SJ structure trench gate structure (device structure) comprising an active region 10 and an edge termination region (termination structure) 30 on a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC), and an n-type drift layer (second semiconductor layer of the first conductivity type) 2 arranged in parallel pn layers (first and second parallel pn layers 51, 54) extending from the active region 10 to the edge termination region 30. The active region 10 is the region through which the main current flows when the MOSFET is ON, and is located in the center of the semiconductor substrate 40 (center of the chip).

[0034] The edge termination region 30 is the region between the active region 10 and the edge of the semiconductor substrate 40, and surrounds the active region 10. The active region 10 has an SJ structure in which the n-type drift layer 2 is a first parallel pn layer 51. The edge termination region 30 has an SJ structure in which the n-type drift layer 2 is a second parallel pn layer 54.

[0035] The edge termination region 30 has the function of mitigating the electric field on the front side (first main surface) of the semiconductor substrate 40 of the n-type drift layer 2 in the active region 10, thereby maintaining the breakdown voltage. Breakdown voltage is the limit voltage at which leakage current does not increase excessively and the element does not malfunction or break down. The boundary between the active region 10 and the edge termination region 30 is the inner end (inner circumference) of the JTE structure 32 described later and the p described later + This is the boundary with type regions 11 and 12. Near the boundary, in the active region 10, p + Type region 11 and p + The type region 12 consists of two layers, but the edge termination region 30 consists of a single layer of JTE structure 32.

[0036] As shown in Figures 1 and 2, the silicon carbide semiconductor device 50 according to this embodiment has a general trench gate structure on the front side of the semiconductor substrate 40 in the active region 10. The trench gate structure is a p-type base region (first semiconductor region of the second conductivity type) 4, n + It consists of a type source region (second semiconductor region of the first conductivity type) 5, a gate trench 7, a gate insulating film 8, and a gate electrode 9. ++ A type contact region (not shown) may be provided. The semiconductor substrate 40 is made of n ++ An n-type epitaxial layer 42, which will become the n-type drift layer 2, is deposited on the front surface of a type starting substrate (a first-conductivity type semiconductor substrate) 41.

[0037] With the main surface of the semiconductor substrate 40 on the side of the n-type epitaxial layer 42 as the front surface, ++ The main surface on the mold starting substrate 41 side is designated as the back surface (second main surface). ++ The starting substrate 41 is n ++This is the n-type drain region 1. The gate trench 7 penetrates the surface of the semiconductor substrate 40 in the depth direction Z and reaches into the n-type epitaxial layer 42.

[0038] The gate trenches 7 extend in a stripe-like manner in a direction parallel to the front surface of the semiconductor substrate 40 (here, in the second direction Y). A gate electrode 9 is provided inside the gate trenches 7 via a gate insulating film 8. The p-type base region 4 extends in a stripe-like manner in the second direction Y between adjacent gate trenches 7. + The type source regions 5 are selectively provided on the surface of the p-type base region 4 between adjacent gate trenches 7. ++ The type contact regions may be selectively provided on the surface of the p-type base regions 4 between adjacent gate trenches 7.

[0039] In the active region 10, between the p-type base region 4 and the first parallel pn layer 51 (n-type drift layer 2), + Type region 11 is selectively provided. + The type region 11 has the function of mitigating the electric field applied to the bottom surface of the gate trench 7. + The type region 11 is positioned separately from the p-type base region 4 and faces the bottom surface of the gate trench 7 in the depth direction Z. + The p-type region 11 and the p-type base region 4 are periodically connected in a second direction Y (not shown). In the gate trench 7 on the edge terminal region 30 side of the active region 10, p + The mold region 11 extends from the side wall on the edge end region 30 side of the gate trench 7 to the JTE structure 32. + Type region 12 is p + It is provided on the mold region 11 and is exposed on the surface of the semiconductor substrate 40.

[0040] The edge termination region 30 has a pressure-resistant structure, a joint termination extension (JTE) structure 32, and n + A channel stopper region 34 is located there. The JTE structure 32 surrounds the active region 10.

[0041] The JTE structure 32 is a structure in which multiple p-type regions are arranged concentrically adjacent to the active region 10, with the impurity concentration decreasing as they move away from the active region 10. The JTE structure 32 mitigates electric field concentration on the active region side, preventing device failure due to the application of a voltage below a predetermined voltage (the breakdown voltage of the edge termination region 30).

[0042] n + The channel stopper region 34 is located outside the JTE structure 32 and at a distance from the JTE structure 32, and reaches the edge of the semiconductor substrate 40, for example, along the four sides (straight sections) of the edge of the semiconductor substrate 40. + The channel stopper region 34 extends along the edge of the semiconductor substrate 40 and surrounds the JTE structure 32.

[0043] The first parallel pn layer (first parallel pn structure) 51 is an SJ structure in which n-type regions (first column regions of the first conductivity type) 52 and p-type regions (second column regions of the second conductivity type) 53 are alternately and repeatedly arranged adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 40. The n-type regions 52 and p-type regions 53 of the first parallel pn layer 51 extend in a stripe-like manner in a second direction Y parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X, up to near the edge of the edge termination region 30. Furthermore, the first parallel pn layer 51 is located in the active region 10 in the first direction X. Therefore, the boundary between the first parallel pn layer 51 and the second parallel pn layer 54 is located at the edge of the active region 10.

[0044] The adjacent n-type region 52 and p-type region 53 of the first parallel pn layer 51 are approximately charge-balanced. Charge balance means that the charge amount, expressed as the product of the carrier concentration (impurity concentration) and width of the n-type region of the parallel pn layer, and the charge amount, expressed as the product of the carrier concentration and width of the p-type region, are approximately the same within a range that includes tolerances due to process variations. Therefore, the carrier concentration and width (width in the first direction X) of the n-type region 52 and p-type region 53 are set so that the adjacent n-type region 52 and p-type region 53 of the first parallel pn layer 51 are approximately charge-balanced.

[0045] It is sufficient that the adjacent n-type region 52 and p-type region 53 of the first parallel pn layer 51 are roughly charge-balanced, and the carrier concentrations and widths of the n-type region 52 and p-type region 53 of the first parallel pn layer 51 are set as appropriate. For example, the widths of the n-type region 52 and p-type region 53 of the first parallel pn layer 51 may be approximately the same. In this case, the carrier concentrations of the n-type region 52 and p-type region 53 should be set to be approximately the same. "Approximately the same width and carrier concentration" means that they are the same width and the same carrier concentration, respectively, within a range that includes tolerances due to process variations.

[0046] The second parallel pn layer (second parallel pn structure) 54 is an SJ structure in which n-type regions (third column regions of the first conductivity type) 55 and p-type regions (fourth column regions of the second conductivity type) 56 are alternately and repeatedly arranged adjacently in a first direction X parallel to the front surface of the semiconductor substrate 40. The n-type regions 55 and p-type regions 56 of the second parallel pn layer 54 extend in a stripe shape in a second direction Y parallel to the n-type regions 52 and p-type regions 53 of the first parallel pn layer 51. The second parallel pn layer 54 is located in the edge termination region 30, connected to both sides of the first parallel pn layer 51 of the active region 10 in the second direction Y. The second parallel pn layer 54 is located in the edge termination region 30, adjacent to both sides of the first parallel pn layer 51 in the first direction X. The second parallel pn layer 54 is positioned such that an n-type region 55 is adjacent to the outermost p-type region 53 of the first parallel pn layer 51 in the first direction X, also in the first direction X. Furthermore, the second parallel pn layer 54 extends beyond the outer edge (periphery) of the JTE structure 32 in the first direction X, such that at least one p-type region 56 is positioned beyond the outer edge (periphery) of the JTE structure 32 in the first direction X.

[0047] By positioning the p-type region 56 of the second parallel pn layer 54 beyond the outer edge of the JTE structure 32 in the first direction X, electric field concentration at the outer edge of the JTE structure 32 can be suppressed when the MOSFET is off. The outer edge of the JTE structure 32 refers to the outer edge of the outermost p-type region among the multiple p-type regions that constitute the JTE structure 32.

[0048] The range in which the second parallel pn layer 54 is placed is defined as the range from the outer edge of the JTE structure 32 in the first direction X, thereby reducing the number of floating p-type regions 56 placed in the edge termination region 30. This reduces the amount of accumulated charge of minority carriers (holes) that accumulate in the edge termination region 30 due to MOSFET switching, etc., and remain without being discharged to the outside. For this reason, it is preferable to have a small number of p-type regions 56 placed outside the outer edge of the JTE structure 32 in the first direction X.

[0049] The second parallel pn layer 54 is within the above range from the outer end of the JTE structure 32 in the first direction X, and in the first direction X, n + Directly below the type channel stopper region 34 (n ++ It may be arranged up to the drain region 1 side. A normal n-type drift region 2 may be arranged between the second parallel pn layer 54 and the edge of the semiconductor substrate 40 in the first direction X. The less this normal n-type drift region 2 is provided, or the narrower the width of this normal n-type drift region 2 is made, the smaller the semiconductor substrate 40 can be made.

[0050] The n-type region 55 and p-type region 56 of the second parallel pn layer 54 are in contact with the JTE structure 32 in the depth direction Z. The p-type region 56 of the second parallel pn layer 54, which is located outside the JTE structure 32, is located at a depth D1 from the surface of the semiconductor substrate 40 and is not exposed to the surface of the semiconductor substrate 40. The depth D1 is, for example, the same as the thickness of the JTE structure 32. Between the second parallel pn layer 54 located outside the JTE structure 32 and the surface of the semiconductor substrate 40, there is an n-type drift region 2 with a lower impurity concentration than the normal n-type drift region 2. - A layer 35 is present. This makes it easier for the depletion layer to spread outwards.

[0051] The adjacent n-type region 55 and p-type region 56 of the second parallel pn layer 54 are roughly charge-balanced. The carrier concentrations and widths (width in the first direction X) of the n-type region 55 and p-type region 56 are set so that the adjacent n-type region 55 and p-type region 56 of the second parallel pn layer 54 are roughly charge-balanced. The carrier concentrations and widths of the adjacent n-type region 55 and p-type region 56 of the second parallel pn layer 54 are set as appropriate, provided that the adjacent n-type region 55 and p-type region 56 of the second parallel pn layer 54 are roughly charge-balanced. For example, the widths of the n-type region 55 and p-type region 56 of the second parallel pn layer 54 may be approximately the same. In this case, the carrier concentrations of the n-type region 55 and p-type region 56 should be set to be approximately the same.

[0052] In this embodiment, the SJ structure of the second parallel pn layer 54 of the edge-terminating region 30 (length of the n-type region 55 and the p-type region 56) is longer than the column length of the first parallel pn layer 51 of the active region 10 (length of the n-type region 52 and the p-type region 53). The n-type region 55 and the p-type region 56 are n ++ From the front surface of the type drain region 1, n - n of mold layer 35 or JTE structure 34 ++ The n-type drain region 52 and p-type region 53 are provided on the side of the drain region 1, and the n-type region 52 and p-type region 53 are n + From the front surface of type buffer layer 3, p + n of type region 11 ++ It is provided up to the side of the drain region 1. As shown in Figures 1 and 2, the column length L2 of the second parallel pn layer 54 is longer than the column length L1 of the first parallel pn layer 51 (L2 > L1). Furthermore, this difference in length (L2 - L1) is preferably 10% to 25% of the column length L1, and more preferably 15% to 20%. This is because if it is shorter than 10%, the effect of the embodiment will be reduced, and if it is longer than 25%, the on-resistance will increase and the manufacturing cost will be higher.

[0053] Since the breakdown voltage of the SJ structure is determined by the column length of the SJ structure, by making the column length of the edge-terminating region 30 longer than the column length of the active region 10, the breakdown voltage of the edge-terminating region 30 can be made higher than that of the active region 10. In this way, the avalanche current when avalanche occurs is shared by the active region 10, which has a larger area, thus suppressing the breakdown of the silicon carbide semiconductor device.

[0054] Furthermore, the second parallel pn layer 54 is n ++ It is preferable that the drain region 1 side is longer than the first parallel pn layer 51. ++ n between the type drain region 1 and the drain region 1 + A type buffer layer (first semiconductor layer of the first conductivity type) 3 is provided. + The buffer layer 3 provides a depletion layer extending beneath the SJ structure to the semiconductor substrate (n ++ It can be kept to the drain region 1). Also, n + An n-type region 55 with the same depth as the type buffer layer 3, n + The same impurity concentration as buffer layer 3 may be used. In this case, to balance the charge, n + The impurity concentration in the p-type region 56, which is the same depth as the type buffer layer 3, is increased.

[0055] As shown in Figures 1 and 2, the p-type region 56 on the most active region 10 side of the edge termination region 30 is partially located on the active region 10 side. Therefore, the p-type region 56 is p + It is in contact with both the p-type region 12 and the JTE structure 32. For example, the approximate center of the p-type region 56 may be midway between the active region 10 and the edge-terminal region 30.

[0056] Furthermore, as shown in Figures 1 and 2, at the outer ends of the JTE structure 32 in the first direction X and the second direction Y, the JTE structure 32 is in contact with the p-type region 56, but it may also be a structure that is in contact with the n-type region 55.

[0057] Figures 4 and 5 are cross-sectional views taken along line X-X' in Figure 3, showing other structures of the silicon carbide semiconductor device according to the embodiment. As shown in Figure 4, the first parallel pn layer 51 and n ++ n between the type drain region 1 and the drain region 1 - A buffer layer 3a may also be provided. Furthermore, n - An n-type region 55 with the same depth as the type buffer layer 3a, n - The same impurity concentration as buffer layer 3a may be used. In this case, to balance the charge, n - The impurity concentration in the p-type region 56, which is the same depth as the type buffer layer 3a, is reduced.

[0058] As shown in Figure 5, n ++ n on the drain region 1 + A buffer layer (first semiconductor layer) 3 is provided, and on top of it, n - A buffer layer (second first semiconductor layer) 3a may be provided. Here, n - Type buffer layer 3a, n-type region 52, n + Type buffer layer 3, n ++ In the drain region 1, the impurity concentration increases in this order. Also, in the edge termination region 30, n + An n-type region 55 with the same depth as the type buffer layer 3, n + The same impurity concentration as buffer layer 3 may be used. In this case, to balance the charge, n + The impurity concentration in the p-type region 56, which is the same depth as the type buffer layer 3, is increased. Similarly, n - An n-type region 55 with the same depth as the type buffer layer 3a, n - The same impurity concentration as buffer layer 3a may be used. In this case, to balance the charge, n - The impurity concentration in the p-type region 56, which is the same depth as the type buffer layer 3a, is reduced.

[0059] Next, a method for manufacturing the silicon carbide semiconductor device 50 according to the embodiment will be described. First, n ++ n becomes type drain region 1 ++ On the front surface of the starting substrate (semiconductor wafer) 41, n including the first and second parallel pn layers 51 and 54 +A type buffer layer 3 and an n-type drift layer 2 are formed. For example, when using a multi-stage epitaxial method, n + Each time the n-type epitaxial layer 42, which will become the n-type buffer layer 3 and the n-type drift layer 2, is epitaxially grown in multiple stages (for example, 9 stages), ion implantation is used to selectively form n-type regions 52, 55 and p-type regions 53, 56 in the n-type epitaxial layer 42 so that regions of the same conductivity type are adjacent to each other in the depth direction Z. For example, the n-type in the first and second stages + After growing the n-type epitaxial layer 42 which becomes the type buffer layer 3, by not performing p-type ion implantation in the active region 10, the column length of the second parallel pn layer 54 in the edge-terminal region 30 is made longer than the column length of the first parallel pn layer 51 in the active region 10, and the first parallel pn layer 51 and n ++ n between the type drain region 1 and the drain region 1 + A buffer layer 3 is formed.

[0060] Furthermore, the first and second parallel pn layers 51 and 54 are, for example, n + After forming an n-type epitaxial layer 42 which will become an n-type buffer layer 3 and an n-type drift layer 2, trenches (hereinafter referred to as SJ trenches) may be formed in the n-type epitaxial layer 42 to leave portions which will become n-type regions 52 and 55, and the SJ trenches may be filled with p-type epitaxial layers which will become p-type regions 53 and 56, using a trench-embedded epitaxial method. For example, by making the SJ trench length of the active region 10 shorter than the SJ trench length of the edge-terminal region 30, the column length of the second parallel pn layer 54 of the edge-terminal region 30 is made longer than the column length of the first parallel pn layer 51 of the active region 10, and the first parallel pn layer 51 and n ++ n between the type drain region 1 and the drain region 1 + A buffer layer 3 is formed.

[0061] Another structure of the silicon carbide semiconductor device according to the embodiment in Figure 4 is an n-type epitaxial layer 42 - The structure can be formed similarly to that in Figures 1 and 2 by forming it as two layers: an n-type buffer layer 3a and an n-type drift layer 2. Furthermore, another structure of the silicon carbide semiconductor device according to the embodiment in Figure 5 is formed by using an n-type epitaxial layer 42. +Type buffer layer 3 and n - By forming it as a three-layer structure of the type buffer layer 3a and the n-type drift layer 2, it can be formed in the same manner as the structures of FIGS. 1 and 2.

[0062] Also, p + type regions 11, 12, n + type source region 5, p ++ type contact region, JTE structure 32, n + type channel stopper region 34 and n - type layer 35 can be formed by ion implantation. After that, a gate trench 7 is formed, and a gate insulating film 8 is formed along the front surface of the semiconductor substrate 40 and the inner wall of the gate trench 7. Next, the polysilicon layer deposited on the front surface of the semiconductor substrate 40 is etched back so as to be embedded inside the gate trench 7, and the portion that becomes the gate electrode 9 is left inside the gate trench 7. Thereby, the silicon carbide semiconductor device 50 shown in FIGS. 1 and 2 can be formed.

[0063] As described above, according to the embodiment, the column length of the second parallel pn layer in the edge termination region is longer than the column length of the first parallel pn layer in the active region. Thereby, the breakdown voltage of the edge termination region can be made higher than the breakdown voltage of the active region. Since the avalanche current when avalanche occurs is shared in the active region with a large area, the breakdown of the silicon carbide semiconductor device can be suppressed.

[0064] In the above description of the present disclosure, the case where a MOS gate structure is formed on the first main surface of a silicon carbide substrate has been described as an example. However, the present disclosure is not limited to this, and various changes such as the surface orientation of the substrate main surface are possible. Further, in the embodiments of the present disclosure, a trench-type MOSFET has been described as an example. However, the present disclosure is not limited to this, and it can be applied to semiconductor devices having various configurations such as MOS-type semiconductor devices such as trench-type IGBTs. Further, in each of the above-described embodiments, the case where silicon carbide is used as the semiconductor has been described as an example. However, the present disclosure is also applicable to semiconductors other than silicon carbide, such as silicon (Si) and gallium nitride (GaN). Further, in the present disclosure, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present disclosure also holds true when the first conductivity type is p-type and the second conductivity type is n-type.

Industrial Applicability

[0065] As described above, the silicon carbide semiconductor device according to the present disclosure is useful for high-voltage-resistant semiconductor devices used in power conversion devices, power supply devices such as various industrial machines, and the like.

Explanation of Reference Numerals

[0066] 1, 101 n ++ -type drain region 2, 102 n-type drift layer 3 n + -type buffer layer 3a n - -type buffer layer 4, 104 p-type base region 5, 105 n + -type source region 7, 107 gate trench 8, 108 gate insulating film<00oo348>9, 109 gate electrode 10, 110 active region 11, 12, 111, 112 p + -type region 30, 130 edge termination region 32, 132 JTE structure 34, 134 n + -type channel stopper region 35 n- mold layer 40, 140 semiconductor substrates 41, 141 n ++ Mold starting substrate 42, 142 n-type epitaxial layers 50, 150 Silicon Carbide Semiconductor Devices 51 1st parallel pn layer 52 n-type region of the first parallel pn layer 53 p-type region of the first parallel pn layer 54 2nd parallel pn layer 55 n-type region of the second parallel pn layer 56 p-type region of the second parallel pn layer 103 n - Type buffer layer 151 parallel pn layer 152 n-type region of parallel pn layer 153 p-type region of parallel pn layer X Direction parallel to the front surface of the semiconductor substrate (first direction) Y: A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction). Z-direction (depth)

Claims

1. A semiconductor device having an active region and a terminal structure disposed outside the active region and surrounding the periphery of the active region, A first semiconductor layer of the first conductivity type, having a lower impurity concentration than the semiconductor substrate, is provided on the front surface of the first conductivity type semiconductor substrate. A second semiconductor layer of a first conductivity type having a lower impurity concentration than the first semiconductor layer is provided on the upper surface of the first semiconductor layer, Equipped with, In the aforementioned active region, A first parallel pn structure is provided in which a first column region of a first conductivity type and a second column region of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface within the second semiconductor layer, A first semiconductor region of a second conductivity type is provided on the surface layer of the first parallel pn structure of the active region, A second semiconductor region of a first conductivity type is selectively provided on the surface layer of the first semiconductor region of the active region, A gate electrode is provided via a gate insulating film that is in contact with a part of the first semiconductor region and a part of the second semiconductor region, Equipped with, In the aforementioned terminal structure, The second semiconductor layer comprises a second parallel pn structure in which a third column region of a first conductivity type and a fourth column region of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface. A semiconductor device characterized in that the column length of the second parallel pn structure is longer than the column length of the first parallel pn structure.

2. The semiconductor device according to claim 1, characterized in that the second parallel pn structure is longer on the semiconductor substrate side than the first parallel pn structure.

3. The semiconductor device according to claim 1, characterized in that the first column region and the third column region have a lower impurity concentration than the first semiconductor layer.

4. The semiconductor device according to claim 1, characterized in that the first column region and the third column region have a higher impurity concentration than the first semiconductor layer.

5. The first semiconductor layer is composed of a first semiconductor layer provided on the front surface of the semiconductor substrate and a second semiconductor layer provided on the first semiconductor layer. The first semiconductor layer has a lower impurity concentration than the semiconductor substrate and a higher impurity concentration than the first column region and the third column region. The semiconductor device according to claim 1, characterized in that the second first semiconductor layer has a lower impurity concentration than the semiconductor substrate and a lower impurity concentration than the first column region and the third column region.

6. The semiconductor device according to claim 1, characterized in that the fourth column region is provided at the boundary between the active region and the terminal structure.

7. The semiconductor device according to claim 1, characterized in that the third column region and the fourth column region are not exposed on the surface of the second semiconductor layer opposite to the semiconductor substrate.

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