Semiconductor package having edge interconnects, semiconductor package assembly, and method for forming the same.

Abstract

We provide silicon IP, ICs / chiplets, and IC packages that address power and thermal challenges. [Solution] In a semiconductor package assembly 1900, the IC stack 1901 includes a transversely extending thermal conductive layer 1914 that covers each second side wall 1920S2 of a plurality of IC structures 1920 and is thermally bonded to each of the upwardly extending thermal conductive layers 1912, the transversely extending RDL structure 118 is on the opposite side of the transversely extending thermal conductive layer 1914, and the thermal conductivity of the transversely extending thermal conductive layer 1914 is higher than the thermal conductivity of Si or SiO2 such as SiC chips.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of forming the same, and more particularly, to semiconductor devices having side-edge interconnects and methods of forming the same.

Background Art

[0002] Due to significant features of engineering and materials science including very complex multi-step lithographic patterning, new strain-enhanced materials, and metal-oxide gates, the two-dimensional (2D) geometric scaling of conventional transistors has been advancing very much. However, the scaling of 2D devices is losing momentum as the above-mentioned technologies approach their practical limits. Three-dimensional integrated circuits (3D ICs) are a fundamental development of conventional 2D IC integration and are recognized as next-generation semiconductor technologies that simultaneously achieve high performance, low power consumption, small size, and high integration. 3D ICs provide a way to continuously meet the performance and cost requirements of next-generation devices while reducing the process complexity and relaxing the gate length for high-end applications such as high-performance computing (HPC), data centers, and artificial intelligence (AI).

[0003] 3D IC integration can be advanced by · monolithic integration, and / or · vertical integration of heterogeneous dies and can be advanced thereby.

[0004] 3D monolithic integration typically involves the vertical integration of multiple active silicon layers with vertical interconnections between layers. Recently, "cache-on-a-central processing unit (CPU)" 3D IC structures have been demonstrated and commercialized using copper hybrid junctions. Today, high-bandwidth memory (HBM) dynamic random-access memory (DRAM) stacks, each created by vertically integrating several DRAM dies on a control IC, represent the highest capacity commercially available 3D ICs today. These HBM DRAM stacks are typically implemented alongside processor ICs on a silicon interposer in 2.5D IC packaging (Figure 1A) for high-end applications such as HPC, data centers, and AI. 2.5D ICs typically include through-silicon vias (TSVs) both within the active dies, such as the DRAM and control ICs, and within the silicon interposer, which can be passive or active. 2.5D ICs may also include redistribution layers (RDLs) within the interposer and active dies. For example, considering ChatGPT, a 2.5D IC configuration is powered by an nVidia H100 GPU. In the future, 3D ICs can enable memory on memory, logic on memory, and logic on logic using interconnect technologies including TSVs, RDLs including interconnect wiring and microvias, flip-chip bonding based on copper pillar microbumps or solder bumps, and newly emerging copper hybrid bonding technologies. 3D ICs created by monolithic and / or heterointegration enable vertical stacking of heterodies and / or active silicon layers from different manufacturing processes and nodes, chip / chiplet reuse, and in-package chiplets. Ultimately, 3D IC integration enables stacking of HBM DRAM stacks on processors, significantly reducing data transfer times between DRAM dies and processors and drastically reducing the peak compute memory bandwidth gap.3D ICs are ideal for applications that require the integration of more transistors within a given footprint (such as mobile systems-on-chip, SoCs), or for applications that already push the limits of single-die capabilities in modern nodes such as HPC, data centers, AI / machine learning, 5G / 6G networks, graphics, smartphones / wearables, and automobiles, requiring ultra-high-performance, high-power-efficiency devices. These devices include CPUs, GPUs (graphics processing units), FPGAs (field-programmable gate arrays), ASICs (application-specific integrated circuits), TPUs (tensor processing units), integrated photonics, APs (application processors for mobile phones), packet buffer / router devices, and more.

[0005] To accelerate the adoption of 3D IC systems, it is necessary to design them comprehensively through collaborative design of IC package systems, including silicon IP, ICs / chiplets, and IC packages, and to address the associated power and thermal challenges. In contrast to PPAC (Performance, Power, Area, and Cost) optimization per square centimeter, which is applied in 2D packaging, collaborative design of IC package systems for 3D ICs aims to achieve "PPAC optimization per cubic millimeter," and the vertical dimensions covering the IC, interposer, IC package substrate, IC package, and system printed circuit board (PCB) must all be considered in all trade-off decisions.

[0006] Today, all 3D ICs employ packaging topologies with single-sided electrical interconnects, for example, from the bottom of a control IC in an HBM DRAM stack connected to an interposer to the DRAM die above the control IC, or from the multilayer substrate to the bottom of the CPU in a cache-on-CPU. When powering a 3D IC that relies on single-sided interconnects, designers must consider all stack layers when designing a power supply network where the bottom die and processor die receive power from a 2.5D interposer, the interposer receives power from the multilayer substrate, and then the multilayer substrate receives power from the PCB, and so on, with the top die receiving power from the die below it, the die below that receiving power from the die immediately below it, and so on. Single-sided interconnects are not scalable because the 3D IC footprint is invariant with respect to the number of dies mounted vertically. For example, considering an HBM DRAM stack, the number of dies in the stack increases from 5 in HBM1 to 13 in HBM3. Single-sided electrical interconnects impose strict constraints on PPAC optimization of 3D ICs. [Overview of the project]

[0007] One aspect of the present disclosure provides an IC stack comprising a plurality of integrated circuit (IC) structures separated horizontally from each other, each IC structure having a top surface, a bottom surface opposite the top surface, and four side walls having a first side wall, a second side wall, a third side wall, and a fourth side wall, wherein the area of ​​the bottom surface or top surface is greater than the area of ​​any side wall; a laterally extending RDL structure covering each first side wall of the plurality of IC structures; and an upwardly extending thermal conductive layer between two adjacent IC structures. The thermal conductivity of the upwardly extending thermal conductive layer is higher than that of Si.

[0008] Another aspect of the present disclosure provides an IC stack comprising a plurality of integrated circuit (IC) structures separated horizontally from each other, each IC structure having a top surface, a bottom surface opposite the top surface, and four side walls having a first side wall, a second side wall, a third side wall, and a fourth side wall, wherein the area of ​​the bottom or top surface is greater than the area of ​​any side wall; a set of upward-extending thermal conductive layers, the corresponding upward-extending thermal conductive layers being positioned between any two adjacent IC structures of the plurality of IC structures; and a first laterally-extending thermal conductive layer covering each second side wall of the plurality of IC structures and thermally coupled to the set of upward-extending thermal conductive layers. The thermal conductivity of any upward-extending thermal conductive layer and / or laterally-extending thermal conductive layer is greater than the thermal conductivity of Si.

[0009] A further aspect of the present disclosure provides an IC stack comprising a plurality of semiconductor structures separated horizontally from each other, each semiconductor structure having a top surface, a bottom surface opposite the top surface, and four side walls having a first side wall, a second side wall, a third side wall, and a fourth side wall, wherein the area of ​​the bottom or top surface is greater than the area of ​​any side wall; and a lateral-extending RDL structure covering the first side wall of each semiconductor structure. The first semiconductor structure of the plurality comprises a first integrated circuit (IC) structure and a first adjacent structure physically separated from the first IC structure, wherein the first IC structure and the first adjacent structure are arranged along the first side wall of the first semiconductor structure. The lateral-extending RDL structure comprises a first plurality of junction pads arranged along the first side wall of the first semiconductor structure, wherein the first plurality of junction pads are on the edge of the first integrated circuit (IC) structure and on the edge of the first adjacent structure.

[0010] In this disclosure, four untapped sidewalls of a 3D IC stack are used to interconnect dies within the 3D IC stack, enabling skip-die and multi-side signaling, power distribution, and heat dissipation. As a result, power and signal paths and heat dissipation paths can be supplied from the bottom die on the front (or from the interposer supporting the bottom die) to all other dies in the die stack, not just the die directly above it. Thus, routing area, heat dissipation performance, and design flexibility can be increased or improved without substantially increasing the footprint of the 3D IC, and performance can be improved through a more efficient interconnection strategy. [Brief explanation of the drawing]

[0011] The aspects of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in this industry, various structures are not drawn to scale. In fact, the dimensions of various structures may be arbitrarily enlarged or reduced for illustrative purposes.

[0012] [Figure 1A] This disclosure shows various in-package systems (SIPs) according to comparative embodiments. [Figure 1B] This disclosure shows various in-package systems (SIPs) according to comparative embodiments. [Figure 1C] This disclosure shows various in-package systems (SIPs) according to comparative embodiments. [Figure 1D] This disclosure shows various in-package systems (SIPs) according to comparative embodiments. [Figure 1E] This disclosure shows various in-package systems (SIPs) according to comparative embodiments. [Figure 1F] This disclosure shows various in-package systems (SIPs) according to comparative embodiments. [Figure 2A] The following are cross-sectional views of structures at different stages of a method for manufacturing an integrated circuit (IC) structure according to some embodiments of this disclosure. [Figure 2B]Cross-sectional views of structures at different stages of a method of manufacturing an integrated circuit (IC) structure according to some embodiments of the present disclosure are shown. [Figure 2C] Cross-sectional views of structures at different stages of a method of manufacturing an integrated circuit (IC) structure according to some embodiments of the present disclosure are shown. [Figure 2D] Perspective views of redistribution layers according to various embodiments of the present disclosure are shown. [Figure 2E] Cross-sectional views of structures at different stages of a method of manufacturing an integrated circuit (IC) structure according to some embodiments of the present disclosure are shown. [Figure 2F] Cross-sectional views of structures at different stages of a method of manufacturing an integrated circuit (IC) structure according to some embodiments of the present disclosure are shown. [Figure 2G] Cross-sectional views of redistribution layers of the IC structures shown in FIGS. 2B, 2C, 2E, and 2F according to various embodiments of the present disclosure are shown. [Figure 3A] Cross-sectional views of structures at different stages of a method of manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 3B] Cross-sectional views of structures at different stages of a method of manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 3C] Cross-sectional views of structures at different stages of a method of manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 3D] Cross-sectional views of structures at different stages of a method of manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 3E] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 3F] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 4A] Cross-sectional views of structures at different stages of a method of manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 4B] [ Cross-sectional views of structures at different stages of a method of manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 4C]Cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 4D] Cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 4E] Cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 4F] Cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 4G] Cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of the present disclosure are shown. [Figure 4H] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 4I] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 4J] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 4K] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 4L] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 4M] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 4N] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 5A] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 5B] Cross-sectional views of an IC structure according to various embodiments of the present disclosure are shown. [Figure 5C] Cross-sectional views of the interconnection structure of the IC structure shown in FIGS. 5A and 5B according to various embodiments of the present disclosure are shown. [Figure 6A] Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure are shown. [Figure 6B]This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 6C] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 6D] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 6E] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7A] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7B] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7C] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7D] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7E] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7F] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7G] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7H] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7I] Cross-sectional views of semiconductor packages according to various embodiments of this disclosure are shown. [Figure 7J] Cross-sectional views of semiconductor packages according to various embodiments of this disclosure are shown. [Figure 8A] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 8B] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 8C] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 8D] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 8E] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 9A] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 9B] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 10A] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 10B] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 10C] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 10D] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 10E] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 10F] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 10G] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 10H] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 11A] Cross-sectional views of semiconductor packages according to various embodiments of this disclosure are shown. [Figure 11B] Cross-sectional views of semiconductor packages according to various embodiments of this disclosure are shown. [Figure 12A] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 12B] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 12C] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 13A] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 13B] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 13C] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 13D] Figure 13C shows a perspective view of a semiconductor package according to various embodiments of this disclosure. [Figure 14A] Cross-sectional views of semiconductor package assemblies according to various embodiments of this disclosure are shown. [Figure 14B] Cross-sectional views of semiconductor package assemblies according to various embodiments of this disclosure are shown. [Figure 15A] A cross-sectional view of a semiconductor package assembly according to the comparative example of this disclosure is shown. [Figure 15B]Cross-sectional views of semiconductor package assemblies according to various embodiments of this disclosure are shown. [Figure 16A] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 16B] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 16C] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 16D] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 16E] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 17] Cross-sectional views of semiconductor package assemblies according to various embodiments of this disclosure are shown. [Figure 18A] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 18B] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 18C] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 18D] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 18E] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 18F] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 18G]This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 18H] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 19A] Cross-sectional views of semiconductor package assemblies according to various embodiments of this disclosure are shown. [Figure 19B] Cross-sectional views of semiconductor package assemblies according to various embodiments of this disclosure are shown. [Figure 20A] Block diagrams of circuits within semiconductor package assemblies according to various embodiments of this disclosure are shown. [Figure 20B] Block diagrams of circuits within semiconductor package assemblies according to various embodiments of this disclosure are shown.

[0013] The following detailed description includes numerous specific details for illustrative purposes to provide a complete understanding of the disclosed embodiments. However, it is clear that one or more embodiments may be carried out without these specific details. In other examples, well-known structures and devices are shown schematically for the sake of simplifying the drawings. Furthermore, similar reference numerals across different figures indicate similar features, and therefore, a detailed description of similar features may be provided when such features are first introduced in this disclosure and not thereafter. [Modes for carrying out the invention]

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. For the sake of brevity, specific examples of components and configurations are described below. Naturally, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, or it may include embodiments in which an additional feature can be formed between the first and second features so that they do not come into direct contact. Furthermore, in various examples in this disclosure, reference numbers and / or letters may be repeated. This repetition is for the purpose of simplification and clarity and does not in itself indicate relationships between the various embodiments and / or configurations discussed.

[0015] Furthermore, spatially relative terms such as “downward,” “below,” “bottom,” “upward,” “top,” and “above” may also be used herein to describe the relationship between one element or feature and another, as shown in the drawings for the sake of clarity. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. The device may be oriented in a different orientation (it may be rotated 90° or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] When used herein, terms such as “first,” “second,” and “third” describe various elements, components, areas, layers, and / or sections, but these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, area, layer, or section from another. When used herein, terms such as “first,” “second,” and “third” do not imply a sequence or order unless explicitly indicated by the context.

[0017] Embodiments of the present invention disclose methodologies, processes, and concepts (details of which are described below) for creating redistribution layers (RDLs) and interconnections (e.g., through-silicon vias, through-molding vias, metal vias, metal pads for copper hybrid junctions, and microbumps or solder bumps for flip-chip assemblies) on four sides of a 3D IC and a short 3D IC structure stack, wherein each stack layer consists of one or more ICs in the xy direction (in-plane direction) and the z direction (out-of-plane direction or IC thickness direction).

[0018] Embodiments of the package structure proposed in this disclosure have at least the following features: (a) 5-sided power and signal distribution (penetrating the front and four sides of the 3D IC package); (b) skip die and multi-sided interconnects through the four sides and / or internal interconnects using a combination of RDL, TSV, and through-molded vias (TMV) (e.g., directly reaching the upper die and other ICs in the stack from the substrate such as the bottom die or interposer); (c) RDL on the sides interconnected in three dimensions by the use of flexible printed circuit (Flex); and (d) the ability to use a variety of interconnection techniques covering RDL, TSV, microbumps, solder bumps, copper hybrid junctions, and fine-pitch Flex. Thus, the proposed package structure can effectively shorten the length of global and IC packaging interconnection paths and increase the number of transistors accessed within one clock cycle.

[0019] Figures 1A to 1F show various in-package systems (SIPs) according to comparative embodiments of the present disclosure.

[0020] For high-end applications such as HPC, data centers, AI, and smart handhelds, the cost of IC (integrated circuit) scaling increases exponentially with respect to system-on-chip (SoC) designs. This increase in complexity and cost is exacerbated by the industry's increasing reliance on complex and advanced SiPs (system-in-packages) to package advanced ICs. The advanced SiPs described herein include 2.5D ICs shown in Figure 1A, fan-out SiPs shown in Figure 1B, embedded SiPs shown in Figure 1C, silicon photonics shown in Figure 1D, 3D ICs assembled using chip-to-wafer (C2W) bonding shown in Figure 1E, and 3D ICs assembled using wafer-to-wafer (W2W) bonding shown in Figure 1F. Advanced SiPs may also include chiplet-in-SiPs to enable high-end SoC partitioning to improve yield, cost, time to market, and performance, using chiplets and one or more of the advanced SiP technologies and their enabling building block technologies shown in Figures 1A-1F. All advanced SiPs involve the integration of multiple dies, and some SiPs (e.g., 2.5D and 3D ICs) can include wafer-level components in thin active ICs such as HBM DRAM chips, which have small through-silicon vias (TSVs) with a diameter of approximately 5 μm (and a depth of approximately 30 μm, equal to the typical silicon substrate thickness) and L / S redistribution layers (RDLs) with fine L(linewidth) / S(line spacing) of 2 μm / 2 μm or less. All advanced SiPs commercially available today are packaged with single-sided power and signal.

[0021] Referring to Figure 1A, the 2.5D IC structure 90 includes a laminated substrate 901 supporting a silicon interposer 902 via a plurality of solder connections 903. The silicon interposer 902, commonly used in 2.5D IC packaging, includes through-silicon vias (TSVs) 904 and can be used as a platform to bridge the fineness / spacing / pitch capability gap between the laminated substrate 901 and the IC block covering the 3D IC, such as an HBM DRAM stack, i.e., the memory structure 905 and the processor IC 907. A wide variety of electronic components produced by wafer-level processes can be placed on the silicon interposer 902 and may include memory devices (e.g., 905), logic ICs (e.g., 907), MEMS (micro-electromechanical systems) devices, and passive devices mounted on the top side (i.e., chip side) of the silicon interposer 902, and the electronic components can be placed in 2D IC, 2.5D IC, or 3D IC package configurations. For example, the memory structure 905 may be an HBM DRAM stack including multiple DRAM dies 905a stacked vertically on a base die (typically a control die) 905b via copper pillar microbumps. If necessary, the combination of the interposer 902 and the laminated substrate 901 can be replaced with a laminated substrate including a silicon interconnect substrate that is embedded in the substrate (Figure 1C) or mounted on the substrate. As shown in Figure 1A, the laminated substrate 901 to which the silicon interposer 902 is bonded using microbumps or solder bumps can be bonded to a printed circuit board (PCB, not shown) via multiple ball grid array (BGA) solder balls 906 located beneath the laminated substrate 901.

[0022] Referring to Figure 1B, the fan-out package structure 91 can be employed with electrical connections on chips 913a and 913b, where the electrical connections are fanned out from the active surface of chips 913a and 913b, allowing solder bumps 903a to be placed distal to chips 913a and 913b, beyond the chip boundary that functions as external I / O. The fan-out package structure 91, which can include one or more semiconductor chips (e.g., chips 913a and 913b), allows individual chips to be connected to fan-out wiring layers 911 and solder bumps 903a or alternatively to microbumps, depending on the application. As shown in Figure 1B, the fan-out package structure 91 produced by a wafer-level fan-out process is bonded to a substrate 901, which can be a multilayer substrate, an interposer, or another fan-out package structure, and is then bonded to the next level substrate using solder bumps or solder balls 906.

[0023] In Figure 1C, the embedded SiP 92 includes one or more devices 923 embedded in the laminated substrate 901. The one or more devices 923 may be an embedded silicon interconnect (which may be a passive or active device), an active device such as a power IC, or an embedded passive device such as a capacitor or inductor. Furthermore, the laminated substrate 901 in which the devices 923 are embedded can be bonded to another laminated substrate or PCB 908 via solder balls 906 or microbumps, depending on the application.

[0024] Referring to Figure 1D, the silicon photonics structure 93 includes a CMOS die 916, a waveguide RDL structure 918, a modulator 919 and a photodetector 920 embedded in the waveguide RDL structure 918, and an optical fiber 921 that couples optical signals inside and outside the waveguide RDL structure 918. The laser diode 917 and the waveguide RDL structure 918, as well as the components coupled to the waveguide RDL structure 918, are integrated on the silicon interposer 914, with or without TSV. The silicon interposer 914, manufactured by a wafer-level process, is configured to be mounted on a substrate via a plurality of solder bumps or microbumps 903 for external connections.

[0025] Referring to Figure 1E, the C2W structure 94 includes a first carrier 940, a first die 941, and a second die 942. The first die 941 and the second die 942 are positioned covering the first carrier 940 through various preferred bonding techniques, including a flip-chip assembly based on microbumps and copper hybrid bonding. The first carrier 940 can be an active or passive device including an interposer having through vias 943, and the first carrier 940 serves as a platform for interconnecting the first die 941 and the second die 942 with a substrate (not shown) on which the C2W structure 94 is mounted.

[0026] Referring to Figure 1F, the W2W structure 95 includes a first carrier 951, a second carrier 952, and an interconnection layer 953 that electrically couples the first carrier 951 to the second carrier 952. The interconnection layer 953 includes a flip-chip junction, a polyimide (PI)-PI or oxide-oxide based copper hybrid junction, or another suitable junction structure. Through vias 954 can be formed within the first carrier 951, for example, using solder bumps, microbumps, or solder balls 955 to establish an electrical connection between the first carrier 951, the second carrier 952, and a substrate (not shown) on which the W2W structure 95 is mounted.

[0027] In Figures 1A to 1F, interconnections between components are currently achieved by flip-chip assemblies based on solder bumps, microbumps, or BGA solder balls. Copper hybrid bonding is relatively new to high-end applications, including HPC, data center, and AI applications, and can be employed to achieve finer pitch bonding compared to flip-chip and higher density functional integration as required by the application.

[0028] A 3D IC typically includes an IC and / or connector (e.g., an interposer) having a top or bottom surface of similar or similar size. In some embodiments of this disclosure, the semiconductor package structures interconnected via their sides may be an IC stack containing ICs of similar or similar size, or an IC stack consisting of several packaging layers embedded with ICs of different sizes but with the same size after embedding, or an IC stack where both the ICs and the embedded ICs are the same size. Embedding of the ICs is achieved using a fan-out-like process and a potting material, molding compound, or encapsulating material, which is a dielectric material to ensure that ICs of different sizes in different stack layers are the same size after embedding. As a result, the side interconnects of the 3D IC are formed using conductive edge connections such as edge contact pads or edge vias in the RDL, edge through-silicon vias, and edge molded through-vias present at the edges of the packaging layers. The components integrated into the 3D IC can perform different electronic functions and are preferably available as known good dies or components. They may include ICs, other types of active devices such as MEMS (micro-electromechanical systems) devices, and passive devices. This means that the selection of components available for lamination and embedding is essentially unlimited.

[0029] Figures 2A to 2C show cross-sectional views of structures at different stages of a method for manufacturing an IC structure 100A according to some embodiments of the present disclosure. According to some embodiments, the IC structure 100A shown in Figure 2C is a semiconductor package device. The IC structure 100A may be formed from a semiconductor device 100W which is a wafer-level device, and the IC structure 100A is formed by separating the semiconductor device 100W using a singulation or dicing process that covers mechanical dicing, laser dicing, plasma etching or dicing, dry etching, wet etching (e.g., using acid etching), or a combination thereof.

[0030] Referring to Figure 2A, a semiconductor device 100W is accepted or provided. First, a substrate 102 is provided or accepted. According to some embodiments, the substrate 102 is formed of a semiconductor material such as bulk silicon. According to some embodiments, the substrate 102 is formed of other semiconductor materials such as silicon germanium, silicon carbide, or gallium arsenide. In this embodiment, the substrate 102 is a P-type semiconductor substrate (acceptor type). In some other embodiments, an N-type semiconductor substrate (donor type) can be used. Alternatively, the substrate 102 includes another elemental semiconductor such as germanium; a compound semiconductor including gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimony; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof. In yet another embodiment, the substrate 102 includes a portion forming a semiconductor on-insulator (SOI) substrate. In other embodiments, the substrate 102 may include semiconductor layers covering different types of semiconductor layers, such as a doped epitaxial layer, a gradient semiconductor layer, and / or a silicon layer on a silicon germanium layer.

[0031] Multiple conductive vias 104 are formed on the substrate 102. The conductive vias 104 may extend from the primary surface 102P1 of the substrate 102 to the thickness of the substrate 102. Throughout this disclosure, the “primary surface” is used to indicate the top or bottom surface of a circuit or device and has the largest surface area among the six surfaces of the device or layer. Similarly, the “secondary surface” is used to indicate the side surfaces of a circuit or device (there are often four such sides of a circuit or device) and has a smaller surface area than the primary surface. The conductive vias 104 may include conductive materials such as copper, tungsten, molybdenum, cobalt, ruthenium, titanium, tantalum, aluminum, silver, gold, or other suitable materials. The conductive vias 104 may include a single-layer or multilayer structure which may include a diffusion barrier layer, a seed layer to aid in electroplating, a filler layer, or a combination thereof.

[0032] In an exemplary process for forming conductive vias 104, a number of holes (not shown) are formed on the primary surface 102P1 of the substrate 102. The holes may be formed using dry etching (e.g., reactive ion etching, RIE), wet etching, or a combination thereof. After the holes are formed, the openings of the holes can be passivated by depositing silicon dioxide using a deposition process, such as plasma chemical vapor deposition (PECVD), or by performing physical vapor deposition (PVD), sputter deposition, atomic layer deposition (ALD), or other suitable deposition operations to deposit the material for the conductive vias 104 inside the holes and on the primary surface 102P1. The conductive vias 104 may be referred to herein as through-silicon vias (TSVs) after the hole-filling process.

[0033] According to some embodiments, a planarization process, such as chemical mechanical planarization (CMP), dry etching (e.g., using RIE), grinding, wet etching, and / or other suitable etching operations, is performed to remove excess conductive material and planarize the upper surface of the conductive vias 104 so that they are coplanar with the primary surface 102P1. Following planarization, primary RDL 108A is deposited on the primary surface 102P1, which is then surface-finished and padded for subsequent bonding as needed.

[0034] Referring to Figure 2B, another substrate or temporary carrier 106 is provided or accepted, and the semiconductor structure 100W is bonded to the temporary carrier 106. According to some embodiments, the substrate 106 is a carrier substrate or a support substrate. The carrier substrate 106 may be formed from glass, silicon, ceramic, or other suitable carrier material. A release layer 110 is formed on the carrier substrate 106. Examples of release layers include release / adhesion layers commonly used in fan-out processes. The release layer 110 is a temporary layer formed on the carrier substrate 106, which can make it easier to remove the carrier substrate 106 from the semiconductor device 100W by laser irradiation, thermomechanical delamination, grinding, CMP, dry or wet etching / cleaning, or a combination thereof.

[0035] In addition to the delamination layer used in the fan-out process, the delamination layer may be a combination of Ti (titanium) / Au (gold) on the carrier and Ti / Au on the back side of the IC structure. Here, Au may be Cu (copper) or double-sided solder. Bonding between the carrier and the IC structure can also be achieved using compression or reflow bonding. Annealing is optional and can be performed as needed. When silicon is used as the carrier, the delamination layer may be SiO2, Si3N4, etc., which are common in wafer BEOL and / or MEMS / NEMS processing. Such a delamination layer may also serve as a permanent bonding layer between IC structures (such as those shown in Figure 7B).

[0036] Pre-bonding preparation of the carrier and IC structure surface may include the following: For both diamond and silicon, chemical mechanical polishing (CMP) is performed as needed, preferably, to achieve a surface roughness RA (arithmetic mean roughness or sometimes root mean square roughness) < 1 nm. This level of RA can be achieved by CMP for silicon, and by a combination of sacrificial SiO2 layer deposition and SiO2 planarization by CMP and deep reactive ion etching (DRIE) for diamond. • Wet surface pretreatment including ultrasonic deionization (DI) water purification, H2SO4 / H2O2 treatment, NH3 / H2O2 treatment, and N2 blow drying. • Plasma / Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE): O2, H2 / O2, • Deep-dive RIE (DRIE): O2 / CF4, and Prior to bonding using a high-speed atomic beam gun, FAB (e.g., using an argon neutral atomic beam of approximately 1 keV), or ion gun (e.g., using argon ions of approximately 60 eV), the bonding surface inside the bonding machine is activated (with or without an adhesive layer) to remove the oxide film in a vacuum and expose the dangling bond on the surface for bonding. (Note 1: FAB works well on (sputtered) Si / Si, Si / SiO2, metals, compound semiconductors, and single-crystal oxides, while ion guns are known to work on SiO2 / SiO2, glass, Si3N4 (silicon nitride) / Si3N4, Si / Si, Si / SiO2, metals, compound semiconductors, and single-crystal oxides.) ·(Note 2:10 -6 A Pascal vacuum is required during bonding to prevent re-adsorption to the activated bonding surface.

[0037] In addition to the direct bonding approach described above, ultrathin adhesives or bonding layers such as CVD polysilicon (poly-Si) can be deposited as permanent bonding layers on the interlocking IC structure (Figure 7B) or as temporary delamination layers on both the IC structure and the carrier to achieve high low-temperature direct bonding yields. For heat-sensitive applications, poly-Si (with a thermal conductivity TC more than 100 times that of SiO2) is preferred over SiO2 for use in forming thin bonding layers, as it minimizes the impact of thermal resistance on the final IC or package structure. The adhesive layers are typically extremely thin, about 100 nm or less, to minimize their thermal effects. When used as permanent layers, materials with higher TC and lower thermal expansion are preferred. Candidate adhesive layers include the following and combinations (or alloys) thereof: Nonmetals: Si (e.g., polysilicon), SiO2, Si3N4, Al2O3 (alumina), diamond, boron nitride, graphene Metals: Ti, W, Pt, Cr, Au, Cu, Ir, Nickel (Ni), Iron (Fe), Ag-In, Au-In, Ag, Sn, Mo • Oxides on oxides: Ir on SrTiO3, Ir on YSZ / Si, MgO, sapphire, or Ir on TaO3

[0038] When using a metal adhesive layer to bond IC structures (see, for example, Figure 7B), it is desirable to deposit a barrier layer such as Ti on the back side of the IC structure before depositing the adhesive layer to prevent metal diffusion within the silicon lattice, which could damage the device. This is especially true for ultrathin ICs. Diamond growth on silicon seeds is a common practice during diamond CVD. Silicon nitride (Si3N4) is common in wafer BEOL processing. Alumina can be deposited by atomic layer deposition. In addition to diamond, graphene is also a material worth considering due to its extremely high thermal conductivity. In a single layer, graphene can have a thermal conductivity of 30-50 W / cm·K. This can be considered an adhesive or bonding layer, assuming a suitable 3D molecular structure. Graphene can be grown on a silicon(100) surface using direct cobalt-assisted two-step ion beam synthesis. It can also be grown on silicon by a simple transfer-free synthesis method. Epitaxial graphene can be grown on crystalline and semi-insulating surfaces (e.g., SiC and silicon), and graphene nanostructures with excellent properties have been realized by selective growth processes on SiC surfaces. In addition to diamond and graphene, cubic boron nitride is also noteworthy, as it is known to have a crystalline structure similar to diamond and a high in-plane TC (~16 W / cm·K). Furthermore, the adhesive layer can be a combination of Ti / Au on one IC structure and Ti / Au on the back side of another IC structure for bonding. A thin metallization based on Ti, W, or Cr can also be deposited before Au deposition, if necessary. Thin layers of transient liquid bonding materials such as silver-indium (Ag-In) and Au-In, sintered Ag, In, Au, or Cu can also be applied together with coherent metallization (e.g., Au, Ag, or Cu). The adhesive layer can be deposited by CVD, atomic layer deposition (ALD), physical vapor deposition, thermal oxidation (in the case of silicon), or other means.After deposition, the adhesive layer can be prepared through a combination of the aforementioned pre-bonding surface pretreatment, DRIE (e.g., using a mixture of SF6 and O2), plasma / ICP-RIE (using O2, Ar, N2, Ar / O2), and FAB (e.g., using neutral Ar atoms) or ion gun (e.g., using Ar ions) at a bonding station.

[0039] Following the creation of the primary RDL108A, the planarized structure having the primary RDL108A is bonded to the substrate 106 with the help of a delamination layer, and the bulk portion of the substrate 102 beneath the conductive via 104 is removed, exposing the bottom surface of the conductive via 104 (see Figure 2B). Another RDL108B can then be deposited on the exposed conductive via 104 in Figure 2B and completed with surface finishing and solder bumps or microbumps as necessary. Following the formation of the RDL108B, the mounting of the resulting structure having RDL108A and 108B on the carrier 106 on the wafer mount tape frame, the release of the carrier 106, and the individualization of the packages, the semiconductor structure 100A in Figure 2C is formed.

[0040] Based on the processes shown in Figures 2A to 2C, various layers and structures can be formed to create semiconductor structures 100A including exposed edge pads, edge vias, and edge TSVs that can completely or partially penetrate the thickness of silicon or potting material or a subset thereof, for example, a structure including only RDL108A having edge pad / via interconnects within the RDL (Figure 2E), or a structure including both RDL108A having edge interconnects and edge TSVs (see Figure 2F).

[0041] According to some embodiments, the release layer 110 comprises a polymer-based material. According to some embodiments, the release layer 110 is an epoxy-based thermal release material, such as a photothermal conversion (LTHC) release coating, which loses its adhesive properties when heated or exposed to a laser. According to other embodiments, the release layer 110 is an ultraviolet (UV) adhesive, which loses its adhesive properties when exposed to UV light. The release layer 110 may be a thermoplastic or thermosetting material. According to some embodiments, the release layer 110 comprises a polyimide or silicone-based material. According to some other embodiments, the release layer 110 is a mixture of metallic and nonmetallic materials. Candidate metallic materials for the release layer may include nickel, chromium, titanium, gold, copper, manganese, iron, cobalt, tungsten, molybdenum, ruthenium, and tantalum, while nonmetallic candidates may include metal oxides, nitrides, phosphates, and chromates. The release layer 110 may be deposited as a liquid by spin coating and then cured. In other embodiments, the release layer 110 may be a laminate film laminated on the carrier substrate 106. In some other embodiments, bonding between the substrate 102 and the temporary carrier 106 may be achieved without requiring the release layer 110, for example, by direct bonding based on oxide-oxide or polyimide-polyimide.

[0042] RDL108A is part of the interconnection structure 101 of IC structure 100A. RDL108A includes one or more interconnected conductive paths formed through one or more conductive wires in a conductive wire layer and one or more conductive vias (not shown separately) in a conductive via layer for routing power and signals of a first circuit from one side of RDL108A to a second circuit on the same or opposite side of RDL108A. RDL108A may include a sealing material (or a sealing material such as a polyimide or oxide layer to facilitate direct or copper hybrid bonding) that seals the conductive wire layer and the conductive via layer. According to some embodiments, the sealing material includes one or more dielectric materials, e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide, a combination thereof, or equivalents. Using RDL108A of interconnection structure 101, the distribution of signals and power of devices or circuits in IC structure 100A can meet design requirements. Throughout this disclosure, an RDL formed on the primary surface of a circuit or device, for example, the primary surface 102P1, e.g., an RDL108A, is referred to as a primary RDL108A. Further structural details of the primary RDL108A are discussed below.

[0043] According to some embodiments, the substrate 102 is placed on and bonded to the primary RDL 108A. Bonding of the substrate 102 to the primary RDL 108A may be performed using thermal bonding, thermocompression bonding, flip-chip bonding, hybrid bonding, etc. Although not shown, conductive vias 104 of the substrate 102 are electrically coupled to one of the conductive wires or one of the conductive vias of the primary RDL 108A to extend the signal delivery network or power delivery network of the RDL 108A. Furthermore, the upper portion of the substrate 102 is removed or thinned from the top portion of the substrate 102. The bottom surface of the conductive vias 104 is exposed accordingly. Removal or thinning of the upper portion of the substrate 102 may be performed using CMP, grinding, dry etching (e.g., RIE), wet etching, etc. Conductive vias 104 become TSV 104 accordingly.

[0044] Referring to Figure 2C, the structure having RDL108A and RDL108B is mounted on a wafer mount frame, and after releasing the carrier 106, a fragmentation or dicing process is performed to separate the semiconductor device 100W into individual IC structures 100A. The fragmentation or dicing process may be performed using a diamond blade, a laser, plasma with a masking layer deposited on RDL108A, for example, wet etching, or a combination thereof to fragment the semiconductor device 100W along the scribe lines and form individual IC structures 100A. The interconnection structure 101 within the IC structure 100A comprises a TSV die 122A, an internal interconnection structure 108X such as internal pads and vias in RDL108A and 108B, and an edge interconnection structure 118X such as edge pads and vias in RDL.

[0045] During dicing or fragmentation, the area to be cut off is called the dicing, saw, or die street, and is typically 50 μm to 100 μm wide. The dicing saw may use a diamond blade that rotates at 30,000 rpm and is cooled with deionized water. To expose edge pads or vias, the size of the edge pads or vias is comparable to the dicing street width, and dicing is preferably performed in close proximity to the edge pads or vias (but not directly through them), followed by light wet etching of silicon as needed and to be ensured. To minimize bottom-side chipping during mechanical blade dicing, it may be advantageous to first dice the wafer with a carrier support and then peel off the carrier. Laser ablation dicing, which can allow for a dicing street width of 10 μm, may also use a non-contact laser to first remove a fine wire layer on the surface of the dicing street (and expose the adjacent edge pad), followed by cutting the residual substrate by laser scribing and / or blade dicing. This process reduces problems such as chipping, die cracking, and delamination. In laser ablation dicing, the laser heats the material to a temperature such that the area beneath the laser spot is ablated or simply vaporized. Alternatively, dicing can be performed by dry, liquid-free stealth dicing. Stealth dicing functions as a two-step process, in which a laser beam (e.g., a pulsed Nd:YAG laser with a wavelength of 1064 nm for silicon) is first directed to scan along the intended cutting line, creating a defect region, and then the underlying film (adhered to the wafer and subsequently released from the wafer carrier) is expanded, inducing fracture. Stealth laser dicing has the potential to replace blade dicing as a next-generation ultrathin wafer dicing technology to support 3D IC packaging, as stealth lasers enable faster, more accurate, less damaging, and smaller dicing street widths.Compared to mechanical and laser dicing, plasma dicing (also known as deep reactive ion etching) is a relatively new method that applies the Bosch dry etching process, enabling dies to be cut with high precision and free from particles and contamination. This method requires custom mask design for effective plasma dicing. It achieves high precision, throughput, and quality by using a plasma gas such as sulfur hexafluoride to simultaneously etch all narrow dicing streets into the wafer. Plasma dicing can produce cuts with non-rectangular shapes, going beyond the range of blade dicing. Because plasma dicing minimizes damage to the wafer surface or trench sidewalls, it results in better die strength, improved device reliability, and a longer device lifespan. Plasma dicing is rapidly gaining popularity within the semiconductor industry as a preferred solution, especially as chips become smaller, thinner, and more complex.

[0046] As a result of the dicing or fragmentation process, the IC structure 100A includes four secondary planes or sides 100AS, although Figure 2D shows only two secondary planes 100AS. The TSV die 122A includes sides 102S on its four sides, while the primary RDL 108A and primary RDL 108B include sides 108S on their four sides. The sides 102S of the TSV die 122A and the sides 108S of the two primary RDLs 108A and 108B together constitute or coincide with the secondary plane 100AS of the IC structure 100A. Through appropriate arrangement, the TSV 104 is formed on the TSV die 122A and, after the dicing or dicing process, comprises two TSV types (internal TSV 104A and edge TSV 104B), where the internal TSV 104A is completely surrounded by the substrate 102 and primary RDLs 108A and 108B, while the edge TSV 104B has at least one side exposed through the side surface 102S of the substrate 102.

[0047] Similarly, the primary RDL 108A or 108B includes conductive pads 212 and conductive vias 214, respectively, formed from conductive elements 202 such as conductive wires and conductive vias, and the conductive element 202 includes two parts (internal conductive element 202 and edge conductive element 202). By appropriate arrangement, the conductive pads 212 and conductive vias 214 are formed on the IC structure 100A and, after the dicing or dicing process, include two parts (internal conductive pads / vias 212 and 214, and edge conductive pads / vias 212 and 214), the internal conductive pads / vias 212 and 214 are completely surrounded by the substrate material and encapsulating material of the two primary RDLs 108A and 108B, while the edge conductive pads / vias 212 and 214 have at least one side exposed through the side 108S of the primary RDL, 108A or 108B.

[0048] According to some embodiments, the edge conductive pad 212 has at least one upper surface exposed through the primary surface 108P of the primary RDL 108A or 108B. The internal or edge conductive pad 212 may be positioned on the uppermost conductive wire layer of each primary RDL 108A or 108B that is furthest distal to the TSV die 122A. According to some embodiments, the conductive pad 212 is positioned parallel to the primary surface 108P of the primary RDL 108A or 108B. The conductive pad 212 may stop in front of the TSV die 122A. Furthermore, the edge conductive pad 212 has at least one side surface exposed through the secondary plane 100AS of the IC structure 100A or the secondary surface 108S of the primary RDL 108A or 108B.

[0049] Similarly, according to some embodiments, the edge conductive via 214 has at least one upper surface exposed through the primary surface 108P of the primary RDL 108A or 108B. The edge conductive via 214 may be arranged to extend through the thickness (z-direction) of each primary RDL 108A or 108B. According to some embodiments, the edge conductive via 214 is referred to herein as the TSV of the primary RDL 108A or 108B. Furthermore, the edge conductive via 214 has at least one side surface exposed through the secondary plane 100AS of the IC structure 100A or the secondary surface 108S of the primary RDL 108A or 108B.

[0050] Figure 2D shows a perspective view of a primary RDL 108A or 108B according to various embodiments of the present disclosure. The primary RDL 108A or 108B includes a primary surface 108P (e.g., an upper primary surface 108P1 and a lower primary surface 108P2) and four secondary (side) surfaces 108S (e.g., a front secondary surface 108S1, a rear secondary surface 108S2, a right secondary surface 108S3, and a left secondary surface 108S4). Multiple conductive elements 202, such as conductive pads / vias 212, are formed on the primary RDL 108A or 108B and exposed through the four secondary surfaces 108S. The arrangement of conductive pads 212 on the primary RDL 108A or 108B in Figure 2D is shown for illustrative purposes only. Conductive pads 212 or other conductive elements may be formed or exposed through one or more of the four secondary surfaces 108S.

[0051] As described above, throughout this disclosure, the TSV 104 (see 104A and 104B in Figure 2C), the conductive pad 212, the conductive via 214, and all other conductive members of the interconnect structure 101 in Figure 2C are part of what is collectively referred to as the conductive elements 202 within the interconnect structure 101 of the IC structure 100A. The TSV 104, the conductive pad 212, and the conductive via 214 are configured to form at least a portion of the interconnect structure 101 of the IC structure 100A for fan-in or fan-out interconnects for devices or package layers electrically coupled to the IC structure 100A, through the two primary surfaces 108P in Figure 2C of the IC structure 100A (i.e., the upper primary surface 108P1 and the lower primary surface 108P2; see Figure 2D), and through the four secondary surfaces 108S1 to 108S4 of the IC structure 100A (see Figure 2D). According to some embodiments, the TSVs 104 and conductive vias 214 of primary RDLs 108A and 108B can be coupled to form a combined TSV of IC structure 100A. For example, the right-side conductive via 214 of primary RDL 108A (Figure 2C), the right-side TSV 104, and the right-side conductive via 214 of primary RDL 108B constitute a stacked edge TSV of IC structure 100A that extends through the substrate thickness of IC structure 100A.

[0052] Figure 2E shows a cross-sectional view of IC structure 100B according to various embodiments of the present disclosure. IC structure 100B is similar to IC structure 100A in many embodiments, for example, in the primary RDL 108A, conductive pad 212, and conductive via 214, and therefore details of such similar embodiments will not be repeated for brevity. The main difference between IC structure 100A and IC structure 100B is that the TSV die 122A in IC structure 100A is replaced by the semiconductor die 122B in IC structure 100B, and the primary RDL 108B in IC structure 100A is absent in IC structure 100B. According to some embodiments, the semiconductor die 122B can be at least one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, memory die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die. The semiconductor die 122B may include a substrate 102 containing a material similar to that of the substrate 102 of the IC structure 100A shown in Figure 2D. Thus, the semiconductor die 122B constitutes the substrate or body of the IC structure 100B. According to some embodiments, the semiconductor die 122B does not include the edge interconnect structure 118X exposed through the side surface 102S of the semiconductor die 122B.

[0053] Figure 2F shows a cross-sectional view of IC structure 100C according to various embodiments of the present disclosure. IC structure 100C is similar to IC structure 100B in many embodiments, for example, in the primary RDL 108A, conductive pad 212, and conductive via 214, and therefore details of such similar embodiments are not repeated for brevity. Furthermore, IC structure 100C includes a semiconductor die 122C, which can be at least one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, memory die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die. Semiconductor die 122C may include a substrate 102 similar to the substrate 102 of IC structure 100A shown in Figure 2D. The main difference between semiconductor die 122C and semiconductor die 122B is that semiconductor die 122C further includes edge interconnection structures 118X, such as edge conductive pads 222, exposed through the secondary plane or side surface 102S of semiconductor die 122C. According to some embodiments, the edge conductive pads 222 are electrically connected to conductive vias 214 of the primary RDL 108A to establish stacked conductive vias for semiconductor die 122C. Thus, semiconductor die 122C constitutes the body of IC structure 100C.

[0054] Figure 2G shows a cross-sectional view of the primary RDL 108A or 108B of the IC structures 100A, 100B, or 100C shown in Figures 2B to 2F, according to various embodiments of the present disclosure. As shown in Figure 2G, the primary RDL 108A or 108B is formed of a first major conductive line / via layer 240 and a second major conductive line / via layer 250 located beneath the first major conductive line / via layer 240. Each of the first major conductive line / via layer 240 and the second major conductive line / via layer 250 contains one or more conductive lines and conductive vias extending horizontally or vertically (all of which are part of a collection of conductive elements 202 of the interconnection structure 101 within the primary RDL 108A or 108B). The conductive lines or vias are electrically insulated by a dielectric layer called an intermetallic dielectric (IMD) layer. The IMD layer may contain one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, polyimide, or other suitable dielectric materials. Some of the conductive vias in the first main conductive wire / via layer 240 extend halfway vertically, while some of the conductive vias in the first main conductive wire / via layer 240, for example conductive via 214-1, extend through the entire thickness of the first main conductive wire / via layer 240. Similarly, some of the conductive vias in the second main conductive wire / via layer 250 extend partway vertically, while some of the conductive vias in the second main conductive wire / via layer 250, for example conductive via 214-2, extend through the entire thickness of the second main conductive wire / via layer 250. Conductive vias 214-1 and 214-2 are electrically connected to form a laminated conductive via 214 of the primary RDL 108A or 108B that traverses the primary RDL 108A or 108B. According to some embodiments, the first main conductive wire / via layer 240 includes two conductive wire layers and a conductive via layer between the two conductive wire layers, and the conductive via 216 is located within the conductive via layer to electrically connect two conductive wires in adjacent conductive wire layers. Referring to Figures 2F and 2G, the conductive via 214 of the IC structure 100C shown in Figure 2F is considered a conductive via connecting adjacent first and second main conductive wire / via layers 240 and 250.According to some embodiments, the laminated conductive via 214 is part of the edge interconnect structure 118X and is exposed through the secondary surface 108S of the primary RDL 108A or 108B. Figure 2G shows only two main conductive wire / via layers 240 and 250, but the disclosure is not limited thereto. A number of other main conductive wire / via layers and the configuration of conductive wires or conductive vias in each main conductive wire / via layer are also within the scope intended by the disclosure.

[0055] Figures 3A to 3D show cross-sectional views of structures at different stages of a method for manufacturing an IC structure 300A according to some embodiments of the present disclosure. According to some embodiments, the IC structure 300A shown in Figure 3D is a semiconductor package device. The IC structure 300A may be formed from a semiconductor device 300W which is a wafer-level device, and the IC structure 300A is formed by separating the semiconductor device 300W using a dicing or dicing process.

[0056] Referring to Figure 3A, a carrier substrate 106 is received or provided. Also, similar to Figures 2A-2C, a release layer 110 is formed on the carrier substrate 106. Multiple semiconductor dies 122D are placed on the release layer 110. The semiconductor dies 122D may include at least one of CPU dies, GPU dies, TPU dies, MEMS dies, AP dies, FPGA dies, ASIC dies, memory dies, transceiver dies, network interface dies, integrated photonics dies, packet buffer / router dies, or other suitable dies. Furthermore, multiple conductive pillars or vias 232 are formed on the release layer 110 between adjacent semiconductor dies 122D with a suitable pitch and encapsulated by a molding compound or a suitable potting material (epoxy, e.g., Epotek 377) as shown in Figure 3B. The conductive vias 232 may be created alternately within the semiconductor dies 122D. Multiple semiconductor dies 122D and conductive vias (pillars) 232 are referred to herein as a reconfigured structure and are arranged on the delamination layer 110 or the carrier surface 110S of the carrier substrate 106. The conductive vias 232 may contain a conductive material, such as tungsten, copper, titanium, tantalum, molybdenum, ruthenium, cobalt, aluminum, silver, gold, or another suitable material. Multiple semiconductor dies 122D and conductive vias 232 may have substantially equal heights. According to some embodiments, the semiconductor dies 122D and conductive vias 232 are arranged on the delamination layer 110 by a pick-and-place bonding process.

[0057] Referring to Figure 3B, the reconfigured structure of the semiconductor device 300W is formed or sealed using a potting material (e.g., sealing material, molding material, or insulating element) 242. The potting material 242 may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, epoxy-based molding materials, and polymer materials. The forming or deposition process is performed to deposit the potting material 242 between the semiconductor die 122D and the conductive vias 232, which can be created before bonding the semiconductor die 122D and depositing the potting material. According to some embodiments, a planarization process, e.g., CMP, grinding, wet etching, dry etching (e.g., RIE), and / or another preferred etching operation is performed to remove excess potting material 242, planarize the top surface of the potting material 242, and expose the conductive vias 232 from the top surface of the semiconductor die 122D. According to some embodiments, the conductive via 232 is located within the potting material 242 and is thereby surrounded laterally; therefore, the conductive via 232 is also referred to herein as a through-mold via (TMV) 232.

[0058] Referring to Figure 3C, the primary RDL108A is formed on the potting material 242, the semiconductor die 122D, and the upper surface of the TMV232. The material, configuration, and method for forming the primary RDL108A are the same as those described with reference to Figures 2B to 2G, and a repeated description of the primary RDL108A is omitted for brevity.

[0059] Referring to Figure 3D, the dicing or fragmentation process is performed to separate the semiconductor device 300W into individual IC structures 300A. Furthermore, the carrier substrate 106 is removed or detached from the semiconductor device 300W by peeling off the delamination layer 110 from the semiconductor device 300W. By appropriate arrangement, conductive pads / vias 212 / 214 are formed on the IC structure 300A, comprising two pad / via types (internal conductive pads / vias (not shown separately) 212 and edge conductive pads / vias 214) after the dicing or fragmentation process. The properties of conductive pads / vias 212 and conductive pads / vias 214 are similar to those of IC structure 100C shown in Figure 2F, and a repeated explanation is omitted for brevity. The main difference between IC structure 300A and IC structure 100C is that in IC structure 300A, the semiconductor die 122D is either surrounded or encapsulated laterally by the potting material 242, whereas in 100C, only the edges of the die and RDL are exposed. The semiconductor die 122D and the potting material 242 constitute the main body of IC structure 300A.

[0060] Figure 3E shows a cross-sectional view of IC structure 300B according to various embodiments of the present disclosure. IC structure 300B is similar to IC structure 300A in many embodiments, for example, in the primary RDL 108A, conductive pad 212, and conductive via 214, and therefore details of such similar embodiments will not be repeated for brevity. The main difference between IC structure 300A and IC structure 300B is that, in addition to the semiconductor die 122D and potting material 242, the body of IC structure 300B further includes an edge TMV 232 that extends through or partially through the thickness of the semiconductor die 122D. The edge TMV 232 is part of the edge interconnect structure 118X.

[0061] Figure 3F shows a cross-sectional view of IC structure 300C according to various embodiments of the present disclosure. IC structure 300C is similar to IC structure 300B in many embodiments, e.g., in the primary RDL 108A, conductive pad 212, conductive via 214, and TMV 232, and therefore details of such similar embodiments are not repeated for brevity. Furthermore, IC structure 300C includes a semiconductor die 122D1, which replaces semiconductor die 122D and can be at least one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, memory die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die. The main difference between semiconductor die 122D and semiconductor die 122D1 is that semiconductor die 122D1 further includes an edge conductive pad 222 exposed through a portion of the edge interconnection structure 118X, for example, a secondary plane or side surface 102S of semiconductor die 122D1. The material, structure and method for forming the edge conductive pad 222 of IC structure 300C are similar to those of the conductive via 222 described with reference to Figure 2F. Thus, the body of IC structure 300C includes semiconductor die 122D1, potting material 242, conductive via 222, and TMV 232. According to some embodiments, the primary RDL 108A of IC structure 300C includes a conductive via 214 electrically connected to the TMV 232 in the body of IC structure 300C to establish stacked conductive vias for IC structure 300C.

[0062] Figures 4A to 4G show cross-sectional views of structures at different stages of a method for manufacturing an IC structure 400A according to some embodiments of the present disclosure. According to some embodiments, the IC structure 400A shown in Figure 4G is a semiconductor package device. The IC structure 400A may be formed from a semiconductor device 100W (see Figure 4A), which is a wafer-level device, and the IC structure 400A is formed by separating the semiconductor device 400W using a dicing or dicing process.

[0063] Referring to Figure 4A, the substrate 102 is received or supplied as a semiconductor device 100W. Furthermore, conductive vias 104 are formed on the substrate 102. Referring to Figure 4B, the bulk portion of the substrate 102 beneath the conductive vias 104 is removed, for example, by CMP, grinding, or etching, so that the conductive vias 104 become a TSV 104. A dicing or fragmentation process is performed to separate the semiconductor device 100W into a plurality of TSV dies 122E, the TSV die 122 being similar to the TSV die 122A described with reference to Figure 2C.

[0064] Referring to Figure 4C, the carrier substrate 106 is received or provided within the semiconductor device 400W. Furthermore, a release layer 110 is formed on the carrier substrate 106. Multiple TSV dies 122E and multiple TMV 232 are arranged on the release layer 110 to form a reconfigured structure on the release layer 110 or the carrier surface 110S of the carrier substrate 106. The TMV 232 may be arranged alternately with the TSV dies 122E. The TMV 232 may include a conductive material, such as tungsten, copper, titanium, tantalum, molybdenum, cobalt, ruthenium, aluminum, silver, gold, or another suitable material. Multiple TSV dies 122E and multiple TMV 232 may have substantially equal heights. According to some embodiments, the TSV dies 122E and TMV 232 are arranged on the release layer 110 by a pick-and-place bonding process.

[0065] Referring to Figure 4D, the semiconductor device 400W is molded or sealed using a potting material (e.g., encapsulating material or molding material) 242. A deposition or molding process is performed to deposit the potting material 242 between the TSV die 122E and the TMV 232. According to some embodiments, a planarization process, such as CMP, grinding, etching, or another preferred etching operation, is performed to remove excess potting material 242 and to planarize the top surface of the potting material 242, the top surface of the TSV die 122E, and the top surface of the TMV 232 to expose the TSV and TMV.

[0066] Referring to Figure 4E, the primary RDL108A is formed on the upper surfaces of the potting material 242, TSV die 122E, and TMV232. The material, composition, and method for forming the primary RDL108A are the same as those described with reference to Figures 2B to 2G, and a repeated description of the primary RDL108A is omitted for brevity.

[0067] According to some embodiments, the order of the processing steps shown in Figures 4C and 4D can be changed. For example, first, a plurality of TSV dies 122E are placed on the release layer 110 without TMV 232. Subsequently, potting material 242 is deposited and planarized to fill the gaps between the TSV dies 122E. For example, a laser drilling operation is performed to form via holes between the TSV dies 122E, after which the TSV dies are filled with a conductive material to form TMV 232. The vias may be laterally surrounded by the potting material 242.

[0068] Referring to Figure 4F, another carrier substrate 116 is provided or received within another semiconductor device 401W. Another release layer 120 is formed on the carrier substrate 116. Furthermore, the structure in Figure 4E is inverted with its RDL108A side bonded to the second carrier substrate 116 using the release layer 120, and the carrier 106 is peeled off. Subsequently, another primary RDL108B with surface finish and bonding pads is formed on the opposite side of the TSV die 122E, potting material 242, and TMV232s supported by the second carrier 116. The materials, configuration, and method for forming the carrier substrate 116, release layer 120, and primary RDL108B are the same as those for the carrier substrate 106, release layer 110, and primary RDL108A described with reference to Figure 2C, and therefore, details of such similar features will not be repeated for brevity. Furthermore, the carrier substrate 116 is peeled off from the semiconductor device 401W by peeling off the release layer 120 after wafer mounting.

[0069] Referring to Figure 4G, the dicing process is performed to separate the reconfigured structure of the semiconductor device 401W into individual IC structures 400A. By appropriate arrangement, TMV232 and edge TSV104B are formed in IC structure 400A. • Two TMV types after the dicing or dicing process (internal TMV (not shown) and edge TMV232), • Two TSV types after the individualization or dicing process (internal TSV and edge TSV104B), It is equipped with.

[0070] The characteristics of the conductive pads 212 and conductive vias 214 of the primary RDL108A or 108B are the same as those of IC structure 100A shown in Figure 2C, and for brevity, a repeated explanation of them is omitted. IC structure 400A differs from IC structure 100A mainly in that IC structure 400A further includes a potting material 242 that fills the space between the semiconductor die 122D and the TMV232. The semiconductor die 122D, TMV232, and potting material 242 constitute the main body of IC structure 400A.

[0071] Figures 4H to 4N show cross-sectional views of IC structures 400B, 400C, 400D, 400E, 400F, 400G, and 400H according to various embodiments of the present disclosure. Since IC structures 400B, 400C, 400D, 400E, 400F, 400G, and 400H are seen in many embodiments as variations of baseline IC structure 400A, the following description will focus only on the differences between IC structure 400A and the other IC structures 400B to 400H.

[0072] Referring to Figure 4H, the main difference between IC structure 400B and IC structure 400A is that in IC structure 400B, the TSV die 122E containing the internal TSV is laterally surrounded or enclosed by the potting material 242, and there are no edge TSVs in IC structure 400B.

[0073] Referring to Figure 4I, the main difference between IC structure 400C and IC structure 400A is that TMV232 is not present in IC structure 400C. Referring to Figure 4J, IC structure 400D does not have edge TSV or edge TMV, while both are present in IC structure 400A.

[0074] The IC structures 400E, 400F, 400G, and 400H shown in Figures 4K to 4N can be viewed as multi-die versions of the corresponding single-die IC structures 400A, 400B, 400C, and 400D, with multiple dies arranged within the same package layer of IC structures 400E to 400H. Referring to Figure 4K, the main difference between IC structure 400E and IC structure 400A is that IC structure 400E further includes a second semiconductor die 122D in addition to the first semiconductor die, namely the TSV die 122E, both of which may be the same or different in size. Thus, the body of IC structure 400E consists of semiconductor die 122D, TSV die 122E, TMV 232, potting material 242, and RDL 108A and 108B. Semiconductor die 122D and TSV die 122E are arranged in the same package layer. The semiconductor die 122D (which may also include internal or edge TSVs) is laterally surrounded or encapsulated by a potting material 242. Furthermore, in the IC structure 400E, the TMV 232 functions as an edge TMV, which is electrically connected to the edge conductive vias 214 of the primary RDL 108A and the edge conductive vias 214 of the primary RDL 108B to form a stacked TSV that extends across the entire thickness of the IC structure 400E.

[0075] Referring to Figure 4L, the main difference between IC structure 400F and IC structure 400E is that in IC structure 400F, the TSV die 122E is further surrounded or enclosed laterally by the potting material 242, while IC structure 400F does not include edge TSVs.

[0076] Referring to Figure 4M, the main difference between IC structure 400G and IC structure 400E is that IC structure 400G, which includes edge TSV104B, does not have edge TMV232.

[0077] Referring to Figure 4N, IC structure 400H can be seen as a combination of the features of IC structures 400F and 400G, where the body of IC structure 400H comprises only a semiconductor die 122D, a TSV die 122E, potting material 242, and RDLs 108A and 108B, without edge TSVs and edge TMVs. According to some embodiments, the potting material 242 laterally surrounds and encapsulates the semiconductor dies 122D and 122E. The potting material 242 is exposed through two secondary planes 102S of the body of IC structure 400H.

[0078] Figure 5A shows a cross-sectional view of an IC structure 500A according to various embodiments of the present disclosure. The body of the IC structure 500A comprises a semiconductor die 122F, a TMV 232, and a potting material 242. The semiconductor die 122F may include at least one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, memory die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die. The semiconductor die 122F is similar to the semiconductor die 122D1 shown in Figure 3F, except that the edge conductive pads 222 of the semiconductor die 122D1 are replaced by a plurality of TSVs 104 (including internal TSVs 104A and edge TSVs 104B), one edge TSV 104B being exposed through the secondary plane 500AS of the IC structure 500A. Furthermore, in contrast to the aforementioned IC structure, the IC structure 500A further includes a secondary RDL118A which is arranged on the secondary plane 500AS of the IC structure 500A and electrically connected to the primary RDL108A.

[0079] Figure 5C shows a more detailed cross-sectional view of the secondary RDL 118A of the IC structure 500A shown in Figure 5A, according to various embodiments of the present disclosure. The secondary RDL 118A is similar to the primary RDL 108, for example, the primary RDL 108A or 108B described with reference to Figure 2G. The secondary RDL 118A shown in Figure 5C includes two main conductive wire / via layers 340, 350, similar to the first and second main conductive wire / via layers 240 and 250 of the primary RDL 108A or 108B in Figure 2G. Referring to Figure 5C, the secondary RDL 118A includes a front interconnect surface 118F and a rear interconnect surface 118R opposite to the front interconnect surface 118F. The secondary RDL118A is electrically connected to the edge interconnection structure 118X of the IC structure 500A, for example, the edge TSV104B of the semiconductor die 122F or the edge conductive pad 212 of the primary RDL108A. According to some embodiments, the secondary RDL118A is considered to be part of the edge interconnection structure 118X of the IC structure 500A. With such a configuration, the primary RDL108A can be electrically connected to the semiconductor die 122F not only via the internal interconnection structure 108X, but also via the edge interconnection structure 118X, which includes the edge TSV104B and the secondary RDL118A, via the primary surface 102P of the substrate 102 of the IC structure 500A and the primary surface 108P of the primary RDL108A facing the substrate 102, as well as via the side surface (secondary plane) 102S of the body of the IC structure 500A and the front interconnection surface 118F of the secondary RDL118A. Therefore, the routing capacity and design flexibility of the IC structure 500A provided for semiconductor die 122F are increased compared to the secondary RDL118A and other IC structures without edge interconnects.

[0080] Figure 5B shows a cross-sectional view of IC structure 500B according to various embodiments of the present disclosure. IC structure 500B is substantially similar to IC structure 500A in many embodiments, and therefore, a description of similar features will not be repeated for brevity. The main difference between IC structure 500B and IC structure 500A is that, in addition to the secondary RDL 118A located in the secondary plane 500BS1 on the left side of IC structure 500B, IC structure 500B further includes a secondary RDL 118B located in the secondary plane 500BS2 on the right side of IC structure 500B opposite to the secondary RDL 118A. The material and configuration of the secondary RDL 118B may be the same as that of the secondary RDL 118A, as shown in Figure 5C. However, other configurations and numbers of main conductive wire / via layers for secondary RDL 118A and 118B are also within the scope intended of the present disclosure. Therefore, the secondary RDLL118B can also be considered part of the edge interconnection structure 118X of the IC structure 500B and can be electrically connected to the primary RDL108A.

[0081] Figures 6A to 6E show cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 600A according to various embodiments of the present disclosure. According to some embodiments, the IC structure 600A shown in Figure 6E is a semiconductor package device. The IC structure 600A may be formed from a semiconductor device 600W which is a wafer-level device, and the IC structure 600A in Figure 6E is formed by separating the semiconductor device 600W using a dicing or dicing process.

[0082] Referring to Figure 6A, a carrier substrate 106 is provided or received. A delamination layer 110 is formed on the upper surface of the carrier substrate 106. A plurality of semiconductor dies, for example, semiconductor dies 122E, 122G, and 122H, are prepared. According to some embodiments, the semiconductor die 122G or 122H can be at least one of any of the following: a CPU die, a GPU die, a TPU die, a MEMS die, an AP die, an FPGA die, an ASIC die, a memory die, a transceiver die, a network interface die, an integrated photonics die, a packet buffer / router die, another suitable die, or any of the aforementioned semiconductor dies. The TSV die 122E includes a plurality of TSVs 104 on the upper surface of the TSV 104 and a primary RDL 108A. According to some embodiments, the semiconductor die 122G or 122H can be at least one of any of the following: a CPU die, a GPU die, a TPU die, a MEMS die, an AP die, an FPGA die, an ASIC die, a memory die, a transceiver die, a network interface die, an integrated photonics die, a packet buffer / router die, another suitable die, or any of the aforementioned semiconductor dies.

[0083] The semiconductor dies 122E, 122G, and 122H may be similar in size or dimensions, or they may be different. For example, the semiconductor dies 122E, 122G, and 122H may be substantially equal in height, length, or width, or they may be different.

[0084] A pick-and-place process is performed to pick up known good dies (KGDs) of semiconductor dies 122E, 122G, and 122H and bond the KGDs onto a release layer 110. After semiconductor die 122H is placed on the release layer 110, a bonding layer or die attachment layer 160 is formed on semiconductor die 122H. The bonding layer 160 may assist in attaching semiconductor die 122G to semiconductor die 122H. According to some embodiments, the bonding layer 160 is a die attachment film, an array of microbumps configured to perform flip-chip bonding, a direct bonding layer, or a hybrid bonding layer configured to generate a bond. According to some embodiments, semiconductor dies 122G and 122H are stacked vertically. Semiconductor die 122E may be placed adjacent to the stacked semiconductor dies 122G and 122H in the same package layer. Semiconductor dies 122E, 122G, and 122H may be substantially the same size or different in size.

[0085] Referring to Figure 6B, the semiconductor device 600W is formed or encapsulated using a potting material or a preferred material 252. The material and composition of the potting material 252 are similar to those of the potting material 242 and may include a molding compound and a thick-film photoresist. The molding or deposition process is carried out to deposit the potting material 252 between the semiconductor dies 122E, 122G, and 122H, thereby embedding the semiconductor dies 122E, 122G, and 122H. The embedding material 252 may have a height exceeding the height of the semiconductor dies 122E, 122G, and 122H. According to some embodiments, a planarization process, e.g., CMP, grinding, etching (dry and / or wet), or another preferred etching operation is carried out to remove excess potting material 252 and produce a uniform top surface of the potting material 252 (see Figure 6B).

[0086] Figure 6C shows the formation of multiple via holes 252R in the potting material 252. The holes may be formed by laser ablation. Alternatively, if a thick-film photoresist is used as a encapsulant, it can be laminated, patterned, and developed to form holes extending from the top surface of the potting material 252 to bonding pads with proper surface finish of the semiconductor dies 122E, 122G, and 122H, exposing the pads below the via holes 252R.

[0087] Referring to Figure 6D, a conductive material with appropriate passivation is deposited in the via hole 252R by, for example, PVD, CVD, ALD, plating, etc. The conductive material may include at least one of tungsten, copper, titanium, molybdenum, cobalt, ruthenium, tantalum, aluminum, silver, gold, and other suitable materials. Thus, one or more conductive pillars 224 are formed on the semiconductor die 122G and electrically connected to it. At least one conductive pillar 224 formed on the secondary plane 600AS2 of the semiconductor device 600W (at this point, such a secondary plane 600AS2 is still a virtual plane before the dicing process) is configured as an edge conductive pillar 224. Furthermore, one or more conductive plugs 234 are formed on the TSV die 122E and / or semiconductor die 122H and electrically connected to them. As a result, the body of the IC structure 600A includes semiconductor dies 122E, 122H, and 122G, a primary RDL 108A, a junction layer 160, a potting material 252, a conductive via 104, an internal conductive pillar 224, a conductive plug 234, and an edge conductive pillar 224. According to some embodiments, the TSV 104, the conductive pillar 224, and the conductive plug 334 are substantially the same in length or different.

[0088] Another primary RDL108C is formed on the upper surface of the potting material 252 and electrically connected to the semiconductor dies 122E, 122G, and 122H. According to some embodiments, the primary RDL108C includes at least an edge conductive pad 212 on the secondary plane 600AS1 or 600AS2 of the semiconductor wafer 600W (at present, the secondary planes 600AS1 and 600AS2 are still virtual planes before the dicing process).

[0089] Subsequently, following wafer mounting, the carrier substrate 106 is removed or separated from the semiconductor device 600W by removing or peeling the delamination layer 110 from the semiconductor device 600W. Figure 6E shows individual IC structures 600A formed using a dicing or dicing process to separate the semiconductor device 600W into individual IC structures 600A. By appropriate arrangement, edge conductive pads 212, edge TSV 104B, and edge conductive pillars 224 may be formed and exposed through at least one of the secondary planes 600AS1 and 600AS2 of the IC structure 600A. The primary RDL 108C is configured to be electrically connected to the semiconductor dies 122E, 122G, and 122H through internal interconnection structures 108X, e.g., conductive plugs 234 and internal conductive copper pillars 224. Furthermore, the primary RDL108C is configured to be electrically connected to semiconductor dies 122E, 122G, and 122H via edge interconnection structures 118X, such as edge TSV104 and edge conductive pillars 224. Thus, the routing distance can be reduced with the help of the edge interconnection structures 118X.

[0090] Referring to Figures 6E and 5A and 5B, according to several embodiments, the secondary RDLs 118A and 118B of IC structures 500A and 500B are applicable to IC structure 600A. In other words, although not shown separately, the secondary RDLs 118A or 118B may be placed on secondary surfaces 600AS1 and 600AS2, respectively, so as to be electrically connected to the conductive element 202, edge TSV 104 (in Figure 6E, 104 is used instead of 104B to match Figure 6D), and / or edge conductive pillar 224 of the primary RDL 108C. According to several embodiments in which IC structure 600A includes an edge conductive plug 234, the secondary RDLs 118A or 118B can be electrically connected to such an edge conductive plug 234.

[0091] The embodiments of the present disclosure described above offer advantages. The aggregate edge conductive element 202 can be seen in the form of an edge conductive pad 212, an edge conductive via 214, an edge TSV 104, or an edge TMV 224, as shown in Figure 6E. Furthermore, primary RDLs 108A and 108C, or secondary RDLs 118A and 118B (see Figure 5B) may be formed with or without the edge conductive pad 212, with or without the edge conductive via 214, with or without the edge TSV 104, with or without the edge conductive via 222 (see Figures 2F and 3F), with or without the edge TMV 232 (Figure 5B), with or without the edge conductive pillar 224, and with or without the edge conductive plug 234. The edge conductive element 202 can be positioned around the IC structure or around the RDL. Furthermore, the edge conductive via 222 can cover all or part of the thickness of the body of each IC structure. Furthermore, the edge TSV104, edge TMV232, edge conductive pillar 224, and edge conductive plug 234 appear inside the IC structure, facilitating internal interconnection of the IC structure in different stack layers, in addition to the edge interconnections located on the sides.

[0092] The conductive pillars 224, conductive plugs 234, and TMV 232 (Figure 5B) are formed based on drilling and hole-filling process steps, and they can be fabricated by several methods, including a bonding vertical wire (e.g., palladium, Pd, coated Cu) approach, a laser via approach, and a photosensitive thick film through-film (TPTF) approach. In the bonding vertical wire approach, the wire bonding follows a high copper pillar process step, and the wire bonding replaces the high copper pillar formation step. When using Pd-coated Cu wire, thin gold (Au) can be used as a bonding pad. In the laser via approach, the IC is first bonded to the carrier substrate 106, followed by, for example, overmolding, planarization, laser via hole opening, via hole sidewall Cu plating, via hole plating, or plugging with photosensitive polymer or solder, planarization, RDL fabrication, carrier delamination, and dicing. The TPTF process flow consists of sequentially laminating thick photosensitive films onto bonded ICs, multiple or single exposures and development to generate TMV holes (i.e., photosensitive thick-film through-via holes), barrier / seed layer deposition, Cu plating, via hole plug formation as needed, back grinding / planarization, RDL generation, carrier delamination, and dicing. The ICs here may have RDLs and TSVs. Multiple exposures increase process flexibility for forming vias of different sizes and depths. The TMV-related processes can accommodate multiple ICs in both the xy plane and the vertical z direction, as shown in Figure 6E. Furthermore, the semiconductor dies 122E, 122H, and / or 122G in Figure 6E can be pre-bumped with solder bumps or copper pillar microbumps before bonding them to the carrier substrate 106 in Figure 6A. Die bonding is followed by overmolding, followed by planarization and RDL generation.

[0093] Figures 7A to 7H show cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 700A according to various embodiments of the present disclosure. According to some embodiments, the semiconductor package 700A shown in Figure 7H is a semiconductor package device. The semiconductor package 700A may be formed from semiconductor devices 700W and 701W, which are wafer-level devices, and the semiconductor package 700A is formed by separating the semiconductor device 701W using a dicing or dicing process.

[0094] Figures 7A and 7C illustrate the formation of multiple tall IC stacks 322 from multiple IC structures 142. Referring to Figure 7A, a carrier substrate or support substrate 106 is provided or received. A release layer 110 is formed on the upper surface of the carrier substrate 106. A pick-and-place process is performed to pick up and bond multiple known good IC structures 142, e.g., IC structure 142A, with the help of a bonding layer, to form the first tier of a short IC stack 312, as shown in Figure 7A, on the release layer 110 at a pitch suitable for improving yield. According to some embodiments, the IC structures 142 may consist of IC structures 400A, 400B, 400C, 400D, 400E, 400F, 400G, 400H, 500A, 500B, and / or 600A. However, other types of IC structures are also possible, such as IC structures 100A, 100B, 100C, 300A, 300B, 300C, etc. As illustrated in Figure 7B, IC structure 142 covering 142A, 142B, 142C, and 142D may include memory and / or processor analog dies. IC structure 142 may also cover MEMS devices, passive and analog, mixed-signal, and digital signal processing ICs.

[0095] Referring to Figure 7B, several other IC structures 142, for example IC structure 142B, are bonded to the corresponding IC structure 142A to form a second layer of the low IC stack 312. The bonding of IC structure 142B to IC structure 142A may be achieved using thermocompression bonding (TCB), flip-chip bonding, hybrid bonding, direct bonding, bonding via an adhesive layer (e.g., Ti / Au), a die attachment film or paste, or other suitable bonding process. The process of forming the low IC stack 312 can continue until a predetermined number of tiers (total number of tiers) K is reached, where the number of tiers K is a natural number. In the example shown in Figure 7B, the number of tiers K is 4. This means that each low IC stack 312 is constructed from four stacked IC structures 142A, 142B, 142C, and 142D. This process produces a known good low IC stack. Alternatively, the low IC stack 312 can be formed by bonding multiple 142Ds to multiple 142Cs, the resulting structure is further processed as needed, then peeled off, known good structure is picked up, and the known good structure is bonded to multiple known good 142Bs, etc., and the process is repeated until the low IC stack 312 is formed as shown in Figure 7B.

[0096] After the first low IC stack 312 is completed, a release (or bonding) layer 140 of appropriate thickness is formed on top of each low IC stack 312. The material of the release layer 140 may be different from the material of the release layer 110 so as not to interfere with each other in their respective release processes. Subsequently, another set of known good low IC stacks 312 is formed on top of the release layer 140 of the first known good low IC stack 312. As shown in Figure 7B, the formation of the low IC stacks 312 and the release layer 140 proceed alternately until a predetermined number L of low IC stacks are achieved, forming the high IC stack 322 shown in Figure 7C, where the number of low IC stacks L (total number of low IC stacks) is a natural number. In the illustrated example, the number of low IC stacks L is 4. As a result, the low IC stacks 312 are stacked to form the high IC stack 322 that penetrates the release layer 140.

[0097] Referring to Figure 7C, each high IC stack 322 is detached from the carrier substrate 106 by peeling off the release layer 110. As a result, four low IC stacks 312 are arranged alternately with three release layers 140 to form rows of high IC stacks 322. In the illustrated example, the semiconductor device 700W has three rows of high IC stacks 322. The numbers K, L, and number of rows introduced above are for illustrative purposes only. Other numbers are also within the scope intended of this disclosure.

[0098] Figures 7D to 7H illustrate the formation of a semiconductor package 700A from multiple high IC stacks 322. Referring to Figure 7D, a carrier substrate 116 is provided or received. A release layer 120 is formed on the top surface of the carrier substrate 116. A pick-and-place process is performed to pick up and bond multiple known good high IC stacks 322 and place them on the release layer 120 at a pitch suitable for improving yield. The high IC stacks 322 are reconfigured on the carrier substrate 116 and bonded to the release layer 120 via their sides. In other words, the high IC stacks 322 are laid down such that the vertical stacked IC structures 142 within the high IC stacks 322 are positioned upright in the xy plane or in the length and width direction of the IC, with one of their four sides bonded to the release layer 120.

[0099] Referring to Figure 7E, the reconfigured high IC stack 322 of the semiconductor device 701W is formed or encapsulated using potting material 262. The material and composition of potting material 262 are the same as those of potting material 242 or 252. A forming or deposition process is performed to deposit the potting material 262 between the stacked high IC stacks 322. According to some embodiments, a planarization process, e.g., CMP, grinding, etching (dry and / or wet), or another preferred etching operation is performed to remove excess potting material 262 and to planarize the top surface of the potting material 262 so that it is coplanar with the side surface of the high IC stack 322. Subsequently, an edge interconnect structure RDL118A is formed on or bonded to at least the edge interconnects on the side surface (secondary plane) of the high IC stack 322.

[0100] Figure 7F shows the formation of another edge interconnect structure RDL118B on another side of the high IC stack 322 opposite the secondary RDL118A. Another carrier substrate 126 is provided or received within another semiconductor device 702W. Another delamination layer 130 is formed on the carrier substrate 126 to facilitate the formation of 118B. The materials, configurations, and methods for forming the carrier substrate 126 and the secondary RDL118A and 118B are the same as those for the secondary RDL108A and 108B described in Figure 5B and the primary RDL108A and 108B described in Figure 2C, and therefore, details of such similar features are not repeated for brevity. The material of the delamination layer 130 may differ from the material of the delamination layer 120 so as not to interfere with each other in their respective delamination processes. Next, after the semiconductor structure 701W shown in Figure 7E is bonded to the second carrier 126 on the RDL 118A side, the carrier substrate 116 is removed from the semiconductor device 701W by removing the delamination layer 120. The edge interconnection RDL structure 118B is formed or bonded to the lower secondary surface of the high IC stack 322, opposite to the upper secondary surface of the high IC stack 322.

[0101] Referring to Figure 7G, the fragmentation or dicing process is performed to separate the semiconductor device 701W into a high IC stack structure 700L. The fragmentation or dicing process may be performed to cut the semiconductor device 701W at the location of the potting material 262, which has been cleaned by, for example, dry and / or wet etching, while taking care to keep each high IC stack 322 intact during the dicing process. According to some embodiments, a wet etching or cleaning process is performed to remove any residual potting material 262 remaining on the high IC stack structure 700L.

[0102] Figure 7H shows that individual semiconductor packages 700A, i.e., low IC stack structures, are formed from their respective IC structures, i.e., high IC stack structures 700L. Delamination, fragmentation, and / or dicing processes are performed to separate the delamination layer 140 (Figure 7B) from each of the high IC stack structures 700L so that each low IC stack 312, i.e., each containing edge interconnect RDL structures 118A and 118B, is separated from one another. According to some embodiments, etching or dicing processes are performed to penetrate and cut the secondary RDLs 118A and 118B at the location of the delamination layer 140, for example, by dicing, continuous wave laser beam, dry etching (e.g., by plasma), and / or wet etching to assist the delamination process. As shown in Figure 7H, the semiconductor package 700A includes a stack of low IC stack structures 142 and two secondary RDLs 118A and 118B located on two sides of the low IC stack 142. Secondary RDL118A and 118B can help increase the routing area of ​​the IC structure 142, shorten the routing distance, and improve the routing capacity and design flexibility of the semiconductor package 700A.

[0103] Figures 7I and 7J show cross-sectional views of semiconductor packages 700B and 700C according to various embodiments of the present disclosure. Semiconductor packages 700B and 700C can be seen as detailed versions of semiconductor package 700A with some minor modifications. Referring to Figure 7I, semiconductor package 700B includes three IC structures 142A, 142B, and 142C in a vertical stack, each IC structure 142A, 142B, or 142C comprising its respective body and its apex having its respective primary RDL 108A, 108B, or 108C positioned on its respective upper primary surface 142AP, 142BP, or 142CP. The body of IC structure 142A consists of a semiconductor die 143A, an edge TMV 232, an edge TSV 104, and a potting material 242, and the semiconductor die 143A includes a plurality of TSVs 104 and a plurality of TMVs 232. Furthermore, the body of IC structure 142B consists of a semiconductor die 143B, an edge TMV 232, and a potting material 242, with the semiconductor die 143B containing multiple TSVs 104 and multiple TMVs 232. Similarly, the body of IC structure 142C consists of a semiconductor die 143C, an edge TMV 232, and a potting material 242, with the semiconductor die 143C containing multiple TSVs 104 and multiple TMVs 232. IC structures 142A, 142B, and 142C can be of different sizes and can include a wide variety of combinations of internal interconnects and edge interconnects covering the TSVs and TMVs. According to some embodiments, the semiconductor die, 143A, 143B, or 143C may be at least one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, memory die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die (e.g., an interconnect die such as an interposer). According to some embodiments, the semiconductor package 700B includes only a single secondary RDL118A located on the left secondary plane 700BS of the semiconductor package 700B.

[0104] According to some embodiments, IC structures 142A, 142B, and 142C are characterized by substantially equal or unequal thicknesses T1, T2, and T3, respectively. Each IC structure 142A, 142B, or 142C may include a thickness in the range of about 30 μm to about 775 μm.

[0105] The secondary RDL118A includes a front interconnect surface 118F and a rear interconnect surface 118R opposite the front interconnect surface 118F. The secondary RDL118A is electrically connected to the secondary plane 700BS through the front interconnect surface 118F to support routing efficiency and flexibility. For example, the secondary RDL118A includes a conductive trace or wire 172 that extends along the longitudinal axis of the secondary RDL118A and electrically connects the edge conductive pad 212 of the primary RDL108C to the edge TSV104B of the semiconductor dies 143C and 143A, while bypassing the bodies of the IC structures 142A, 142B, and 142C. Furthermore, the secondary RDL118A can be used to connect other circuits through the rear interconnect surface 118R. For example, the secondary RDL118A includes one or more conductive bumps, microbumps, or bump pad arrays 244 (all referred to as external connections of the secondary RDL118A) on the rear interconnect surface 118R, and the conductive bumps 244 are configured to electrically connect the secondary RDL118A to a circuit or layer adjacent to the secondary RDL118A.

[0106] Referring to Figure 7J, the semiconductor package 700C is similar to the semiconductor package 700B in many embodiments, and a description of such similar features will not be repeated for brevity. According to some embodiments, the semiconductor package 700C includes three IC structures 142D, 142E, and 142F in a stack, each IC structure 142D, 142E, or 142F comprising its respective body and two respective primary RDLs 108A / 108D, 108B / 108E, and 108C / 108F arranged on their respective upper and lower primary surfaces 142AP, 142BP, and 142CP.

[0107] The semiconductor package 700C further differs from the semiconductor package 700B in that, in the case of 700C, the secondary RDL 118A, which is located on the secondary plane 700CS1 of the semiconductor package 700C, includes an array of conductive pads 254 on the rear interconnect surface 118R of the secondary RDL 118A. According to some embodiments, the conductive pads 254 have an upper surface that is coplanar with the rear interconnect surface 118R of the secondary RDL 118A. The coplanar arrangement of the secondary RDL 118A in this manner helps to perform hybrid bonding with other circuits or layers. Furthermore, in contrast to the semiconductor package 700B, the semiconductor package 700C further includes another secondary RDL 118B located on the secondary plane 700CS2. The interconnect configuration in the secondary RDL 118B may be similar to or different from the interconnect configuration in the secondary RDL 118A. The secondary RDL118B may include external connections such as microbumps, hybrid adhesive layers, direct adhesive layers, flexible circuit connectors (see Figure 9A for details, described later), and combinations thereof. Furthermore, the secondary RDLL118A (or 118B) includes conductive traces or wires 172 that extend along the longitudinal axis of the secondary RDLL118A and bypass the bodies of the IC structures 142D, 142E, and 142F, electrically connecting the edge conductive pads 212 of the primary RDL108C and 108B with the edge conductive vias 214 of the primary RDL108D, thereby enabling skip die and multi-side power supply and signaling.

[0108] According to some embodiments, IC structures 142D, 142E, and 142F have substantially equal or unequal thicknesses T4, T5, and T6, respectively. Each IC structure 142D, 142E, or 142F may include a thickness in the range of about 30 μm to about 775 μm.

[0109] The semiconductor packages 700A, 700B, and 700C enable skip die and multi-side power supply and signaling through an internal interconnect structure 108X covering the TMV, primary RDL108, and TSV; skip die and multi-side power supply and signaling through an edge interconnect structure 118X covering the secondary RDL118 and edge interconnects; and skip die and multi-side power supply and signaling through both the internal interconnect structure 108X and the edge interconnect structure 118X. These semiconductor packages with multi-side power supply and signaling enable the achievement of "PPAC optimization per cubic millimeter" for 3D ICs (exemplified herein by low IC stacks), and the vertical dimensions of the 3D IC can be expanded to cover the IC, interposer, IC package substrate, IC package, and system PCB (see, for example, Figures 7I, 7J, 12C, 13C, 14A, and 14B).

[0110] Figures 8A to 8E show cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 800A according to various embodiments of the present disclosure. The steps shown in Figures 8A to 8E are similar in many embodiments to the steps shown in Figures 7D to 7H, and such similar features will not be repeated for brevity. The main difference between the steps shown in Figures 8A to 8E and those shown in Figures 7D to 7H is that the edge interconnect RDL structures 118A and 118B in Figures 7D to 7H are replaced by edge interconnect RDL structures 138A and 138B formed by bonding flexible printed circuit (Flex) to the sides of the low IC stack and high IC stack. The Flex may be formed from a plurality of conductive wire layers (not shown separately), each conductive wire layer comprising a conductive wire and an IMD layer material for electrically insulating the conductive wire, such as polyimide or benzocyclobutene (BCB). Flex may further include a bonding pad (not shown separately) formed from gold, solder, or other suitable bonding material. Because Flex is flexible and has the advantage of having a high-density fine-pitch bonding pad (having a pitch of up to about 10 μm), Flex is suitable for secondary RDL 138A and 138B for edge interconnection structure 118X.

[0111] Figure 9A shows cross-sectional views of the structure at different stages of a method for manufacturing a semiconductor package 900A according to various embodiments of the present disclosure. A cross-sectional view of the semiconductor device 900W is a detail view of the semiconductor device 802W shown in Figure 8C. In Figure 9A, it can be seen that the semiconductor device 900W includes two connection layers 150, for example, a first connection layer 150A located between the molded high IC stack 322 and the edge interconnect structure 118A, and a second connection layer 150B located between the molded high IC stack 322 and the edge interconnect structure 118B. According to some embodiments, the connection layer 150A or 150B may include an array of flexible circuit connectors 154 and a non-conductive filler 152 enclosing the flexible circuit connectors 154. The flexible circuit connectors 154 are bonded to the secondary plane 900AS of the low IC stack 312 (Figure 9B). The flexible circuit connector 154 may contain a conductive material such as copper, tin, or gold, or another conductive material suitable for bonding. The non-conductive filler 152 may be a encapsulant such as a non-conductive adhesive (NCA), a non-conductive film, or a non-conductive paste (NCP), or an encapsulant used for chip-on-film (CoF) packaging of driver ICs for display applications. The encapsulant or non-conductive filler 152 may fill the spaces between the flexible circuit connectors 154 and between the secondary plane 900AS and the respective connection layers 150A and 150B. Referring to Figure 9B, after the dicing or dicing process, individual low IC stack structures 900A are formed from semiconductor devices 900W.

[0112] Flex, based on polyimide dielectrics with multiple, for example, two, metal (copper, Cu) layers, can be a suitable interconnection solution for high-speed applications. Because Flex is also mechanically formable and flexible, it can be used to interconnect metal pads on multiple sides, not just one side. Flex can provide high-density interconnection (with pitches up to 20 μm, and even down to 10 μm), DC power distribution, integrated I / O (input and output), power distribution, decoupling, and electromagnetic compatibility. In addition to all the above desirable attributes, Flex (especially adhesive-free Flex) is an ideal candidate for 3D IC edge interconnects covering one or more sides, as it can be tested against known good products before bonding. For example, considering chip-on-film (COF) bonding for liquid crystal display applications, adhesive-free Flex with Cu leads (which can be pre-plated with tin, Sn) can be bonded using thermocompression bonding (TCB) to gold bumps, Sn bumps, or tin / copper (Sn / Cu) bumps on glass for applications such as mobile devices. Solvent-free epoxy underfills can be applied after bonding to avoid bubbles that may be associated with solvent-based underfills if not properly baked. Alternatively, a non-conductive adhesive (NCA) or non-conductive paste (NCP) may be applied before bonding to the glass in a manner similar to that of fine-pitch flip-chip microbump assemblies, followed by TCB. For edge interconnection of low 3D IC structure stacks using Flex, bumps can first be created on edge pads, edge vias, edge TSVs, and / or edge TMVs, and then Flex can be bonded to the bumps on one or more sides using thermocompression bonding and NCA. Circuits can be pre-baked before Flex bonding to ensure that delamination does not occur. Flex can also be used to interconnect metal pads and RDLs on different sides of low 3D IC structure stacks. Metal pads on bonded Flex located on different sides can be interconnected using Flex with leads / pads containing palladium (Pd) passivation for Flex-to-Flex bonding at low temperatures, such as 140°C.

[0113] Figures 10A to 10H show cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 1000A according to various embodiments of the present disclosure. The steps shown in Figures 10A to 10H are similar in many embodiments to the steps shown in Figures 7D to 7H, and such similar features will not be repeated for brevity. Referring to Figure 10A, a semiconductor device 1001W is provided. The semiconductor device 1001W includes a carrier substrate 106 and a delamination layer 110 on the carrier substrate 106. A plurality of high IC stacks 422 are prepared and arranged on the delamination layer 110. The high IC stacks 422 are formed in the same manner as described in the steps with reference to Figures 7A to 7C. In other words, each high IC stack 422 includes a plurality of low IC stacks 1000A (see Figure 10H) arranged alternately with a plurality of delamination layers 140 (see Figure 10G). Furthermore, each low IC stack 1000A includes multiple IC structures 162 (for example, IC structures 162A, 162B, 162C, and 162D shown in Figure 10H). The main difference between IC structures 162 and IC structures 142 in Figures 7D to 7H is that IC structures 162 include edge conductive pads 282, for example, edge conductive pads 282A and 282B (Figure 10B), which are located on two sides of each IC structure 162. The edge conductive pads 282A and 282B may be arranged on each IC structure 162 in a manner similar to the structure of edge TSV 104B, edge conductive via 214, or edge conductive pad 212 in IC structure 100A (Figure 2D), or edge TMV 232 in IC structure 300C (Figure 3F).

[0114] Referring to Figure 10B, the semiconductor device 1001W, i.e., the high IC stack 422, is formed or encapsulated and planarized using a potting material 262, similar to that shown in Figure 7E. Referring to Figure 10C, another carrier substrate 126 is provided within the semiconductor device 1002W, and another delamination layer or sacrificial layer 120 is formed on the carrier substrate 126. A secondary RDL 148A is formed on the delamination layer or sacrificial layer 120, and the secondary RDL 148A includes an array of conductive pads 264 on its upper surface. According to some embodiments, the semiconductor device 1001W is bonded to the RDL 148A supported by the carrier substrate 126 to form the semiconductor device 1002W through a hybrid or flip-chip bonding process. The semiconductor device 1001W may include a metallic surface of conductive pads 282A and a bonding surface formed of a dielectric surface substantially similar to or different from the dielectric surface of the secondary RDL 148A. Similarly, the secondary RDL148A includes a junction surface formed by the metallic surface of the matched conductive pad 264 and the dielectric surface of the IMD layer of the secondary RDL148A. The hybrid junction is performed to form a metal-metal junction and a dielectric-dielectric junction at the interface of the junction surface between the semiconductor device 1001W and the secondary RDL148A.

[0115] Referring to Figure 10D, the carrier substrate 126 is removed or separated from the semiconductor device 1002W by peeling off the release layer 120. According to some embodiments, referring to Figure 10C, the carrier substrate 126 includes a plurality of holes 124 extending through the thickness of the carrier substrate 126. The holes 124 facilitate the peeling of the carrier substrate 126 from the semiconductor device 1002W by wet chemical treatment.

[0116] The release layer or sacrificial layer 120 in Figure 10C can be made from a mixture of metals and nonmetals. In this case, candidate metals may include nickel (Ni), chromium (Cr), titanium (Ti), copper (Cu), manganese (Mn), iron (Fe), cobalt (Co), tungsten (W), molybdenum (Mo), and tantalum (Ta), while candidate nonmetals may include metal oxides, phosphates, and chromates. Preferred mixtures include chromium and chromium oxide, and nickel and nickel oxide. Deposition methods include vapor deposition, sputtering, electroplating, and dipping. Many types of sacrificial layers used in MEMS processing can also be considered (metallic materials such as Cu, Al (aluminum), Ti, and Cr, nonmetallic materials such as silicon dioxide and polysilicon, and polymers such as poly(methyl methacrylate), polyimide, and photoresist (including photosensitive polyimide)). The release layer can be very thin, for example, less than 0.3 μm thick. Chromium oxide (Cr2O3) possesses many desirable properties as a sacrificial layer, can be sputter-deposited to form stress-controlled films several hundred nanometers thick, adheres well to both dielectric and metal surfaces, is resistant to most acids and bases, etches rapidly in standard chromium etching solutions, and has minimal tendency to react with other commonly used materials even at high temperatures. To facilitate subsequent etching removal, through-holes can be formed in the substrate to expose the release layer, accelerating the removal of wet chemicals.

[0117] Figure 10E shows the formation of the secondary RDL148B. Another carrier substrate 136 having holes 134 is provided within the semiconductor device 1003W, and another delamination layer or sacrificial layer 130 is formed on the carrier substrate 136. The secondary RDL148B is formed on the delamination layer 130, and the secondary RDL148B includes an array of conductive pads 274 on the upper surface of the secondary RDL148B. The semiconductor device 1002W is bonded to the carrier substrate 136 using the delamination layer 130, as in the case of 1001W, and after the carrier substrate 106 is delaminated, it is bonded to the semiconductor device 1003W via a hybrid bonding process, supported by the carrier substrate 116 by wafer-level bonding. The semiconductor device 1003W includes a bonding surface formed by a metallic surface of conductive pads 282B and a dielectric surface substantially similar to or different from the dielectric surface of the secondary RDL148B. Similarly, the secondary RDL148B includes a junction surface formed by the metallic surface of the conductive pad 274 and the matched dielectric surface of the IMD layer of the secondary RDL148B. Hybrid junctions are performed to form metal-metal and dielectric-dielectric junctions at the interface of the junction surface between the semiconductor device 1003W and the secondary RDL148B. Following the junction, the carrier substrate 136 is peeled off from the semiconductor structure 1003W (see Figure 10F), the semiconductor structure 1003W is wafer-mounted, and the carrier substrate 136 is removed, leaving the semiconductor structure 1003W mounted on a wafer-mounting frame ready for dicing or splitting from the semiconductor device 1003W, as shown in Figure 10F.

[0118] Referring to Figure 10G, a dicing or fragmentation process is then performed to separate the semiconductor device 1003W into individual IC structures 1000L, i.e., high IC stacks. A dicing or fragmentation process including dicing, laser ablation, plasma etching, dry etching, wet etching (e.g., acid etching), wet cleaning, or a combination thereof may be performed to cut the semiconductor device 1003W at the location of the potting material 262 and free the high IC stack 422 (Figure 10G) from the semiconductor structure 1003W (Figure 10F). Secondary RDLs 148A and 148B may be formed so as not to be present in the delamination layer 140 on the dicing or fragmentation street between adjacent low IC stacks in order to facilitate fragmentation.

[0119] Figure 10H shows the formation of individual semiconductor packages 1000A, i.e., low IC stacks, from each IC structure 1000L. The delamination process is performed to remove the delamination layer 140 from each of the IC structures 1000L so that the semiconductor packages 1000A, i.e., low IC stacks 332 including secondary RDLs 148A and 148B, are separated from one another. According to some embodiments, a dicing or parsing process including laser irradiation, thermomechanical shearing, dicing, laser ablation, plasma etching, dry etching, wet etching (e.g., acid etching), wet cleaning, or a combination thereof is performed to assist the delamination process by cutting the secondary RDLs 148A and 148B at the location of the delamination layer 140. The secondary RDLs may be formed so as not to be present in the delamination layer 140 on the dicing street between adjacent low IC stacks in order to facilitate parsing. As shown in Figure 10H, the semiconductor package 1000A includes a stack of IC structures 162 and two secondary RDLs 148A and 148B positioned on two sides of the stack of IC structures 162. The secondary RDLs 148A and 148B can help increase the routing area of ​​the IC structures 162, shorten the routing distance, and improve the routing capacity and flexibility of the semiconductor package 1000A.

[0120] Figure 11A shows a cross-sectional view of a semiconductor package 1100A according to various embodiments of the present disclosure. The semiconductor package 1100A is similar to the semiconductor package 1000A in many embodiments, and such similar features will not be repeated for brevity. The semiconductor package 1100A includes IC structures 162A, 162B, 162C and 162D and secondary RDLs 148A and 148B. The semiconductor package 1100A further includes a first junction layer 322L1 and a second junction layer 322L2, respectively, which are arranged on two opposing secondary planes 1100AS1 and 1100AS2 to perform edge interconnection. The first junction layer 322L1 includes a first junction surface on the secondary plane 1100AS1. The second junction layer 322L2 includes a second junction surface on the secondary plane 1100AS2. The secondary RDL148A faces the secondary plane 1100AS1 and includes a first bonding layer 148L1 configured to bond to the first bonding layer 322L1. Similarly, the secondary RDL148B faces the secondary plane 1100AS2 and includes a second bonding layer 148L2 configured to bond to the second bonding layer 322L2.

[0121] According to some embodiments, a first bonding layer 322L1 is bonded to a first bonding layer 148L1 via a hybrid bonding. The first bonding layer 322L1 includes a bonding surface formed by the metallic surface of the conductive pad 282A and the dielectric material of the first bonding layer 322L1, for example, the dielectric surface of the IMD layer within the first bonding layer 322L1. Similarly, the secondary RDL 148A includes a first bonding surface formed by the metallic surface of the conductive pad 264 and the dielectric surface of the IMD layer of the secondary RDL 148A. Hybrid bonding is performed to form a metal-metal bonding and a dielectric-dielectric (e.g., oxide-oxide or polyimide-polyimide) bonding at the interface of the first bonding surfaces of the first bonding layer 322L1 and the first bonding layer 148L1. In scenarios in which hybrid bonding is employed, the first bonding layers 322L1 and 148L1 are referred to herein as hybrid bonding layers.

[0122] Similarly, according to some embodiments, a second bonding layer 322L2 is bonded to a second bonding layer 148L2 via a hybrid bonding. The second bonding layer 322L2 includes a second bonding surface formed by the metallic surface of the conductive pad 282B and the dielectric material of the second bonding layer 322L2, for example, the dielectric surface of the IMD layer within the second bonding layer 322L2. Similarly, the secondary RDL 148B includes a second bonding surface formed by the metallic surface of the conductive pad 274 and the dielectric surface of the IMD layer of the secondary RDL 148B. Hybrid bonding is performed to form a metal-metal bonding and a dielectric-dielectric (e.g., oxide-oxide or polyimide-polyimide) bonding at the interface of the second bonding surfaces of the second bonding layer 322L2 and the second bonding layer 148L2. In scenarios in which hybrid bonding is employed, the second bonding layers 322L2 and 148L2 are referred to herein as hybrid bonding layers.

[0123] According to some embodiments, the first bonding layer 322L1 includes an array of microbumps 282A protruding from the bonding surface of the first bonding layer 322L1, and the first bonding layer 148L1 includes bonding pads (or microbumps) 264 or an array of bonding pads protruding from the first bonding surface of the first bonding layer 148L1, wherein the bonding pads match those of the microbumps 282A. The first bonding layer 322L1 is flip-chip bonded to the first bonding layer 148L1. An underfill material, such as an epoxy material, a non-conductive paste, or a non-conductive film, may be distributed between the first bonding layers 322L1 and 148L1 to fill the space between the microbumps 282A and the bonding pads 264. Similarly, according to some embodiments, the second bonding layer 322L2 includes an array of microbumps 282B protruding from the second bonding surface of the second bonding layer 322L2, and the second bonding layer 148L2 includes an array of bonding pads (or microbumps) 274 corresponding to the microbumps 282B. The second bonding layer 322L2 is flip-chip bonded with the second bonding layer 148L2. An underfill material, such as an epoxy material, a non-conductive paste, or a non-conductive film, may be distributed between the second bonding layer 322L2 and 148L2 to fill the space between the microbumps 282B and the bonding pads 274. In scenarios where flip-chip bonding is employed, the first bonding layers 322L1, 148L1 and the second bonding layers 322L2, 148L2 are referred to herein as flip-chip bonding layers.

[0124] According to some embodiments, at least one of the secondary RDLs 148A and 148B includes a third bonding layer 148L3 on a third bonding surface 148S1 opposite the secondary planes 1100AS1 and 1100AS2 or the aforementioned first / second bonding surface (Figure 11A shows only one third bonding layer 148L3 in the secondary RDL 148B). Depending on the application, the third bonding layer 148L3 may include conductive pads 284 or microbumps 284 on the third bonding surface 148S1 having a configuration similar to that of the first bonding layer 148L1 or the second bonding layer 148L2, and the third bonding layer 148L3 is configured for hybrid bonding, flip-chip bonding, or flex bonding to another circuit or device, as appropriate.

[0125] Figure 11B shows a cross-sectional view of a semiconductor package 1100B according to various embodiments of the present disclosure. The semiconductor package 1100B is similar to the semiconductor package 1100A in many embodiments, and such similar features will not be repeated for brevity. The main difference between the semiconductor package 1100B and the semiconductor package 1100A is that the semiconductor package 1100B has a fourth bonding layer 148L4 instead of the third bonding layer 148L3 of the semiconductor package 1100A. The fourth bonding layer 148L4 may be located on a secondary RDL 148A or 148B on a bonding surface 148S1, and the bonding pads protrude from the surface 148S1 on the opposite side of the secondary plane 1100BS1 or 1100BS2. Furthermore, the fourth bonding layer 148L4 includes an array of bond pads 286 located on the bonding surface 148S1 of the secondary RDL 148B. The bond pad array of the fourth bonding layer 148L4 may be used to perform flip-chip bonding or other preferred bonding processes with adjacent circuits or devices. The third bonding layer 148L3 or the fourth bonding layer 148L4 may be referred to as a hybrid bonding layer or a flip-chip bonding layer, depending on the bonding scenario.

[0126] Figures 12A to 12C show cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 1200A according to various embodiments of the present disclosure. Referring to Figure 12A, a carrier substrate 106 is provided for or received within a semiconductor device 1200W. A release layer 110 is formed on the upper surface of the carrier substrate 106. A pick-and-place process is performed to pick up and bond a plurality of known good IC structures 142, e.g., IC structure 142A, and position them at appropriate pitches in the first layer of each low IC stack 312 on the release layer 110. According to some embodiments, the IC structures 142 may be IC structures 500A, 500B, or 600A. However, other types of IC structures, e.g., IC structures 100A, 100B, 100C, 300A, 300B, 300C, etc., are also possible. Multiple other IC structures 142, for example IC structure 142B, are bonded to the corresponding IC structure 142A to form IC structures 142 in the second tier of each low IC stack 312. The bonding between IC structures 142A and 142B may be performed using flip-chip bonding, hybrid bonding, die attachment, or another preferred bonding process. The process of forming the low IC stack 312 can continue until a predetermined number of tiers K is reached, where K is a natural number. In the illustrated example, the number of tiers K is 4. This means that each low IC stack 312 contains four stacked IC structures 142A, 142B, 142C, and 142D.

[0127] Referring to Figure 12B, the semiconductor device 1200W is formed or encapsulated using potting material 242. The forming or deposition process is performed to deposit the potting material 242 during the low IC stack 312. According to some embodiments, a planarization process, e.g., CMP, grinding, etching (e.g., RIE and / or wet drying), and / or another preferred etching operation is performed to remove excess potting material 242 and to planarize the top surface of the potting material 242 so that it is level with the main surface of the low IC stack 312. Subsequently, an array of microbumps 302 is formed on the primary surface of the low IC stack 312 or upper die, e.g., IC structure 142D, which acts as part of the internal interconnection structure 108X of the low IC stack 312.

[0128] Referring to Figure 12C, the fragmentation or dicing process is performed to separate the semiconductor device 1200W into individual semiconductor packages 1200A. The fragmentation or dicing process may also be performed to cut the semiconductor device 1200W at the location of the potting material 242 while keeping each low IC stack 312 intact during the dicing process. According to some embodiments, a wet etching or cleaning process is performed to remove any residual potting material 242 left on the semiconductor package 1200A.

[0129] Figures 13A to 13C show cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 1300A according to various embodiments of the present disclosure. Referring to Figure 13A, a carrier substrate 106 is provided for or received within a semiconductor device 1300W. A release layer 110 is formed on the upper surface of the carrier substrate 106. Multiple low IC stacks 312 are prepared in separate processes, each of which comprises, for example, four stacked IC structures 142A, 142B, 142C, and 142D, and the low IC stacks 312 are formed through the aforementioned processes. The low IC stacks 312 are arranged on the release layer 110 at appropriate pitches. The main difference between the steps for manufacturing the semiconductor package 1300A and the steps for manufacturing the semiconductor package 1200A is that the low IC stacks 312 shown in Figure 13A are arranged upright with one side exposed upwards in Figures 13A and 13B. In other words, the primary surfaces of the ICs in the low IC stack 312 face each other in the horizontal direction.

[0130] Referring to Figure 13B, the semiconductor device 1300W is molded or encapsulated using potting material 242 in a manner similar to that described with reference to Figure 12B. Subsequently, an array of microbumps 302 is formed on the side surface of the low IC stack 312 and functions as part of the edge interconnect structure 118X of the low IC stack 312.

[0131] Referring to Figure 13C, the fragmentation or dicing process is performed to separate the semiconductor device 1300W into individual semiconductor packages 1300A. The fragmentation or dicing process may also be performed to cut the semiconductor device 1300W at the location of the potting material 242 in order to free the low IC stack 312 from the potting material 242. According to some embodiments, a wet etching or cleaning process is performed to remove any residual potting material 242 left on the semiconductor packages 1300A.

[0132] Figure 13D shows a perspective view of the semiconductor package 1300A shown in Figure 13C, according to various embodiments of the present disclosure. The semiconductor package 1300A is an exemplary low IC stack structure having six sides, the six of which include an upper primary surface 312P1, a lower primary surface 312P2, and four sides 312S1, 312S2, 312S3, and 312S4 between the two primary surfaces 312P1 and 312P2. The semiconductor package 1300A further includes edge conductive elements 302, such as edge conductive pads, edge conductive vias, edge conductive bumps, microbumps, and / or hybrid junction pads, etc., dispersed on the sides of the four IC structures 142A, 142B, 142C, and 142D. The semiconductor package 1300A also includes edge conductive traces or wires 304 and 306. Conductive trace 304 may be configured to act as an adjacent die interconnect and may be used to interconnect edge conductive elements of adjacent IC structures 142, for example, IC structures 142B and 142C. Furthermore, conductive trace 306 may be configured as a skip die interconnect and may be used to interconnect edge conductive elements of non-adjacent IC structures 142, for example, IC structures 142A and 142C, while bypassing the body of IC structure 142B. Such a configuration allows the semiconductor package 1300A to offer shorter routing distances, higher wiring efficiency, and greater flexibility than existing semiconductor packages lacking edge wiring structures 118X.

[0133] Figure 14A shows a cross-sectional view of a semiconductor package assembly 1400A according to various embodiments of the present disclosure. The semiconductor package assembly 1400A includes a substrate 1410, a carrier 1420, a first semiconductor package 1430, and a second semiconductor package 1440, all of which are bonded to each other.

[0134] According to some embodiments, the carrier 1420 can be a silicon interposer or a laminated substrate, and the substrate 1410 can be a laminated substrate or a printed circuit board (PCB). The substrate 1410 may be formed from a first build-up layer 1412, a second build-up layer 1414, and a core layer 1416 sandwiched between the first build-up layer 1412 and the second build-up layer 1414. Each of the first build-up layer 1412 and the second build-up layer 1414 is formed from one or more conductive / dielectric layers containing copper or other suitable conductive materials. The conductive materials are insulated from each other by an insulating material, such as BT, ABF, polyimide, FR-4, etc. The core layer 1416 may be formed from one or more dielectric materials, such as glass, resin, etc. The core layer 1416 may be formed from a conductive material such as copper and may include plated through-holes 1418 configured to be electrically connected to the first build-up layer 1412 and the second build-up layer 1414. The semiconductor package assembly 1400A further includes an external electrical connection 1413 for connecting to a next level substrate (not shown). The external connection 1413 may be a microbump, solder bump, ball grid array ball, land grid array pad, or other suitable interconnect.

[0135] According to some embodiments, the carrier 1420 is the aforementioned IC structure, interposer, etc. The carrier 1420 may support a first semiconductor package 1430 and a second semiconductor package 1440, and may be configured to electrically connect the first semiconductor package 1430 to the second semiconductor package 1440, or to electrically connect the first semiconductor package 1430 and the second semiconductor package 1440 to the substrate 1410. According to some embodiments, the carrier 1420 includes a substrate 102 and a plurality of TSVs 104 within the substrate 102. The materials, configurations, and methods for forming the substrate 102 and TSVs 104 are similar to those described with reference to the IC structure 100A shown in Figure 2D or other suitable IC structures described above. The carrier 1420 further includes a first primary RDL 108A located on the upper side of the substrate 102 and a second primary RDL 108B located on the lower side of the substrate 102. The first primary RDL108A may be electrically connected to the secondary RDL108B via the TSV104. The first primary RDL108A includes an interconnect surface 1420S1 electrically bonded to the first semiconductor package 1430 and the second semiconductor package 1440. Similarly, the second primary RDL108B includes an interconnect surface 1420S2 electrically bonded to the substrate 1410. The semiconductor package assembly 1400A may include an external connection 1423 that electrically connects the substrate 1410 to the carrier 1420 via a flip-chip bonding process. The external connection 1423 may include microbumps, solder bumps, ball grid array balls, or other suitable connectors.

[0136] According to several embodiments, the structural configuration of the first semiconductor package 1430 is similar to the structural configurations of semiconductor packages 1300A, 700B, 700C, and 1100A, as shown in Figures 13C, 7I, 7J, and 11A, respectively. Therefore, for details of the first semiconductor package 1430, refer to the descriptions of these semiconductor packages. Referring to Figures 11A and 14A, the first semiconductor package 1430 includes a secondary RDL 118B formed on the lower secondary plane 1430S of the first semiconductor package 1430. Furthermore, as shown in Figure 14A, the secondary RDL 118B includes a front interconnect surface 118F facing the IC structures 143A, 143B, and 143C, and a rear interconnect surface 118R opposite the front interconnect surface 118F. The rear interconnect surface 118R is electrically joined to the interconnect surface 1420S1 of the carrier 1420. As a result, the first semiconductor package 1430 is bonded to the carrier 1420 via the edge wiring structure 118X of the first semiconductor package 1430. According to some embodiments, the rear interconnect surface 118R includes a first bonding pad array, and the interconnect surface 1420S1 includes a second bonding pad array corresponding to the first bonding pad array. The first bonding pad array and the second bonding pad array are bonded by flip-chip bonding, and a flip-chip assembly is formed together by performing the flip-chip bonding.

[0137] According to some embodiments, the structural configuration of the second semiconductor package 1440 is similar to that of the semiconductor packages 1200A and 700C shown in Figures 12C and 7J. Therefore, for details of the second semiconductor package 1440, refer to the semiconductor package 700C. Referring to Figures 7I and 14A, the second semiconductor package 1440 includes three bodies, including IC structures 144A, 144B, and 144C. The body of IC structure 144A includes an upper primary surface 144AP1 and a lower primary surface 144AP2 that coincides with the lower primary surface 1440P of the second semiconductor package 1440, so that the lower primary surface 1440P functions as the interconnection surface of the second semiconductor package 1440. The semiconductor package assembly 1400A further includes an external connection 1443 between the second semiconductor package 1440 and the carrier 1420, electrically connecting them. According to some embodiments, the external connection 1443 includes a microbump, a solder bump, or other suitable connector. The carrier 1420 is bonded to the second semiconductor package 1440 via a flip-chip bonding process through the interconnection surface of the first interconnection surface 1420S1 of the carrier 1420 and the interconnection surface of the lower primary surface 1440P of the second semiconductor package 1440. According to some embodiments, the interconnection surface of the lower primary surface 1440P includes a third bonding pad array, and the interconnection surface 1420S1 includes a second bonding pad array corresponding to the third bonding pad array. The second and third bonding pad arrays jointly form a flip-chip assembly by performing flip-chip bonding.

[0138] Figure 14B shows a cross-sectional view of a semiconductor package assembly 1400B according to various embodiments of the present disclosure. In many embodiments, the semiconductor package assembly 1400B is similar to the semiconductor package assembly 1400A, and such similar embodiments are not repeated for brevity. Referring to Figures 7J and 14B, the first semiconductor package 1430 includes a secondary RDL 118A bonded to the lower secondary plane 1430S of the first semiconductor package 1430. Furthermore, the secondary RDL 118A includes a front interconnect surface 118F facing the IC structures 143A, 143B, and 143C, and a rear interconnect surface 118R opposite the front interconnect surface 118F. The rear interconnect surface 118R is electrically bonded to the interconnect surface 1420S1 of the carrier 1420. As a result, the first semiconductor package 1430 is bonded to the carrier 1420 via the edge wiring structure 118X of the first semiconductor package 1430. According to some embodiments, the secondary RDL118A includes a first bonding layer 118L1 bonded to the first bonding layer of the first primary RDL108A by a hybrid bonding process. According to some embodiments, the rear interconnect surface 118R includes a first hybrid bonding layer, and the interconnect surface 1420S1 includes a second hybrid bonding layer corresponding to the first hybrid bonding layer for performing the hybrid bonding.

[0139] According to some embodiments, the structural configuration of the second semiconductor package 1440 shown in Figure 14B is similar to the structural configuration of the semiconductor package 700B shown in Figure 7I. Referring to Figures 7I and 14A, the second semiconductor package 1440 includes three bodies, including IC structures 144A, 144B, and 144C. The body of IC structure 144A includes an upper primary surface 144AP1 and a lower primary surface 144AP2 that coincides with the lower primary surface 1440P of the second semiconductor package 1440, so that the lower primary surface 1440P is the interconnection surface of the second semiconductor package 1440. IC structure 144A further includes an adhesive layer facing the carrier 1420, and the first primary RDL 108A further includes an adhesive layer facing the second semiconductor package 1440. The carrier 1420 is bonded to the second semiconductor package 1440 via a hybrid bonding process through the first interconnect surface 1420S1 and interconnect surface 1440P of the semiconductor package 1440. According to some embodiments, the interconnect surface of the lower primary surface 1440P includes a third hybrid bonding layer, and the interconnect surface 1420S1 includes a second hybrid bonding layer corresponding to the third hybrid bonding layer for performing the hybrid bonding.

[0140] The embodiments described above are illustrated using a 3D IC scenario as an example. However, the disclosure is not limited thereto. The methodologies, processes, and structures discussed herein can also be applied to other advanced in-package systems (SiPs) that employ fan-out, embedded SiP, silicon photonics, and combinations thereof, such as the embodiments shown in Figures 1A, 1B, 1C, 1D, 1E, and 1F, in which thickness-direction die stacking is employed.

[0141] According to some embodiments, IC structures 100A, 300A-300C, and 400A-400H can be based on a silicon substrate 102 or other types of substrates 102 such as SiC.

[0142] Referring to Figures 7A and 7B, according to some embodiments, the carrier substrate 106 can be a 12” wafer carrier or a larger panel carrier to increase carrier utilization. Referring to Figure 7B, the release layer 140 can also be a permanent bonding layer such as a die adhesion film (DAF) used in stacked die packaging (similar to the one used when bonding dies (IC structures 142A-142D) together) to form a low 3D IC stack 312, the film being pre-applied to the back of the dies 142A-142B while they are still in wafer form, and the die / film combo is picked up from the wafer tape for die bonding following a wafer saw.

[0143] Referring to Figure 7E, as previously mentioned, the reconfigured high IC stack 322 of the semiconductor device 701W is molded or encapsulated using potting material 262. The material and composition of potting material 262 are the same as those of potting material 242 or 252. A molding or deposition process is performed to deposit the potting material 262 between the tiled high IC stacks 322. According to some embodiments, an overmolding operation is performed to deposit the potting material 262. According to some embodiments, the potting material 262 may also be a permanent adhesive layer such as a molding compound or encapsulant. According to some embodiments, a planarization process, e.g., CMP, grinding, etching (dry and / or wet), or another preferred etching operation is performed to remove excess potting material 262 and to planarize the top surface of the potting material 262 so that it is coplanar with the sides of the high IC stack 322 that are planarized simultaneously with the potting material 262. Subsequently, the edge interconnect structure RDL118A is formed on or bonded to at least the edge interconnect on the side (second plane) of the high IC stack 322. According to some embodiments, a bump action is performed for the die edge interconnect, and a plurality of bonding pads are formed on one side of the high IC stack 322 or RDL118A to electrically connect the high IC stack 322 to the RDL118A.

[0144] Referring to Figure 7F, another carrier substrate 126 is provided or received within another semiconductor device 702W. Another release layer 130 is formed on the carrier substrate 126 to facilitate the formation of RDL118B. The semiconductor device 701W in Figure 7E is bonded to the RDL118A side of the second carrier 126. Subsequently, the carrier substrate 116 is peeled off from the semiconductor device 701W by peeling off the release layer 120. According to some embodiments, after the carrier substrate 116 is removed and before the RDL118B is formed, a planarization operation is performed on the exposed secondary surfaces of the high IC stack 322 and the potting material 262. The edge interconnect RDL structure 118B is formed or bonded to the lower secondary surface of the high IC stack 322, opposite the upper secondary surface of the high IC stack 322.

[0145] Referring to Figure 7G, the carrier substrate 126 is removed or separated from the semiconductor device 702W by peeling off the release layer 130. A flaking or dicing process is performed to separate the semiconductor device 702W into high IC stack structures 700L. The flaking or dicing process may be performed to cut open the semiconductor device 702W at the location of the potting material 262, which may even lack metal wiring and dielectric passivation, in order to facilitate clean separation of the etching or dicing operation by the potting material 262, which has been cleaned by, for example, dry etching and / or wet etching, while taking care to keep each high IC stack structure 700L intact during the dicing process. According to some embodiments, a wet etching or cleaning process is performed to remove any residual potting material 262 left on the high IC stack structure 700L. According to some embodiments, a planarization operation is performed on the exposed primary surface of the high IC stack structure 700L to remove any residual potting material 262.

[0146] Referring to Figure 7H, individual semiconductor packages 700A, i.e., low IC stack structures 312, are formed from their respective IC structures, i.e., high IC stack structures 700L. Delamination, fragmentation, and / or dicing processes are performed to separate the delamination layer 140 (Figure 7B) from each of the high IC stack structures 700L so that each low IC stack 312, i.e., containing different semiconductor packages 700A, i.e., edge interconnect RDL structures 118A and 118B, is separated from each other. According to some embodiments, etching or dicing processes are performed, for example, by dicing, continuous wave laser beam, dry etching (e.g., by plasma), and / or wet etching, to assist the delamination process and cut open the secondary RDLs 118A and 118B at the location of the delamination layer 140, which can also lack metal wiring and dielectric passivation. According to some embodiments, a combination of wet etching, dicing, and planarization operations is performed.

[0147] Figures 8A to 8E show cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 800A according to various embodiments of the present disclosure. The steps shown in Figures 8A to 8E are similar to the steps shown in Figures 7D to 7H in many embodiments described in the paragraphs above, and such similar features will not be repeated for the sake of brevity. The main difference between the steps shown in Figures 8A to 8E and those shown in Figures 7D to 7H is that the edge interconnect RDL structures 118A and 118B in Figures 7D to 7H are replaced by edge interconnect RDL structures 138A and 138B formed by bonding flexible printed circuit (Flex) to the sides of the low IC stack and high IC stack.

[0148] Referring to Figure 10B, the semiconductor device 1001W, i.e., the high IC stack 422, is formed, overmolded, or encapsulated and planarized using the potting material 262 in a manner similar to that shown in Figure 7E.

[0149] Figure 10E shows the formation of the secondary RDL148B. Another support substrate 136 having holes 134 is provided within the semiconductor device 1003W, and another delamination or sacrificial layer 130 is formed on the support substrate 136. The secondary RDL148B is formed on the delamination layer 130, and the secondary RDL148B includes an array of conductive pads 274 on its upper surface. The carrier substrate 106 is delaminated from the semiconductor device 1002W by delamination of the delamination layer 110, and then by a planarization operation, such as CMP, grinding, etching (dry and / or wet), or another preferred etching operation. Next, the semiconductor device 1002W is bonded to the support substrate 136 to form the semiconductor device 1003W using a wafer-level bonding process such as a hybrid bonding process.

[0150] Referring to Figure 10G, a dicing or fragmentation process is then performed to separate the semiconductor device 1003W into individual IC structures 1000L, i.e., high IC stacks. Dicing or fragmentation processes, including dicing, laser ablation, plasma etching, dry etching, wet etching (e.g., acid etching), wet cleaning, or a combination thereof, may be performed to cut open the semiconductor device 1003W at the location of the potting material 262, which may even lack metal wiring and dielectric passivation, in order to facilitate clean separation of the etching or dicing operation to free the high IC stack 422 (Figure 10G) from the semiconductor structure 1003W (Figure 10F). Secondary RDLs 148A and 148B may be formed so as not to be present in the delamination layer 140 on the dicing or fragmentation street between adjacent low IC stacks in order to facilitate dicing. According to some embodiments, a planarization process, such as CMP, grinding, etching (dry and / or wet), or another preferred etching operation is performed to remove the potting material 262 (see Figure 10G) or the release layer 140 (see Figure 10H) and to planarize the upper surfaces of the secondary RDLs 148A and 148B so that they are coplanar with the sides of the high IC stack 422 (see Figure 10G) or high IC stack 322 (see Figure 10H).

[0151] Process options / improvements and IC options other than those mentioned above will be highlighted below. In the building block structures 100A, 300A-300C and 400A-400H shown in Figures 2C, 3D, 3E, 3F, 4G, 4H, 4I, 4J, 4K, 4L, 4M and 4N, (a) Active ICs, for example IC structures 100A, 300A-300C and 400A-400H, can be based on a silicon substrate or a high thermal conductivity (HTC), low thermal expansion coefficient (HTCC) substrate, such as diamond, aluminum nitride, boron nitride, or silicon carbide. (b) ICs, for example IC structures 100A, 300A-300C and 400A-400H, and interconnect spacers (e.g., passive or active silicon interposers) having HTC RDLs on both sides or RDLs on one side, with or without through vias, to facilitate heat conduction from adjacent chips and routing more I / O to the 3D IC side, the substrate material of the interconnect spacer can be an HTC material such as diamond, aluminum nitride, boron nitride, silicon carbide, or a metallic material such as Cu with appropriate separation as needed, or an HTCC material such as diamond, aluminum nitride, boron nitride, silicon carbide, or a clad metal such as Cu / Invar / Cu or Cu / Mo / Cu. (c) ICs, for example, IC structures 100A, 300A-300C and 400A-400H may also be HTCC or HTC spacers as directly mentioned above, containing only HTC RDLs without through vias, to help conduct heat from adjacent chips and route more I / O to the side of the IC. (d) The RDL (Redistribution Layer) structures 108A, 108B, 108C, 108D, 108E, 108F, 118A, 118B, 138A, 138B, 148A, 148B, etc. may be based on an HTCC or HTC dielectric with metal wiring of a suitable metal such as Cu or tungsten (W).

[0152] Figure 15A shows a cross-sectional view of a conventional semiconductor package assembly 96. The semiconductor package assembly 96 includes a laminated substrate 1502, an interposer 1504, a first semiconductor HBM stack 1542, a second semiconductor logic die 1508, and a logic memory control chip 1510 (also called a controller or controller die). The first HBM semiconductor stack 1542 is a stack of memory dies 1543 stacked on its primary surface. The second logic semiconductor die 1508 is one of the following: CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die. However, the problems facing next-generation HBM, i.e. HBM4, include the following: (a) Shortage of known good dies, low yield, and extremely high costs due to increased TSV, (b) A monopoly by the three major companies: SK Hynix, Samsung, and Micron. (c) Lack of support from the three major companies regarding customization or memory optimization, (d) Advanced packaging technologies may shift from flip-chip designs based on copper pillar microbumps to very expensive copper hybrid bonding, but this technology is still in its early stages and could significantly increase costs. (e) The capabilities and capacity of advanced packaging often become a bottleneck, and this, combined with low yield, affects the stable supply of HBM. (f) In particular, as the number of DRAMs increases from 12 in HBM3 to 16 in HBM4, there is a concern that the intermediate and bottom memory tiers in the HBM stack may overheat (since cooling is performed from the back of the top tier DRAM). The above problem worsens when HBM exceeds HBM4, which has 16 or more DRAM dies. The consensus is that even if copper hybrid junctions are not implemented in HBM4, they will be implemented in HBM5, which has more DRAM tiers.

[0153] One or more of the four chip-side (CSS) interconnects described above (see Figure 13D) can be used to overcome the challenges faced when scaling HBM from HBM3 (12+1 dies) to HBM4 (16+1 dies), to transcend the HBM domain, and in some cases, to revolutionize it. Using a 2.5D IC with a side-junction memory stack as an example, as shown in Figure 15B (only interconnects on one side are shown, but these interconnects can connect to chip-side interconnects on other chip sides to support high I / O counts), almost all of the above problems can be solved (or mitigated) as described below. (a) Any memory die can be a known good die prior to assembly, and if necessary, the number of TSVs and / or edge vias required is only a small number compared to an HBM stack, leading to substantial cost savings. (b) Smaller memory players (such as DRAM and SRAM) can compete with the three major players by using RDL and flip-chip technologies that are more easily accessible from OSATS. (c) Regarding customization or memory optimization, there will be opportunities to work with more players than the three major companies. (d) No need to use expensive copper hybrid junctions, (e) Overheating in the intermediate and bottom memory tiers within the HBM stack can be prevented because (cooling is performed from the back of the top tier DRAM) heat is conducted through silicon having a thermal conductivity more than 100 times that of silicon dioxide (instead of the conventional combination of silicon and low-heat-dissipating silicon dioxide in the HBM stack), using the HTCC substrate / interposer and / or HTC spacer as needed. This also makes it possible to increase the number of DRAMs or suitable memory devices from 12 in HBM3 to 16 in HBM4, and in the future to more than 16, where the effects of overheating are a concern. (f) Most importantly, compared to conventional HBM technology, where the overall height is set at approximately 750 μm near the height of the GPU (see Figure 15B), it is easier to scalable, allowing for more memory dies. This is because as the number of DRAM dies increases from 12 to 16 and beyond, the requirements for thinner DRAM dies and their interconnections further exacerbate the aforementioned technical, manufacturing, cost, and supply chain challenges.

[0154] In one embodiment of the present invention, using an HBM2E DRAM (10.5 mm long × 9.5 mm wide) as a reference, and assuming a total of 16 semiconductor structures 1522 (16 DDR dies and / or spacer / interconnect combinations of the same thickness of 500 μm) connected to a control die 1510 on one chip side in the width direction (see Figure 15B), with a length of 5.25 mm (half the length of the HBM2E), a width of 9.5 mm, and a thickness of 500 μm, provides a total chip side surface area of ​​76 mm² (not counting the thickness of the junction layer between dies). Assuming a DRAM bump pitch of 60 μm (57 μm or 29 μm for HBM2E, 60 μm assumed here) and a DRAM junction pad diameter of 14.6 μm, as in HBM2E, the 76 mm² surface area can indicate a maximum I / O count of 87,040, which is more than necessary. Furthermore, in addition to bonding pads located on the edges or sidewalls of the DRAM chip, additional bonding pads can be placed on the edges or sidewalls of other integrated circuit (IC) structures, interconnect spacers, potting or molding compound layers, or high thermal conductivity layers (adjacent to the DRAM chip as shown in Figures 2C, 3D-3F, 4G-4N, and 6A-6E). Thus, the present invention can provide adjustable or expandable bonding pads (1200-1500, or 1500-2400, etc.) on the edges or sidewalls of one semiconductor structure as shown in Figures 2C, 3D-3F, 4H-4N, and 6A-6E, and a set of semiconductor structures can then provide 10 times or more bonding pads (12000-15000, or 15000-2400, etc.) across the edges or sidewalls of the set of semiconductor structures.

[0155] As shown in Figure 15B, the semiconductor package assembly 1500 includes an IC stack 1501 including a first semiconductor stack 1506 and a logic control chip 1510, a laminated substrate 1502, an interposer 1504, and a second semiconductor die 1508. According to some embodiments, the first semiconductor stack 1506 is a memory stack structure, and the second semiconductor die 1508 is one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another preferred die. According to some embodiments, the first semiconductor stack 1506 includes a plurality of IC structures 1523 (which are low IC stacks 312), a plurality of support substrates 1524, and a plurality of junction layers or adhesive layers 1526 between adjacent IC structures 1523 or between one IC structure 1523 and a support substrate 1524. According to some embodiments, the adhesive layer 1526 may further include an HTC layer having a thermal conductivity higher than that of silicon or SiO2. According to some embodiments, the support substrate 1524 is an HTCC (high-temperature co-fired ceramic) interposer, an HTCC substrate, an HTC substrate, etc.

[0156] According to some embodiments, the support substrate 1524 is positioned as a high thermal conductivity layer adjacent to the semiconductor structure 1522, and the high thermal conductivity layer is used to conduct the large amount of heat generated by the IC structure 1523 of the semiconductor structure 1522. The semiconductor structure 1522 prevents the DRAM from overheating and ensures that the DRAM operates under normal conditions. The external connector 1518 is located on the edge of the IC structure 1523 and the edge of the adjacent structure 1524.

[0157] Figures 16A to 16E show cross-sectional views at different stages of a method for manufacturing a semiconductor package 1600A according to various embodiments of the present disclosure. Referring to Figure 16A, a carrier substrate 106 is received or provided. A release layer 1602 is deposited on or attached to the carrier substrate 106. According to some embodiments, the release layer 1602 is a UV-peelable layer or a heat-peelable tape. A defining layer 1604 is deposited on the carrier substrate 106 and includes a plurality of recesses 1604R, the recesses 1604R exposing the release layer 1602.

[0158] Referring to Figure 16B, a plurality of semiconductor dies 1600A are prepared or formed. Each of the semiconductor dies 1600A may be similar to the low IC stack 312 described above, or to other IC stacks including a plurality of IC structures 1603 arranged in the stack. According to some embodiments, the semiconductor die 1600A may further include an external connector 302 or bonding pads on the side of the low IC stack 312 on the RDL 168.

[0159] Referring to Figure 16C, the thermal interface material (TIM) 1606 and the heat spreader 1608 are continuously deposited or formed on the respective exposed sides of the semiconductor die 1600A. According to some embodiments, the sides of the TIM 1606 or the heat spreader 1608 are aligned with the primary surface of the semiconductor die 1600A. According to some embodiments, the TIM 1606 is pre-coated onto the heat spreader 1608 and deposited on the sides of the semiconductor die 1600A along with the mounting or deposition of the heat spreader 1608 onto the semiconductor die 1600A.

[0160] Referring to Figure 16D, the semiconductor die 1600A is removed from the carrier substrate 106 through the peeling of the delamination layer 1602. The semiconductor die 1600A is rotated one face at a time toward the remaining two sides and two primary surfaces of the short IC stack, and the process shown in Figures 16A-16C is repeated under the TIM / heat spreader combo until all five faces are formed except for the side left for the edge interconnects of the short IC stack.

[0161] Figure 17 shows a cross-sectional view of a semiconductor package assembly 1700 according to various embodiments of the present disclosure. The semiconductor package assembly 1700 includes a first interposer 1702, a first semiconductor structure 312A, a second semiconductor structure 312B, three bridge dies 1704, a second interposer 1706, a third semiconductor die 1708, and two heat spreader plates 1710.

[0162] According to some embodiments, the first semiconductor structure 312A and the second semiconductor structure 312B include a memory die, and the third semiconductor die 1708 is one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another preferred die. According to some embodiments, each of the first semiconductor structure 312A and the second semiconductor structure 312B includes a plurality of low memory IC stacks 312 (e.g., a 3D IC structure stack 1901 as described with reference to Figure 19A or Figure 19B) or other IC stacks. According to some embodiments, the first interposer 1702 or the second interposer 1706 includes a plurality of TSVs (through-silicon vias or, if a non-silicon substrate material is used) 1722 that electrically connect the first interposer 1702 or the second interposer 1706 to an adjacent circuit. According to some embodiments, the bridge die 1704 includes a plurality of TSVs 1724 that electrically connect the first interposer 1702 to the second interposer 1706.

[0163] According to some embodiments, the first interposer 1702 is silicon-based, an HTC material, or a material with lower thermal conductivity (e.g., glass). The first interposer 1702 can be bonded to an IC stack substrate or a printed circuit board. According to some embodiments, the second interposer 1706 includes an HTC substrate. According to some embodiments, the bridge die 1704 is used to power up the third semiconductor die 1708 and provide an additional signal path for the third semiconductor die 1708.

[0164] According to some embodiments, thermal management of the semiconductor package assembly 1700 is achieved through direct interchip liquid cooling with fluid microchannels and / or jets that strike the back of the third semiconductor die 1708 as needed, or through immersion cooling with a dielectric coolant or water, which requires the use of conformal coating material such as parylene to protect the circuitry of the semiconductor package assembly 1700.

[0165] According to some embodiments, the semiconductor package assembly 1700 further includes a plurality of external connectors 1712 on the upper surface of the first interposer 1702, which electrically connect the first interposer 1702 to the first semiconductor die 312A, the second semiconductor die 312B, and the bridge die 1704. The semiconductor package assembly 1700 may further include a plurality of external connectors 1714 on the upper surface of the first semiconductor die 312A, the second semiconductor die 312B, and the bridge die 1704, which electrically connect the first semiconductor die 312A, the second semiconductor die 312B, and the bridge die 1704 to the second interposer 1706, and a plurality of external connectors 1716 on the upper surface of the second interposer 1706, which electrically connect the second interposer 1706 to the third semiconductor die 1708. The sealing material 242 is placed between the plurality of external connectors 1712, 1714 and 1716. According to some embodiments, the semiconductor package assembly 1700 further includes a plurality of external connectors 1718 on the underside of the first interposer 1702 that electrically connect the first interposer 1702 to an external circuit.

[0166] As shown in Figures 16A to 16E, the top or back side of a side-connected 3D memory (such as the first semiconductor die 1506 shown in Figure 15B) can be coated with HTC material to promote heat dissipation. Similar concepts underlying Figures 15B and 16A to 16E on chip-side surface interconnects can also be applied to the 3D IC in Figure 17, where the low 3D IC stacks 312A and 312B are memory devices connected to either one or two chip sides, including the use of thermal metamaterials to minimize thermal crosstalk between the GPU (e.g., the third semiconductor die 1708) and the HTC interposer (e.g., the second interposer 1706), and between the first interposer 1702 and the new 3D memory structure, the low 3D IC structure.

[0167] In the conventional 2.5D IC packaging shown in Figure 15A, cooling is achieved using direct inter-chip liquid cooling, which involves mounting a combination of thermal interface material, heat spreader, and cold plate on the back of the upper DRAM and GPU. In the new 3D memory stack structure shown in Figure 15B, cooling of the GPU (e.g., the second semiconductor die 1508) and 3D memory (e.g., the first semiconductor die 1506) can also be achieved by direct inter-chip liquid cooling, or by a combination of direct inter-chip cooling for the GPU and air cooling for the low-power dissipation 3D memory. Furthermore, both configurations in Figures 15A and 15B can be cooled using immersion cooling.

[0168] As referred to in this disclosure, the sides of the 3D IC stack are used to interconnect the dies within the 3D IC stack, enabling skip-die signaling and power distribution. That is, power and signals can be supplied directly from the front top bottom die (or the interposer supporting the bottom die) to all other dies in the 3D IC stack, not just the die directly above it. Furthermore, the HTC material is placed between two adjacent semiconductor dies and thermally coupled to another HTC material covering the other side of the 3D IC stack.

[0169] In one embodiment, a 3D IC stack includes a plurality of semiconductor die or IC chip structures, the semiconductor die or IC chip structure, for example, having a rectangular cuboid shape, such as represented by structure 108A shown in Figure 2D, having a top surface 108P1, a bottom surface 108P2, and four side walls 108S1, 108S2, 108S3, and 108S4, where the area of ​​the top / bottom surface 108P1 / 108P2 is much larger than the area of ​​the side walls 108S1-108S4 (as shown in Figure 2D). There are "edge pads / vias" in the form of peripheral pads present on the periphery, sides, or side walls (one or more side walls 108S1-108S4, etc.) of the semiconductor die or IC chip structure shown in Figure 2D, and / or pads / vias within the RDL structure of the semiconductor die. Furthermore, "edge TSVs (Through-Silicon Vias)" in the semiconductor die may be available as if traversing the entire thickness or a portion thereof of the semiconductor die, as shown in Figure 2D. To expand the area for edge connections on the sidewall or lateral surface, edge pads within the RDL structure can be connected to edge TSVs. These TSVs can penetrate part and / or all of the semiconductor die from the top surface 108P1.

[0170] Figures 18A to 18H show cross-sectional views of the structure at different stages of a method for manufacturing a semiconductor package 1800A according to various embodiments of the present disclosure. To form the low IC stack 1812, the IC structure 142A of the low IC stack 1812 is bonded to the carrier 106, as shown in Figures 18A to 18C, and subsequently, (a) More IC structures 142 of the same size, e.g., 142B, 142C, and 142D, are stacked on top of the bottom IC structure 142A to initially form a low IC stack 1812 (i.e., the final 3D IC package structure interconnected on the sides), and an HTC material (AlN / BN / W / Cu / SiC, etc.) 1802 is inserted between two adjacent IC structures 142 (or covers all surfaces between two adjacent IC structures 142). In one embodiment, the thermal conductivity of the HTC layer 1802 is higher than that of Si or SiO2. Alternatively or additionally, a thermoplastic adhesive (not shown separately) can be used to delaminate, for example, by heating the adhesive to its softening temperature and applying a shear force to slide one low IC stack 1812 off the other low IC stack, followed by wet chemical cleaning or etching of the low IC stack 1812 after delamination. (b) Insert the delamination layer 140 onto the low IC stack 1812, (c) Repeat the above process to construct a high 3D IC stack 1822 (see Figure 18B) that is thick enough to facilitate subsequent processing.

[0171] Processing high 3D IC stacks 1822 on the side is more economical than processing low IC stacks 1812. Low IC stacks 1812 tend to be thin, for example, on the order of 100 μm, and the formation of high IC stacks 1822 makes it possible to create edge interconnects for low IC stacks 1812 with a higher yield using existing commercial precision equipment. Consider today's latest 3D ICs (the ICs are in the IC structure configuration in Figure 2C), namely HBM3 DRAMs, which can support, for example, 12 dies. The thickness of individual DRAM ICs can be about 30-50 μm, close to the practical limit of backgrinding. This means that the thickness of a 3D HBM3 DRAM stack including 12 DRAM ICs and a base logic die is about 500 μm (about 0.5 mm). By stacking 10 HBM3 stacks (or the low IC stack 1812 based on the IC structure configuration in Figure 2C), the total number of dies (in the high IC stack 1822) becomes 120, and the total thickness becomes approximately 5,000 μm, or 5 mm, which is easier to handle in manufacturing compared to 0.5 mm.

[0172] Obtain the high IC stack 1822, then bond them laterally to another carrier substrate 116 as shown in Figure 18D, pot them with a polymer material 262 as shown in Figure 18E, for example, Epotek 377 epoxy in a vacuum, and cure the polymer, and so on. (a) Planarization (and photoetching or wrapping to ensure all edge connections are visible), (b) As shown in Figure 18E, create an RDL structure 118 on the side of the long IC stack 1822. (c) As shown in Figure 18F, bonding to the carrier substrate 126 and peeling off the carrier substrate 116, (d) Flattening (or light wrapping) of the top surface of the long IC stack 1822, (e) Creation of a high thermal conductivity layer 1824 as shown in Figure 18F (or covering one / two / three other sidewalls of the high IC stack 1822, or covering the remaining sidewalls of the high IC stack 1822 without an RDL layer structure). In one embodiment, the thermal conductivity of the high thermal conductivity layer is higher than that of Si or SiO2 (AlN / BN / W / Cu / SiC…). (g) As shown in Figure 18G, peeling of the carrier substrate 126, (h) As shown in Figure 18F, the separation of multiple high IC stacks 1822 into individual high IC stack structures 1800L, and finally, (i) Detachment of the high IC stack 1822 into individual low IC stacks 1812 or semiconductor package 1800A.

[0173] The aforementioned process can also create RDL structures on two or more sides. RDL structures on other sides can be created by following part of the process shown in Figures 18E to 18H. The high IC stack 1822 can be stripped by laser cutting and dicing (however care must be taken not to damage the electrical leads), and then the potting polymer 262 is removed by acid etching.

[0174] After the high 3D IC structure stack 1822 is delaminated, the low IC stack 1812 or semiconductor package 1800A can be released by a series of steps beginning with laser cutting the RDL structure 118 between two low IC stacks 1812, followed by one of the following two approaches: (1) dicing the delamination layer 140 between two adjacent low IC stacks 1812, followed by wet etching, cleaning and / or light lapping to remove residual material from the delamination layer 140, or (2) thermally softening the delamination layer 140, mechanically separating the low IC stacks 1812 one by one using a kit, followed by wet etching, cleaning and / or light lapping to remove residual material from the delamination layer 140.

[0175] The low IC stack 1812 or semiconductor package 1800A may include a plurality of DRAM semiconductor dies to form an HBM structure, or may include a set of DRAM semiconductor dies and a set of FLASH or SRAM semiconductor dies, or may include a plurality of logic dies, or may include any other combination of DRAM / SRAM / FLASH / logic dies.

[0176] Next, as shown in Figure 19A, the low IC structure stack 1812 or semiconductor package 1800A can be bonded to another interposer or IC chip to form a semiconductor package assembly 1900 including a 3D IC structure stack 1901, a substrate 1902, an interposer 1904, and a logic control chip 1906. In this embodiment, the 3D IC structure stack 1901 includes a plurality of DRAM semiconductor dies 1920 (or a plurality of DRAM dies and control ICs) and side RDLs 118, each DRAM semiconductor die 1920 being horizontally separated from the others. Laterally extending RDL structures 118 on the side walls of the plurality of DRAM semiconductor dies (or DRAM and control ICs) 1920 are bonded to the logic memory control chip 1906 or interposer 1904, which is then bonded to the substrate 1902. The power / signaling function of each DRAM semiconductor die 1920 can be addressed by using an RDL structure 118 connected to a logic memory control chip 1906 and an interposer 1904. Unlike conventional HBM structures, in the present invention, each DRAM semiconductor die 1920 can transmit or receive power / signals independently without passing through other DRAM semiconductor dies, and each DRAM semiconductor die can generate high-bandwidth data with low latency, and can therefore be appropriately called HBLM (High-Bandwidth Low-Latency Memory), and a combination of horizontally separated DRAM semiconductor dies 1920 can be called an HBLM shelf.

[0177] Furthermore, an intermediate high thermal conductivity layer 1912 (extending upward) (made of AlN, BN, W, copper, SiC, etc.) and an HTC adhesive layer 1908 may be present between the primary surfaces of two adjacent DRAM semiconductor dies 1920, which may be connected to an optional top HTC layer 1914 (extending laterally) (made of AlN, BN, W, copper, SiC, etc.) located on the other sidewall of the low 3D IC structure stack 1901. Thus, heat generated from these two DRAM semiconductor dies 1920 can be transferred from the dies through the high thermal conductivity layer 1912 to the top high thermal conductivity layer 1914, and then to a heat sink device (e.g., a cold plate; not shown) thermally coupled to the HTC layer 1914.

[0178] According to some embodiments, the RDL118 further includes a plurality of bonding pads 1927 on the upper surface of the RDL118 to electrically connect the interposer 1904 to the DRAM semiconductor die 1920.

[0179] As described above, if there is a need for more signal transmission in multiple DRAM semiconductor dies 1920, more upward-extending RDL structures 1916 may be formed on two or more sides, as shown in Figure 19B, with the bottom RDL structure 118 formed on one side of the multiple DRAM semiconductor dies 1920, and another side RDL structure (or side RDL structure) formed on the other side of the multiple DRAM semiconductor dies 1920 opposite or adjacent to the mutually high thermal conductivity layer 1912, and the bottom RDL structure 118 is electrically connected to these side RDL structures 1916.

[0180] As described above, when multiple DRAM semiconductor dies 1920 require greater heat dissipation, as shown in Figure 19B, more intermediate HTC layers 1917, similar to the intermediate HTC 1912 or top HTC 1914, may be formed on one or two of two or more sides and / or primary surfaces, and the intermediate HTC layers 1917 are thermally bonded to the top HTC 1914 and intermediate HTC 1912. According to some embodiments, the HTC layers 1912, 1914, and 1917 have a higher thermal conductivity than silicon or SiO2.

[0181] Figure 20A illustrates a coupling relationship between a low 3D IC stack (or HBLM shelf) 2012 and a logic chip (or logic control chip or memory control IC) 2014 according to another embodiment of the present invention. The low 3D IC stack 2012 comprises an HBLM shelf structure 2012 and multiple DRAM semiconductor dies MR1-MR4 (or more) forming a base die 2022, each DRAM semiconductor die (or HBLM) MR1-MR4 having multiple data read / write functions to / from it. As described above, in this low 3D IC stack 2012, each DRAM semiconductor die MR1-MR4 is isolated from each other horizontally rather than vertically. This novel memory architecture of the HBLM shelf within the low 3D IC stack 2012 enables even faster random access times.

[0182] As shown in Figure 20A, the logic bridge area 2024 of the logic / SOC chip (or logic control chip) 2014 includes logic I / O pads P31, P33, ..., P3N, which are electrically coupled to I / O pads P11, P13, ..., P1N of the base die 2022, respectively, where N is a positive integer greater than 3. The I / O pads P11, P13, ..., P1N located within the base die 2022 of the low 3D IC stack 2012 are further coupled to external bidirectional repeaters ER1, ER2, ..., ERN within the base die 2022, respectively, via metal wires or the aforementioned RDL structure 118, for transmitting and amplifying data or signals. Furthermore, each DRAM semiconductor die MR1, MR2, MR3, or MR4 has the same or substantially the same structure. For example, DRAM semiconductor die MR1 includes a plurality of first memory I / O pads MIO11, a bidirectional repeater or driver R1 corresponding to the plurality of memory I / O pads MIO11, and micropads MP11, MP12. Similarly, other DRAM semiconductor dies such as MR2 include a plurality of second memory I / O pads MIO12, a bidirectional repeater or driver R2 corresponding to the plurality of second memory pads MIO12, and micropads MP21, MP22, etc. In another embodiment, each DRAM semiconductor die MR1 to MR4 has row-address I / O pads (or interfaces) and column-address I / O pads (or interfaces) that are physically independent from the row-address I / O pads. Such a non-multiplexed mode using parallel access paths that activate both row-address and column-address can be used in the present invention.

[0183] As mentioned above, this low 3D IC stack 2012 is a complete HBLM shelf structure that embodies the following important design attributes: (1) an access mode for simultaneously activating both row data selection paths and column data selection paths in a manner similar to SRAM access modes, without requiring the multiplexing required by conventional packaged DRAMs; (2) the incorporation of the aforementioned RDL structure enabling smooth planes to create higher simultaneous I / O and higher bandwidth interconnects; and (3) each DRAM semiconductor die MR1~MR4 has its own complete test and probing structure for verifying functionality, yield, and performance based on smaller probe pads that are not connected to the environment outside the chip, thereby often large (4) Each DRAM semiconductor die MR1-MR4 can function on its own in terms of RAM operation such as row and column address inputs, READ and WRITE command inputs, the positions of necessary clock and control signals and I / O, and more importantly, the signals from each DRAM die can be directly and independently connected to control positions on a control IC (e.g., base die 2022) which has a corresponding bilateral repeater or driver R1, R2, ..., RN, high-performance transistors and a high-conductance BEOL structure, which is a common logic technology for each DRAM die.

[0184] In this embodiment, the bidirectional repeater R1 within the DRAM semiconductor die MR1 is coupled to the external bidirectional repeater ER1 via the metal wires of the aforementioned RDL structure 118, the bidirectional repeater R2 is coupled to the bidirectional repeater R1 via other metal wires of the aforementioned RDL structure 118, the bidirectional repeater R3 is coupled to the bidirectional repeater R2 via other metal wires of the aforementioned RDL structure 118, and the bidirectional repeater R4 is coupled to the bidirectional repeater R3 via other metal wires of the aforementioned RDL structure 118. A selection signal or control signal can be further applied to the bidirectional repeater ER1 and / or bidirectional repeaters R1 to R4 for data selection.

[0185] The operation of the logic chip 2014 + low 3D IC stack 2012 (or HBLM shelf structure) as shown in Figure 20A is described below. For example, the logic die 2014 transmits all essential signals via its own I / O pads P31-P3N (i.e., all relevant signal pads). This is similar to the signal paths defined by JEDEC for HBM, but these conventional HBMs require the use of TSVs to connect all signals / IOs. On the other hand, the low 3D IC structure stack or HBLM shelf 2012 does not require TSVs and can accomplish the same job more easily by conveniently using the aforementioned RDL structure 118 and all proven repeater / driver circuits. Since the signal / IO paths are connected together through the aforementioned RDL structure 118, operation for receiving and transmitting signals is required to tap the control signals in Figure 20A in order to determine which signals are loaded from the DRAM semiconductor dies MR1, MR2, MR3, and MR4 and then received or transmitted. In another embodiment, the bidirectional repeaters ER1, ER2, ..., ERN within the base die 2022 may be removed, and the base die 2022 may be the RDL structure or bottom RDL structure 118 described in Figure 19A or 19B.

[0186] Furthermore, in another embodiment of the logic chip 2014 + low 3D IC stack 2012 (or HBLM shelf structure) as shown in Figure 20B, each of the bidirectional repeaters R1, R2, R3, and R4 is coupled to an external bidirectional repeater ER1. Specifically, bidirectional repeater R1 is coupled to the external bidirectional repeater ER1 via some metal wires of the aforementioned RDL structure 118, bidirectional repeater R2 is coupled to the external bidirectional repeater ER1 via another metal wire of the aforementioned RDL structure 118, bidirectional repeater R3 is coupled to the external bidirectional repeater ER1 via another metal wire of the aforementioned RDL structure 118, and bidirectional repeater R4 is coupled to the external bidirectional repeater ER1 via another metal wire of the aforementioned RDL structure 118. A selection circuit can be coupled to bidirectional repeater ER1 and / or bidirectional repeaters R1-R4 to selectively pick up desired signals.

[0187] In another embodiment of the present invention, the bidirectional repeaters R1 (via MIO11), R2 (via MIO12), R3 (via MIO13), and R4 (via MIO14) can be directly coupled to the I / O pad P11, i.e., the external bidirectional repeaters ER1, ER2, ..., ERN as shown can be omitted, and the base die 2022 may be the RDL structure or bottom RDL structure 118 described in Figure 19A or Figure 19B. Furthermore, in another embodiment, the base die 2022 is unnecessary, and all memory I / O pads MIO11 of MR1 can be directly coupled to the corresponding logical I / O pads P11, P13, ..., P1N via the bottom RDL structure 118, but not via MR2~MR4, and all memory I / O pads MIO12 of MR2 can be directly coupled to the corresponding logical I / O pads P21, P23, ..., P2N via the bottom RDL structure 118, but not via MR1, MR3~ All memory I / O pads MIO13 of MR3 can be directly coupled to the corresponding logical I / O pads P31, P33, ..., P3N via the bottom RDL structure 118, but they cannot be coupled via MR1, MR2, and MR4, and all memory I / O pads MIO14 of MR4 can be directly coupled to the corresponding logical I / O pads P41, P43, ..., P4N via the bottom RDL structure 118, but they cannot be coupled via MR1 to MR3.

[0188] Furthermore, the micropads MP11 and MP12 can be coupled to an external probe (not shown) for testing (e.g., verification of functionality, yield, and performance). According to some embodiments, the micropads MP11 and MP12 can be coupled to an environment outside the logic chip 2014 and the low 3D IC structure stack 2012 (or HBLM shelf structure). In this case, conventional electrostatic discharge (ESD) protection circuits must be provided, and the size of each micropad MP11 and MP12 is larger than the size of each of the other memory I / O pads MIO11, MIO12, ... configured to be internally coupled with I / O pads P11, P13, ..., P1N or the logic chip 2014.

[0189] According to some embodiments, referring to Figures 19A and 19B, the IC stack 1901 includes a plurality of IC structures 1920 separated horizontally from each other. Each IC structure 1920 can be a semiconductor structure as shown in Figures 2C-2F, 3D-3F, 4G-4N, and 5A-5B, and has a top surface 108P1, a bottom surface 108P2 opposite the top surface 108P1, a first side wall 1920S1 or 108S1, a second side wall 1920S2 or 108S2, a third side wall 1920S3 or 108S3 (parallel to the paper sheet), and four side walls 108S having a fourth side wall (a side wall parallel to the paper sheet opposite the side wall 1920S3 shown in Figure 19B, or side wall 108S4 in Figure 2D). The area of ​​the base 108P2 or the top 108P1 is greater than the area of ​​any side wall 102S in Figure 2C, for example, 1920S1 (108S1), 1920S2 (108S2), 1920S3 (108S3), or 108S4. The low 3D IC stack 1901 may further include a laterally extending RDL structure 118 covering the first side wall 1920S1 of each of the multiple IC structures 1920.

[0190] According to several embodiments, with reference to Figures 19A, 19B, 4G-4N, 5A-5B, and 6E, each semiconductor structure includes a first integrated circuit (IC) structure such as the IC structure 1920 in Figure 19A or 19B or the die 122E in Figures 4G-4N, and a first adjacent structure such as a high thermal conductivity layer 1912 in Figure 19A or 19B, or a molded compound layer 242 and / or die 122D in Figures 4G-4N, which is physically separated from the first IC structure. The first IC structure and the first adjacent structure are (1) arranged along a first sidewall 1912S1 extending in the Z direction in Figure 19A or 19B, or (2) arranged along a first sidewall 1912S1 extending in the XZ plane in Figure 19A or 19B. In the above condition (2), referring to Figures 4K to 4N, the respective XZ planes of IC structures 400E to 400H may face the RDL structure 118 and form an electrical connection with the RDL structure. The first IC structure 122E and the first adjacent structure 122D may be arranged on the respective XZ planes of IC structures 400E to 400H along the X direction shown in Figure 19A or Figure 19B. According to some embodiments, the laterally extending RDL structure 118 shown in Figures 19A and 19B comprises a first plurality of bonding pads 1927 arranged along the first sidewall of each semiconductor structure 1920, the first plurality of bonding pads being on or facing the edges of the first IC structure and the edges of the first adjacent structure.

[0191] In some embodiments, the first IC structure may include a plurality of semiconductor dies, for example, dies 122E, 122G, and / or 122H shown in Figures 4K to 4N or Figure 6D. The first adjacent structure 122D may be an active die or an HTC dummy interconnect spacer. The interconnect spacer may be a passive or active silicon interposer. According to some embodiments, the interconnect spacer is a semiconductor interposer having a set of through-semiconductor vias (TSVs) electrically coupled to a plurality of first bonding pads or a subset of external connectors.

[0192] According to some embodiments, the first adjacent structure includes another IC structure such as the semiconductor die 122D shown in Figures 4G to 4N, an interconnection spacer such as the interposer 122D shown in Figures 4G to 4N, a molded compound layer such as the potting material or molded compound layer 242 shown in Figures 4G to 4N, or a high thermal conductivity (HTC) layer such as the die 122D shown in Figures 4G to 4N, and has a thermal conductivity higher than that of Si or SiO2 to dissipate heat generated from the adjacent IC structure.

[0193] According to some embodiments, the number of first multiple bonding pads 1927 exceeds 1,300 to 1,500 per IC structure 1920.

[0194] Referring to some embodiments, specifically Figures 4G, 4I, 4K, 4M, 5A, and 5B, a first IC structure 122E or another IC structure acting as a first adjacent structure includes a set of through-semiconductor vias (TSVs) 104B exposed from the side wall 102S in the XZ plane and electrically coupled to a subset of first multiple junction pads 1927 of a laterally extending RDL structure 118 of a 3D IC stack 1901 shown in Figure 19A or 19B.

[0195] According to some embodiments, referring to Figures 4G, 4H, 4K, 4L, 5A, and 5B, the molding compound layer 242 is exposed from the molding sidewall 102S in the XZ plane and includes a set of through-molding vias (TMVs) 232 electrically coupled to a subset of first multiple bonding pads 1927 of a laterally extending RDL structure 118 of the 3D IC stack 1901 shown in Figure 19A or 19B (see also, for example, RDL 118A shown in Figure 5A or 5B).

[0196] According to some embodiments, with reference to Figures 4G, 4H, 4K, 4L, 5A, and 5B, the first adjacent structure 122D may include interconnect spacers with or without active components, along with a set of through-semiconductor vias (TSVs) similar to the TSVs 104B in the first IC strut structure 122E, which are exposed from the side wall 102S in the XZ plane and electrically coupled to a subset of the first plurality of bonding pads 1927 of the laterally extending RDL structure 118 of the low 3D IC stack 1901 shown in Figure 19A or 19B.

[0197] According to some embodiments, the IC stack 1901 further includes a high thermal conductivity structure, such as the interposer 1702 or 1706 of Figure 17, between two semiconductor structures 1920, 1912, or next to some of the semiconductor structures 1920, 1912 of the IC stack 1901, in a manner similar to the mutually high thermal conductivity layer 1912 shown in Figure 19A or Figure 19B. The thermal conductivity of the high thermal conductivity structure is higher than that of Si or SiO2.

[0198] According to some embodiments, each IC structure 1920 can be a DRAM semiconductor die, and the IC stack 1901 can be an HBM-compatible structure.

[0199] According to some embodiments, the IC stack 1901 further includes a logic control chip 1906 that lies beneath a laterally extending RDL structure 118 of the IC stack 1901 and is electrically connected thereto.

[0200] According to some embodiments, referring to Figure 19A or Figure 19B, the IC stack 1901 further includes a transversely extending thermal conductive layer 1914 covering each second side wall 1920S2 of a plurality of IC structures 1920, the transversely extending RDL structure 118 is on the opposite side of the transversely extending thermal conductive layer 1914, and the thermal conductivity of the transversely extending thermal conductive layer is higher than that of Si or SiO2.

[0201] Referring to some embodiments, specifically Figures 19A and 19B, the IC stack 1901 includes a plurality of IC structures 1920 separated horizontally from each other. Referring to Figures 2C-2F, 3D-3F, 4G-4N, 5A-5B and 19A, each IC structure 1920 can be referred to as IC structures 100A, 100A, 300A-300C, 400A-400H, 500A and 500B in Figures 2C-2F, 3D-3F, 4G-4N and 5A-5B. As shown in Figure 2D, each IC structure 1920 has dimensions similar to those of the RDL structure 108A and includes a top surface 108P1, a bottom surface 108P2 opposite the top surface 108P1, and four side walls having a first side wall 1920S1 or 108S1, a second side wall 1920S2 or 108S2, a third side wall 1920S3 or 108S3, and a fourth side wall 108S4. The area of ​​the bottom surface 108S2 or the top surface 108S1 is larger than the area of ​​any of the side walls, e.g., 1920S1(108S1), 1920S2(108S2), 1920S3(108S3), and 108S4. The IC stack 1901 may further include a laterally extending RDL structure 118 covering each of the first side walls 1920S1 (108S1) of each of the multiple IC structures 1920. The IC stack 1901 may also include an upwardly extending thermal conductive layer 1912 between two adjacent IC structures 1920. According to some embodiments, the thermal conductivity of the upwardly extending thermal conductive layer 1912 is higher than the thermal conductivity of Si or SiO2, such as a SiC chip having the same size as the IC structure 1920.

[0202] According to some embodiments, the IC stack 1901 further includes a transversely extending thermal conductive layer 1914 that covers each second side wall 108S2 or 1920S2 of a plurality of IC structures 1920 and is thermally bonded to each of the upwardly extending thermal conductive layers 1912, the transversely extending RDL structure 118 is on the opposite side of the transversely extending thermal conductive layer 1914, and the thermal conductivity of the transversely extending thermal conductive layer 1914 is higher than the thermal conductivity of Si or SiO2 such as a SiC chip.

[0203] According to some embodiments, the upward-extending thermal conductive layer 1912 or the laterally-extending thermal conductive layer 1914 comprises a material such as BN, AlN, W, SiC, or copper.

[0204] According to some embodiments, referring to Figure 19B, the IC stack 1901 further includes an upward-extending RDL structure 1916 covering each third side wall 108S3 or 1920S3 of a plurality of IC structures 1920, the upward-extending RDL structure 1916 being electrically connected to a laterally-extending RDL structure 118.

[0205] According to some embodiments, each IC structure 1920 includes a DRAM semiconductor die, and the IC stack 1901 is an HBM-compatible structure (i.e., essential signals passing through its own I / O pads P31-P3N are compatible with the signal paths defined by JEDEC for HBM).

[0206] According to some embodiments, the IC stack 1901 further includes a logic control chip 1906 that lies beneath a laterally extending RDL structure 118 of the IC stack 1901 and is electrically connected thereto.

[0207] According to some embodiments, referring to Figures 19A and 20A or 20B, each IC structure 1920 is a DRAM semiconductor die MR1, MR2, MR3 or MR4, each including a plurality of memory I / O pads MIO11, MIO12, MIO13 or MIO14. According to some embodiments, the logic control chip 1906 shown in Figure 19A or 19B may be the logic control chip 2014 shown in Figure 20A or 20B, which includes a plurality of logic I / O pads P31 to P3N. The plurality of memory I / O pads MIO11 to MIO14 of each DRAM semiconductor die MR1 to MR4 are electrically connected to the plurality of logic I / O pads P31 to P3N via a laterally extending RDL structure 118 shown in Figure 19A or 19B.

[0208] According to some embodiments, the memory I / O pads MIO11 to MIO14 do not include electrostatic discharge (ESD) protection circuits. Each DRAM semiconductor die MR1 to MR4 includes a plurality of row-address I / O pads (not shown separately) and a plurality of column-address I / O pads (not shown separately) that are physically independent of the plurality of row-address I / O pads.

[0209] According to some embodiments, referring to Figure 20A, each DRAM semiconductor die MR1 to MR4 further includes a plurality of external bidirectional repeaters R1, R2, R3, or R4. The bidirectional repeater R2 of the second DRAM semiconductor die MR2 is electrically coupled to the corresponding bidirectional repeater R1 of the first DRAM semiconductor die MR1 via a second metal wire of a laterally extending RDL structure 118 or an upwardly extending RDL structure 1916, and the corresponding bidirectional repeater R1 of the first DRAM semiconductor die MR1 is electrically coupled to the corresponding logic I / O pad P31 of the logic control chip 2014 via a first metal wire of a laterally extending RDL structure 118 or an upwardly extending RDL structure 1916.

[0210] According to some embodiments, referring to Figure 20B, each DRAM semiconductor die MR1 to MR4 further includes a plurality of external bidirectional repeaters R1 to R4, where the bidirectional repeater R1 of the first DRAM semiconductor die MR1 is electrically coupled to the corresponding logic I / O pad P31 of the logic control chip 2014 through a first metal wire of a laterally extending RDL structure 118 or an upward extending RDL structure 1916, and the bidirectional repeater R2 of the second DRAM semiconductor die MR2 is electrically coupled to the corresponding logic I / O pad P31 of the logic control chip through a second metal wire of a laterally extending RDL structure 118 or an upward extending RDL structure 1916.

[0211] Referring to several embodiments, with reference to Figures 19A, 19B and Figures 2C, 2D-2F, 3D-3F, 4G-4N, 5A, 5B and 6E, the IC structure 1920 may include the IC structures 100A-100C, 300A-300C, 400A-400H, 500A, 500B and 600A described herein. For example, with reference to Figures 5A, 5B and Figure 19A or 19B, the IC structure 1920 includes IC structure 500A, the IC structure includes a first semiconductor body 122F and an interconnection structure 108A or 108B. The first semiconductor body (122E or 122F) has a first primary surface (102P) and a first secondary surface (102S), the first primary surface being substantially perpendicular to the first secondary surface. The interconnection structure includes a primary redistribution layer (RDL) (Figure 5A, 108A) on a first primary surface 102P, the primary RDL 108A having a second secondary surface (Figure 5A, 108S) aligned with the first secondary surface 102S of the first semiconductor body 122F, the first secondary surface 102S and the second secondary surface 108S together forming a secondary plane (Figure 5A, 500AS) that can correspond to the first sidewall 1920S1 or the second sidewall 1920S2 of the IC structure 1920, and the primary RDL 108S further comprises a first conductive element (Figure 5A, 212, 214) exposed through the second secondary surface 108S of the primary RDL 108A.

[0212] According to some embodiments, the first conductive element may be a conductive pad 212 on the surface 108P of the primary RDL structure 108A / 108B substantially parallel to the first primary surface 102P1 (see Figure 2C), a conductive via 216 connecting adjacent layers of the primary RDL 118A / 118B (see Figure 2G), a stacked via 214 traversing the primary RDL 118A / 118B (see Figure 2G), or a combination thereof.

[0213] According to some embodiments, the first semiconductor body (122E in Figure 4G or Figure 4I) further includes at least through-silicon vias 104B (Figure 4G), through-molding vias 232 (Figure 4G), or insulating elements 242 (Figure 4I) exposed through the first secondary surface.

[0214] According to some embodiments, the first semiconductor body of the IC structure 1920 shown in FIG. 19A or FIG. 19B can be the counterpart of the semiconductor dies 400A - 400H or 600A shown in FIGS. 4K - 4N or FIG. 6E, and can include (1) a plurality of first dies 122D and 122E (FIGS. 4K - 4N) arranged within the same package layer, (2) a plurality of second dies 122G, 122H (FIG. 6E) stacked vertically, (3) a plurality of second dies 122G, 122H (FIG. 6E) arranged side by side with another third die 122E within the same package layer, or a combination thereof. The first, second, and third dies 122D, 122E, 122G, 122H can be of the same or different sizes.

[0215] According to some embodiments, the first semiconductor body of the IC structure 1920 shown in FIG. 19A or 19B (refer to the partial structure of the semiconductor die 600A excluding the primary RDL 108C) also includes a plurality of conductive vias 104B (refer to the semiconductor die 122E), pillars 224, or plugs 234 of the same or different lengths that electrically connect the plurality of first dies 122E, 122G, and 122H to the primary RDL 108C along the Z - axis as shown in FIG. 6E, and / or to the lateral - extending RDL structure 118 within the XZ plane as shown in FIGS. 6E, FIG. 19A, or FIG. 19B.

[0216] According to some embodiments, the lateral - extending RDL structure 118 shown in FIG. 19A or FIG. 19B is electrically connected to the first conductive element of the primary RDL, to the conductive pad 212 or the conductive via 214 shown in FIG. 4G or FIG. 6D, and to the pillar 224 or the plug 234 shown in FIG. 6D.

[0217] According to some embodiments, the lateral - extending RDL structure 118 (corresponding to the RDL 118A shown in FIG. 7I) includes a hybrid bonding layer or a bump pad array (244).

[0218] According to some embodiments, referring to FIGS. 19A and 19B, the IC stack 1901 includes a plurality of IC structures 1920 horizontally separated from each other. Referring to FIGS. 2C, 2D, and 19A, each IC structure 1920 can be the structure 108A shown in FIG. 2D, and includes a top surface 108P1, a bottom surface 108P2 opposite to the top surface, and four side walls including a first side wall 1920S1 or 108S1, a second side wall 1920S2 or 108S2, a third side wall 1920S3 or 108S3, and a fourth side wall 108S4. The area of the bottom surface or the top surface is larger than the area of any of the four side walls, for example, 1920S1(108S1), 1920S2(108S2), 1920S3(108S3), and 108S4. The IC stack 1901 may further include a laterally extending RDL structure 118 covering each of the first side walls 1920S1(108S1) of the plurality of IC structures 1920.

[0219] According to some embodiments, the IC stack 1901 further includes a set of upwardly extending thermal conduction layers 1912, and the corresponding upwardly extending thermal conduction layers 1912 are disposed between any two adjacent IC structures 1920 of the plurality of IC structures 1920. The IC stack 1901 may also include a first laterally extending thermal conduction layer 1914 that covers each of the second side walls 1920S2(108S2) of the plurality of IC structures 1920 and is thermally coupled to the set of upwardly extending thermal conduction layers 1912. The thermal conductivity of either the upwardly extending thermal conduction layer 1912 or the first laterally extending thermal conduction layer 1914 is higher than the thermal conductivity of Si or SiO2.

[0220] According to some embodiments, referring to FIG. 19B, the IC stack 1901 further includes a second laterally extending thermal conduction layer 1917 that covers each of the third side walls 1920S3(108S3) of the plurality of IC structures 1920. The second laterally extending thermal conduction layer 1917 is thermally coupled to the set of upwardly extending thermal conduction layers 1912.

[0221] According to some embodiments, the IC stack 1901 is an HBM-compatible structure, and each IC structure 1920 includes a DRAM semiconductor die 1920. The IC stack 1901 further includes a logic control chip 1906 that lies beneath a laterally extended RDL structure 118 of the IC stack 1901 and is electrically connected thereto.

[0222] In summary, the present invention provides a 3D IC stack having multiple semiconductor dies, wherein RDLs are located on the sides of the 3D IC stack to interconnect the dies within the 3D IC stack and enable skip die signaling and power distribution. Furthermore, a high thermal conductivity material is placed between two adjacent semiconductor dies and thermally coupled to another high thermal conductivity material covering the other sides of the 3D IC stack.

[0223] The above outlines the structures of several embodiments so that those skilled in the art may better understand the aspects of this disclosure. Those skilled in the art should understand that the aspects of this disclosure can be readily used as a basis for designing or modifying other operations and structures to accomplish the same objectives and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A plurality of integrated circuit (IC) structures separated horizontally from each other, each IC structure comprising a top surface, a bottom surface opposite the top surface, and four side walls having a first side wall, a second side wall, a third side wall, and a fourth side wall, wherein the area of ​​the bottom surface or the top surface is larger than the area of ​​any of the side walls, A laterally extending RDL structure covering each of the first side walls of the plurality of IC structures, An upward-extending thermal conductive layer is placed between two adjacent IC structures, An IC stack comprising, The thermal conductivity of the upward-extending thermal conductive layer is higher than that of Si in this IC stack.

2. The IC stack according to claim 1, further comprising a laterally extending heat conduction layer that covers each of the second side walls of the plurality of IC structures and is thermally bonded to the upwardly extending heat conduction layer, wherein the laterally extending RDL structure faces the laterally extending heat conduction layer, and the thermal conductivity of the laterally extending heat conduction layer is higher than that of Si.

3. The IC stack according to claim 2, wherein the upward-extending thermal conductive layer or the laterally-extending thermal conductive layer comprises BN, AlN, W, SiC, or copper.

4. The IC stack according to claim 1, further comprising an upward-extending RDL structure covering the third side wall of each of the plurality of IC structures, wherein the upward-extending RDL structure is electrically connected to the laterally-extending RDL structure.

5. The IC stack according to claim 4, wherein each IC structure comprises a DRAM semiconductor die, and the IC stack has an HBM-compatible structure.

6. The IC stack according to claim 4, further comprising a logic control chip located below the laterally extending RDL structure of the IC stack and electrically connected thereto.

7. The IC stack according to claim 6, wherein each of the IC structures comprises a DRAM semiconductor die having a plurality of memory I / O pads, the logic control chip comprises a plurality of logic I / O pads, and the plurality of memory I / O pads of each DRAM semiconductor die are electrically coupled to the plurality of logic I / O pads through the laterally extending RDL structure.

8. The IC stack according to claim 7, wherein the memory I / O pads are not equipped with electrostatic discharge (ESD) protection circuits, or each DRAM semiconductor die further comprises a plurality of row address pads and a plurality of column address pads that are physically independent from the plurality of row address pads.

9. The IC stack according to claim 7, wherein each DRAM semiconductor die further comprises a plurality of external bidirectional repeaters, the bidirectional repeaters of the second DRAM semiconductor die being electrically coupled to the corresponding bidirectional repeaters of the first DRAM semiconductor die via a second metal wire of the laterally extending RDL structure or the upward extending RDL structure, and the corresponding bidirectional repeaters of the first DRAM semiconductor die being electrically coupled to the corresponding logic I / O pads of the logic control chip via a first metal wire of the laterally extending RDL structure or the upward extending RDL structure.

10. The IC stack according to claim 7, wherein each DRAM semiconductor die further comprises a plurality of external bidirectional repeaters, the bidirectional repeaters of the first DRAM semiconductor die being electrically coupled to the corresponding logic I / O pads of the logic control chip via first metal wires of the laterally extending RDL structure or the upward extending RDL structure, and the bidirectional repeaters of the second DRAM semiconductor die being electrically coupled to the corresponding logic I / O pads of the logic control chip via second metal wires of the laterally extending RDL structure or the upward extending RDL structure.

11. The first IC structure among the plurality of IC structures is A first semiconductor body having a first primary surface and a first secondary surface, wherein the first primary surface is substantially perpendicular to the first secondary surface, An interconnection structure comprising a primary redistribution layer (RDL) on the first primary surface, wherein the primary RDL has a second secondary surface that is aligned with the first secondary surface of the first semiconductor body, Equipped with, The IC stack according to claim 1, wherein the first secondary surface and the second secondary surface jointly form a secondary plane, and the primary RDL further comprises a first conductive element exposed through the second secondary surface of the primary RDL.

12. The IC stack according to claim 11, wherein the first conductive element comprises a conductive pad on the surface of the primary RDL structure substantially parallel to the first primary surface, conductive vias connecting adjacent layers of the primary RDL, stacked vias traversing the primary RDL, or a combination thereof.

13. The IC stack according to claim 12, wherein the first semiconductor body further includes at least through-silicon vias, through-molding vias, or insulating elements exposed through the first secondary surface.

14. The IC stack according to claim 11, wherein the first semiconductor body comprises a plurality of first dies arranged in the same package layer, a vertically stacked second die, the vertically stacked second die arranged alongside other third dies in the same package layer, or a combination thereof.

15. The IC stack according to claim 14, wherein the first semiconductor body comprises a plurality of conductive vias, pillars, or plugs of the same or different lengths that electrically connect the plurality of first dies to the primary RDL and / or the laterally extended RDL structure.

16. The IC stack according to claim 11, wherein the laterally extending RDL structure is electrically connected to a first conductive element of the primary RDL to a conductive via, pillar or plug in the first semiconductor body, or a combination thereof, and the laterally extending RDL structure includes a hybrid junction layer or a bump pad array.

17. A plurality of integrated circuit (IC) structures separated horizontally from each other, each IC structure comprising a top surface, a bottom surface opposite the top surface, and four side walls having a first side wall, a second side wall, a third side wall, and a fourth side wall, wherein the area of ​​the bottom surface or the top surface is larger than the area of ​​any of the four side walls, A set of upward-extending thermal conductive layers, wherein the corresponding upward-extending thermal conductive layer is positioned between any two adjacent IC structures among the plurality of IC structures, A first laterally extending heat conductive layer covers each of the second side walls of the plurality of IC structures and is thermally bonded to the set of upwardly extending heat conductive layers, An IC stack comprising, An IC stack in which the thermal conductivity of any upward-extending thermal conductive layer and / or the laterally-extending thermal conductive layer is higher than the thermal conductivity of Si.

18. The IC stack according to claim 17, further comprising a laterally extending RDL structure covering each of the first side walls of the plurality of IC structures.

19. The IC stack according to claim 18, wherein each IC structure comprises a DRAM semiconductor die, the IC stack further comprises a logic control chip located below the laterally extended RDL structure of the IC stack and electrically connected thereto, and the IC stack has an HBM-compatible structure.

20. The IC stack according to claim 17, further comprising a second laterally extending thermal conductive layer covering each third side wall of the plurality of IC structures, wherein the second laterally extending thermal conductive layer is thermally coupled to the set of upwardly extending thermal conductive layers.

21. A plurality of semiconductor structures separated horizontally from each other, each semiconductor structure having a top surface, a bottom surface opposite the top surface, and four side walls having a first side wall, a second side wall, a third side wall, and a fourth side wall, wherein the area of ​​the bottom surface or the top surface is larger than the area of ​​any of the side walls, A laterally extending RDL structure covering the first side wall of each semiconductor structure, An IC stack comprising, The first semiconductor structure among the plurality of semiconductor structures comprises a first integrated circuit (IC) structure and a first adjacent structure physically separated from the first IC structure, and the first IC structure and the first adjacent structure are arranged along the first side wall of the first semiconductor structure. The laterally extending RDL structure comprises a plurality of first bonding pads arranged along the first sidewall of the first semiconductor structure, wherein the plurality of first bonding pads are on the edges of the first integrated circuit (IC) structure and on the edges of the first adjacent structures, forming an IC stack.

22. The IC stack according to claim 21, wherein the number of the first plurality of bonding pads is greater than 1,300 to 1,500.

23. The IC stack according to claim 21, wherein the first adjacent structure comprises another IC structure, an interconnection spacer, a molding compound layer, or a high thermal conductivity layer having a higher thermal conductivity than Si.

24. The IC stack according to claim 23, wherein the first IC structure or the other IC structure includes a set of through-semiconductor vias (TSVs) electrically coupled to a subset of the first plurality of bonding pads.

25. The IC stack according to claim 23, wherein the molding compound layer comprises a set of through-molding vias (TMVs) electrically coupled to a subset of the first plurality of bonding pads.

26. The IC stack according to claim 23, wherein the interconnection spacer is a semiconductor interposer having a set of through-semiconductor vias (TSVs) electrically coupled to a subset of the first bonding pads.

27. The IC stack according to claim 21, further comprising a high thermal conductivity structure adjacent to the first semiconductor structure, wherein the thermal conductivity of the high thermal conductivity structure is higher than that of Si.

28. The IC stack according to claim 21, wherein each first IC structure comprises a DRAM semiconductor die, and the IC stack has an HBM-compatible structure.

29. The IC stack according to claim 28, further comprising a logic control chip located below the laterally extending RDL structure of the IC stack and electrically connected thereto.

30. The IC stack according to claim 21, further comprising a transversely extending thermal conductive layer covering each of the second side walls of the plurality of semiconductor structures, wherein the transversely extending RDL structure faces the transversely extending thermal conductive layer, and the thermal conductivity of the transversely extending thermal conductive layer is higher than that of Si.

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