High-bandwidth memory stack with side-edge interconnects and 3D IC structure having the same

Abstract

This invention provides a high-bandwidth memory stack having side-edge interconnects and a 3D IC structure having the same. [Solution] The semiconductor wafer 31 is a 3D IC structure on which edge pad semiconductor dies 10a and 10b are formed, wherein the boundary between adjacent edge pad semiconductor dies 10a and 10b is defined by a scribe line region SL, and each edge pad semiconductor die includes a memory die 1031a or memory die 1031b and redistribution layers (RDLs) 15a and 15b disposed on the respective memory die. Each memory die further includes a signal pad 12a or signal pad 12b and a seal ring 13a or seal ring 13b.

Description

Technical Field

[0001] (Priority Claim and Cross - Reference) This application claims the benefit of U.S. Provisional Application No. 63 / 733,458, filed on December 13, 2024, and is also a partial continuation application of U.S. Non - Provisional Application No. 18 / 471,670, filed on September 21, 2023, which claims the benefit of U.S. Provisional Application No. 63 / 409,852, filed on September 26, 2022. The entire disclosure of each is hereby incorporated by reference in its entirety into this specification.

[0002] The present disclosure generally relates to memory stacks within an IC structure, and more specifically to high - bandwidth memory stacks having side - edge interconnects and 3D IC structures having the same.

Background Art

[0003] 2.5D / 3D ICs are recognized as next - generation semiconductor technologies and have the advantages of high performance, low power consumption, small size, and high integration. 2.5D / 3D ICs provide a path to reduce the complexity of the process and continue to meet the performance / cost requirements of next - generation devices while maintaining a more relaxed gate length. Therefore, 2.5D / 3D ICs are expected to find extensive benefits in applications that require "extreme" ultra - high - performance, high - power - efficiency devices such as HPC (High - Performance Computing) and data centers, AI (Artificial Intelligence) / ML (Machine Learning), 5G / 6G networks, graphics, smartphones / wearables, and automobiles.

[0004] Commercially available 2.5D / 3D ICs, such as logic-based 3D high-bandwidth memory (HBM) DRAM memory die stacks, are increasingly being used, and these HBM devices include through-silicon vias (TSVs) in both the active die and the silicon interposer. Furthermore, 2.5D / 3D ICs enable vertical stacking of heterogeneous dies from different manufacturing processes and nodes, chip reuse, and in-package chiplets (systems in a package) for high-performance applications, which is already pushing the limits of single-die architectures at state-of-the-art nodes. As shown in Figure 1, the COWOS (chips-on-wafer-on-substrate) structure 20 includes an HBM structure 21 having a TSV 201 (having multiple DRAM memory dies 211 and a controller 213), a logic die 22 (such as a GPU or SOC chip), a silicon interposer 23 having a TSV, and a packaging substrate 24. The HBM structure 21 and the logic die 22 are stacked on the silicon interposer 23, and then the silicon interposer 23 is stacked on the packaging substrate 24.

[0005] However, 2.5D / 3D ICs employ packaging topologies with bottom / top electrical interconnects created by the aforementioned interconnection technologies such as microbumps, TSVs, and redistribution layers (RDLs). Bottom / top electrical interconnects impose strict constraints on PPAC (Power, Performance, Area, and Cost) optimization by 3D IC designers, making it difficult to create optimal design solutions, particularly in forming TSVs within the semiconductor die and aligning the TSVs relative to each semiconductor die.

[0006] Furthermore, as the monolithic integration capability of silicon chips approaches TSI (Trillions of transistors on one die) from GSI (Gigascale Integration: Billions of transistors on one die), the power consumption required to operate such a vast number of transistors increases dramatically. As a result, the junction temperature of the transistors rises, and therefore, the overall temperature of the chip unfavorably increases due to the current limited heat dissipation capacity (e.g., the thermal conductivity index of silicon dioxide / silicon). Even worse, the stacking of numerous DRAM memory semiconductor dies (or HBMs) in 2.5D / 3D ICs leads to insufficient heat dissipation problems, causing high temperatures during chip operation, which is considered the worst problem with HBM structures. [Overview of the project]

[0007] According to a first aspect of this disclosure, the IC structure includes a first memory stack, the first memory stack comprising a plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads arranged along the first side wall. The area of ​​the bottom or top surface of each semiconductor die is greater than the area of ​​any side wall. The IC structure further includes a logic die having a memory controller located below the first memory stack and electrically connected to the plurality of edge pads of each semiconductor die, a logic die having a processor circuit located above the logic die having the memory controller and electrically connected to it, and a packaging substrate located below the logic die having the memory controller and processor and electrically connected to it. The die area of ​​the logic die having the memory controller is greater than the sum of the horizontal cross-sectional area of ​​the first memory stack and the die area of ​​the logic die having the processor circuit. There is no interposer between the packaging substrate and the logic die having the memory controller, and there are no TSVs within each semiconductor die.

[0008] According to some embodiments of the present disclosure, the IC structure further includes an upward-extending thermal conductive layer and / or a laterally-extending thermal conductive layer. The upward-extending thermal conductive layer is located between two adjacent semiconductor dies. The thermal conductivity of the upward-extending thermal conductive layer is higher than that of Si or SiO2. The laterally-extending thermal conductive layer covers the second sidewall of each of the plurality of semiconductor dies and is thermally coupled to the upward-extending thermal conductive layer, and the laterally-extending thermal conductive layer faces the first sidewall of the plurality of semiconductor dies, and the thermal conductivity of the laterally-extending thermal conductive layer is higher than that of Si or SiO2.

[0009] According to some embodiments of the present disclosure, the upward-extending or laterally-extending thermal conductive layer comprises undoped polysilicon, large-crystal silicon, SiC, BN, AlN, W, or copper.

[0010] According to some embodiments of the present disclosure, each semiconductor die includes a DRAM die or a memory die, and the multiple edge pads of each DRAM die include approximately 128 to 5000 edge pads, with a pitch between two adjacent edge pads being approximately 5 μm to approximately 100 μm.

[0011] According to some embodiments of the present disclosure, each semiconductor die comprises multiple edge pads including a subset of data pads, and a logic die having a memory controller selects a predetermined data width from a subset of data pads of one semiconductor die, or a subset of data pads of a plurality of semiconductor dies, or all of the data pads of a plurality of semiconductor dies.

[0012] According to some embodiments of the present disclosure, a predetermined data width selected by a logic die having a memory controller is set by a mode register in each semiconductor die.

[0013] According to some embodiments of the present disclosure, a logic die having a memory controller selects a predetermined data width from a subset of data pads of some or all of a plurality of semiconductor dies using a crossbar circuit.

[0014] According to some embodiments of the present disclosure, a logic die having a memory controller selects a predetermined data width from a subset of data pads of one, some, or all of the semiconductor dies by means of a plurality of SRAM arrays, each corresponding to a plurality of semiconductor dies, and each SRAM array temporarily holds the predetermined data width from the corresponding semiconductor die.

[0015] According to some embodiments of the present disclosure, a logical die having a memory controller includes a plurality of TSVs.

[0016] According to some embodiments of the present disclosure, the IC structure further comprises a heatsink on a logic die having a processor circuit, the top surface of the heatsink being flush with the top surface of a first memory stack.

[0017] According to some embodiments of the present disclosure, the IC structure further includes a second memory stack. The second memory stack includes a plurality of semiconductor dies and an upward-extending thermal conductive layer. The plurality of semiconductor dies are horizontally separated from each other, and each semiconductor die has a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall, with a plurality of edge pads arranged along the first side wall, and the area of ​​the bottom or top surface of each semiconductor die of the second memory stack is greater than the area of ​​any side wall. The upward-extending thermal conductive layer is located between two adjacent semiconductor dies, and the thermal conductivity of the upward-extending thermal conductive layer is higher than the thermal conductivity of Si or SiO2, and the first and second memory stacks are horizontally spaced apart from a logic die having a processor circuit and are arranged along one side of the logic die having a processor circuit.

[0018] According to some embodiments of the present disclosure, the IC structure further includes a second memory stack, a third memory stack, and a fourth memory stack. Each memory stack includes a plurality of semiconductor dies and an upward-extending thermal conductive layer. The plurality of semiconductor dies are separated horizontally from each other, and each semiconductor die has a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall, with a plurality of edge pads arranged along the first side wall, and the area of ​​the bottom or top surface is greater than the area of ​​any side wall. The upward-extending thermal conductive layer is located between two adjacent semiconductor dies, and the thermal conductivity of the upward-extending thermal conductive layer is higher than that of Si or SiO2, and the first, second, third, and fourth memory stacks are horizontally spaced apart from a logic die having a processor circuit and are arranged along the four sides of the logic die having a processor circuit.

[0019] According to some embodiments of the present disclosure, each edge pad of each semiconductor die includes an edge contact in the back-end obline (BEOL) region and a conductive via in a dielectric layer on the top surface above the edge contact, wherein the area of ​​the conductive via is larger than the area of ​​the edge contact.

[0020] According to some embodiments of the present disclosure, each edge pad of each semiconductor die includes an edge contact in a back-end obline (BEOL) region and a conductive via in a top surface redistribution layer (RDL) above the edge contact, wherein the area of ​​the conductive via is greater than the area of ​​the edge contact.

[0021] According to some embodiments of the present disclosure, the edge contact electrically connects to a signal pad in the back-end ob-line (BEOL) region of a semiconductor die surrounded by a seal ring structure.

[0022] According to some embodiments of the present disclosure, each edge pad of each semiconductor die includes a conductive wire within a redistribution layer (RDL), which is electrically connected to a signal pad in the back-end ob-line (BEOL) region of the semiconductor die, surrounded by a sealing ring structure.

[0023] According to some embodiments of this disclosure, the RDL includes a plurality of multilayer dielectric layers on which conductive wires are located.

[0024] According to some embodiments of the present disclosure, a portion of the conductive wire is configured to be placed in the scribe line region of the semiconductor wafer before the semiconductor wafer is diced.

[0025] According to a second aspect of the present disclosure, the IC structure includes a first memory stack, the first memory stack includes a plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads arranged along the first side wall. The area of ​​the bottom or top surface of each semiconductor die is greater than the area of ​​any side wall. The IC structure further includes a logic die having memory controller and processor circuits located below the first memory stack and electrically connected to the plurality of edge pads of each semiconductor die, and a packaging substrate located below the logic die having the memory controller and processor and electrically connected to it. There is no interposer between the packaging substrate and the logic die having the memory controller and processor circuits, and there are no TSVs within each semiconductor die.

[0026] According to some embodiments of the present disclosure, the IC structure further includes an upwardly extending thermal conduction layer and / or a laterally extending thermal conduction layer. The upwardly extending thermal conduction layer is disposed between two adjacent semiconductor dies. The thermal conductivity of the upwardly extending thermal conduction layer is higher than that of Si or SiO2. The laterally extending thermal conduction layer covers each second sidewall of the plurality of semiconductor dies, is thermally coupled to the upwardly extending thermal conduction layer, the laterally extending thermal conduction layer faces the first sidewall of the plurality of semiconductor dies, and the thermal conductivity of the laterally extending thermal conduction layer is higher than that of Si or SiO2.

[0027] According to some embodiments of the present disclosure, the upwardly extending thermal conduction layer or the laterally extending thermal conduction layer includes undoped polysilicon, single crystal silicon, SiC, BN, AlN, W, or copper.

[0028] According to some embodiments of the present disclosure, each semiconductor die includes a DRAM die or a memory die, the plurality of edge pads of each DRAM die includes about 128 to 5000 edge pads, and the pitch between two adjacent edge pads is about 5 μm to about 100 μm.

[0029] According to some embodiments of the present disclosure, the plurality of edge pads of each semiconductor die includes a subset of data pads, and a logic die having a memory controller selects a predetermined data width from a subset of the data pads of one semiconductor die, or a part of the plurality of semiconductor dies, or all of the plurality of semiconductor dies.

[0030] According to some embodiments of the present disclosure, the predetermined data width selected by the logic die having a memory controller is set by a mode register in each semiconductor die.

[0031] According to some embodiments of the present disclosure, a logic die having a memory controller and a processor circuit selects a predetermined data width from a subset of the data pads of a part or all of the plurality of semiconductor dies by a crossbar circuit.

[0032] According to some embodiments of the present disclosure, a logic die having a memory controller and processor circuitry includes a plurality of TSVs.

[0033] According to some embodiments of the present disclosure, the IC package further includes a heatsink on a logic die having memory controller and processor circuits adjacent to a first memory stack, the top surface of the heatsink being flush with the top surface of the first memory stack.

[0034] According to some embodiments of the present disclosure, the IC package further includes a second memory stack. The second memory stack includes a plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads arranged along the first side wall, wherein the area of ​​the bottom or top surface of each semiconductor die of the second memory stack is greater than the area of ​​any side wall. The first and second memory stacks are arranged on a logic die having a memory controller and a processor circuit.

[0035] According to some embodiments of the present disclosure, the IC package further includes a second memory stack, a third memory stack, and a fourth memory stack. Each memory stack includes a plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads arranged along the first side wall, wherein the area of ​​the bottom or top surface of each semiconductor die of the second memory stack is greater than the area of ​​any side wall. The first, second, third, and fourth memory stacks are each arranged on a logic die having a memory controller and a processor circuit.

[0036] According to a third aspect of the present disclosure, the IC structure includes a memory stack, the memory stack includes a plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads arranged along the first side wall. The area of ​​the bottom or top surface of each semiconductor die in the second memory stack is greater than the area of ​​any side wall. The IC structure further includes a logic die having a memory controller and processor circuit horizontally separated from the memory stack, and a packaging substrate below the memory stack and the logic die having the memory controller and processor circuit, the packaging substrate including an embedded multi-die interconnect bridge (EMIB) structure electrically connected to the memory stack and the logic die having the memory controller and processor circuit. There is no interposer between the packaging substrate and the logic die having the memory controller and processor circuit, and there are no TSVs within each semiconductor die.

[0037] According to some embodiments of the present disclosure, the IC structure further includes an upward-extending thermal conductive layer and / or a laterally-extending thermal conductive layer. The upward-extending thermal conductive layer is located between two adjacent semiconductor dies. The thermal conductivity of the upward-extending thermal conductive layer is higher than that of Si or SiO2. The laterally-extending thermal conductive layer covers the second sidewall of each of the plurality of semiconductor dies and is thermally coupled to the upward-extending thermal conductive layer, and the laterally-extending thermal conductive layer faces the first sidewall of the plurality of semiconductor dies, and the thermal conductivity of the laterally-extending thermal conductive layer is higher than that of Si or SiO2.

[0038] According to some embodiments of the present disclosure, each semiconductor die includes a DRAM die, and the multiple edge pads of each DRAM die include approximately 128 to 5000 edge pads.

[0039] According to some embodiments of the present disclosure, a logic die having a memory controller and processor circuitry includes a plurality of TSVs.

[0040] According to some embodiments of the present disclosure, each edge pad of each semiconductor die includes an edge contact in the back-end obline (BEOL) region and a conductive via in a dielectric layer on the top surface above the edge contact, wherein the area of ​​the conductive via is larger than the area of ​​the edge contact.

[0041] According to some embodiments of the present disclosure, each edge pad of each semiconductor die includes an edge contact in a back-end obline (BEOL) region and a conductive via in a top surface redistribution layer (RDL) above the edge contact, wherein the area of ​​the conductive via is greater than the area of ​​the edge contact.

[0042] According to some embodiments of the present disclosure, the edge contact electrically connects to a signal pad in the back-end ob-line (BEOL) region of a semiconductor die surrounded by a seal ring structure.

[0043] According to some embodiments of the present disclosure, each edge pad of each semiconductor die includes a conductive wire within a redistribution layer (RDL), which is electrically connected to a signal pad in the back-end ob-line (BEOL) region of the semiconductor die, surrounded by a sealing ring structure.

[0044] According to some embodiments of this disclosure, the RDL includes a plurality of multilayer dielectric layers on which conductive wires are located. [Brief explanation of the drawing]

[0045] The aspects of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in this industry, various structures are not drawn to scale. In fact, the dimensions of various structures may be arbitrarily enlarged or reduced for illustrative purposes.

[0046] [Figure 1] This disclosure shows a semiconductor COWOS structure according to a comparative embodiment.

[0047] [Figure 2A] The following are cross-sectional views of structures at different stages of a method for manufacturing an integrated circuit (IC) structure according to some embodiments of this disclosure. [Figure 2B] The following are cross-sectional views of structures at different stages of a method for manufacturing an integrated circuit (IC) structure according to some embodiments of this disclosure. [Figure 2C] The following are cross-sectional views of structures at different stages of a method for manufacturing an integrated circuit (IC) structure according to some embodiments of this disclosure.

[0048] [Figure 2D] Perspective views of the redistribution layer according to various embodiments of this disclosure are shown.

[0049] [Figure 2E] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown. [Figure 2F] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown.

[0050] [Figure 2G] Figures 2B, 2C, 2E, and 2F show cross-sectional views of the redistribution layer of the IC structure according to various embodiments of this disclosure.

[0051] [Figure 3A] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure. [Figure 3B] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure. [Figure 3C] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure. [Figure 3D] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure.

[0052] [Figure 3E]Cross-sectional views of IC structures according to various embodiments of this disclosure are shown. [Figure 3F] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown.

[0053] [Figure 4A] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure. [Figure 4B] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure. [Figure 4C] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure. [Figure 4D] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure. [Figure 4E] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure. [Figure 4F] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure. [Figure 4G] The following are cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of this disclosure.

[0054] [Figure 4H] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown. [Figure 4I] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown. [Figure 4J] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown. [Figure 4K] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown. [Figure 4L] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown. [Figure 4M] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown. [Figure 4N] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown.

[0055] [Figure 5A] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown. [Figure 5B] Cross-sectional views of IC structures according to various embodiments of this disclosure are shown.

[0056] [Figure 5C] Figures 5A and 5B show cross-sectional views of the interconnection structure of the IC structure shown in Figures 5A and 5B according to various embodiments of the present disclosure.

[0057] [Figure 6A] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 6B] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 6C] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 6D] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 6E] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure.

[0058] [Figure 7A] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7B] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7C] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7D]This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7E] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7F] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7G] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure. [Figure 7H] This disclosure shows cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of this disclosure.

[0059] [Figure 7I] Cross-sectional views of semiconductor packages according to various embodiments of this disclosure are shown. [Figure 7J] Cross-sectional views of semiconductor packages according to various embodiments of this disclosure are shown.

[0060] [Figure 8A] The following are perspective views of memory dies having multiple edge pads according to some embodiments of the present disclosure. [Figure 8B] The following are cross-sectional views of memory dies having multiple edge pads according to some embodiments of the present disclosure.

[0061] [Figure 8C] The following are cross-sectional views of a semiconductor wafer including a memory die having multiple edge pads, according to some embodiments of the present disclosure.

[0062] [Figure 8D] The following is a cross-sectional view of another memory die having multiple edge pads according to some embodiments of the present disclosure. [Figure 8E] The following is a cross-sectional view of another memory die having multiple edge pads according to some embodiments of the present disclosure.

[0063] [Figure 9A] A perspective view of a conventional high-bandwidth memory (HBM) structure is shown.

[0064] [Figure 9B] Perspective views of novel high-bandwidth memory (NuHBM) stacks or shelves according to some embodiments of the present disclosure are shown.

[0065] [Figure 10A] An exemplary layout 40a of low-power double data rate 5 (LPDDR5) memory according to some embodiments of the present disclosure is shown. [Figure 10B] The following table shows the specifications for low-power double data rate 5 (LPDDR5) memory according to some embodiments of this disclosure.

[0066] [Figure 11] The following are cross-sectional views of intermediate stages in forming a NuHBM stack or shelf according to some embodiments of the present disclosure.

[0067] [Figure 12A] This disclosure shows IC structures having NuHBM shelves according to some embodiments. [Figure 12B] This disclosure shows IC structures having NuHBM shelves according to some embodiments. [Figure 12C] This disclosure shows IC structures having NuHBM shelves according to some embodiments.

[0068] [Figure 13A] This disclosure shows another IC structure having a NuHBM shelf according to some embodiments. [Figure 13B] This disclosure shows another IC structure having a NuHBM shelf according to some embodiments.

[0069] [Figure 14A]This disclosure shows another IC structure having a NuHBM shelf according to some embodiments. [Figure 14B] This disclosure shows another IC structure having a NuHBM shelf according to some embodiments.

[0070] [Figure 15A] This disclosure shows another IC structure having multiple NuHBM shelves according to some embodiments. [Figure 15B] This disclosure shows another IC structure having multiple NuHBM shelves according to some embodiments.

[0071] [Figure 16] This disclosure shows another IC structure having multiple NuHBM shelves according to some embodiments.

[0072] [Figure 17A] Cross-sectional views of semiconductor package assemblies according to various embodiments of this disclosure are shown. [Figure 17B] Cross-sectional views of semiconductor package assemblies according to various embodiments of this disclosure are shown. [Modes for carrying out the invention]

[0073] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. For the sake of brevity, specific examples of components and configurations are described below. Naturally, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, or it may include embodiments in which an additional feature can be formed between the first and second features so that they do not come into direct contact. Furthermore, in various examples in this disclosure, reference numbers and / or letters may be repeated. This repetition is for the purpose of simplification and clarity and does not in itself indicate relationships between the various embodiments and / or configurations discussed.

[0074] Furthermore, spatially relative terms such as “downward,” “below,” “bottom,” “upward,” “top,” and “above” may also be used herein to describe the relationship between one element or feature and another, as shown in the drawings for the sake of clarity. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. The device may be oriented in a different orientation (it may be rotated 90° or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0075] When used herein, terms such as “first,” “second,” and “third” describe various elements, components, areas, layers, and / or sections, but these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, area, layer, or section from another. When used herein, terms such as “first,” “second,” and “third” do not imply a sequence or order unless explicitly indicated by the context.

[0076] Embodiments of the present invention disclose methodologies, processes, and subsequents (details of which are described below) for creating redistribution layers (RDLs) and interconnections (e.g., through-silicon vias, molded through-vias, metal vias, metal pads for copper hybrid bonding, and microbumps or solder bumps for flip-chip assemblies) on four sides of a 3D IC and a short 3D IC structure stack, wherein each stack layer consists of one or more ICs in the xy direction (in-plane direction) and the z direction (out-of-plane direction or IC thickness direction).

[0077] Embodiments of the package structure proposed in this disclosure enable at least the following features: (a) 5-sided power and signal distribution (penetrating the front and four sides of the 3D IC package); (b) skip die and multi-sided interconnects through the four sides and / or internal interconnects using a combination of RDL, TSV, and through-mold vias (TMV) (e.g., directly reaching the top die and other ICs in the stack from the substrate such as the bottom die or interposer); (c) RDL on the sides interconnected in three dimensions by the use of flexible printed circuit (Flex); and (d) the ability to use a variety of interconnection techniques covering RDL, TSV, microbumps, solder bumps, copper hybrid junctions, and fine-pitch Flex. Thus, the proposed package structure can effectively shorten the length of global and IC packaging interconnection paths and increase the number of transistors accessed within one clock cycle.

[0078] In this invention, the sides of the memory die are used for interconnecting dies within a 2.5D / 3D IC stack, enabling signal and power distribution through the die. Furthermore, a high thermal conductivity material is placed between two adjacent memory dies and thermally coupled to another high thermal conductivity material covering the other sides of the memory die stack.

[0079] Figures 2A to 2C show cross-sectional views of structures at different stages of a method for manufacturing an IC structure 100A according to some embodiments of the present disclosure. According to some embodiments, the IC structure 100A shown in Figure 2C is a semiconductor package device. The IC structure 100A may be formed from a semiconductor device 100W which is a wafer-level device, and the IC structure 100A is formed by separating the semiconductor device 100W using a singulation or dicing process that covers mechanical dicing, laser dicing, plasma etching or dicing, dry etching, wet etching (e.g., using acid etching), or a combination thereof.

[0080] Referring to Figure 2A, a semiconductor device 100W is accepted or provided. First, a substrate 102 is provided or accepted. According to some embodiments, the substrate 102 is formed of a semiconductor material such as bulk silicon. According to some embodiments, the substrate 102 is formed of other semiconductor materials such as silicon germanium, silicon carbide, or gallium arsenide. In this embodiment, the substrate 102 is a P-type semiconductor substrate (acceptor type). In some other embodiments, an N-type semiconductor substrate (donor type) can be used. Alternatively, the substrate 102 includes another elemental semiconductor such as germanium; a compound semiconductor including gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimony; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof. In yet another embodiment, the substrate 102 includes a portion forming a semiconductor on-insulator (SOI) substrate. In other embodiments, the substrate 102 may include semiconductor layers covering different types of semiconductor layers, such as a doped epitaxial layer, a gradient semiconductor layer, and / or a silicon layer on a silicon germanium layer.

[0081] Multiple conductive vias 104 are formed on the substrate 102. The conductive vias 104 may extend from the primary surface 102P1 of the substrate 102 to the thickness of the substrate 102. Throughout this disclosure, the “primary surface” is used to indicate the top or bottom surface of a circuit or device and has the largest surface area among the six surfaces of the device or layer. Similarly, the “secondary surface” is used to indicate the side surfaces of a circuit or device (there are often four such sides of a circuit or device) and has a smaller surface area than the primary surface. The conductive vias 104 may include conductive materials such as copper, tungsten, molybdenum, cobalt, ruthenium, titanium, tantalum, aluminum, silver, gold, or other suitable materials. The conductive vias 104 may include a single-layer or multilayer structure which may include a diffusion barrier layer, a seed layer to aid in electroplating, a filler layer, or a combination thereof.

[0082] In an exemplary process for forming conductive vias 104, a number of holes (not shown) are formed on the primary surface 102P1 of the substrate 102. The holes may be formed using dry etching (e.g., reactive ion etching, RIE), wet etching, or a combination thereof. After the holes are formed, the openings of the holes can be passivated by depositing silicon dioxide using a deposition process, such as plasma chemical vapor deposition (PECVD), or by performing physical vapor deposition (PVD), sputter deposition, atomic layer deposition (ALD), or other suitable deposition operations to deposit the material for the conductive vias 104 inside the holes and on the primary surface 102P1. The conductive vias 104 may be referred to herein as through-silicon vias (TSVs) after the hole-filling process.

[0083] According to some embodiments, a planarization process, such as chemical mechanical planarization (CMP), dry etching (e.g., using RIE), grinding, wet etching, and / or other suitable etching operations, is performed to remove excess conductive material and planarize the upper surface of the conductive vias 104 so that they are coplanar with the primary surface 102P1. Following planarization, primary RDL 108A is deposited on the primary surface 102P1, which is then surface-finished and padded for subsequent bonding as needed.

[0084] Referring to Figure 2B, another substrate or temporary carrier 106 is provided or accepted, and the semiconductor structure 100W is bonded to the temporary carrier 106. According to some embodiments, the substrate 106 is a carrier substrate or a support substrate. The carrier substrate 106 may be formed from glass, silicon, ceramic, or other suitable carrier material. A release layer 110 is formed on the carrier substrate 106. Examples of release layers include release / adhesion layers commonly used in fan-out processes. The release layer 110 is a temporary layer formed on the carrier substrate 106, which can allow for easier removal of the carrier substrate 106 from the semiconductor device 100W by laser irradiation, thermomechanical delamination, grinding, CMP, dry or wet etching / cleaning, or a combination thereof.

[0085] In addition to the release layer used in the fan-out process, the release layer may be a combination of Ti (titanium) / Au (gold) on the carrier and Ti / Au on the back surface of the IC structure. Here, Au may be Cu (copper) or double-sided solder. Bonding between the carrier and the IC structure can also be achieved using compression or reflow bonding. Annealing is optional and can be performed as needed. When silicon is used as the carrier, the release layer may be SiO2, Si3N4, etc., which are common in wafer BEOL and / or MEMS / NEMS processing. Such a release layer may also serve as a permanent bonding layer between IC structures (such as those shown in Figure 7B).

[0086] Pre-bonding preparation of the carrier and IC structure surface may include the following: For both diamond and silicon, chemical mechanical polishing (CMP) is performed as needed, preferably, to achieve a surface roughness RA (arithmetic mean roughness or sometimes root mean square roughness) < 1 nm. This level of RA can be achieved by CMP for silicon, and by a combination of sacrificial SiO2 layer deposition and SiO2 planarization by CMP and deep reactive ion etching (DRIE) for diamond. Wet surface pretreatment including ultrasonic deionization (DI) water purification, H2SO4 / H2O2 treatment, NH3 / H2O2 treatment, and N2 blow drying. • Plasma / Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE): O2, H2 / O2 • Deep-dive RIE (DRIE): O2 / CF4, and Prior to bonding using a high-speed atomic beam gun, FAB (e.g., using an argon neutral atomic beam of approximately 1 keV), or ion gun (e.g., using argon ions of approximately 60 eV), the bonding surface inside the bonding machine is activated (with or without glue layers) to remove the oxide film in a vacuum and expose the dangling bond on the surface for bonding. (Note 1: FAB works well on (sputtered) Si / Si, Si / SiO2, metals, compound semiconductors, and single-crystal oxides, while ion guns are known to work on SiO2 / SiO2, glass, Si3N4 (silicon nitride) / Si3N4, Si / Si, Si / SiO2, metals, compound semiconductors, and single-crystal oxides.) ·(Note 2:10 -6 A Pascal vacuum is required during bonding to prevent re-adsorption to the activated bonding surface.

[0087] In addition to the direct bonding approach described above, ultrathin adhesives or bonding layers such as CVD polysilicon (poly-Si) can be deposited as permanent bonding layers on the interlocking IC structure (Figure 7B) or as temporary delamination layers on both the IC structure and the carrier to achieve high low-temperature direct bonding yields. For heat-sensitive applications, poly-Si (with a thermal conductivity TC more than 100 times that of SiO2) is preferred over SiO2 for use in forming thin bonding layers, as it minimizes the impact of thermal resistance on the final IC or package structure. The adhesive layers are typically extremely thin, about 100 nm or less, to minimize their thermal effects. When used as permanent layers, materials with higher TC and lower thermal expansion are preferred. Candidate adhesive layers include the following and combinations (or alloys) thereof: Nonmetals: Si (e.g., polysilicon), SiO2, Si3N4, Al2O33 (alumina), diamond, boron nitride, graphene Metals: Ti, W, Pt, Cr, Au, Cu, Ir, Nickel (Ni), Iron (Fe), Ag-In, Au-In, Ag, Sn, Mo • Oxides on oxides: Ir on SrTiO3, Ir on YSZ / Si, MgO, sapphire, or Ir on TaO3

[0088] When using a metal adhesive layer to bond IC structures (see, for example, Figure 7B), it is desirable to deposit a barrier layer such as Ti on the back side of the IC structure before depositing the adhesive layer to prevent metal diffusion within the silicon lattice, which could damage the device. This is especially true for ultrathin ICs. Diamond growth on silicon seeds is a common practice during diamond CVD. Silicon nitride (Si3N4) is common in wafer BEOL processing. Alumina can be deposited by atomic layer deposition. In addition to diamond, graphene is also a material worth considering due to its extremely high thermal conductivity. In a single layer, graphene can have a thermal conductivity of 30-50 W / cm·K. This can be considered an adhesive or bonding layer, assuming a suitable 3D molecular structure. Graphene can be grown on a silicon(100) surface using direct cobalt-assisted two-step ion beam synthesis. It can also be grown on silicon by a simple transfer-free synthesis method. Epitaxial graphene can be grown on crystalline and semi-insulating surfaces (e.g., SiC and silicon), and graphene nanostructures with excellent properties have been realized by selective growth processes on SiC surfaces. In addition to diamond and graphene, cubic boron nitride is also noteworthy, as it is known to have a crystalline structure similar to diamond and a high in-plane TC (~16 W / cm·K). Furthermore, the adhesive layer can be a combination of Ti / Au on one IC structure and Ti / Au on the back surface of another IC structure for bonding. A thin metallization based on Ti, W, or Cr can also be deposited before Au deposition, if necessary. Thin layers of transient liquid bonding materials such as silver-indium (Ag-In) and Au-In, sintered Ag, In, Au, or Cu can also be applied together with coherent metallization (e.g., Au, Ag, or Cu). The adhesive layer can be deposited by CVD, atomic layer deposition (ALD), physical vapor deposition, thermal oxidation (in the case of silicon), or other means.After deposition, the adhesive layer can be prepared through a combination of the aforementioned pre-bonding surface pretreatment, DRIE (e.g., using a mixture of SF6 and O2), plasma / ICP-RIE (using O2, Ar, N2, Ar / O2), and FAB (e.g., using neutral Ar atoms) or ion gun (e.g., using Ar ions) at the bonding station.

[0089] Following the creation of the primary RDL108A, the planarized structure having the primary RDL108A is bonded to the substrate 106 via a delamination layer, and the bulk portion of the substrate 102 beneath the conductive via 104 is removed, exposing the bottom surface of the conductive via 104 (see Figure 2B). Another RDL108B can then be deposited on the exposed conductive via 104 in Figure 2B, and completed with surface finishing and solder bumps or microbumps as needed. Following the formation of the RDL108B, the mounting of the resulting structure having RDL108A and 108B on the carrier 106 on the wafer mount tape frame, the release of the carrier 106, and the individualization of the packages, the semiconductor structure 100A in Figure 2C is formed.

[0090] Based on the processes shown in Figures 2A to 2C, various layers and structures can be formed to create semiconductor structures 100A including exposed edge pads, edge vias, and edge TSVs that can completely or partially penetrate the thickness of silicon or potting material or a subset thereof, for example, a structure including only RDL108A having edge pad / via interconnects within the RDL (Figure 2E), or a structure including both RDL108A having edge interconnects and edge TSVs (see Figure 2F).

[0091] According to some embodiments, the release layer 110 comprises a polymer-based material. According to some embodiments, the release layer 110 is an epoxy-based thermal release material, such as a photothermal conversion (LTHC) release coating, which loses its adhesive properties when heated or exposed to a laser. According to other embodiments, the release layer 110 is an ultraviolet (UV) adhesive, which loses its adhesive properties when exposed to UV light. The release layer 110 may be a thermoplastic or thermosetting material. According to some embodiments, the release layer 110 comprises a polyimide or silicone-based material. According to some other embodiments, the release layer 110 is a mixture of metallic and nonmetallic materials. Candidate metallic materials for the release layer may include nickel, chromium, titanium, gold, copper, manganese, iron, cobalt, tungsten, molybdenum, ruthenium, and tantalum, while nonmetallic candidates may include metal oxides, nitrides, phosphates, and chromates. The release layer 110 may be deposited as a liquid by spin coating and cured. In other embodiments, the release layer 110 may be a laminate film laminated on the carrier substrate 106. In some other embodiments, bonding between the substrate 102 and the temporary carrier 106 may be achieved without requiring the release layer 110, for example, by direct bonding based on oxide-oxide or polyimide-polyimide.

[0092] RDL108A is part of the interconnection structure 101 of IC structure 100A. RDL108A includes one or more interconnected conductive paths formed through one or more conductive wires in a conductive wire layer and one or more conductive vias (not shown separately) in a conductive via layer for routing power and signals of a first circuit from one side of RDL108A to a second circuit on the same or opposite side of RDL108A. RDL108A may include a sealing material (or a sealing material such as a polyimide or oxide layer to facilitate direct or copper hybrid bonding) that seals the conductive wire layer and the conductive via layer. According to some embodiments, the sealing material includes one or more dielectric materials, e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide, a combination thereof, or equivalents. Using RDL108A of interconnection structure 101, the distribution of signals and power of devices or circuits in IC structure 100A can meet design requirements. Throughout this disclosure, an RDL formed on the primary surface of a circuit or device, for example, the primary surface 102P1, e.g., an RDL108A, is referred to as a primary RDL108A. Further structural details of the primary RDL108A are discussed below.

[0093] According to some embodiments, the substrate 102 is placed on and bonded to the primary RDL 108A. Bonding of the substrate 102 to the primary RDL 108A may be performed using thermal bonding, thermocompression bonding, flip-chip bonding, hybrid bonding, etc. Although not shown, conductive vias 104 of the substrate 102 are electrically coupled to one of the conductive wires or one of the conductive vias of the primary RDL 108A to extend the signal delivery network or power delivery network of the RDL 108A. Furthermore, the upper portion of the substrate 102 is removed or thinned from the top portion of the substrate 102. The bottom surface of the conductive vias 104 is exposed accordingly. Removal or thinning of the upper portion of the substrate 102 may be performed using CMP, grinding, dry etching (e.g., RIE), wet etching, etc. Conductive vias 104 become TSV 104 accordingly.

[0094] Referring to Figure 2C, the structure having RDL108A and RDL108B is mounted on a wafer mount frame, and after releasing the carrier 106, a fragmentation or dicing process is performed to separate the semiconductor device 100W into individual IC structures 100A. The fragmentation or dicing process may be performed using a diamond blade, a laser, plasma with a masking layer deposited on RDL108A, for example, wet etching, or a combination thereof to fragment the semiconductor device 100W along the scribe lines and form individual IC structures 100A. The interconnection structure 101 within the IC structure 100A comprises a TSV die 122A, an internal interconnection structure 108X such as internal pads and vias in RDL108A and 108B, and an edge interconnection structure 118X such as edge pads and vias in RDL.

[0095] During dicing or fragmentation, the area to be cut off is called the dicing, saw, or die street, and is typically 50 μm to 100 μm wide. The dicing saw may use a diamond blade that rotates at 30,000 rpm and is cooled with deionized water. To expose edge pads or vias, the size of the edge pads or vias is comparable to the dicing street width, and dicing is preferably performed in close proximity to the edge pads or vias (but not directly through them), followed by light wet etching of silicon as needed and to be ensured. To minimize bottom-side chipping during mechanical blade dicing, it may be advantageous to first dice the wafer with a carrier support and then peel off the carrier. Laser ablation dicing, which can allow for a dicing street width of 10 μm, may also use a non-contact laser to first remove a fine wire layer on the surface of the dicing street (and expose the adjacent edge pad), followed by cutting the residual substrate by laser scribing and / or blade dicing. This process reduces problems such as chipping, die cracking, and delamination. In laser ablation dicing, the laser heats the material to a temperature such that the area beneath the laser spot is ablated or simply vaporized. Alternatively, dicing can be performed by dry, liquid-free stealth dicing. Stealth dicing functions as a two-step process, in which a laser beam (e.g., a pulsed Nd:YAG laser with a wavelength of 1064 nm for silicon) is first directed to scan along the intended cutting line, creating a defect region, and then the underlying film (adhered to the wafer and subsequently released from the wafer carrier) is expanded, inducing fracture. Stealth laser dicing has the potential to replace blade dicing as a next-generation ultrathin wafer dicing technology to support 3D IC packaging, as stealth lasers enable faster, more accurate, less damaging, and smaller dicing street widths.Compared to mechanical and laser dicing, plasma dicing (also known as deep reactive ion etching) is a relatively new method that applies the Bosch dry etching process, which allows dies to be cut with high precision and be free of particles and contamination. This method requires custom mask design for effective plasma dicing. This method uses a plasma gas such as sulfur hexafluoride to etch all narrow dicing streets into the wafer simultaneously, resulting in high precision, throughput, and quality. Plasma dicing can produce cuts with non-rectangular shapes beyond the range of blade dicing. Because plasma dicing minimizes damage to the wafer surface or trench sidewalls, it results in better die strength, improved device reliability, and a longer device lifespan. Plasma dicing is rapidly gaining popularity within the semiconductor industry as a preferred solution, especially as chips become smaller, thinner, and more complex.

[0096] As a result of the dicing or fragmentation process, the IC structure 100A includes four secondary planes or sides 100AS, although Figure 2D shows only two secondary planes 100AS. The TSV die 122A includes sides 102S on its four sides, while the primary RDL 108A and primary RDL 108B include sides 108S on their four sides. The sides 102S of the TSV die 122A and the sides 108S of the two primary RDLs 108A and 108B together constitute or coincide with the secondary plane 100AS of the IC structure 100A. Through appropriate arrangement, the TSV 104 is formed on the TSV die 122A and, after the dicing or dicing process, comprises two TSV types (internal TSV 104A and edge TSV 104B), where the internal TSV 104A is completely surrounded by the substrate 102 and primary RDLs 108A and 108B, while the edge TSV 104B has at least one side exposed through the side surface 102S of the substrate 102.

[0097] Similarly, the primary RDL 108A or 108B includes conductive pads 212 and conductive vias 214, respectively, formed from conductive elements 202 such as conductive wires and conductive vias, and the conductive element 202 includes two parts (internal conductive element 202 and edge conductive element 202). By appropriate arrangement, the conductive pads 212 and conductive vias 214 are formed on the IC structure 100A and, after the dicing or dicing process, include two parts (internal conductive pads / vias 212 and 214, and edge conductive pads / vias 212 and 214), the internal conductive pads / vias 212 and 214 are completely surrounded by the substrate material and encapsulating material of the two primary RDLs 108A and 108B, while the edge conductive pads / vias 212 and 214 have at least one side exposed through the side 108S of the primary RDL, 108A or 108B.

[0098] According to some embodiments, the edge conductive pad 212 has at least one upper surface exposed through the primary surface 108P of the primary RDL 108A or 108B. The internal or edge conductive pad 212 may be positioned on the uppermost conductive wire layer of each primary RDL 108A or 108B that is furthest distal to the TSV die 122A. According to some embodiments, the conductive pad 212 is positioned parallel to the primary surface 108P of the primary RDL 108A or 108B. The conductive pad 212 may stop in front of the TSV die 122A. Furthermore, the edge conductive pad 212 has at least one side surface exposed through the secondary plane 100AS of the IC structure 100A or the secondary surface 108S of the primary RDL 108A or 108B.

[0099] Similarly, according to some embodiments, the edge conductive via 214 has at least one upper surface exposed through the primary surface 108P of the primary RDL 108A or 108B. The edge conductive via 214 may be arranged to extend through the thickness (z-direction) of each primary RDL 108A or 108B. According to some embodiments, the edge conductive via 214 is referred to herein as the TSV of the primary RDL 108A or 108B. Furthermore, the edge conductive via 214 has at least one side surface exposed through the secondary plane 100AS of the IC structure 100A or the secondary surface 108S of the primary RDL 108A or 108B.

[0100] Figure 2D shows a perspective view of a primary RDL 108A or 108B according to various embodiments of the present disclosure. The primary RDL 108A or 108B includes a primary surface 108P (e.g., an upper primary surface 108P1 and a lower primary surface 108P2) and four secondary (side) surfaces 108S (e.g., a front secondary surface 108S1, a rear secondary surface 108S2, a right secondary surface 108S3, and a left secondary surface 108S4). Multiple conductive elements 202, such as conductive pads / vias 212, are formed on the primary RDL 108A or 108B and exposed through the four secondary surfaces 108S. The arrangement of conductive pads 212 on the primary RDL 108A or 108B in Figure 2D is shown for illustrative purposes only. Conductive pads 212 or other conductive elements may be formed or exposed through one or more of the four secondary surfaces 108S.

[0101] As described above, throughout this disclosure, the TSV 104 (see 104A and 104B in Figure 2C), the conductive pad 212, the conductive via 214, and all other conductive members of the interconnect structure 101 in Figure 2C are part of what is collectively referred to as the conductive elements 202 within the interconnect structure 101 of the IC structure 100A. The TSV 104, the conductive pad 212, and the conductive via 214 are configured to form at least a portion of the interconnect structure 101 of the IC structure 100A for fan-in or fan-out interconnects for device or package layers electrically coupled to the IC structure 100A, through the two primary surfaces 108P in Figure 2C of the IC structure 100A (i.e., the upper primary surface 108P1 and the lower primary surface 108P2; see Figure 2D), and through the four secondary surfaces 108S1 to 108S4 of the IC structure 100A (see Figure 2D). According to some embodiments, the TSVs 104 and conductive vias 214 of primary RDLs 108A and 108B can be coupled to form a combined TSV of IC structure 100A. For example, the right-side conductive via 214 of primary RDL 108A (Figure 2C), the right-side TSV 104, and the right-side conductive via 214 of primary RDL 108B constitute a stacked edge TSV of IC structure 100A that extends through the substrate thickness of IC structure 100A.

[0102] Figure 2E shows a cross-sectional view of IC structure 100B according to various embodiments of the present disclosure. IC structure 100B is similar to IC structure 100A in many embodiments, for example, in the primary RDL 108A, conductive pad 212, and conductive via 214, and therefore details of such similar embodiments will not be repeated for brevity. The main difference between IC structure 100A and IC structure 100B is that the TSV die 122A in IC structure 100A is replaced by the semiconductor die 122B in IC structure 100B, and the primary RDL 108B in IC structure 100A is absent in IC structure 100B. According to some embodiments, the semiconductor die 122B may be at least one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, memory die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die. The semiconductor die 122B may include a substrate 102 containing a material similar to that of the substrate 102 of the IC structure 100A shown in Figure 2D. Thus, the semiconductor die 122B constitutes the substrate or body of the IC structure 100B. According to some embodiments, the semiconductor die 122B does not include the edge interconnect structure 118X exposed through the side surface 102S of the semiconductor die 122B.

[0103] Figure 2F shows a cross-sectional view of IC structure 100C according to various embodiments of the present disclosure. IC structure 100C is similar to IC structure 100B in many embodiments, for example, in the primary RDL 108A, conductive pad 212, and conductive via 214, and therefore details of such similar embodiments are not repeated for brevity. Furthermore, IC structure 100C includes a semiconductor die 122C, which may be at least one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, memory die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die. Semiconductor die 122C may include a substrate 102 similar to the substrate 102 of IC structure 100A shown in Figure 2D. The main difference between semiconductor die 122C and semiconductor die 122B is that semiconductor die 122C further includes edge interconnection structures 118X, such as edge conductive pads 222, exposed through the secondary plane or side surface 102S of semiconductor die 122C. According to some embodiments, the edge conductive pads 222 are electrically connected to conductive vias 214 of the primary RDL 108A to establish stacked conductive vias for semiconductor die 122C. Thus, semiconductor die 122C constitutes the body of IC structure 100C.

[0104] Figure 2G shows a cross-sectional view of the primary RDL 108A or 108B of the IC structures 100A, 100B, or 100C shown in Figures 2B to 2F, according to various embodiments of the present disclosure. As shown in Figure 2G, the primary RDL 108A or 108B is formed of a first major conductive line / via layer 240 and a second major conductive line / via layer 250 located beneath the first major conductive line / via layer 240. Each of the first major conductive line / via layer 240 and the second major conductive line / via layer 250 contains one or more conductive lines and conductive vias extending horizontally or vertically (all of which are part of a collection of conductive elements 202 of the interconnection structure 101 within the primary RDL 108A or 108B). The conductive lines or vias are electrically insulated by a dielectric layer called an intermetallic dielectric (IMD) layer. The IMD layer may contain one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, polyimide, or other suitable dielectric materials. Some of the conductive vias in the first main conductive wire / via layer 240 extend halfway vertically, while some of the conductive vias in the first main conductive wire / via layer 240, for example conductive via 214-1, extend through the entire thickness of the first main conductive wire / via layer 240. Similarly, some of the conductive vias in the second main conductive wire / via layer 250 extend partway vertically, while some of the conductive vias in the second main conductive wire / via layer 250, for example conductive via 214-2, extend through the entire thickness of the second main conductive wire / via layer 250. Conductive vias 214-1 and 214-2 are electrically connected to form a laminated conductive via 214 of the primary RDL 108A or 108B that traverses the primary RDL 108A or 108B. According to some embodiments, the first main conductive wire / via layer 240 includes two conductive wire layers and a conductive via layer between the two conductive wire layers, and the conductive via 216 is located within the conductive via layer to electrically connect two conductive wires in adjacent conductive wire layers. Referring to Figures 2F and 2G, the conductive via 214 of the IC structure 100C shown in Figure 2F is considered a conductive via connecting adjacent first and second main conductive wire / via layers 240 and 250.According to some embodiments, the laminated conductive via 214 is part of the edge interconnect structure 118X and is exposed through the secondary surface 108S of the primary RDL 108A or 108B. Figure 2G shows only two main conductive wire / via layers 240 and 250, but the disclosure is not limited thereto. A number of other main conductive wire / via layers and the configuration of conductive wires or conductive vias in each main conductive wire / via layer are also within the scope intended by the disclosure.

[0105] Figures 3A to 3D show cross-sectional views of structures at different stages of a method for manufacturing an IC structure 300A according to some embodiments of the present disclosure. According to some embodiments, the IC structure 300A shown in Figure 3D is a semiconductor package device. The IC structure 300A may be formed from a semiconductor device 300W which is a wafer-level device, and the IC structure 300A is formed by separating the semiconductor device 300W using a dicing or dicing process.

[0106] Referring to Figure 3A, a carrier substrate 106 is received or provided. Also, as in Figures 2A-2C, a release layer 110 is formed on the carrier substrate 106. Multiple semiconductor dies 122D are placed on the release layer 110. The semiconductor dies 122D may include at least one of CPU dies, GPU dies, TPU dies, MEMS dies, AP dies, FPGA dies, ASIC dies, memory dies, transceiver dies, network interface dies, integrated photonics dies, packet buffer / router dies, or other suitable dies. Furthermore, multiple conductive pillars or vias 232 are formed on the release layer 110 between adjacent semiconductor dies 122D with a suitable pitch and encapsulated by a molding compound or a suitable potting material (epoxy, e.g., Epotek 377) as shown in Figure 3B. The conductive vias 232 may be created alternately within the semiconductor dies 122D. Multiple semiconductor dies 122D and conductive vias (pillars) 232 are referred to herein as a reconfigured structure and are arranged on the delamination layer 110 or the carrier surface 110S of the carrier substrate 106. The conductive vias 232 may contain a conductive material, such as tungsten, copper, titanium, tantalum, molybdenum, ruthenium, cobalt, aluminum, silver, gold, or another suitable material. Multiple semiconductor dies 122D and conductive vias 232 may have substantially equal heights. According to some embodiments, the semiconductor dies 122D and conductive vias 232 are arranged on the delamination layer 110 by a pick-and-place bonding process.

[0107] Referring to Figure 3B, the reconfigured structure of the semiconductor device 300W is formed or sealed using a potting material (e.g., sealing material, molding material, or insulating element) 242. The potting material 242 may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, epoxy-based molding materials, and polymer materials. The forming or deposition process is performed to deposit the potting material 242 between the semiconductor die 122D and the conductive vias 232, which can be created before bonding the semiconductor die 122D and depositing the potting material. According to some embodiments, a planarization process, e.g., CMP, grinding, wet etching, dry etching (e.g., RIE), and / or another preferred etching operation is performed to remove excess potting material 242, planarize the top surface of the potting material 242, and expose the conductive vias 232 from the top surface of the semiconductor die 122D. According to some embodiments, the conductive via 232 is located within the potting material 242 and is thereby enclosed laterally; therefore, the conductive via 232 is also referred to herein as a through-molding via (TMV) 232.

[0108] Referring to Figure 3C, the primary RDL108A is formed on the potting material 242, the semiconductor die 122D, and the upper surface of the TMV232. The material, configuration, and method for forming the primary RDL108A are the same as those described with reference to Figures 2B to 2G, and a repeated description of the primary RDL108A is omitted for brevity.

[0109] Referring to Figure 3D, the dicing or fragmentation process is performed to separate the semiconductor device 300W into individual IC structures 300A. Furthermore, the carrier substrate 106 is removed or detached from the semiconductor device 300W by peeling off the delamination layer 110 from the semiconductor device 300W. By appropriate arrangement, conductive pads / vias 212 / 214 are formed on the IC structure 300A, comprising two pad / via types (internal conductive pads / vias (not shown separately) 212 and edge conductive pads / vias 214) after the dicing or fragmentation process. The properties of conductive pads / vias 212 and conductive pads / vias 214 are similar to those of IC structure 100C shown in Figure 2F, and a repeated explanation is omitted for brevity. The main difference between IC structure 300A and IC structure 100C is that in IC structure 300A, the semiconductor die 122D is either surrounded or encapsulated laterally by the potting material 242, whereas in 100C, only the edges of the die and RDL are exposed. The semiconductor die 122D and the potting material 242 constitute the main body of IC structure 300A.

[0110] Figure 3E shows a cross-sectional view of IC structure 300B according to various embodiments of the present disclosure. IC structure 300B is similar to IC structure 300A in many embodiments, for example, in the primary RDL 108A, conductive pad 212, and conductive via 214, and therefore details of such similar embodiments will not be repeated for brevity. The main difference between IC structure 300A and IC structure 300B is that, in addition to the semiconductor die 122D and potting material 242, the body of IC structure 300B further includes an edge TMV 232 that extends through or partially through the thickness of the semiconductor die 122D. The edge TMV 232 is part of the edge interconnect structure 118X.

[0111] Figure 3F shows a cross-sectional view of IC structure 300C according to various embodiments of the present disclosure. IC structure 300C is similar to IC structure 300B in many embodiments, e.g., in the primary RDL 108A, conductive pad 212, conductive via 214, and TMV 232, and therefore details of such similar embodiments are not repeated for brevity. Furthermore, IC structure 300C includes a semiconductor die 122D1, which replaces semiconductor die 122D and can be at least one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, memory die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die. The main difference between semiconductor die 122D and semiconductor die 122D1 is that semiconductor die 122D1 further includes an edge conductive pad 222 exposed through a portion of the edge interconnection structure 118X, for example, a secondary plane or side surface 102S of semiconductor die 122D1. The material, structure and method for forming the edge conductive pad 222 of IC structure 300C are similar to those of the conductive via 222 described with reference to Figure 2F. Thus, the body of IC structure 300C includes semiconductor die 122D1, potting material 242, conductive via 222, and TMV 232. According to some embodiments, the primary RDL 108A of IC structure 300C includes a conductive via 214 electrically connected to the TMV 232 in the body of IC structure 300C to establish stacked conductive vias for IC structure 300C.

[0112] Figures 4A to 4G show cross-sectional views of structures at different stages of a method for manufacturing an IC structure 400A according to some embodiments of the present disclosure. According to some embodiments, the IC structure 400A shown in Figure 4G is a semiconductor package device. The IC structure 400A may be formed from a semiconductor device 100W (see Figure 4A), which is a wafer-level device, and the IC structure 400A is formed by separating the semiconductor device 400W using a dicing or dicing process.

[0113] Referring to Figure 4A, the substrate 102 is received or supplied as a semiconductor device 100W. Furthermore, conductive vias 104 are formed on the substrate 102. Referring to Figure 4B, the bulk portion of the substrate 102 beneath the conductive vias 104 is removed, for example, by CMP, grinding, or etching, so that the conductive vias 104 become a TSV 104. A dicing or fragmentation process is performed to separate the semiconductor device 100W into a plurality of TSV dies 122E, the TSV die 122 being similar to the TSV die 122A described with reference to Figure 2C.

[0114] Referring to Figure 4C, the carrier substrate 106 is received or provided within the semiconductor device 400W. Furthermore, a release layer 110 is formed on the carrier substrate 106. Multiple TSV dies 122E and multiple TMV 232 are arranged on the release layer 110 to form a reconfigured structure on the release layer 110 or the carrier surface 110S of the carrier substrate 106. The TMV 232 may be arranged alternately with the TSV dies 122E. The TMV 232 may include a conductive material, such as tungsten, copper, titanium, tantalum, molybdenum, cobalt, ruthenium, aluminum, silver, gold, or another suitable material. Multiple TSV dies 122E and multiple TMV 232 may have substantially equal heights. According to some embodiments, the TSV dies 122E and TMV 232 are arranged on the release layer 110 by a pick-and-place bonding process.

[0115] Referring to Figure 4D, the semiconductor device 400W is molded or sealed using a potting material (e.g., encapsulating material or molding material) 242. A deposition or molding process is performed to deposit the potting material 242 between the TSV die 122E and the TMV 232. According to some embodiments, a planarization process, such as CMP, grinding, etching, or another preferred etching operation, is performed to remove excess potting material 242 and to planarize the top surface of the potting material 242, the top surface of the TSV die 122E, and the top surface of the TMV 232 to expose the TSV and TMV.

[0116] Referring to Figure 4E, the primary RDL108A is formed on the top surface of the potting material 242, TSV die 122E, and TMV232. The material, configuration, and method for forming the primary RDL108A are the same as those described with reference to Figures 2B to 2G, and a repeated description of the primary RDL108A is omitted for brevity.

[0117] According to some embodiments, the order of the processing steps shown in Figures 4C and 4D can be changed. For example, first, a plurality of TSV dies 122E are placed on the release layer 110 without TMV 232. Subsequently, potting material 242 is deposited and planarized to fill the gaps between the TSV dies 122E. For example, a laser drilling operation is performed to form via holes between the TSV dies 122E, after which the TSV dies are filled with a conductive material to form TMV 232. The vias may be laterally surrounded by the potting material 242.

[0118] Referring to Figure 4F, another carrier substrate 116 is provided or received within another semiconductor device 401W. Another release layer 120 is formed on the carrier substrate 116. Furthermore, the structure in Figure 4E is inverted with its RDL108A side bonded to the second carrier substrate 116 using the release layer 120, and the carrier 106 is peeled off. Subsequently, another primary RDL108B with surface finish and bonding pads is formed on the opposite side of the TSV die 122E, potting material 242, and TMV232s supported by the second carrier 116. The materials, configuration, and method for forming the carrier substrate 116, release layer 120, and primary RDL108B are the same as those for the carrier substrate 106, release layer 110, and primary RDL108A described with reference to Figure 2C, and therefore, details of such similar features will not be repeated for brevity. Furthermore, the carrier substrate 116 is peeled off from the semiconductor device 401W by peeling off the release layer 120 after wafer mounting.

[0119] Referring to Figure 4G, the dicing process is performed to separate the reconfigured structure of the semiconductor device 401W into individual IC structures 400A. By appropriate arrangement, TMV232 and edge TSV104B are formed in IC structure 400A.

[0120] • Two TMV types after the dicing or dicing process (internal TMV (not shown) and edge TMV232),

[0121] • Two TSV types after the individualization or dicing process (internal TSV and edge TSV104B), It is equipped with.

[0122] The characteristics of the conductive pads 212 and conductive vias 214 of the primary RDL108A or 108B are the same as those of IC structure 100A shown in Figure 2C, and for brevity, a repeated explanation of them is omitted. IC structure 400A differs from IC structure 100A mainly in that IC structure 400A further includes a potting material 242 that fills the space between the semiconductor die 122D and the TMV232. The semiconductor die 122D, TMV232, and potting material 242 constitute the main body of IC structure 400A.

[0123] Figures 4H to 4N show cross-sectional views of IC structures 400B, 400C, 400D, 400E, 400F, 400G, and 400H according to various embodiments of the present disclosure. Since IC structures 400B, 400C, 400D, 400E, 400F, 400G, and 400H are seen in many embodiments as variations of baseline IC structure 400A, the following description will focus only on the differences between IC structure 400A and the other IC structures 400B to 400H.

[0124] Referring to Figure 4H, the main difference between IC structure 400B and IC structure 400A is that in IC structure 400B, the TSV die 122E containing the internal TSV is laterally surrounded or enclosed by the potting material 242, and there are no edge TSVs in IC structure 400B.

[0125] Referring to Figure 4I, the main difference between IC structure 400C and IC structure 400A is that TMV232 is not present in IC structure 400C. Referring to Figure 4J, IC structure 400D does not have edge TSV or edge TMV, while both are present in IC structure 400A.

[0126] The IC structures 400E, 400F, 400G, and 400H shown in Figures 4K to 4N can be viewed as multi-die versions of the corresponding single-die IC structures 400A, 400B, 400C, and 400D, with multiple dies arranged within the same package layer of IC structures 400E to 400H. Referring to Figure 4K, the main difference between IC structure 400E and IC structure 400A is that IC structure 400E further includes a second semiconductor die 122D in addition to the first semiconductor die, namely the TSV die 122E, both of which may be the same or different in size. Thus, the body of IC structure 400E consists of semiconductor die 122D, TSV die 122E, TMV 232, potting material 242, and RDL 108A and 108B. Semiconductor die 122D and TSV die 122E are arranged in the same package layer. The semiconductor die 122D (which may also include internal or edge TSVs) is laterally surrounded or encapsulated by a potting material 242. Furthermore, in the IC structure 400E, the TMV 232 functions as an edge TMV, which is electrically connected to the edge conductive vias 214 of the primary RDL 108A and the edge conductive vias 214 of the primary RDL 108B to form a stacked TSV that extends across the entire thickness of the IC structure 400E.

[0127] Referring to Figure 4L, the main difference between IC structure 400F and IC structure 400E is that in IC structure 400F, the TSV die 122E is further surrounded or enclosed laterally by the potting material 242, while IC structure 400F does not include edge TSVs.

[0128] Referring to Figure 4M, the main difference between IC structure 400G and IC structure 400E is that IC structure 400G, which includes edge TSV104B, does not have edge TMV232.

[0129] Referring to Figure 4N, IC structure 400H can be seen as a combination of the features of IC structures 400F and 400G, where the body of IC structure 400H comprises only a semiconductor die 122D, a TSV die 122E, potting material 242, and RDLs 108A and 108B, without edge TSVs and edge TMVs. According to some embodiments, the potting material 242 laterally surrounds and encapsulates the semiconductor dies 122D and 122E. The potting material 242 is exposed through two secondary planes 102S of the body of IC structure 400H.

[0130] Figure 5A shows a cross-sectional view of an IC structure 500A according to various embodiments of the present disclosure. The body of the IC structure 500A comprises a semiconductor die 122F, a TMV 232, and a potting material 242. The semiconductor die 122F may include at least one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, memory die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die. The semiconductor die 122F is similar to the semiconductor die 122D1 shown in Figure 3F, except that the edge conductive pads 222 of the semiconductor die 122D1 are replaced by a plurality of TSVs 104 (including internal TSVs 104A and edge TSVs 104B), one edge TSV 104B being exposed through the secondary plane 500AS of the IC structure 500A. Furthermore, in contrast to the aforementioned IC structure, the IC structure 500A further includes a secondary RDL118A which is arranged on the secondary plane 500AS of the IC structure 500A and electrically connected to the primary RDL108A.

[0131] Figure 5C shows a more detailed cross-sectional view of the secondary RDL 118A of the IC structure 500A shown in Figure 5A, according to various embodiments of the present disclosure. The secondary RDL 118A is similar to the primary RDL 108, for example, the primary RDL 108A or 108B described with reference to Figure 2G. The secondary RDL 118A shown in Figure 5C includes two main conductive wire / via layers 340, 350, similar to the first and second main conductive wire / via layers 240 and 250 of the primary RDL 108A or 108B in Figure 2G. Referring to Figure 5C, the secondary RDL 118A includes a front interconnect surface 118F and a rear interconnect surface 118R opposite to the front interconnect surface 118F. The secondary RDL118A is electrically connected to the edge interconnect structure 118X of the IC structure 500A, for example, the edge TSV104B of the semiconductor die 122F or the edge conductive pad 212 of the primary RDL108A. According to some embodiments, the secondary RDL118A is considered to be part of the edge interconnect structure 118X of the IC structure 500A. With such a configuration, the primary RDL108A can be electrically connected to the semiconductor die 122F not only via the internal interconnect structure 108X, but also via the edge interconnect structure 118X, which includes the edge TSV104B and the secondary RDL118A, via the primary surface 102P of the substrate 102 of the IC structure 500A and the primary surface 108P of the primary RDL108A facing the substrate 102, as well as via the side surface (secondary plane) 102S of the body of the IC structure 500A and the front interconnect surface 118F of the secondary RDL118A. Therefore, the routing capacity and design flexibility of the IC structure 500A provided for semiconductor die 122F are increased compared to the secondary RDL118A and other IC structures without edge interconnects.

[0132] Figure 5B shows a cross-sectional view of IC structure 500B according to various embodiments of the present disclosure. IC structure 500B is substantially similar to IC structure 500A in many embodiments, and therefore, a description of similar features will not be repeated for brevity. The main difference between IC structure 500B and IC structure 500A is that, in addition to the secondary RDL 118A located in the secondary plane 500BS1 on the left side of IC structure 500B, IC structure 500B further includes a secondary RDL 118B located in the secondary plane 500BS2 on the right side of IC structure 500B opposite to the secondary RDL 118A. The material and configuration of the secondary RDL 118B may be the same as that of the secondary RDL 118A, as shown in Figure 5C. However, other configurations and numbers of main conductive wire / via layers for secondary RDL 118A and 118B are also within the scope intended of the present disclosure. Therefore, the secondary RDLL118B can also be considered part of the edge interconnection structure 118X of the IC structure 500B and can be electrically connected to the primary RDL108A.

[0133] Figures 6A to 6E show cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 600A according to various embodiments of the present disclosure. According to some embodiments, the IC structure 600A shown in Figure 6E is a semiconductor package device. The IC structure 600A may be formed from a semiconductor device 600W which is a wafer-level device, and the IC structure 600A in Figure 6E is formed by separating the semiconductor device 600W using a dicing or dicing process.

[0134] Referring to Figure 6A, a carrier substrate 106 is provided or received. A delamination layer 110 is formed on the upper surface of the carrier substrate 106. A plurality of semiconductor dies, for example, semiconductor dies 122E, 122G, and 122H, are prepared. The TSV die 122E may be replaced with one of the above-mentioned semiconductor dies, such as semiconductor dies 100A, 100B, 100C, 300A, 300B, 300C, and 400A-400H. The TSV die 122E includes a plurality of TSVs 104 on the upper surface of the TSV 104 and a primary RDL 108A. According to some embodiments, the semiconductor die 122G or 122H can be at least one of any of the following: a CPU die, a GPU die, a TPU die, a MEMS die, an AP die, an FPGA die, an ASIC die, a memory die, a transceiver die, a network interface die, an integrated photonics die, a packet buffer / router die, another suitable die, or the aforementioned semiconductor dies.

[0135] The semiconductor dies 122E, 122G, and 122H may be similar in size or dimensions, or they may be different. For example, the semiconductor dies 122E, 122G, and 122H may be substantially equal in height, length, or width, or they may be different.

[0136] A pick-and-place process is performed to pick known good dies (KGDs) of semiconductor dies 122E, 122G, and 122H and bond the KGDs onto a release layer 110. After semiconductor die 122H is placed on the release layer 110, a bonding layer or die attachment layer 160 is formed on semiconductor die 122H. The bonding layer 160 may assist in attaching semiconductor die 122G to semiconductor die 122H. According to some embodiments, the bonding layer 160 is a die attachment film, an array of microbumps configured to perform flip-chip bonding, a direct bonding layer, or a hybrid bonding layer configured to generate a bond. According to some embodiments, semiconductor dies 122G and 122H are stacked vertically. Semiconductor die 122E may be placed adjacent to the stacked semiconductor dies 122G and 122H in the same package layer. Semiconductor dies 122E, 122G, and 122H may be substantially the same size or different in size.

[0137] Referring to Figure 6B, the semiconductor device 600W is formed or encapsulated using a potting material or a preferred material 252. The material and composition of the potting material 252 are similar to those of the potting material 242 and may include a molding compound and a thick-film photoresist. The molding or deposition process is carried out to deposit the potting material 252 between the semiconductor dies 122E, 122G, and 122H, thereby embedding the semiconductor dies 122E, 122G, and 122H. The embedding material 252 may have a height exceeding the height of the semiconductor dies 122E, 122G, and 122H. According to some embodiments, a planarization process, e.g., CMP, grinding, etching (dry and / or wet), or another preferred etching operation is carried out to remove excess potting material 252 and produce a uniform top surface of the potting material 252 (see Figure 6B).

[0138] Figure 6C shows the formation of multiple via holes 252R in the potting material 252. The holes may be formed by laser ablation. Alternatively, if a thick-film photoresist is used as a encapsulant, it can be laminated, patterned, and developed to form holes extending from the top surface of the potting material 252 to bonding pads with proper surface finish of the semiconductor dies 122E, 122G, and 122H, exposing the pads below the via holes 252R.

[0139] Referring to Figure 6D, a conductive material with appropriate passivation is deposited in the via hole 252R by, for example, PVD, CVD, ALD, plating, etc. The conductive material may include at least one of tungsten, copper, titanium, molybdenum, cobalt, ruthenium, tantalum, aluminum, silver, gold, and other suitable materials. Thus, one or more conductive pillars 224 are formed on the semiconductor die 122G and electrically connected to it. At least one conductive pillar 224 formed on the secondary plane 600AS2 of the semiconductor device 600W (at this point, such a secondary plane 600AS2 is still a virtual plane before the dicing process) is configured as an edge conductive pillar 224. Furthermore, one or more conductive plugs 234 are formed on the TSV die 122E and / or semiconductor die 122H and electrically connected to them. As a result, the body of the IC structure 600A includes semiconductor dies 122E, 122H, and 122G, a primary RDL 108A, a junction layer 160, a potting material 252, a conductive via 104, an internal conductive pillar 224, a conductive plug 234, and an edge conductive pillar 224. According to some embodiments, the TSV 104, the conductive pillar 224, and the conductive plug 334 are substantially the same in length or different.

[0140] Another primary RDL108C is formed on the upper surface of the potting material 252 and electrically connected to the semiconductor dies 122E, 122G, and 122H. According to some embodiments, the primary RDL108C includes at least an edge conductive pad 212 on the secondary plane 600AS1 or 600AS2 of the semiconductor wafer 600W (at present, the secondary planes 600AS1 and 600AS2 are still virtual planes before the dicing process).

[0141] Subsequently, following wafer mounting, the carrier substrate 106 is removed or separated from the semiconductor device 600W by removing or peeling the delamination layer 110 from the semiconductor device 600W. Figure 6E shows individual IC structures 600A formed using a dicing or dicing process to separate the semiconductor device 600W into individual IC structures 600A. By appropriate arrangement, edge conductive pads 212, edge TSV 104B, and edge conductive pillars 224 may be formed and exposed through at least one of the secondary planes 600AS1 and 600AS2 of the IC structure 600A. The primary RDL 108C is configured to be electrically connected to the semiconductor dies 122E, 122G, and 122H through internal interconnection structures 108X, e.g., conductive plugs 234 and internal conductive copper pillars 224. Furthermore, the primary RDL108C is configured to be electrically connected to semiconductor dies 122E, 122G, and 122H via edge interconnection structures 118X, such as edge TSV104 and edge conductive pillars 224. Thus, the routing distance can be reduced with the help of the edge interconnection structures 118X.

[0142] Referring to Figures 6E and 5A and 5B, according to several embodiments, the secondary RDLs 118A and 118B of IC structures 500A and 500B are applicable to IC structure 600A. In other words, although not shown separately, the secondary RDLs 118A or 118B may be placed on secondary surfaces 600AS1 and 600AS2, respectively, so as to be electrically connected to the conductive element 202, edge TSV 104 (in Figure 6E, 104 is used instead of 104B to match Figure 6D), and / or edge conductive pillar 224 of the primary RDL 108C. According to several embodiments in which IC structure 600A includes an edge conductive plug 234, the secondary RDLs 118A or 118B can be electrically connected to such an edge conductive plug 234.

[0143] The embodiments of the present disclosure described above offer advantages. The aggregate edge conductive element 202 can be seen in the form of an edge conductive pad 212, an edge conductive via 214, an edge TSV 104, or an edge TMV 224, as shown in Figure 6E. Furthermore, primary RDLs 108A and 108C, or secondary RDLs 118A and 118B (see Figure 5B) may be formed with or without the edge conductive pad 212, with or without the edge conductive via 214, with or without the edge TSV 104, with or without the edge conductive via 222 (see Figures 2F and 3F), with or without the edge TMV 232 (Figure 5B), with or without the edge conductive pillar 224, and with or without the edge conductive plug 234. The edge conductive element 202 can be positioned around the IC structure or around the RDL. Furthermore, the edge conductive via 222 can cover all or part of the thickness of the body of each IC structure. Furthermore, the edge TSV104, edge TMV232, edge conductive pillar 224, and edge conductive plug 234 appear inside the IC structure, facilitating internal interconnection of the IC structure in different stack layers, in addition to the edge interconnections located on the sides.

[0144] The conductive pillars 224, conductive plugs 234, and TMV 232 (Figure 5B) are formed based on drilling and hole-filling process steps, and they can be fabricated by several methods, including a bonding vertical wire (e.g., palladium, Pd, coated Cu) approach, a laser via approach, and a photosensitive thick film through-film (TPTF) approach. In the bonding vertical wire approach, the wire bonding follows a high copper pillar process step, and the wire bonding replaces the high copper pillar formation step. When using Pd-coated Cu wire, thin gold (Au) can be used as a bonding pad. In the laser via approach, the IC is first bonded to the carrier substrate 106, followed by, for example, overmolding, planarization, laser via hole opening, via hole sidewall Cu plating, via hole plating, or plugging with photosensitive polymer or solder, planarization, RDL fabrication, carrier delamination, and dicing. The TPTF process flow consists of sequentially laminating thick photosensitive films onto bonded ICs, multiple or single exposures and development to generate TMV holes (i.e., photosensitive thick-film through-via holes), barrier / seed layer deposition, Cu plating, via hole plug formation as needed, back grinding / planarization, RDL generation, carrier delamination, and dicing. The ICs here may have RDLs and TSVs. Multiple exposures increase process flexibility for forming vias of different sizes and depths. The TMV-related processes can accommodate multiple ICs in both the xy plane and the vertical z direction, as shown in Figure 6E. Furthermore, the semiconductor dies 122E, 122H, and / or 122G in Figure 6E can be pre-bumped with solder bumps or copper pillar microbumps before bonding them to the carrier substrate 106 in Figure 6A. Die bonding is followed by overmolding, followed by planarization and RDL generation.

[0145] Figures 7A to 7H show cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 700A according to various embodiments of the present disclosure. According to some embodiments, the semiconductor package 700A shown in Figure 7H is a semiconductor package device. The semiconductor package 700A may be formed from semiconductor devices 700W and 701W, which are wafer-level devices, and the semiconductor package 700A is formed by separating the semiconductor device 701W using a dicing or dicing process.

[0146] Figures 7A and 7C illustrate the formation of multiple tall IC stacks 322 from multiple IC structures 142. Referring to Figure 7A, a carrier substrate or support substrate 106 is provided or received. A release layer 110 is formed on the upper surface of the carrier substrate 106. A pick-and-place process is performed to pick up and bond multiple known good IC structures 142, e.g., IC structure 142A, with the help of a bonding layer, to form the first tier of a short IC stack 312, as shown in Figure 7A, on the release layer 110 at a pitch suitable for improving yield. According to some embodiments, the IC structures 142 may consist of IC structures 400A, 400B, 400C, 400D, 400E, 400F, 400G, 400H, 500A, 500B, and / or 600A. However, other types of IC structures are also possible, such as IC structures 100A, 100B, 100C, 300A, 300B, 300C, etc. As illustrated in Figure 7B, IC structure 142 covering 142A, 142B, 142C, and 142D may include memory and / or processor analog dies. IC structure 142 may also cover MEMS devices, passive and analog, mixed-signal, and digital signal processing ICs.

[0147] Referring to Figure 7B, several other IC structures 142, for example IC structure 142B, are bonded to the corresponding IC structure 142A to form a second layer of the low IC stack 312. The bonding of IC structure 142B to IC structure 142A may be achieved using thermocompression bonding (TCB), flip-chip bonding, hybrid bonding, direct bonding, bonding via an adhesive layer (e.g., Ti / Au), die attachment film or paste, or other suitable bonding processes. The process of forming the low IC stack 312 can continue until a predetermined number of tiers (total number of tiers) K is reached, where the number of tiers K is a natural number. In the example shown in Figure 7B, the number of tiers K is 4. This means that each low IC stack 312 is constructed from four stacked IC structures 142A, 142B, 142C, and 142D. This process produces a known good low IC stack. Alternatively, the low IC stack 312 can be formed by bonding multiple 142Ds to multiple 142Cs, the resulting structure is further processed as needed, then peeled off, known good structure is picked up, and the known good structure is bonded to multiple known good 142Bs, etc., and the process is repeated until the low IC stack 312 is formed as shown in Figure 7B.

[0148] After the first low IC stack 312 is completed, a release (or bonding) layer 140 of appropriate thickness is formed on top of each low IC stack 312. The material of the release layer 140 may be different from the material of the release layer 110 so as not to interfere with each other in their respective demolding processes. Subsequently, another set of known good low IC stacks 312 is formed on top of the release layer 140 of the first known good low IC stack 312. As shown in Figure 7B, the formation of the low IC stacks 312 and the formation of the release layer 140 proceed alternately until a predetermined number L of low IC stacks are achieved, forming the high IC stack 322 shown in Figure 7C, where the number of low IC stacks L (total number of low IC stacks) is a natural number. In the illustrated example, the number of low IC stacks L is 4. As a result, the low IC stacks 312 are stacked to form the high IC stack 322 that penetrates the release layer 140.

[0149] Referring to Figure 7C, each high IC stack 322 is detached from the carrier substrate 106 by peeling off the release layer 110. As a result, four low IC stacks 312 are arranged alternately with three release layers 140 to form rows of high IC stacks 322. In the illustrated example, the semiconductor device 700W has three rows of high IC stacks 322. The numbers K, L, and number of rows introduced above are for illustrative purposes only. Other numbers are also within the scope intended of this disclosure.

[0150] Figures 7D to 7H illustrate the formation of a semiconductor package 700A from multiple high IC stacks 322. Referring to Figure 7D, a carrier substrate 116 is provided or received. A release layer 120 is formed on the top surface of the carrier substrate 116. A pick-and-place process is performed to pick up and bond multiple known good high IC stacks 322 and position them on the release layer 120 at a pitch suitable for improving yield. The high IC stacks 322 are reconfigured on the carrier substrate 116 and bonded to the release layer 120 via their sides. In other words, the high IC stacks 322 are laid down such that the vertical stacked IC structures 142 within the high IC stacks 322 are positioned upright in the xy plane or in the length and width direction of the IC, with one of their four sides bonded to the release layer 120.

[0151] Referring to Figure 7E, the reconfigured high IC stack 322 of the semiconductor device 701W is formed or encapsulated using potting material 262. The material and composition of potting material 262 are the same as those of potting material 242 or 252. A forming or deposition process is performed to deposit the potting material 262 between the stacked high IC stacks 322. According to some embodiments, a planarization process, e.g., CMP, grinding, etching (dry and / or wet), or another preferred etching operation is performed to remove excess potting material 262 and to planarize the top surface of the potting material 262 so that it is coplanar with the side surface of the high IC stack 322. Subsequently, an edge interconnect structure RDL118A is formed on or bonded to at least the edge interconnect on the side surface (secondary plane) of the high IC stack 322.

[0152] Figure 7F shows the formation of another edge interconnect structure RDL118B on another side of the high IC stack 322 opposite the secondary RDL118A. Another carrier substrate 126 is provided or received within another semiconductor device 702W. Another delamination layer 130 is formed on the carrier substrate 126 to facilitate the formation of 118B. The materials, configurations, and methods for forming the carrier substrate 126 and the secondary RDL118A and 118B are the same as those for the secondary RDL108A and 108B described in Figure 5B and the primary RDL108A and 108B described in Figure 2C, and therefore, details of such similar features are not repeated for brevity. The material of the delamination layer 130 may differ from the material of the delamination layer 120 so as not to interfere with each other in their respective delamination processes. Next, after the semiconductor structure 701W shown in Figure 7E is bonded to the second carrier 126 on the RDL 118A side, the carrier substrate 116 is removed from the semiconductor device 701W by removing the delamination layer 120. The edge interconnection RDL structure 118B is formed or bonded to the lower secondary surface of the high IC stack 322, opposite to the upper secondary surface of the high IC stack 322.

[0153] Referring to Figure 7G, the fragmentation or dicing process is performed to separate the semiconductor device 701W into a high IC stack structure 700L. The fragmentation or dicing process may be performed to cut the semiconductor device 701W at the location of the potting material 262, which has been cleaned by, for example, dry and / or wet etching, while taking care to keep each high IC stack 322 intact during the dicing process. According to some embodiments, a wet etching or cleaning process is performed to remove any residual potting material 262 remaining on the high IC stack structure 700L.

[0154] Figure 7H shows that individual semiconductor packages 700A, i.e., low IC stack structures, are formed from their respective IC structures, i.e., high IC stack structures 700L. Delamination, fragmentation, and / or dicing processes are performed to separate the delamination layer 140 (Figure 7B) from each of the high IC stack structures 700L so that each low IC stack 312, i.e., each containing edge interconnect RDL structures 118A and 118B, is separated from one another. According to some embodiments, etching or dicing processes are performed to penetrate and cut the secondary RDLs 118A and 118B at the location of the delamination layer 140, for example, by dicing, continuous wave laser beam, dry etching (e.g., by plasma), and / or wet etching to assist the delamination process. As shown in Figure 7H, the semiconductor package 700A includes a stack of low IC stack structures 142 and two secondary RDLs 118A and 118B located on two sides of the low IC stack 142. Secondary RDL118A and 118B can help increase the routing area of ​​the IC structure 142, shorten the routing distance, and improve the routing capacity and design flexibility of the semiconductor package 700A.

[0155] Figures 7I and 7J show cross-sectional views of semiconductor packages 700B and 700C according to various embodiments of the present disclosure. Semiconductor packages 700B and 700C can be seen as detailed versions of semiconductor package 700A with some minor modifications. Referring to Figure 7I, semiconductor package 700B includes three IC structures 142A, 142B, and 142C in a vertical stack, each IC structure 142A, 142B, or 142C comprising its respective body and its apex having its respective primary RDL 108A, 108B, or 108C positioned on its respective upper primary surface 142AP, 142BP, or 142CP. The body of IC structure 142A consists of a semiconductor die 143A, an edge TMV 232, an edge TSV 104, and a potting material 242, and the semiconductor die 143A includes a plurality of TSVs 104 and a plurality of TMVs 232. Furthermore, the body of IC structure 142B consists of a semiconductor die 143B, an edge TMV 232, and a potting material 242, with the semiconductor die 143B containing multiple TSVs 104 and multiple TMVs 232. Similarly, the body of IC structure 142C consists of a semiconductor die 143C, an edge TMV 232, and a potting material 242, with the semiconductor die 143C containing multiple TSVs 104 and multiple TMVs 232. IC structures 142A, 142B, and 142C can be of different sizes and can include a wide variety of combinations of internal interconnects and edge interconnects covering the TSVs and TMVs. According to some embodiments, the semiconductor die, 143A, 143B, or 143C may be at least one of a CPU die, GPU die, TPU die, MEMS die, AP die, FPGA die, ASIC die, memory die, transceiver die, network interface die, integrated photonics die, packet buffer / router die, or another suitable die (e.g., an interconnect die such as an interposer). According to some embodiments, the semiconductor package 700B includes only a single secondary RDL118A located on the left secondary plane 700BS of the semiconductor package 700B.

[0156] According to some embodiments, IC structures 142A, 142B, and 142C are characterized by substantially equal or unequal thicknesses T1, T2, and T3, respectively. Each IC structure 142A, 142B, or 142C may include a thickness in the range of about 30 μm to about 775 μm.

[0157] The secondary RDL118A includes a front interconnect surface 118F and a rear interconnect surface 118R opposite the front interconnect surface 118F. The secondary RDL118A is electrically connected to the secondary plane 700BS through the front interconnect surface 118F to support routing efficiency and flexibility. For example, the secondary RDL118A includes a conductive trace or wire 172 that extends along the longitudinal axis of the secondary RDL118A and electrically connects the edge conductive pad 212 of the primary RDL108C to the edge TSV104B of the semiconductor dies 143C and 143A, while bypassing the bodies of the IC structures 142A, 142B, and 142C. Furthermore, the secondary RDL118A can be used to connect other circuits through the rear interconnect surface 118R. For example, the secondary RDL118A includes one or more conductive bumps, microbumps, or bump pad arrays 244 (all referred to as external connections of the secondary RDL118A) on the rear interconnect surface 118R, and the conductive bumps 244 are configured to electrically connect the secondary RDL118A to a circuit or layer adjacent to the secondary RDL118A.

[0158] Referring to Figure 7J, the semiconductor package 700C is similar to the semiconductor package 700B in many embodiments, and a description of such similar features will not be repeated for brevity. According to some embodiments, the semiconductor package 700C includes three IC structures 142D, 142E, and 142F in a stack, each IC structure 142D, 142E, or 142F comprising its respective body and two respective primary RDLs 108A / 108D, 108B / 108E, and 108C / 108F arranged on their respective upper and lower primary surfaces 142AP, 142BP, and 142CP.

[0159] The semiconductor package 700C further differs from the semiconductor package 700B in that, in the case of 700C, the secondary RDL 118A, which is located on the secondary plane 700CS1 of the semiconductor package 700C, includes an array of conductive pads 254 on the rear interconnect surface 118R of the secondary RDL 118A. According to some embodiments, the conductive pads 254 have an upper surface that is coplanar with the rear interconnect surface 118R of the secondary RDL 118A. The coplanar arrangement of the secondary RDL 118A in this manner helps to perform hybrid bonding with other circuits or layers. Furthermore, in contrast to the semiconductor package 700B, the semiconductor package 700C further includes another secondary RDL 118B located on the secondary plane 700CS2. The interconnect configuration in the secondary RDL 118B may be similar to or different from the interconnect configuration in the secondary RDL 118A. The secondary RDL118B may include external connections such as microbumps, hybrid bonding layers, direct bonding layers, flexible circuit connectors (see Figure 9A for details, described later), and combinations thereof. Furthermore, the secondary RDLL118A (or 118B) includes conductive traces or wires 172 that extend along the longitudinal axis of the secondary RDLL118A, bypassing the bodies of the IC structures 142D, 142E, and 142F, electrically connecting the edge conductive pads 212 of the primary RDL108C and 108B with the edge conductive vias 214 of the primary RDL108D, thereby enabling skip die and multi-side power supply and signaling.

[0160] According to some embodiments, IC structures 142D, 142E, and 142F have substantially equal or unequal thicknesses T4, T5, and T6, respectively. Each IC structure 142D, 142E, or 142F may include a thickness in the range of about 30 μm to about 775 μm.

[0161] The semiconductor packages 700A, 700B, and 700C enable skip die and multi-side power supply and signaling through an internal interconnect structure 108X covering the TMV, primary RDL108, and TSV; skip die and multi-side power supply and signaling through an edge interconnect structure 118X covering the secondary RDL118 and edge interconnects; and skip die and multi-side power supply and signaling through both the internal interconnect structure 108X and the edge interconnect structure 118X. These semiconductor packages with multi-side power supply and signaling enable the achievement of "PPAC optimization per cubic millimeter" for 3D ICs (exemplified herein by low IC stacks), and the vertical dimensions of the 3D IC can be expanded to cover the IC, interposer, IC package substrate, IC package, and system PCB (e.g., Figures 7I and 7J).

[0162] Referring to Figures 7A and 7B, according to some embodiments, the carrier substrate 106 can be a 12” wafer carrier or a larger panel carrier to increase carrier utilization. Referring to Figure 7B, the release layer 140 can also be a permanent bonding layer such as a die adhesion film (DAF) used in stacked die packaging (similar to the one used when bonding dies (IC structures 142A-142D) together) to form a low 3D IC stack 312, the film being pre-applied to the back of the dies 142A-142B while they are still in wafer form, and the die / film combo is picked up from the wafer tape for die bonding following a wafer saw.

[0163] Referring to Figure 7E, as previously described, the reconfigured high IC stack 322 of the semiconductor device 701W is formed or encapsulated using potting material 262. The material and composition of potting material 262 are the same as those of potting material 242 or 252. A forming or deposition process is performed to deposit the potting material 262 between the tiled high IC stacks 322. According to some embodiments, an overmolding operation is performed to deposit the potting material 262. According to some embodiments, the potting material 262 may also be a permanent bonding layer such as a molding compound or encapsulant. According to some embodiments, a planarization process, e.g., CMP, grinding, etching (dry and / or wet), or another preferred etching operation is performed to remove excess potting material 262 and to planarize the top surface of the potting material 262 so that it is coplanar with the sides of the high IC stack 322 which are planarized simultaneously with the potting material 262. Subsequently, the edge interconnect structure RDL118A is formed on or bonded to at least the edge interconnect on the side (second plane) of the high IC stack 322. According to some embodiments, a bump action is performed for the die edge interconnect, and a plurality of bonding pads are formed on one side of the high IC stack 322 or RDL118A to electrically connect the high IC stack 322 to the RDL118A.

[0164] Referring to Figure 7F, another carrier substrate 126 is provided or received within another semiconductor device 702W. Another release layer 130 is formed on the carrier substrate 126 to facilitate the formation of RDL118B. The semiconductor device 701W in Figure 7E is bonded to the RDL118A side of the second carrier 126. Subsequently, the carrier substrate 116 is peeled off from the semiconductor device 701W by peeling off the release layer 120. According to some embodiments, after the carrier substrate 116 is removed and before the RDL118B is formed, a planarization operation is performed on the exposed secondary surfaces of the high IC stack 322 and the potting material 262. The edge interconnect RDL structure 118B is formed or bonded to the lower secondary surface of the high IC stack 322, opposite the upper secondary surface of the high IC stack 322.

[0165] Referring to Figure 7G, the carrier substrate 126 is removed or separated from the semiconductor device 702W by peeling off the release layer 130. A flaking or dicing process is performed to separate the semiconductor device 702W into high IC stack structures 700L. The flaking or dicing process may be performed to cut open the semiconductor device 702W at the location of the potting material 262, which may even lack metal wiring and dielectric passivation, in order to facilitate clean separation of the etching or dicing operation by the potting material 262, which has been cleaned by, for example, dry etching and / or wet etching, while taking care to keep each high IC stack structure 700L intact during the dicing process. According to some embodiments, a wet etching or cleaning process is performed to remove any residual potting material 262 left on the high IC stack structure 700L. According to some embodiments, a planarization operation is performed on the exposed primary surface of the high IC stack structure 700L to remove any residual potting material 262.

[0166] Referring to Figure 7H, individual semiconductor packages 700A, i.e., low IC stack structures 312, are formed from their respective IC structures, i.e., high IC stack structures 700L. Delamination, fragmentation, and / or dicing processes are performed to separate the delamination layer 140 (Figure 7B) from each of the high IC stack structures 700L so that each low IC stack 312, i.e., containing different semiconductor packages 700A, i.e., edge interconnect RDL structures 118A and 118B, is separated from each other. According to some embodiments, etching or dicing processes are performed, for example, by dicing, continuous wave laser beam, dry etching (e.g., by plasma), and / or wet etching, to assist the delamination process and cut open the secondary RDLs 118A and 118B at the location of the delamination layer 140, which can also lack metal wiring and dielectric passivation. According to some embodiments, a combination of wet etching, dicing, and planarization operations is performed.

[0167] Figure 8A shows perspective and cross-sectional views of an edgepad semiconductor die (or hereinafter, semiconductor die) 11 according to several embodiments of the present disclosure. The edgepad semiconductor die 11 has a top surface 11P1, a bottom surface 11P2, and four side walls 11S1, 11S2, 11S3, and 11S4, wherein the area of ​​the top / bottom surface 11P1 / 11P2 is much larger than the area of ​​the side walls 11S1, 11S2, 11S3, and 11S4 (as shown in Figure 8A). The semiconductor die 11 further includes “edge pads” 19 in the form of peripheral pads present on the periphery, sides, or side walls (e.g., side walls 11S1, 11S2, 11S3, and / or 11S4) of the edgepad semiconductor die 11 in Figure 8A.

[0168] Furthermore, through this disclosure, a plurality of edgepad semiconductor dies 11 arranged in a stack or shelf can be named a new high-bandwidth memory (NuHBM) or NuHBM system. Hereinafter, a NuHBM system may also be referred to as a memory stack or memory shelf (or NuHBM stack or NuHBM shelf) comprising edgepad semiconductor dies or a plurality of exemplary semiconductor memory dies 11 as shown in Figure 8A.

[0169] Referring to Figure 8B, in one embodiment, the edgepad semiconductor die 11 includes a memory die 1021 and a redistribution layer (RDL) 15 on the top surface of the memory die 1021. The memory die 1021 may also be a DRAM die. In one embodiment, there are no through-silicon vias (TSVs) within the memory die 1021 of the edgepad semiconductor die 11, which includes an edge pad along one of its sides. The memory die 1021 contains one or more signal pads 12 and a seal ring 13 surrounding the signal pads 12. The memory die 1021 may include a back-end-of-line (BEOL) region located in front of the memory die 1021. In one embodiment, each edge pad 19 of each semiconductor die 11 includes a conductive wire 17 within the redistribution layer 15 (RDL), and the conductive wire 17 is electrically connected to a signal pad 12 in the back-end-of-line (BEOL) region of the semiconductor die 11 surrounded by a seal ring 31. Referring to Figure 8B, on the substrate of the memory die 1021, all signal pads 12 are located within the region defined by the substrate's sealing ring 13, and the edge pads 19 are located within the RDL 15 and are electrically connected to the signal pads 12 in the BEOL region (see Figure 8B).

[0170] In some embodiments, the interconnection structure of the RDL15 may include multiple conductive wire layers, multiple conductive vias, and one or more edge pads 19. The conductive wires, conductive vias, and edge pads together constitute various conductive paths of the interconnection structure. Figure 8B shows conductive wires 17 and vertical conductive vias arranged in the RDL15, which electrically connect the signal pad 12 to the edge pad 19.

[0171] Figure 8C shows a cross-sectional view of a partial semiconductor wafer 31 including a plurality of edge pad semiconductor dies according to some embodiments of the present disclosure. In some embodiments, as shown in Figure 8C, a plurality of edge pad semiconductor dies, for example, exemplary edge pad semiconductor dies 10a and 10b, are formed on the semiconductor wafer 31. The boundaries between adjacent edge pad semiconductor dies 10a and 10b are defined by scribe line regions SL. In some embodiments, each edge pad semiconductor die 10a or 10b includes a memory die 1031a or 1031b and an RDL 15a or 15b disposed on the respective memory die 1031a or 1031b. Each of the memory dies 1031a or 1031b further includes a signal pad 12a or 12b and a seal ring 13a or 13b. Furthermore, RDL15a or 15b includes one or more conductive wires 17a or 17b, or vias 18a or 18b, suitable for RDL design, which are electrically connected to the corresponding signal pads 12a or 12b, respectively. RDL15a (or 15b) further includes stacked dielectric or insulating layers 15a1, 15a2 and 15a3 (or 15b1, 15b2 or 15b3), in which the conductive wires 17a or 17b are arranged. In some embodiments, the exposed portions of the conductive wires or vias 17a or 17b after wafer dicing performed in the scribe line region SL function as edge pads as described above, as shown in Figure 8B. The dielectric or insulating layer according to one embodiment may be made of SiO2.

[0172] Figures 8D and 8E show cross-sectional views of edgepad semiconductor dies or chips 11 according to some embodiments of the present disclosure. In some embodiments, the memory die 1021 of the edgepad semiconductor die 11 has edge contacts 27 formed during the BEOL manufacturing process, such as being formed in an M4 or M5 metal layer. To increase the contact area of ​​the edge pads, one or more conductive vias 29 or dielectric layers 16 having conductive wires are formed on the memory die 1021. Referring to Figure 8D, the conductive vias 29 may correspond to or be aligned with each edge contact 27. In some embodiments, the area of ​​the conductive vias 29 (e.g., exposed lateral area) is larger than the area of ​​the edge contacts 27. In some embodiments, the edge contacts 27 are electrically or physically connected to the corresponding conductive vias 29. Thus, each edge pad 25 of the edgepad semiconductor die 11 may include edge contacts 27 and conductive vias 29. In another embodiment, the dielectric layer 16 is replaced with an RDL 15, as shown in Figure 8E. The same reference numerals in Figures 8D and 8E refer to substantially the same or functionally the same components, and the relevant descriptions can be referenced here without repetition for the sake of brevity.

[0173] Figure 9A shows a perspective view of a conventional high-bandwidth memory (HBM) structure 30a, which includes multiple DRAM chips 31 (12 chips for HBM3 or 16 chips for HBM4, etc.) stacked vertically together on top of a controller 32. Each DRAM chip 31 has a width W1 of approximately 9.5 mm, a length L1 of approximately 10.5 mm, and a thinner thickness T10 of approximately 0.05 mm, depending on the requirements of multiple TSVs 37 within it. Typically, four DRAM chips 31 are grouped together to output a 1K-bit data bus width, with each DRAM chip 31 outputting 256 bits. Therefore, if the 12 DRAM chips in an HBM3 configuration are divided into three groups, each group of four DRAM chips can output 1K bits of data.

[0174] Figure 9B shows a perspective view of a NuHBM stack or shelf 30b according to several embodiments of the present disclosure. In contrast to conventional HBM structures 30a, the NuHBM stack or shelf 30b of the present invention comprises a plurality of edgepad semiconductor dies 33, a plurality of high thermal conductivity layers 34 (optionally), and a memory controller 36. In some embodiments, the plurality of edgepad semiconductor dies 33 consist of 16, 24, or more chips, which are horizontally separate or stacked together horizontally. In some embodiments, each edgepad semiconductor chip 33 has a width W2 of about 9.5 mm, a length L2 of about 10.5 mm (as used in the HBM stack structure 30a), and a regular thickness T20 of about 0.5 mm, which does not contain a TSV. Furthermore, for heat dissipation purposes, a high thermal conductivity "HTC" material or layer 34 (e.g., SiC / AlN / BN / W / Cu / undoped polysilicon / large crystal silicon, etc.) is placed adjacent to each edge pad semiconductor chip 33, or between two placed edge pad semiconductor chips 33. In addition, although not separately shown in Figure 9B, one or more HTC materials or layers, for example, feature 606 shown in Figure 12A, may be used to cover the top of the edge pad semiconductor die or chip 33 and bond to the other HTC layer 34 between the edge pad semiconductor dies 33.

[0175] The NuHBM shelf 30b may further include a plurality of edge pads 35 arranged along the lower wall 33S1 in a direction with a length L2 of approximately 10.5 mm. For example, when using hybrid bonding with a bonding pitch of approximately 5 μm, each edge pad semiconductor die 33 has 2100 edge (I / O) pads 35 (10.5 mm / 5 μm = 2100) in the direction of length L2. When using solder ball bonding with a bonding pitch of approximately 30 μm, each edge pad semiconductor die 33 has 350 edge pads 35 (10.5 mm / 30 μm = 350). When the bonding pitch is 40 μm and the length L2 is 10.5 mm, 262 edge pads 35 (using 128 bits of output data for I / O) can be provided. If necessary, edge RDLs (see U.S. Patent Application No. 18 / 471,670 and U.S. Patent Application No. 19 / 059,275) can be optionally used to form edge pads. Thus, assuming that half of the edge pads 35 are used for data I / O, each edge pad semiconductor chip 33 can have 175 bits of output data (assuming a bonding pitch of approximately 30 μm), 1K bits of output data (assuming a bonding pitch of approximately 5 μm), or any other number of edge pads 35, depending on the difference in bonding pitch. Multiple edge pad semiconductor dies 33 (i.e., NuHBM stacks or shelves) are electrically coupled to a memory controller 36 via the edge pads 35, thereby allowing the memory controller 36 to output data with a desired data width based on the number of output data from one edge pad semiconductor die 33, the combined output data from two or more edge pad semiconductor dies 33, or the combined output data from all edge pad semiconductor dies 33.

[0176] Figures 10A and 10B show exemplary layouts 40a and specifications for a low-power double data rate 5 (LPDDR5) memory chip, respectively. A 16Gb (gigabit) LPDDR5 memory chip 40a is approximately 47mm². 2Having an area of ​​, all pads 41 of the LPDDR5 chip 40a are located close to the edge of the chip with a 16-bit data width. Each I / O pad 41 has a bandwidth of approximately 9.6 Gb / s. When the 16 Gb LPDDR5 memory chip 40a is used in the edge pad semiconductor chip of the present invention, with a bonding pitch of approximately 10 μm, it can have 759 edge pads 35 along a direction of a length L1 of approximately 7.59 mm. Assuming that half of the edge pads 35 are used for data I / O, each edge pad semiconductor die employing the LPDDR5 memory chip 40a can have a data bus width of 379 bits. When four such 16 Gb LPDDR5 memory chips 40a are stacked horizontally as NuHBM shelves, each NuHBM shelf can have a data bus width of 1516 bits (379 bits × 4) and a bandwidth of approximately 14553 Gb / s (1516 × 9.6 Gb / s).

[0177] Figure 11 shows an intermediate cross-sectional view of a NuHBM stack or shelf 50 being formed according to some embodiments of the present disclosure. As shown in the upper and lower plots of Figure 11, a plurality of NuHBM stacks or shelves 50 are formed by bonding a plurality of edge pad semiconductor chips 51 and HTC layers 52 to a carrier 53, and then performing the following: (1) To first form a low NuHBM stack 510 by stacking more edgepad semiconductor chips 51 of the same size, wherein a high thermal conductivity "HTC" material or layer 52 (AlN / BN / W / Cu / ... etc.) is inserted between two adjacent edgepad semiconductor chips 51. In some embodiments, the thermal conductivity (or thermal conductivity coefficient) of the high thermal conductivity layer 52 is higher than the thermal conductivity (or thermal conductivity coefficient) of Si or SiO2. (2) Combine multiple low NuHBM stacks 510 to form a NuHBM shelf 50 that is thick enough to facilitate subsequent processing. (3) Release carrier 53 and release NuHBM shelf 50.

[0178] The present invention further utilizes a NuHBM system for 3D ICs, but does not use a wafer or interposer in the COWOS structure 20 shown in Figure 1. Figures 12A to 12C show 3D IC structures 60 according to several embodiments of the present disclosure. As shown in the plot on the right of Figure 12A, the 3D IC structure 60 includes (1) a package substrate 64, (2) a memory controller 61 (also referred to throughout the disclosure as a “logic die with a memory controller”), (3) a NuHBM shelf 610, (4) a SOC (system-on-a-chip) chip 63 (also referred to throughout the disclosure as a “logic die with processor circuitry”), and (5) optionally a heatsink 65. A NuHBM shelf or stack 610 includes a plurality of edgepad semiconductor dies (or semiconductor dies) 602, optionally a plurality of high thermal conductivity layers 604 (also referred to throughout this disclosure as “upward-extending high thermal conductivity layers”), and optionally a top high thermal conductivity layer 606 (also referred to throughout this disclosure as “lateral-extending high thermal conductivity layer”). An additional adhesive layer may be present between the edgepad semiconductor dies 602 and the high thermal conductivity layers 604.

[0179] The NuHBM shelf 610 and the SOC chip 63 are electrically connected to the memory controller 61. The memory controller 61 is bonded to the package substrate 64. Therefore, there is no silicon interposer between the NuHBM shelf 610 (or memory controller 61) and the package substrate 64. The heatsink 64 is positioned on top of the SOC chip 63 and may have a top surface that is substantially the same height as the top surface of the NuHBM shelf 610.

[0180] In some embodiments, the package substrate 64 is a PCB (printed circuit board) substrate. The package substrate 64 may also be a laminated substrate formed from multiple layers of copper foil having an electrically insulating laminated material, the laminated material including a fiberglass-reinforced epoxy resin, also known as FR-4, Teflon®, polyimide, ceramic, or other suitable material.

[0181] Any commercially available DRAM die, such as a DDR4 die, DDR5 die, LDDR4 die, LDDR5 die, or GDDR7 die, can be used as the edge pad semiconductor die 602. For example, as shown in the left plot of Figure 12A, each edge pad semiconductor die 602 in the embodiment has a die size of approximately 5 or 6.25 mm (with respect to width W3), 10 mm (with respect to length L3), and 100 μm (with respect to thickness T30). Each edge pad semiconductor die 602 may include edge pads 601 arranged along the longitudinal sidewall of the edge pad semiconductor die 602. Thus, in some embodiments, each edge pad semiconductor die 602 can have approximately 500 edge pads 601 when the pad pitch is approximately 20 μm (10 mm / 20 μm) in the longitudinal direction (L3), and at least 250 or more edge pads 601 can be used as data pads.

[0182] Nevertheless, embodiments of the present invention can be used with different die sizes for the edgepad semiconductor die 602 and different bonding pitches for the edgepads 601. For example, referring to Figure 12B, each edgepad semiconductor die 602 may have a reticle size or maximum scanner field of view (MSFA) of 26 mm (for width W4) × 33 mm (for length L4). Assuming that a bonding pitch of approximately 100 μm is used, each edgepad semiconductor die 602 may have 330 I / O edgepads 601 along the 33 mm length direction, and half of the 330 I / O edgepads 601, i.e., 165 bits of I / O edgepad 601 data width, can be used for the data bus. If the NuHBM system 610 includes 24 edgepad semiconductor dies 602, then the NuHBM system 600 in the illustrated embodiment has 3,960 data I / O edgepads 601 (24 × 165 = 3,960), which is larger than the 2K bit data width used in the HBM4 specification. Such an edgepad semiconductor die 602 having a reticle of 26 mm (width W4) × 33 mm (length L4) may have a capacity of approximately 172.7 to 207.2 Gb. For example, the DRAM cell size for 1 bit storage is approximately 0.002484 μm 2 Therefore, if the cell efficiency is 50%, then 33mm × 26mm × 0.5 / 0.002484μm 2 = 172.7 Gb (gigabits), and if the cell efficiency is 60%, then 33 mm × 26 mm × 0.6 / 0.002484 μm 2= 207.2 Gb. Therefore, if there are 24 edge pad semiconductor dies 602 coupled together in one NuHBM system 610, the NuHBM system 610 can provide a capacity of approximately 518.1 to 621.6 Gb (24 × 172.7 Gb to 24 × 207.2 Gb). Of course, in the present invention, larger edge pad semiconductor dies 602 can also be used for larger storage capacities. For example, each edge pad semiconductor die 602 may have a die size of approximately 26 × 2 mm (for width W), 33 × 3 mm (for length L), and 100 μm (for thickness T), where the die area is equal to 6 reticle sizes (each reticle size is represented as 26 mm × 33 mm). Each edge pad semiconductor die 602 may include edge pads 601 arranged along the longitudinal sidewalls of the edge pad semiconductor die 602. Therefore, in some embodiments, each edge pad semiconductor die 602 can have about 5K edge pads 601 when the pad pitch is about 20 μm (99 mm / 20 μm) in the longitudinal direction (L3), and at least 2.5K or more edge pads 601 can be used as data pads.

[0183] Figure 12C is a three-dimensional view of Figure 12A or Figure 12B, and as described above, power / control / data signals from each edge pad semiconductor die 602 of the NuHBM system 610 can be propagated to the memory controller 61 without going through other edge pad semiconductor dies 602. Furthermore, a high thermal conductivity layer 604 (AlN, BN, W, SiC, copper, etc.) is placed between two adjacent edge pad semiconductor dies 602 and is connected to a top high thermal conductivity layer 606 on the other side wall of the NuHBM system 610, so that the heat generated from these edge pad semiconductor dies 602 can be diffused through the high thermal conductivity layer 604 to the top high thermal conductivity layer 606 and transferred to another heat sink (not shown) connected to the top high thermal conductivity layer 606. Note that Figures 12A, 12B, and 12C of this embodiment are schematic diagrams only, and the components in the figures may not be proportional to their actual size.

[0184] As shown in Figure 12C, if each edge pad semiconductor die 602 has a length of 33 mm and a width of 26 mm (i.e., the die area is 26 mm × 33 mm, which is equal to one reticle size), then to accommodate a NuHBM system 610 having such edge pad semiconductor dies 602, the die area of ​​the memory controller 61 could be 26 mm (width) * 66 mm (length), which is approximately two reticle sizes. However, since the width (W) of a NuHBM system 610 having 24 edge pad semiconductor dies 602 and 24 high thermal conductivity layers 604 is just about 4.8 mm (the thickness of each edge pad semiconductor die 602 and each high thermal conductivity layer 604 is about 100 μm), the remaining die area of ​​the memory controller 61 can still accommodate another SOC chip 63 such as a CPU or GPU. The area of ​​the memory controller 61 depends on the size and number of the NuHBM system 610 and the SOC chips 63. Furthermore, it is possible for two or more NuHBM systems 610 to exist on the memory controller 61.

[0185] Both the SOC die 63 and the edge pad semiconductor die 602 are designed to be positioned on the surface of the memory controller 61. Their I / Os are well connected by a monolithic interconnect. The output pads of the SOC die 63 are electrically connected to the package substrate 64 via the memory controller 61. On the memory controller 61, the controller circuitry is designed on the front side, indicated by a dashed line labeled "BEOL" (back-end of line), and is well connected to the I / Os of the SOC die 63, which are designed on the bottom side (indicated by a dashed line labeled "BEOL"). In this memory controller 61, the TSV 611 is formed across the die thickness, and microbumps or hybrid bumps 612 are electrically connected to the TSV 611. The I / Os of the SOC die 63 can be electrically connected to the I / O edge pads of the semiconductor die 602 via the memory controller 61. The memory controller 61 is then electrically connected to the package substrate 64 with a well-designed alignment. In some embodiments, the thickness (T) of the memory controller 61 is approximately 750 μm.

[0186] In this example, the memory controller 61 is facing upwards (indicated by a dashed line labeled "BEOL" in Figure 12A), but in another example, the memory controller 61 can be facing downwards or inverted and connected to the package substrate 64. Because the TSV 611 is located within the memory controller 61, the edge pad semiconductor die (or semiconductor die) 602 can be electrically connected to the memory controller 61 via the TSV 611 within it or via an RDL (not shown) on the memory controller 61.

[0187] These I / Os output high-bandwidth data, and the memory controller 61 can be designed to select an appropriate number of I / Os (e.g., some of the data I / Os of one semiconductor die 602, all of the data I / Os of one semiconductor die 602, some of the data I / Os of multiple semiconductor dies 602, or all of the data I / Os of multiple semiconductor dies 602) by crossbar circuit design. In another embodiment, an SRAM array is used to conduct some or all of the data I / Os of the NuHBM shelf 610 from some or all of the semiconductor dies 602. For example, multiple SRAM arrays each correspond to multiple semiconductor dies 602, and each SRAM array temporarily holds a selected appropriate number of I / Os from the corresponding semiconductor die 602. In some embodiments, multiple edge pads 601 of each semiconductor die 602 include a subset of data pads, and the memory controller 61 selects a predetermined data bit from the data pads 601 of one semiconductor die 602, some of the data pads 601 of multiple semiconductor dies 602, or all of the data pads 601 of multiple semiconductor dies 602. The appropriate number of I / O pins for each semiconductor die 602 can be set by a mode register within each semiconductor die 602.

[0188] As described above, the memory controller 61 of the present invention includes a plurality of TSVs 611, and as a result, power / control / data signals of each semiconductor die 602 and / or SOC die 63 can be received or transmitted to the package substrate 64 via the memory controller 61, as shown in Figure 12A. Furthermore, the heat sink 65 is placed on top of the SOC die 63, and as a result, the top surface of the combination of the heat sink 65 and the SOC die 63 may be flush with the top surface of the NuHBM shelf 610.

[0189] Figure 13A shows another 3D IC structure 70 according to some embodiments of the present disclosure, and Figure 13B is a stereoscopic view of that 3D IC structure 70. As shown in the right plot of Figure 13A, the 3D IC structure 70 includes a package substrate 74, a logic die 71 including a memory controller and processor circuit, and a NuHBM system or stack 710 including a plurality of edge pad semiconductor dies 705, optionally a plurality of high thermal conductivity layers 704, and optionally a top high thermal conductivity layer 706. The NuHBM system 710 is electrically connected to the package substrate 74 via the logic dies 71. Each semiconductor die 705 may include an edge pad 703 arranged along the longitudinal (L3) sidewall 705S1 of the semiconductor die 705. The materials and configurations of the package substrate 74, edge pad semiconductor die 705, high thermal conductivity layer 704, and top high thermal conductivity layer 706 are the same as those of the package substrate 64, edge pad semiconductor die 602, high thermal conductivity layer 604, and top high thermal conductivity layer 606, respectively, and for brevity, the details of these features will not be repeated.

[0190] As shown in Figure 13A, the SOC die (or processor circuit) is combined with the memory controller to form a single logic die; that is, the logic die 71 below the NuHBM shelf 710 includes not only the memory controller 712 but also the SOC die 713 (e.g., GPU, CPU, NPU, TPU, FPGA, etc.), and the memory controller 712 of the logic die 71 can be located directly below the NuHBM shelf 710. In this embodiment, the logic die 71 is placed on the packaging substrate 74 in a flip-chip manner, that is, the memory controller 712 and SOC 713 circuits are designed on the bottom surface of the logic die 71 (indicated by a dashed line labeled "BEOL"). The logic die 71 further includes a TSV 711 that penetrates the logic die 71 (particularly from the memory controller circuit to the NuHBM shelf 710) and optionally includes RDLs (not shown) on both sides. Naturally, a heatsink (not shown) may be placed on the SOC die area, and as a result, the top surface of the heatsink may be flush with the top surface of the NuHBM shelf 710. Similarly, Figures 13A and 13B of this embodiment are merely schematic diagrams, and the components shown in the figures may not be proportional to their actual size.

[0191] Furthermore, the NuHBM shelf 710 includes a high thermal conductivity layer 704 (AlN, BN, W, copper, etc.) between two adjacent semiconductor dies 705, which is connected to a top high thermal conductivity layer 706 on the other side wall of the NuHBM shelf 710. Thus, the heat generated from these semiconductor dies 705 can be diffused through the high thermal conductivity layer 704 to the top high thermal conductivity layer 706 and transferred to another heat sink (not shown) connected to the top high thermal conductivity layer 706.

[0192] In this example, the logic die 71 is facing downwards (indicated by a dashed line labeled "BEOL" in Figure 13A), but in another example, the logic die 71 may be facing upwards. Since the logic die 71 includes a TSV 711 and may further include an RDL, the logic die 71 can be electrically connected to the package substrate 74 via the TSV 711 in this embodiment. Furthermore, the signal and power connections / transmissions in the present invention may be based either on the logic die 71 or on the package substrate 74 (through the logic die 71).

[0193] Figure 14A shows another 3D IC structure 80 according to some embodiments of the present disclosure, and Figure 14B is a stereoscopic view of the 3D IC structure 80. As shown in the right plot of Figure 14A, the 3D IC structure 80 includes a package substrate 84, a logic die 81 including a memory controller and processor circuit, a plurality of edge pad semiconductor dies 802, optionally a plurality of high thermal conductivity layers 804, and optionally a top high thermal conductivity layer 806, and a NuHBM system or NuHBM shelf 800. Each semiconductor die 802 may include an edge pad 801 arranged along the longitudinal side wall 802S1 of the semiconductor die 802 (L3). The NuHBM system 800 is physically and electrically coupled to the package substrate 84. The materials and configurations of the semiconductor die 802, the high thermal conductivity layer 804, and the top high thermal conductivity layer 806 are the same as those of the semiconductor die 602, the high thermal conductivity layer 604, and the top high thermal conductivity layer 606, respectively. For brevity, the details of these features will not be repeated.

[0194] As shown in Figure 14A, the NuHBM system 800 and the logic die 81 are arranged separately on the packaging substrate 84. In some embodiments, the packaging substrate 84 includes a base portion 841 formed of the same material as the packaging substrate 64 or 74, and an EMIB (Embedded Multi-die Interconnect Bridge) 842 embedded in the base portion 841, the EMIB 842 being exposed from the top surface of the base portion 841 of the packaging substrate 84 and used for electrical connection between the NuHBM system 800 and the logic die 81. Here again, the logic die 81 is arranged on the packaging substrate 84 in a flip-chip manner, i.e., the memory controller and SOC or processor circuitry are designed on the bottom surface of the logic die 81 (indicated by a dashed line labeled "BEOL"). However, there is no TSV penetrating the logic die 81. Naturally, there may be a heatsink (not shown) on the logic die 81, and as a result, the top surface of the heatsink may be flush with the top surface of the NuHBM system 800. Similarly, Figures 14A and 14B of this embodiment are purely schematic diagrams, and the components shown in these drawings may not be proportional to their actual sizes.

[0195] In this example, the logic die 81 is facing downwards (indicated by a dashed line labeled "BEOL" in Figure 14A), but in another example, the logic die 81 may be facing upwards. Since TSVs and / or RDLs (not shown) may be present within the logic die 81, the logic die 81 may be electrically connected to the package substrate 84 through these TSVs. Furthermore, the signal and power connections / transmissions in this invention may be based either on the logic die 81 or on the package substrate 84.

[0196] Figure 15A shows another 3D IC structure 90 according to some embodiments of the present disclosure, and Figure 15B is a stereoscopic view of the 3D IC structure 90. As shown in the right plot of Figure 15A, the 3D IC structure 90 includes a package substrate 94, a memory controller 91, a plurality of NuHBM systems or shelves 900 (each including a plurality of edge pad semiconductor dies 902, a plurality of high thermal conductivity layers 904, and a top high thermal conductivity layer 906), an SOC chip 93, and a heat sink 95. Each NuHBM system 900 is separately electrically coupled to the package substrate 94. Each semiconductor die 902 may include an edge pad 901 arranged along the longitudinal (L5) side wall 902S1 of the HBM die 902. The SOC chip 93 is electrically connected to the package substrate 94 via the memory controller 91. The materials and configurations of the package substrate 94, semiconductor die 902, high thermal conductivity layer 904, top high thermal conductivity layer 906, memory controller 91, SOC chip 93, and heat sink 95 are the same as those of the package substrate 64, semiconductor die 602, high thermal conductivity layer 604, top high thermal conductivity layer 606, SOC chip 63, and heat sink 65, respectively, and for brevity, the details of these features will not be repeated.

[0197] In some embodiments, 24 semiconductor dies 902 are divided into 6 NuHBM systems 900, each NuHBM system 900 comprising 4 semiconductor dies 902. These NuHBM systems 900 are arranged on the four sides (26 mm × 33 mm) of the SOC die 93, as shown in Figure 15B. Two NuHBM systems 900 are arranged along the longitudinal side (length 33 mm) of the SOC die 93, two other NuHBM systems 900 are arranged along the opposite longitudinal side (length 33 mm) of the SOC die 93, one NuHBM system 900 is arranged along the widthwise side (width 26 mm) of the SOC die 93, and another NuHBM system 900 is arranged along the opposite widthwise side (width 26 mm) of the SOC die 93. Similarly, Figures 15A and 15B of this embodiment are merely schematic diagrams, and the components of these drawings may not be proportional to the actual dimensions.

[0198] If each semiconductor die 902 is an LPDDR5 DRAM chip having special dimensions of 6.25 mm width (W5) × 10 mm length (L5), and the bonding pitch is 20 μm, it may have 500 edge pads along a 10 mm long sidewall 902S1. Assuming that approximately half of the edge pads are used for data I / O, each semiconductor die 902 can have a data width of 256 bits. If four such 16 Gb LPDDR5 chips are stacked horizontally as a NuHBM system 900, each NuHBM system 900 can have a data width of 1024 bits and a bandwidth of approximately 9830 Gb / s (1024 × 9.6 Gb / s). Since the 3D IC structure 90 includes six NuHBM systems 900, the total of six NuHBM systems 900 can have a data width of 6K bits and a bandwidth of approximately 58980 Gb / s (6 × 10²⁴ × 9.6 Gb / s, with each I / O pad having a bandwidth of 9.6 Gb / s).

[0199] If the bonding pitch is 10 μm, there may be 1000 edge pads along a 10 mm long sidewall. Assuming that approximately half of the edge pads are used for data I / O, each HBM die 902 can have a data width of 512 bits. If four such 16 Gb LPDDR5 chips are stacked horizontally as a NuHBM system 900, each NuHBM system 900 can have a data width of 2048 bits and a bandwidth of approximately 19660 Gb / s (2048 × 9.6 Gb / s). Thus, a 3D IC structure 90 containing six NuHBM systems 900 can have a data width of 12 K bits and a bandwidth of approximately 117964 Gb / s (6 × 2048 × 9.6 Gb / s). If each semiconductor die 902 in the NuHBM system 900 has a capacity of 32 Gb, then each 4-layer NuHBM system 900 can have a capacity of 32 Gb × 4 = 128 Gb, and a total of 6 NuHBM systems 900 can support a capacity of 128 Gb × 6 = 768 Gb.

[0200] Naturally, each NuHBM system 900 may have 6, 8, 10, or more semiconductor dies 902 in the present invention. For example, in Figures 15A and 15B, each NuHBM system 900 may have 10 semiconductor dies 902, resulting in a total of 60 semiconductor dies 902. Again, if each semiconductor die 902 is an LPDDR5 DRAM chip having special dimensions of 6.25 mm width × 10 mm length, and the bonding pitch is 20 μm, it may have 500 edge pads (which may include a 256-bit data width) along a 10 mm long sidewall 902S1. Each NuHBM system 900 can have a data width of 2560 bits (256 bits × 10) and a bandwidth of approximately 24576 Gb / s (2560 × 9.6 Gb / s, with each I / O pad having a bandwidth of 9.6 Gb / s). Since the 3D IC structure 90 includes six NuHBM systems 900, the total of six NuHBM systems 900 can have a data width of 15,360 bits and a bandwidth of approximately 147,456 Gb / s (6 × 2560 × 9.6 Gb / s). If the bonding pitch is 10 μm, there may be 1000 edge pads (which may include a 512-bit data width) along a sidewall having a length of 10 mm. Each NuHBM system 900 can have a data width of 5120 bits (512 bits × 10) and a bandwidth of approximately 49,152 Gb / s (5120 × 9.6 Gb / s). Thus, the 3D IC structure 90 including the six NuHBM systems 900 can have a data width of 12,000 bits and a bandwidth of approximately 294,912 Gb / s (6 × 5120 × 9.6 Gb / s). If each semiconductor die 902 in the NuHBM system 900 has a capacity of 32Gb, then each 10-layer NuHBM system 900 can have a capacity of 32Gb × 10 = 320Gb, and a total of 6 NuHBM systems 900 can support a capacity of 320Gb × 6 = 1920Gb.

[0201] The table below shows a comparison between several existing HBM systems (HBM3, HBM3E, and HBM3E) and the proposed NuHBM system (based on the LPDDR5 specification). [Table 1]

[0202] Under the above architecture for designing a distributed NuHBM system 900 surrounding the four sides of the SOC chip 93, each semiconductor 902 can be reliably achieved using today's DRAM design skills compliant with LPDDR5 specifications (also applicable to JEDEC standards). These I / Os of the NuHBM system 900 are electrically connected to the I / Os of the SOC die 93, which should use advanced logic technologies such as 3nm or 5nm, by advanced bonding techniques such as microbump or hybrid bonding, thereby realizing a high-performance, low-power SOC-DRAM (HBM) interface. The power distribution system can be achieved by a vertical TSV / RDL connection between the bottom of the NuHBM system 900 and the bottom of the SOC chip 93 in the memory controller 91 (see Figure 15A), thus enabling the establishment of a large and stable current flow system.

[0203] In the embodiments shown in Figures 15A and 15B, six NuHBM systems 900 and SOC dies 93 are arranged on a memory controller 91, and the memory controller 91 is then arranged on a packaging substrate 94. The memory controller 91 includes a plurality of TSVs 911. Each NuHBM system 900 includes four or more layers of a stacked semiconductor die 902, along with the heat dissipation system and edge I / O invention of the present invention. Furthermore, data latency in both row data and column data read / write (R / W) performance should be achieved in the same manner as that of the LPDDR5 specification as described in Figures 10A and 10B, and the LPDDR5 latency specification should be achieved.

[0204] The above embodiments describe an example of the proposed architecture of the present invention for designing a NuHBM system to supply high-bandwidth / low-latency memory data to an SOC die. For example, if 24 semiconductor dies 902 are distributed across 8 NuHBM systems 900, each NuHBM system 900 contains only 3 semiconductor dies 902.

[0205] Figure 16 shows another 3D IC structure 1001 of the present disclosure. The 3D IC structure 1001 includes a package substrate 1040, a logic die 1010 having a memory controller 1012 and an SOC or processor circuit 1013, and a plurality of NuHBM systems 1000 (each including a plurality of edge pad semiconductor dies 1002, optionally a plurality of high thermal conductivity layers 1004, and optionally a top high thermal conductivity layer 1006). Each NuHBM system 1000 is electrically connected to the package substrate 1040 via a logic die 91. The materials and configurations of the package substrate 1040, semiconductor die 1002, high thermal conductivity layer 1004, top high thermal conductivity layer 1006, and logic die 1010 are the same as those of the package substrate 74, semiconductor die 705, high thermal conductivity layer 704, top high thermal conductivity layer 706, and logic die 71, respectively, and for brevity, the details of these features will not be repeated.

[0206] Similar to Figure 15B, the 3D IC structure 1001 in Figure 16 may include 24 edge-pad semiconductor dies 1002 divided into six NuHBM systems 1000, each NuHBM system 1000 comprising four semiconductor dies 1002. However, unlike Figure 15B, the SOC circuit 1013 in this embodiment is combined with the memory controller 1012 and logic die 1010, and the six NuHBM systems 1000 are stacked on the logic die 1010 together with the memory controller 1012 and the SOC or processor circuit 1013. These six NuHBM systems 1000 can be coupled close to the memory controller 1012, as shown in Figure 16. Similarly, Figure 16 of this embodiment is a schematic representation only, and the components of those drawings may not be proportional to their actual sizes.

[0207] Next, as shown in Figure 17A, the low IC structure stack 312 or semiconductor package 700A can be bonded to another interposer or IC chip to form a semiconductor package assembly 1900 including a 3D IC structure stack 1901, a substrate 1902, an interposer 1904, and a logic control chip 1906. In this embodiment, the 3D IC structure stack 1901 includes a plurality of DRAM semiconductor dies 1920 (or a plurality of DRAM dies and control ICs) and a side RDL 118, each DRAM semiconductor die 1920 being horizontally separated from the others. The laterally extending RDL structures 118 on the side walls of the plurality of DRAM semiconductor dies (or DRAM and control ICs) 1920 are bonded to the logic memory control chip 1906 or interposer 1904, which is then bonded to the substrate 1902. The power / signaling function of each DRAM semiconductor die 1920 can be addressed by using an RDL structure 118 connected to a logic memory control chip 1906 and an interposer 1904. Unlike conventional HBM structures, in the present invention, each DRAM semiconductor die 1920 can transmit or receive power / signals independently without passing through other DRAM semiconductor dies, and each DRAM semiconductor die can generate high-bandwidth data with low latency, and can therefore be appropriately called HBLM (High-Bandwidth Low-Latency Memory), and a combination of horizontally separated DRAM semiconductor dies 1920 can be called an HBLM shelf.

[0208] Furthermore, an HTC adhesive layer 1908 may be present between the primary surfaces of two adjacent DRAM semiconductor dies 1920, which may be connected to an (upward-extending) intermediate high thermal conductivity layer 1912 (of AlN, BN, W, copper, SiC, etc.) and optionally to a (lateral-extending) top HTC layer 1914 (of AlN, BN, W, copper, SiC, etc.) located on the other sidewall of a low 3D IC structure stack 1901. Thus, heat generated from these two DRAM semiconductor dies 1920 can be transferred from the dies through the high thermal conductivity layer 1912 to the top high thermal conductivity layer 1914, and then to a heat sink device (e.g., a cold plate; not shown) thermally coupled to the HTC layer 1914.

[0209] According to some embodiments, the RDL118 further includes a plurality of bonding pads 1927 on the top surface of the RDL118 to electrically connect the interposer 1904 to the DRAM semiconductor die 1920.

[0210] As described above, if there is a need for more signal transmission in multiple DRAM semiconductor dies 1920, more upward-extending RDL structures 1916 may be formed on two or more sides, as shown in Figure 17B, the bottom RDL structure 118 may be formed on one side of the multiple DRAM semiconductor dies 1920, and another side RDL structure (or multiple side RDL structures) may be formed on the other side of the multiple DRAM semiconductor dies 1920 opposite or adjacent to the mutually high thermal conductivity layer 1912, and the bottom RDL structure 118 is electrically connected to these side RDL structures 1916.

[0211] As described above, when it is necessary to have more heat dissipation in multiple DRAM semiconductor dies 1920, more intermediate HTC layers 1917 similar to the intermediate HTC 1912 or top HTC 1914 may be formed on one or two of two or more sides and / or primary surfaces, as shown in Figure 17B, and the intermediate HTC layers 1917 are thermally bonded to the top HTC 1914 and intermediate HTC 1912. According to some embodiments, the HTC layers 1912, 1914, and 1917 have a higher thermal conductivity than silicon or SiO2.

[0212] According to some embodiments, referring to Figures 17A and 17B, the IC stack 1901 includes a plurality of IC structures 1920 separated horizontally from each other. Each IC structure 1920 can be a semiconductor structure as shown in Figures 2C-2F, 3D-3F, 4G-4N, and 5A-5B, and has a top surface 108P1, a bottom surface 108P2 opposite the top surface 108P1, a first side wall 1920S1 or 108S1, a second side wall 1920S2 or 108S2, a third side wall 1920S3 or 108S3 (parallel to the paper sheet), and four side walls 108S having a fourth side wall (a side wall parallel to the paper sheet, opposite to the side wall 1920S3 shown in Figure 17B, or side wall 108S4 in Figure 2D). The area of ​​the base surface 108P2 or the top surface 108P1 is larger than the area of ​​any side wall 102S in Figure 2C, for example, 1920S1 (108S1), 1920S2 (108S2), 1920S3 (108S3), or 108S4. The low 3D IC stack 1901 may further include a laterally extending RDL structure 118 covering the first side wall 1920S1 of each of the multiple IC structures 1920.

[0213] Referring to several embodiments, specifically Figures 17A, 17B, 4G-4N, 5A-5B, and 6E, each semiconductor structure includes a first integrated circuit (IC) structure, such as the IC structure 1920 in Figure 17A or 17B, or the die 122E in Figures 4G-4N, and a first adjacent structure, such as a high thermal conductivity layer 1912 in Figure 17A or 17B, or a molded compound layer 242 and / or die 122D in Figures 4G-4N, which is physically separated from the first IC structure. The first IC structure and the first adjacent structure are (1) arranged along a first sidewall 1912S1 extending in the Z direction in Figure 17A or 17B, or (2) arranged along a first sidewall 1912S1 extending in the XZ plane in Figure 17A or 17B. In the above condition (2), referring to Figures 4K to 4N, the respective XZ planes of IC structures 400E to 400H may face the RDL structure 118 and form an electrical connection with the RDL structure. The first IC structure 122E and the first adjacent structure 122D may be arranged on the respective XZ planes of IC structures 400E to 400H along the X direction shown in Figure 17A or Figure 17B. According to some embodiments, the laterally extending RDL structure 118 shown in Figures 17A and 17B comprises a first plurality of bonding pads 1927 arranged along the first sidewall of each semiconductor structure 1920, the first plurality of bonding pads being on or facing the edges of the first IC structure and the edges of the first adjacent structure.

[0214] In some embodiments, the first IC structure may include a plurality of semiconductor dies, for example, dies 122E, 122G, and / or 122H shown in Figures 4K to 4N or Figure 6D. The first adjacent structure 122D may be an active die or an HTC dummy interconnect spacer. The interconnect spacer may be a passive or active silicon interposer. According to some embodiments, the interconnect spacer is a semiconductor interposer having a set of through-semiconductor vias (TSVs) electrically coupled to a plurality of first bonding pads or a subset of external connectors.

[0215] According to some embodiments, the first adjacent structure includes another IC structure such as the semiconductor die 122D shown in Figures 4G to 4N, an interconnection spacer such as the interposer 122D shown in Figures 4G to 4N, a molded compound layer such as the potting material or molded compound layer 242 shown in Figures 4G to 4N, or a high thermal conductivity (HTC) layer such as the die 122D shown in Figures 4G to 4N, and has a thermal conductivity higher than that of Si or SiO2 to dissipate heat generated from the adjacent IC structure.

[0216] According to some embodiments, the number of first multiple bonding pads 1927 exceeds 1,300 to 1,500 per IC structure 1920.

[0217] Referring to some embodiments, specifically Figures 4G, 4I, 4K, 4M, 5A, and 5B, a first IC structure 122E or another IC structure acting as a first adjacent structure includes a set of through-semiconductor vias (TSVs) 104B exposed from the side wall 102S in the XZ plane and electrically coupled to a subset of first multiple bonding pads 1927 of a laterally extending RDL structure 118 of a 3D IC stack 1901 shown in Figure 17A or 17B.

[0218] According to some embodiments, referring to Figures 4G, 4H, 4K, 4L, 5A, and 5B, the molded compound layer 242 includes a set of molded through-vias (TMVs) 232 that are exposed from the molded sidewall 102S in the XZ plane and electrically coupled to a subset of a first plurality of bonding pads 1927 of a laterally extending RDL structure 118 of the 3D IC stack 1901 shown in Figure 17A or 17B (see also, for example, RDL 118A shown in Figure 5A or 5B).

[0219] According to some embodiments, with reference to Figures 4G, 4H, 4K, 4L, 5A, and 5B, the first adjacent structure 122D may include interconnect spacers with or without active components, along with a set of through-semiconductor vias (TSVs) similar to the TSV 104B in the first IC structure 122E, which are exposed from the side wall 102S in the XZ plane and electrically coupled to a subset of the first plurality of bonding pads 1927 of the laterally extending RDL structure 118 of the low 3D IC stack 1901 shown in Figure 17A or 17B.

[0220] According to some embodiments, the IC stack 1901 further includes a high thermal conductivity structure, such as the interposer 1702 or 1706 of Figure 17, between two semiconductor structures 1920, 1912, or next to some of the semiconductor structures 1920, 1912 of the IC stack 1901, in a manner similar to the mutually high thermal conductivity layer 1912 shown in Figure 17A or Figure 17B. The thermal conductivity of the high thermal conductivity structure is higher than that of Si or SiO2.

[0221] According to some embodiments, each IC structure 1920 can be a DRAM semiconductor die, and the IC stack 1901 can be an HBM-compatible structure.

[0222] According to some embodiments, the IC stack 1901 further includes a logic control chip 1906 that lies beneath a laterally extending RDL structure 118 of the IC stack 1901 and is electrically connected thereto.

[0223] According to some embodiments, referring to Figure 17A or Figure 17B, the IC stack 1901 further includes a transversely extending thermal conductive layer 1914 covering each second side wall 1920S2 of a plurality of IC structures 1920, the transversely extending RDL structure 118 is on the opposite side of the transversely extending thermal conductive layer 1914, and the thermal conductivity of the transversely extending thermal conductive layer is higher than that of Si or SiO2.

[0224] Referring to some embodiments, specifically Figures 17A and 17B, the IC stack 1901 includes a plurality of IC structures 1920 separated horizontally from each other. Referring to Figures 2C-2F, 3D-3F, 4G-4N, 5A-5B and 17A, each IC structure 1920 can be referred to as IC structures 100A, 100A, 300A-300C, 400A-400H, 500A and 500B in Figures 2C-2F, 3D-3F, 4G-4N and 5A-5B. As shown in Figure 2D, each IC structure 1920 has dimensions similar to those of the RDL structure 108A and includes a top surface 108P1, a bottom surface 108P2 opposite the top surface 108P1, and four side walls having a first side wall 1920S1 or 108S1, a second side wall 1920S2 or 108S2, a third side wall 1920S3 or 108S3, and a fourth side wall 108S4. The area of ​​the bottom surface 108S2 or the top surface 108S1 is larger than the area of ​​any of the side walls, e.g., 1920S1(108S1), 1920S2(108S2), 1920S3(108S3), and 108S4. The IC stack 1901 may further include a laterally extending RDL structure 118 covering each of the first side walls 1920S1 (108S1) of each of the multiple IC structures 1920. The IC stack 1901 may also include an upwardly extending thermal conductive layer 1912 between two adjacent IC structures 1920. According to some embodiments, the thermal conductivity of the upwardly extending thermal conductive layer 1912 is higher than the thermal conductivity of Si or SiO2, such as a SiC chip having the same size as the IC structure 1920.

[0225] According to some embodiments, the IC stack 1901 further includes a transversely extending thermal conductive layer 1914 that covers each second side wall 108S2 or 1920S2 of a plurality of IC structures 1920 and is thermally bonded to each of the upwardly extending thermal conductive layers 1912, the transversely extending RDL structure 118 is on the opposite side of the transversely extending thermal conductive layer 1914, and the thermal conductivity of the transversely extending thermal conductive layer 1914 is higher than the thermal conductivity of Si or SiO2 such as a SiC chip.

[0226] According to some embodiments, the upward-extending thermal conductive layer 1912 or the laterally-extending thermal conductive layer 1914 comprises a material such as BN, AlN, W, SiC, or copper.

[0227] According to some embodiments, referring to Figure 17B, the IC stack 1901 further includes an upward-extending RDL structure 1916 covering each third side wall 108S3 or 1920S3 of a plurality of IC structures 1920, the upward-extending RDL structure 1916 being electrically connected to a laterally-extending RDL structure 118.

[0228] According to some embodiments, each IC structure 1920 includes a DRAM semiconductor die, and the IC stack 1901 is an HBM-compatible structure (i.e., essential signals passing through its own I / O pads P31-P3N are compatible with the signal paths defined by JEDEC for HBM).

[0229] According to some embodiments, the IC stack 1901 further includes a logic control chip 1906 that lies beneath a laterally extending RDL structure 118 of the IC stack 1901 and is electrically connected thereto.

[0230] Referring to several embodiments, with reference to Figures 17A, 19B and Figures 2C, 2D-2F, 3D-3F, 4G-4N, 5A, 5B and 6E, the IC structure 1920 may include the IC structures 100A-100C, 300A-300C, 400A-400H, 500A, 500B and 600A described herein. For example, with reference to Figures 5A, 5B and Figure 17A or 17B, the IC structure 1920 includes IC structure 500A, the IC structure includes a first semiconductor body 122F and an interconnection structure 108A or 108B. The first semiconductor body (122E or 122F) has a first primary surface (102P) and a first secondary surface (102S), the first primary surface being substantially perpendicular to the first secondary surface. The interconnection structure includes a primary redistribution layer (RDL) (Figure 5A, 108A) on a first primary surface 102P, the primary RDL 108A having a second secondary surface (Figure 5A, 108S) aligned with the first secondary surface 102S of the first semiconductor body 122F, the first secondary surface 102S and the second secondary surface 108S together forming a secondary plane (Figure 5A, 500AS) that can correspond to the first sidewall 1920S1 or the second sidewall 1920S2 of the IC structure 1920, and the primary RDL 108S further comprises a first conductive element (Figure 5A, 212, 214) exposed through the second secondary surface 108S of the primary RDL 108A.

[0231] According to some embodiments, the first conductive element may be a conductive pad 212 on the surface 108P of the primary RDL structure 108A / 108B substantially parallel to the first primary surface 102P1 (see Figure 2C), a conductive via 216 connecting adjacent layers of the primary RDL 118A / 118B (see Figure 2G), a stacked via 214 traversing the primary RDL 118A / 118B (see Figure 2G), or a combination thereof.

[0232] According to some embodiments, the first semiconductor body (122E in Figure 4G or Figure 4I) further includes at least through-silicon vias 104B (Figure 4G), molded through-vias 232 (Figure 4G), or insulating elements 242 (Figure 4I) exposed through the first secondary surface.

[0233] According to some embodiments, the first semiconductor body of the IC structure 1920 shown in Figure 17A or Figure 17B may be a counterpart to the semiconductor dies 400A to 400H or 600A shown in Figures 4K to 4N or Figure 6E, and may include (1) a plurality of first dies 122D and 122E arranged in the same package layer (Figures 4K to 4N), (2) a plurality of second dies 122G and 122H stacked vertically (Figure 6E), (3) a plurality of second dies 122G and 122H arranged alongside another third die 122E in the same package layer (Figure 6E), or a combination thereof. The first, second, and third dies 122D, 122E, 122G, and 122H may be the same or different in size.

[0234] According to some embodiments, the first semiconductor body of the IC structure 1920 shown in Figure 17A or 19B (see the substructure of the semiconductor die 600A excluding the primary RDL 108C) also includes a plurality of conductive vias 104B (see semiconductor die 122E), pillars 224, or plugs 234 of the same or different lengths, which electrically connect a plurality of first dies 122E, 122G, and 122H to the primary RDL 108C along the Z axis as shown in Figure 6E, and / or to a laterally extending RDL structure 118 in the XZ plane as shown in Figure 6E, Figure 17A, or Figure 17B.

[0235] According to some embodiments, the laterally extending RDL structure 118 shown in Figure 17A or Figure 17B is electrically connected to the first conductive element of the primary RDL, to the conductive pad 212 or conductive via 214 shown in Figure 4G or Figure 6D, and to the pillar 224 or plug 234 shown in Figure 6D.

[0236] According to some embodiments, the laterally extending RDL structure 118 (corresponding to RDL118A shown in Figure 7I) includes a hybrid bonding layer or a bump pad array (244).

[0237] Referring to several embodiments, specifically Figures 17A and 17B, the IC stack 1901 includes a plurality of IC structures 1920 separated horizontally from each other. Referring to Figures 2C, 2D, and 17A, each IC structure 1920 can be a structure 108A as shown in Figure 2D, and includes a top surface 108P1, a bottom surface 108P2 opposite the top surface, and four side walls, including a first side wall 1920S1 or 108S1, a second side wall 1920S2 or 108S2, a third side wall 1920S3 or 108S3, and a fourth side wall 108S4. The area of ​​the bottom or top surface is greater than the area of ​​any of the four side walls, for example, 1920S1 (108S1), 1920S2 (108S2), 1920S3 (108S3), and 108S4. The IC stack 1901 may further include a laterally extending RDL structure 118 that covers each of the first side walls 1920S1 (108S1) of each of the multiple IC structures 1920.

[0238] According to some embodiments, the IC stack 1901 further includes a set of upward-extending thermal conductive layers 1912, the corresponding upward-extending thermal conductive layers 1912 being positioned between any two adjacent IC structures 1920 of a plurality of IC structures 1920. The IC stack 1901 may also include a first lateral-extending thermal conductive layer 1914 that covers each second side wall 1920S2(108S2) of each of the plurality of IC structures 1920 and is thermally coupled to the set of upward-extending thermal conductive layers 1912. The thermal conductivity of either the upward-extending thermal conductive layer 1912 or the first lateral-extending thermal conductive layer 1914 is higher than the thermal conductivity of Si or SiO2.

[0239] According to some embodiments, referring to Figure 17B, the IC stack 1901 further includes a second transversely extending thermal conductive layer 1917 covering each of the third side walls 1920S3(108S3) of a plurality of IC structures 1920. The second transversely extending thermal conductive layer 1917 is thermally coupled to a set of upwardly extending thermal conductive layers 1912.

[0240] According to some embodiments, the IC stack 1901 is an HBM-compatible structure, and each IC structure 1920 includes a DRAM semiconductor die 1920. The IC stack 1901 further includes a logic control chip 1906 that lies beneath a laterally extended RDL structure 118 of the IC stack 1901 and is electrically connected thereto.

[0241] The present invention provides a 3D IC structure having at least one NuHBM system comprising multiple horizontally stacked edge-pad semiconductor dies. Unlike existing HBM structures, the edge pads of each semiconductor die are positioned on the sides of the semiconductor die for interconnection, enabling skip-die signaling and power distribution without going through other semiconductor dies. Compared to existing DRAM chips used in HBM, die thinning is unnecessary because there are no TSVs within each semiconductor die. Furthermore, a high thermal conductivity material is placed between two adjacent semiconductor dies and optionally coupled to another high thermal conductivity material covering the other sides of the semiconductor dies. Moreover, as shown in the previous table, each NuHBM system can more easily provide an increased number of dies with much higher data bandwidth (approximately 2.457 TB / s to approximately 6.144 TB / s), even based on more stringent access latency requirements (e.g., LPDDR5 latency specifications). Thus, the present invention can eliminate the memory bandwidth bottleneck that has existed for many years in data input and output from processors / SOCs.

[0242] Furthermore, in the 3D IC structure of the present invention, an expensive interposer is not required. As shown in FIG. 1, in the CoWoS structure 20, the HBM structure 21 having the SOC chip 22 has all signal and power connections arranged in a flipped manner so as to be electrically connected to the substrate 24 via the interposer 23 having the TSV 201, and its pitch is about 10 to 20 microns. However, the present invention simplifies the CoWoS structure without the layer of wafers or interposers, which is the most advanced version of integrating the HBM system on the die, so that the memory controller and SOC circuits on the 3nm / 5nm die can be used, and the die performs the functions of both the memory controller and the SOC chip on the same level of silicon layer. The silicon layer has an inverted surface facing directly the substrate. Therefore, the proposed new structure can be called an Integrated Memory System on SoC wafer on Substrate (IMSWonS) on the substrate.

[0243] The following summarizes the advantages of the NuHBM system with a vertical shelf architecture (VSA) in contrast to the HBM specification: (1) The footprint area occupied by the HBM4.0 die is comparable (e.g., 6.25 mm × 7.59 mm) to that of an LPDDR5 HBM die with a capacity of 16 Gb. However, the footprint area of the NuHBM system depends on how many units of the edge pad semiconductor die and the high thermal conduction layer next to the edge pad semiconductor die are used. For example, 24 edge pad semiconductor dies occupy an area of about 4.8 mm (see FIG. 13B), which is much smaller than the area occupied by the HBM4.0 structure. (2) The I / O of the NuHBM system is directly supplied from each single edge pad semiconductor die and does not mix with the I / O from other edge pad semiconductor dies. Therefore, the signals can be better managed (such as less skew) than the signals coming from the 16-die stack used in the HBM4.0 framework. (3) The capacity of the NuHBM system is scalable and adaptable without having to worry about signal transmission through other DRAM dies. Each semiconductor die used in this NuHBM system has its own identity or standalone edge pad, but is not limited by the TSV used in current HBM DRAM stacks, so the capacity of the NuHBM system can be very large, medium, or small. (4) Total data bandwidth can be increased by using more edgepad semiconductor dies on the shelf structure, in contrast to the 1K or 2K I / O fabricated on the stacked dies of the HBL4.0 framework, thereby increasing the total number of I / Os (equal to the product of "number of I / Os from each edgepad semiconductor die" multiplied by "number of edgepad semiconductor dies"). Thus, in addition to being highly dependent on the data rate from each I / O, total bandwidth can be achieved by using more dies to provide more data I / Os. (5) Signals are routed from each edge pad semiconductor die and directly connected to the I / O of the memory controller, and then immediately routed to and from the SOC die, thereby significantly improving signal integrity. It also reduces the power consumption of the I / O.

Claims

1. The first memory stack, A first memory stack comprising: a plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall; and a plurality of edge pads arranged along the first side wall, wherein the area of ​​the bottom surface or the top surface of each semiconductor die is greater than the area of ​​any side wall; A logic die located below the first memory stack and having a memory controller electrically connected to the plurality of edge pads of each semiconductor die, A logic die having a processor circuit arranged on top of the logic die having the memory controller and electrically connected thereto, A packaging board located beneath the logic die having the memory controller and electrically connected thereto, An IC structure comprising, The die area of ​​the logic die having the memory controller is greater than the sum of the horizontal cross-sectional area of ​​the first memory stack and the die area of ​​the logic die having the processor circuit. An IC structure in which there is no interposer between the packaging substrate and the logic die having the memory controller, and there are no TSVs within each semiconductor die.

2. An upward-extending thermal conductive layer between two adjacent semiconductor dies, wherein the thermal conductivity of the upward-extending thermal conductive layer is Si or SiO ２ An upward-extending thermal conductive layer with a thermal conductivity higher than that of, and / or A laterally extending heat conduction layer covers the second sidewall of each of the plurality of semiconductor dies and is thermally bonded to the upwardly extending heat conduction layer, wherein the laterally extending heat conduction layer faces the first sidewall of the plurality of semiconductor dies, and the thermal conductivity of the laterally extending heat conduction layer is Si or SiO ２ A laterally extending heat conductive layer with a higher thermal conductivity than [the other]. The IC structure according to claim 1, further comprising:

3. The IC structure according to claim 2, wherein the upward-extending thermal conductive layer or the laterally-extending thermal conductive layer comprises undoped polysilicon, large-crystal silicon, SiC, BN, AlN, W, or copper.

4. The IC structure according to claim 1, wherein each semiconductor die includes a DRAM die, and the plurality of edge pads of each DRAM die include approximately 128 to 5000 edge pads, and the pitch between two adjacent edge pads is approximately 5 μm to approximately 100 μm.

5. The IC structure according to claim 4, wherein the plurality of edge pads of each semiconductor die include a subset of data pads, and the logic die having the memory controller selects a predetermined data width from a subset of the data pads of one semiconductor die, or a portion of the plurality of semiconductor dies, or all of the plurality of semiconductor dies.

6. The IC structure according to claim 5, wherein the predetermined data width selected by the logic die having the memory controller is set by a mode register in each semiconductor die.

7. The IC structure according to claim 5, wherein the logic die having the memory controller selects the predetermined data width from a subset of the data pads of some or all of the plurality of semiconductor dies by a crossbar circuit.

8. The logic die having the memory controller selects a predetermined data width from a subset of the data pads of one, some, or all of the semiconductor dies, using a plurality of SRAM arrays corresponding to each of the plurality of semiconductor dies. The IC structure according to claim 5, wherein each SRAM array temporarily holds the predetermined data width from the corresponding semiconductor die.

9. The IC structure according to claim 4, wherein the logic die having the memory controller includes a plurality of TSVs.

10. The IC structure according to claim 1, further comprising a heat sink on a logic die having the processor circuit, wherein the top surface of the heat sink is flush with the top surface of the first memory stack.

11. The second memory stack, A second memory stack comprising: a plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall; and a plurality of edge pads arranged along the first side wall, wherein the area of ​​the bottom surface or the top surface of each semiconductor die of the second memory stack is greater than the area of ​​any side wall; An upward-extending thermal conductive layer between two adjacent semiconductor dies, wherein the thermal conductivity of the upward-extending thermal conductive layer is Si or SiO ２ An upward-extending thermal conductive layer with a thermal conductivity higher than that of, An IC structure further comprising, The IC structure according to claim 1, wherein the first memory stack and the second memory stack are horizontally spaced apart from the logic die having the processor circuit and are arranged along one side of the logic die having the processor circuit.

12. A second memory stack, a third memory stack, and a fourth memory stack, each of which is: A plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall; a plurality of edge pads arranged along the first side wall, wherein the area of ​​the bottom surface or the top surface is larger than the area of ​​any side wall; a second memory stack, a third memory stack, and a fourth memory stack; An upward-extending thermal conductive layer between two adjacent semiconductor dies, wherein the thermal conductivity of the upward-extending thermal conductive layer is Si or SiO ２ An upward-extending thermal conductive layer with a thermal conductivity higher than that of, An IC structure further comprising, The IC structure according to claim 1, wherein the first memory stack, the second memory stack, the third memory stack, and the fourth memory stack are horizontally spaced apart from the logic die having the processor circuit and are arranged along the four sides of the logic die having the processor circuit.

13. The IC structure according to claim 1, wherein each edge pad of each semiconductor die includes an edge contact in the back-end obline (BEOL) region and a conductive via in the dielectric layer on the top surface above the edge contact, and the area of ​​the conductive via is larger than the area of ​​the edge contact.

14. The IC structure according to claim 1, wherein each edge pad of each semiconductor die includes an edge contact in a back-end obline (BEOL) region and a conductive via in a redistribution layer (RDL) on the top surface above the edge contact, and the area of ​​the conductive via is larger than the area of ​​the edge contact.

15. The IC structure according to claim 14, wherein the edge contact is electrically connected to a signal pad in the back-end obline (BEOL) region of the semiconductor die surrounded by a seal ring structure.

16. The IC structure according to claim 1, wherein each edge pad of each semiconductor die includes a conductive wire in a redistribution layer (RDL), and the conductive wire is electrically connected to a signal pad in the back-end obline (BEOL) region of the semiconductor die surrounded by a seal ring structure.

17. The IC structure according to claim 16, wherein the RDL includes a plurality of multilayer dielectric layers on which the conductive wires are located.

18. The IC structure according to claim 17, wherein a portion of the conductive wire is configured to be placed in the scribe line region of the semiconductor wafer before dicing the semiconductor wafer.

19. The first memory stack, A first memory stack comprising: a plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall; and a plurality of edge pads arranged along the first side wall, wherein the area of ​​the bottom surface or the top surface of each semiconductor die is greater than the area of ​​any side wall; A logic die located below the first memory stack and having memory controller and processor circuits electrically connected to the plurality of edge pads of each semiconductor die, A packaging board is located beneath the logic die having the memory controller and processor, and is electrically connected thereto. An IC structure comprising, An IC structure in which there is no interposer between the packaging substrate and the logic die having the memory controller and processor circuit, and there are no TSVs within each semiconductor die.

20. An upward-extending thermal conductive layer between two adjacent semiconductor dies, wherein the thermal conductivity of the upward-extending thermal conductive layer is Si or SiO ２ An upward-extending thermal conductive layer with a thermal conductivity higher than that of, and / or A lateral extending heat conduction layer that covers the second sidewall of each of the plurality of semiconductor dies and is thermally coupled to the upward extending heat conduction layer, wherein the lateral extending heat conduction layer faces the first sidewall of the plurality of semiconductor dies, and the thermal conductivity of the lateral extending heat conduction layer is Si or SiO ２ A laterally extending heat conductive layer with a higher thermal conductivity than [the other]. The IC structure according to claim 19, further comprising:

21. The IC structure according to claim 20, wherein the upward-extending thermal conductive layer or the laterally-extending thermal conductive layer comprises undoped polysilicon, large-crystal silicon, SiC, BN, AlN, W, or copper.

22. The IC structure according to claim 19, wherein each semiconductor die includes a DRAM die, and the plurality of edge pads of each DRAM die include approximately 128 to 5000 edge pads.

23. The IC structure according to claim 22, wherein the plurality of edge pads of each semiconductor die include a subset of data pads, and the logic die having the memory controller and processor circuit selects a predetermined data width from a subset of the data pads of one semiconductor die, or a portion of the plurality of semiconductor dies, or all of the plurality of semiconductor dies.

24. The IC structure according to claim 23, wherein the predetermined data width selected by the logic die having the memory controller and processor circuit is set by a mode register in each semiconductor die.

25. The IC structure according to claim 23, wherein the logic die having the memory controller and processor circuit selects the predetermined data width from a subset of the data pads of some or all of the plurality of semiconductor dies using a crossbar circuit.

26. The IC structure according to claim 19, wherein the logic die having the memory controller and processor circuit includes a plurality of TSVs.

27. The IC structure according to claim 19, further comprising a heat sink on a logic die having the memory controller and processor circuit adjacent to the first memory stack, wherein the top surface of the heat sink is flush with the top surface of the first memory stack.

28. The second memory stack, A second memory stack comprising: a plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall; and a plurality of edge pads arranged along the first side wall, wherein the area of ​​the bottom surface or the top surface of each semiconductor die of the second memory stack is greater than the area of ​​any side wall; An upward-extending thermal conductive layer between two adjacent semiconductor memory dies, wherein the thermal conductivity of the upward-extending thermal conductive layer is Si or SiO ２ An upward-extending thermal conductive layer with a thermal conductivity higher than that of, An IC structure further comprising, The IC structure according to claim 19, wherein the first memory stack and the second memory stack are arranged on a logic die having the memory controller and processor circuit.

29. A second memory stack, a third memory stack, and a fourth memory stack, each of which is: A plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall; a plurality of edge pads arranged along the first side wall, wherein the area of ​​the bottom surface or the top surface of each semiconductor die is larger than the area of ​​any side wall; a second memory stack, a third memory stack, and a fourth memory stack; An upward-extending thermal conductive layer between two adjacent semiconductor memory dies, wherein the thermal conductivity of the upward-extending thermal conductive layer is Si or SiO ２ An upward-extending thermal conductive layer with a thermal conductivity higher than that of, An IC structure further comprising, The IC structure according to claim 19, wherein the first memory stack, the second memory stack, the third memory stack, and the fourth memory stack are each arranged on a logic die having the memory controller and processor circuit.

30. It is a memory stack, A memory stack comprising: a plurality of semiconductor dies separated horizontally from each other, each semiconductor die having a top surface, a bottom surface opposite the top surface, and four side walls comprising a first side wall, a second side wall, a third side wall, and a fourth side wall; and a plurality of edge pads arranged along the first side wall, wherein the area of ​​the bottom surface or the top surface of each semiconductor die is greater than the area of ​​any side wall; An upward-extending thermal conductive layer between two adjacent semiconductor memory dies, The thermal conductivity of the upwardly extending thermal conduction layer is higher than that of Si or SiO ２ , an upwardly extending thermal conduction layer, and A logic die having a memory controller and processor circuit horizontally separated from the memory stack, A packaging substrate located beneath the memory stack and the logic die having the memory controller and processor circuit, An IC structure comprising, The packaging substrate comprises an embedded multi-die interconnect bridge (EMIB) structure electrically connected to the memory stack and the logic die having the memory controller and processor circuit. An IC structure in which there is no interposer between the packaging substrate and the logic die having the memory controller and processor circuit, and there are no TSVs within each semiconductor die.

31. A lateral extending heat conduction layer that covers the second sidewall of each of the plurality of semiconductor dies and is thermally coupled to the upward extending heat conduction layer, wherein the lateral extending heat conduction layer faces the first sidewall of the plurality of semiconductor dies, and the thermal conductivity of the lateral extending heat conduction layer is Si or SiO ２ A laterally extending heat conductive layer with a higher thermal conductivity than [the other]. The IC structure according to claim 30, further comprising:

32. The IC structure according to claim 30, wherein each semiconductor die includes a DRAM die, and the plurality of edge pads of each DRAM die include approximately 128 to 5000 edge pads.

33. The IC structure according to claim 30, wherein the logic die having the memory controller and processor circuit includes a plurality of TSVs.

34. The IC structure according to claim 30, wherein each edge pad of each semiconductor die includes an edge contact in the back-end obline (BEOL) region and a conductive via in the dielectric layer on the top surface above the edge contact, and the area of ​​the conductive via is larger than the area of ​​the edge contact.

35. The IC structure according to claim 30, wherein each edge pad of each semiconductor die includes an edge contact in a back-end obline (BEOL) region and a conductive via in a redistribution layer (RDL) on the top surface above the edge contact, and the area of ​​the conductive via is larger than the area of ​​the edge contact.

36. The IC structure according to claim 35, wherein the edge contact is electrically connected to a signal pad in the back-end obline (BEOL) region of the semiconductor die surrounded by a seal ring structure.

37. The IC structure according to claim 30, wherein each edge pad of each semiconductor die includes a conductive wire in a redistribution layer (RDL), and the conductive wire is electrically connected to a signal pad in a back-end obline (BEOL) region of the semiconductor die surrounded by a seal ring structure.

38. The IC structure according to claim 37, wherein the RDL includes a plurality of multilayer dielectric layers on which the conductive wires are located.

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