Semiconductor device and method for manufacturing the same
By forming the trench layer before the gate electrode in DRAM memory cells, the semiconductor device achieves improved crystallinity and electrical performance through varied trench shapes and increased area, addressing the limitations of conventional trench layer formation.
Patent Information
- Authority / Receiving Office
- JP Β· JP
- Patent Type
- Applications
- Current Assignee / Owner
- SWAYSURE TECHNOLOGY CO LTD
- Filing Date
- 2025-09-29
- Publication Date
- 2026-05-19
AI Technical Summary
Conventional DRAM memory cells with vertical trench structures face issues due to restricted trench layer shapes, leading to deteriorated crystallinity and poor electrical performance, primarily because the trench layer is formed after the word line, limiting the trench area and increasing leakage and reducing the operating current.
The trench layer is formed before the gate electrode, allowing for various shapes and increased area, with a semiconductor device configuration that includes a trench structure connected between a first and second electrode, and a gate insulating layer, enhancing crystallinity and reducing leakage.
This approach improves the electrical performance of semiconductor devices by maintaining superior crystallinity of the trench layer, increasing the trench area, and enhancing operating current.
Smart Images
Figure 2026082686000001_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to semiconductor devices and methods for manufacturing the same.
Background Art
[0002] DRAM (Dynamic Random Access Memory) is a semiconductor memory having advantages such as a large capacity and low cost, and is widely used in various fields. A basic memory cell of a conventional DRAM is a 1T1C (1 Transistor - 1 Capacitor) memory cell, and the 1T1C memory cell requires a transistor and a capacitor.
[0003] With the three-dimensionalization of the memory process, transistors with a vertical trench structure are becoming mainstream. In a transistor with a vertical trench structure, a word line (WL, Word Line) for controlling a switching channel layer exists between lead layers. However, in related technologies, the trench layer is often restricted to a circular shape, and since the trench layer is formed after the WL, the crystallinity of the trench layer deteriorates, leading to a degradation in the electrical performance of the memory.
Summary of the Invention
[0004] In the section of the summary of the invention, a series of concepts are introduced in a simplified form and will be further described in detail in the section of the embodiments for carrying out the invention. The section of the summary of the invention of this application is not intended to limit the main features and necessary technical features of the technical solution for which protection is claimed, let alone to determine the protection scope of the technical solution for which protection is claimed.
[0005] Regarding the currently existing problems, in one aspect, this application includes a substrate and a semiconductor module disposed on the substrate, where the semiconductor module includes a trench structure, and a first electrode, a gate electrode, and a second electrode sequentially stacked at intervals along a vertical direction. The trench structure comprises a trench layer and a gate insulating layer. The trench structure extends through the gate electrode in the vertical direction and is connected between the first electrode and the second electrode. The gate insulating layer is disposed between the gate electrode and the trench layer, providing a semiconductor device.
[0006] Exemplary, the semiconductor device further comprises a first insulating layer, the first insulating layer being provided in the same layer as the gate insulating layer and extending horizontally between the first electrode and the gate electrode.
[0007] Exemplary, the first insulating layer is in contact with the first electrode.
[0008] Exemplary, the first insulating layer is in contact with the gate electrode.
[0009] For example, the pitch between the end of the trench layer connected to the second electrode and the gate electrode is smaller than the pitch between the end of the gate insulating layer in contact with the second electrode and the gate electrode.
[0010] Exemplary, the second electrode has a first portion that contacts the trench layer and a second portion that is positioned away from the trench layer of the first portion. The semiconductor device further comprises an insulating dielectric layer, The insulating dielectric layer is disposed between the second portion and the gate electrode. The orthographic projection of the insulating dielectric layer on the substrate does not overlap with the orthographic projection of the trench structure on the substrate.
[0011] For example, the semiconductor device further comprises a first signal line, The first signal line is formed integrally with the first electrode and extends in the first horizontal direction. The orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first signal line on the substrate.
[0012] For example, the orthographic boundary of the trench layer on the substrate extends beyond the orthographic projection of the first signal line on the substrate, or The orthographic boundary of the trench layer on the substrate partially overlaps with the orthographic edge of the first signal line on the substrate, and does not extend beyond the orthographic projection of the first signal line.
[0013] For example, the orthographic projection of the trench structure on the substrate has a ring shape, The orthographic projection of the gate electrode on the substrate has a third portion located within the ring shape and a fourth portion located outside the ring shape.
[0014] Exemplary, the orthographic projection of the trench structure on the substrate has a plurality of fifth portions, The gate electrode has a sixth portion surrounding each of the fifth portions, and the sixth portions of the gate electrode are formed integrally.
[0015] For example, the orthographic projection of the fifth portion on the substrate is rod-shaped, parallel to each other, or The orthographic projection of the fifth portion on the substrate is ring-shaped, and the gate electrode further comprises a seventh portion located inside the ring shape.
[0016] For example, the first electrode includes a first contact material layer and a conductor layer. The first contact material layer is disposed between the conductor layer and the trench layer, The second electrode includes a second contact material layer.
[0017] In other aspects, The process of preparing the circuit board, The process involves forming a first electrode, a trench layer, a gate insulating layer, and a gate electrode on the substrate in this order. The steps include forming a second electrode on the substrate, Includes, The trench layer extends vertically and is connected between the first electrode and the second electrode. The gate insulating layer is disposed between the gate electrode and the trench layer. A manufacturing method is provided.
[0018] Exemplarily, the step of forming the trench layer includes: forming a semiconductor material layer on the first electrode; forming a first patterned mask layer on the semiconductor material layer; etching the semiconductor material layer using the first patterned mask layer as a mask to form the trench layer.
[0019] Exemplarily, the first patterned mask layer includes at least one portion, the orthographic projection of the portion on the substrate includes an annular shape or a rectangular shape, and / or the orthographic projection of the first patterned mask layer on the substrate includes a plurality of parallel bar shapes.
[0020] Exemplarily, the step of forming the second electrode includes: forming a contact material layer on the semiconductor material layer before forming the first patterned mask layer; patterning the contact material layer to form an upper contact portion simultaneously with the semiconductor material layer being etched using the first patterned mask layer as a mask; and the second electrode includes the upper contact portion.
[0021] Exemplarily, the manufacturing method further includes: forming a first signal line, where the first signal line is formed simultaneously with the first electrode, and the orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first signal line on the substrate; forming the gate insulating layer and the gate electrode; forming a gate insulating material layer, where the gate insulating material layer covers the trench layer, the upper contact portion, the first electrode, and the first signal line; A step of forming a gate electrode material layer, wherein the gate electrode material layer covers the gate insulating material layer, A step of pattern etching the gate electrode material layer to form the gate electrode, wherein the surface of the gate electrode away from the substrate is lower than the trench layer. A step of forming an insulating dielectric layer, wherein the insulating dielectric layer covers the gate insulating material layer and the gate electrode. The process further includes removing a portion of the insulating dielectric layer and a portion of the gate insulating material layer to expose the upper contact portion, and forming the gate insulating material layer, which is located on the gate electrode side adjacent to the trench layer, as the gate insulating layer.
[0022] Exemplary, the step of forming the second electrode further includes, after exposing the upper contact portion, forming a connection portion at one end of the upper contact portion away from the trench layer, The second electrode further comprises the connection portion.
[0023] For example, in the orthographic projection on the substrate, The first patterned mask layer has a ring shape, and the gate electrode includes a portion located inside the ring shape and a portion located outside the ring shape, or The first patterned mask layer comprises a plurality of portions, and the gate electrode surrounds each of the portions.
[0024] Exemplary, the manufacturing method further includes the step of forming a first signal line, The first signal line is formed simultaneously with the first electrode, The orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first signal line on the substrate. The boundary of the orthographic projection of the first patterned mask layer on the substrate does not extend beyond the orthographic projection of the first signal line on the substrate, or it partially overlaps with the edge of the orthographic projection of the first signal line and does not extend beyond the orthographic projection of the first signal line.
[0025] For example, the first electrode comprises a conductive layer and a lower contact portion located on the side of the conductive layer away from the substrate. The manufacturing method further includes a step of heat-treating the semiconductor material layer after it has been formed in order to reduce the impedance between the semiconductor material layer and the lower contact portion.
[0026] Exemplary, the manufacturing method further includes the step of forming the contact material layer on the semiconductor material layer and then heat-treating it to allow for a reduction in impedance between the semiconductor material layer and the contact material layer.
[0027] In the semiconductor device and method for manufacturing the semiconductor device according to the embodiment of the present application, the trench layer has superior crystallinity, and the trench layer can be made into various shapes. Since the trench layer is not limited to a circular shape, it is possible to increase the trench area, which contributes to reducing leakage and increasing operating current, thereby improving the electrical performance of the semiconductor device. [Brief explanation of the drawing]
[0028] The attached drawings of this application are incorporated below as part of this application for the purpose of understanding it. The attached drawings illustrate embodiments of this application and their descriptions in order to explain the principles of this application.
[0029] In the attached drawings, [Figure 1A] Figure 1A is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1B] Figure 1B is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1C] Figure 1C is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1D] Figure 1D is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the method for manufacturing a semiconductor device according to an embodiment of the present application. [Figure 1E] Figure 1E is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1F] Figure 1F is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1G] Figure 1G is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1H] Figure 1H is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1I] Figure 1I is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1J] Figure 1J is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1K] Figure 1K is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1L] Figure 1L is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1M]Figure 1M is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 1N] Figure 1N is a schematic diagram of a cross-section along a first direction and a cross-section along a second direction of an apparatus obtained by sequentially carrying out the method for manufacturing a semiconductor device according to an embodiment of the present application. [Figure 2A] Figure 2A is a schematic top view of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 2B] Figure 2B is a schematic top view of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 2C] Figure 2C is a schematic top view of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 2D] Figure 2D is a schematic top view of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 2E] Figure 2E is a schematic top view of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 2F] Figure 2F is a schematic top view of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 2G] Figure 2G is a schematic top view of an apparatus obtained by sequentially carrying out the semiconductor device manufacturing method according to the embodiment of the present application. [Figure 3A] Figure 3A is a schematic orthographic projection of a semiconductor device in an embodiment of the present application. [Figure 3B] Figure 3B is a schematic orthographic projection of a semiconductor device in an embodiment of the present application. [Figure 3C] Figure 3C is a schematic orthographic projection of a semiconductor device according to an embodiment of the present application. [Figure 3D] Figure 3D is a schematic orthographic projection of a semiconductor device in an embodiment of the present application. [Figure 3E] Figure 3E is a schematic orthographic projection of a semiconductor device in an embodiment of the present application. [Figure 3F] Figure 3F is a schematic orthographic projection of a semiconductor device in an embodiment of the present application. [Figure 4] Figure 4 is a flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present application. [Modes for carrying out the invention]
[0030] Next, the present application will be described more completely with reference to the accompanying drawings illustrating embodiments thereof. However, the present application can be carried out in different forms and should not be construed as being limited to the embodiments presented herein. Rather, by providing these embodiments, the disclosure will be made thorough and complete and the scope of the present application will be fully conveyed to those skilled in the art. In the accompanying drawings, the dimensions of layers and areas and their relative sizes may be exaggerated for clarity. The same reference numerals throughout indicate the same elements.
[0031] In this specification, when a component or layer is described as "on top of," "adjacent to," "connected to," or "combined with" another component or layer, it may be directly on top of, directly adjacent to, directly connected to, or directly combined with the other component or layer, or there may be components or layers interposed between them. Conversely, when a component is described as "directly on top of," "directly adjacent to," "directly connected to," or "directly combined with" another component or layer, it means that there are no components or layers interposed between them. The terms first, second, third, etc., may be used to describe various components, modules, regions, layers, and / or parts, but these components, modules, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one component, module, region, layer, or part from another component, module, region, layer, or part. Accordingly, without departing from the teachings of this application, the first component, module, region, layer, or part described below may be represented as the second component, module, region, layer, or part.
[0032] For example, spatial relationship terms such as βbelow,β βunderside,β βbelow,β βabove,β and βaboveβ may be used herein for explanatory purposes to describe the relationship between one part or feature shown in the drawings and another part or feature. Spatial relationship terms are intended to include different orientations of the device in use and operation, in addition to the orientation shown in the drawings. For example, if the device in the accompanying drawings is turned over, a part or feature described as βbelow the other part or featureβ or βbelow itβ is oriented to be βaboveβ the other part or feature. Thus, the exemplary terms βundersideβ and βbelowβ may include both βaboveβ and βbelowβ the other part or feature. The device may be oriented in a different direction (90-degree rotation or other orientations), and the spatial expressions used herein shall be interpreted accordingly.
[0033] The terms used herein are intended solely to describe embodiments and not to limit the application. Where used herein, the singular βone,β βone,β and βthe / the saidβ are also intended to include the plural unless the context explicitly indicates otherwise. Furthermore, where used herein, the terms βconsist of,β βcomprising,β and / or βincludingβ identify the presence of such feature, integer, process, operation, part, and / or module, but do not exclude the presence or addition of one or more other features, integers, processes, operations, parts, modules, and / or sets. Where used herein, the term βand / orβ includes any combination of the relevant enumerated items.
[0034] In this specification, ideal embodiments of the present application are described with reference to cross-sectional views as schematic diagrams of preferred embodiments (and intermediate structures) of the present application. Thus, variations from the shown shapes can be expected, for example, due to manufacturing techniques and / or tolerances. Therefore, embodiments of the present application should not be limited to specific shapes of the regions shown herein, and may include, for example, deviations of shape due to manufacturing. For example, an injection region shown as a rectangle typically has rounded or curved features and / or an injection concentration gradient at its edges, rather than a binary change from an injection region to a non-injection region. Similarly, an embedded region formed by injection may result in some injection in the region between the embedded region and the surface on which the injection is performed. Therefore, the regions shown in the drawings are substantially schematic, and their shapes are not intended to represent the actual shapes of the regions of the apparatus and are not intended to limit the scope of the present application.
[0035] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as they would be generally understood by a person skilled in the art of this application. Furthermore, terms as defined in commonly used dictionaries should be understood to have the meaning consistent with their meaning in the relevant field and / or in the context of this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined herein.
[0036] To fully understand the present application, the following description will present not only the structure but also detailed processes to clarify the technical solutions presented herein. Preferred embodiments of the present application will be described in detail below, but the present application may have other embodiments in addition to those described in detail.
[0037] In the manufacturing process of DRAM transistors, a related technology, word lines (WLs) are generally formed first, then the WLs are etched to create trench holes that penetrate them, and then these are filled to form a trench layer. The shape of the trench layer formed in this way is often limited to circular shapes, and the trench area of ββthe trench layer is relatively small, resulting in relatively poor electrical performance. Furthermore, if the trench layer formed by filling is subjected to a degrading process, the crystallinity of the trench layer deteriorates. All of the above problems lead to a decrease in the electrical performance of the memory.
[0038] Therefore, in light of the technical challenges described above, this application proposes a semiconductor device having the following configuration. This semiconductor device is The system comprises a substrate and a semiconductor module disposed on the substrate, The semiconductor module comprises a trench structure and a first electrode, a gate electrode, and a second electrode sequentially stacked at intervals along the vertical direction, wherein the trench structure comprises a trench layer and a gate insulating layer, the trench structure extends through the gate electrode in the vertical direction and is connected between the first electrode and the second electrode, and the gate insulating layer is disposed between the gate electrode and the trench layer.
[0039] In the semiconductor device of the present invention, the trench layer can be formed before the gate electrode, resulting in better crystallinity. Furthermore, the trench layer can have various shapes and structures, and is no longer limited to circular shapes. The trench area can also be increased, thereby reducing leakage and increasing the operating current, and improving the electrical performance of the semiconductor device.
[0040] The semiconductor device of the present application will be described in detail below with reference to Figures 1A to 3F. Figures 1A to 1N show schematic cross-sectional views along a first direction and along a second direction of a device obtained by sequentially carrying out the manufacturing method of the semiconductor device according to the embodiment of the present application, and Figures 2A to 2G show schematic top views of a device obtained by sequentially carrying out the manufacturing method of the semiconductor device according to the embodiment of the present application. Figures 3A to 3F show schematic orthographic projections of the semiconductor device according to the embodiment of the present application. Illustratively, Figure (a) of Figures 1A to 1N shows a schematic cross-section of the semiconductor device along the first direction, and Figure (b) of Figures 1A to 1N shows a schematic cross-section of the semiconductor device along the second direction. The first direction only needs to intersect with the second direction; for example, the first direction may be perpendicular to the second direction. Illustratively, the semiconductor device according to the embodiment of the present application can be obtained by manufacturing it using the semiconductor device manufacturing method described later.
[0041] The semiconductor device of this application may be any suitable type of device known to those skilled in the art, and in this embodiment, the technical solution of the present invention will be explained and illustrated mainly by taking the case in which the semiconductor device is a DRAM as an example.
[0042] In one embodiment, as shown in Figure 1N, the semiconductor device of the present application comprises a substrate 100. The substrate 100 is a substrate insulated at least on one side, at least between its surface and the first electrode. The substrate 100 may be an entirely insulating substrate, or it may be a composite substrate including a surface insulating layer and a semiconductor substrate, and a transistor may be formed on the semiconductor substrate. While several examples of the substrate 100 are described herein, any material / structure that can be used as a substrate is included in the spirit and scope of the present application.
[0043] In one embodiment, as shown in Figure 1N, the semiconductor device of the present invention further comprises a semiconductor module disposed on a substrate 100. The semiconductor module comprises a trench structure and a first electrode, a gate electrode 113, and a second electrode sequentially stacked at vertical intervals. The trench structure comprises a trench layer 108 and a gate insulating layer 115. The trench structure extends vertically through the gate electrode 113 and is connected between the first electrode and the second electrode. The gate insulating layer 115 is disposed between the gate electrode 113 and the trench layer 108. Exemplarily, a signal line, such as a word line WL electrically connected to the gate electrode 113, extends in a second horizontal direction.
[0044] The vertical direction is the direction perpendicular to the substrate 100 and includes both the direction away from the substrate 100 and the direction toward the substrate 100. When a semiconductor module is formed on the substrate 100 or a temporary substrate and then moved to the substrate 100 in the same direction, the direction away from the substrate 100 is the vertical direction. When a semiconductor device is formed on a temporary substrate and then reversed and moved to the substrate 100, the direction toward the substrate 100 is the vertical direction.
[0045] The trench structure includes at least a trench layer 108 connected between the first electrode and the second electrode. The gate insulating layer 115 may also be connected between the first electrode and the second electrode.
[0046] In one embodiment, as shown in Figure 1N, the first electrode includes a lower contact portion 102 and a conductor layer 101, with the lower contact portion 102 positioned between the conductor layer 101 and the trench layer 108. Exemplarily, the conductor layer 101 is formed from materials including, but not limited to, tungsten, polysilicon, doped polysilicon, tantalum nitride, tantalum, copper, etc. Exemplarily, the lower contact portion 102 is provided corresponding to the conductor layer 101 to reduce the resistance of the electrical connection channel between the conductor layer 101 and the trench layer 108. The lower contact portion 102 may include a contact material layer, and the material of the lower contact portion 102 may include, but not limited to, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, doped polysilicon, etc. The combination of materials for the trench layer 108, the conductor layer 101, and the lower contact portion 102 can be determined according to actual needs.
[0047] In one embodiment, the second electrode includes a first portion that contacts the trench layer 108 and a second portion located on the side of the first portion that is away from the trench layer 108. More specifically, as shown in Figure 1N, the second electrode includes an upper contact portion 109 and a connecting portion 118, where the upper contact portion 109 is the first portion of the second electrode that contacts the trench layer 108, and the connecting portion 118 is the second portion of the second electrode located on the side of the first portion that is away from the trench layer 108.
[0048] For example, the upper contact portion 109 and the connecting portion 118 may be made of the same material or different materials. The upper contact portion 109 may include a contact material layer, and the material of the upper contact portion 109 may include, but is not limited to, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, doped polysilicon, etc. If the materials of the upper contact portion 109 and the connecting portion 118 are different, the material of the connecting portion 118 may include, but is not limited to, tungsten, polysilicon, doped polysilicon, tantalum nitride, tantalum, copper, etc., and the upper contact portion 109 is used to reduce the resistance of the electrically connected channel between the trench layer 108 and the connecting portion 118. Alternatively, the connecting portion 118 may include a contact material layer, and the material of the connecting portion 118 may include, but is not limited to, cobalt silicide, nickel silicide, nickel silicide, titanium silicide, tungsten silicide, doped polysilicon, etc. For example, the lower contact portion 102, the upper contact portion 109, and the connecting portion 118 are made of the same material and are all contact material layers, or the material of the lower contact portion 102 and the material of the second electrode both include contact material layers but are made of different materials.
[0049] Exemplary, the upper contact portion 109 has the same shape as the trench layer 108 (i.e., the same horizontal cross-sectional shape), and as shown in Figure 2G, the shape of the connection portion 118 may be circular, rectangular, or elongated. Exemplary, connection portions 118 above different trench layers 108 may be provided independently, and the connection portions 118 may be used to increase the contact area and reduce resistance. Exemplary, the connection portions 118 are independently connected to the memory structure above. For example, if the semiconductor device is a DRAM memory including a 1T1C cell structure, each of the connection portions 118 may be connected to a capacitor (memory structure). Exemplary, the semiconductor device of the present invention is not limited to being applicable to a memory with a 1T1C structure, but may also be applied to memories with other cell structures (e.g., 1T3C, 2T0C, etc.), and the present invention is not limited thereto. For example, the first electrode may correspond to the source electrode of a transistor, the gate electrode 113 may correspond to the gate electrode of a transistor, and the second electrode may function as the drain electrode of a transistor, and may be directly connected to a capacitor (in the case of a 1T1C cell structure) by the second electrode (connection portion 118 on the second electrode), or it may be possible to form some other film layer on the second electrode to function as the drain electrode of a transistor, and the present invention is not limited thereto.
[0050] In one embodiment, as shown in Figure 1N, the semiconductor device further comprises a first insulating layer 116. The first insulating layer 116 is formed in the same layer as the gate insulating layer 115. The first insulating layer 116 extends horizontally between the first electrode and the gate electrode 113. Specifically, the first insulating layer 116 is positioned between the lower contact portion 102 and the gate electrode 113. Exemplarily, the gate insulating layer 115 and the first insulating layer 116 are made of materials including, but not limited to, silicon oxide and silicon nitride. Exemplarily, the first insulating layer 116 is in contact with the first electrode. Exemplarily, the first insulating layer 116 is in contact with the gate electrode 113.
[0051] In one example, as shown in Figure 1N, the pitch between the end of the trench layer 108 in contact with the second electrode (i.e., the end of the trench layer 108 in contact with the upper contact portion 109) and the gate electrode 113 is smaller than the pitch between the end of the gate insulating layer 115 in contact with the second electrode (i.e., the end of the gate insulating layer 115 in contact with the connection portion 118) and the gate electrode 113. Here, pitch refers to the distance in the vertical direction.
[0052] In one embodiment, as shown in Figure 1N, the semiconductor device of the present invention further comprises an insulating dielectric layer 114. The insulating dielectric layer 114 is positioned between the second portion of the second electrode (i.e., the connection portion 118) and the gate electrode 113, and the orthographic projection of the insulating dielectric layer 114 on the substrate 100 does not overlap with the orthographic projection of the trench structure on the substrate 100. Exemplarily, the insulating dielectric layer 114 covers the gate electrode 113 and the trench structure. Exemplarily, the insulating dielectric layer 114 may be made of conventional insulating materials such as silicon oxide, silicon nitride, silicon oxide nitride, or low dielectric constant materials, and is not limited thereto.
[0053] In one embodiment, the semiconductor device further comprises a first signal line. The first signal line is integrally formed with a first electrode and extends in a first horizontal direction, and the orthographic projection of the first electrode on the substrate 100 is located within the orthographic projection of the first signal line on the substrate 100. Exemplarily, the first electrode is located corresponding to the first signal line, and the two edges in the orthographic projection on the substrate 100 completely overlap, but not limited to this, in some embodiments, the orthographic projection of the first electrode on the substrate 100 does not overlap with the edge of the orthographic projection of the first signal line and is located entirely within the orthographic projection of the first signal line.
[0054] Exemplary, a first signal line electrically connected to the first electrode consists of the same structure as the first electrode, namely a conductor layer and a lower contact portion located on the side of the conductor layer closer to the trench layer 108, but is understood to be merely the same material and structure as the film layer. The present invention is not limited thereto, and in some embodiments, the first signal line includes only a conductor layer which is the same layer as the conductor layer 101, which is determined on a case-by-case basis.
[0055] For example, in a DRAM memory where the semiconductor device is a 1T1C memory cell structure including an array, the first signal line is a bit line (BL).
[0056] In one embodiment, as shown in Figure 3F, the orthographic boundary of the trench layer 108 on the substrate 100 extends beyond the orthographic projection of the lower contact portion 102 on the substrate 100, that is, the orthographic boundary of the trench layer 108 on the substrate 100 extends beyond the orthographic projection of the first electrode on the substrate 100, and when the first electrode is formed integrally with the first signal line, the orthographic boundary of the trench layer 108 on the substrate 100 extends beyond the orthographic projection of the first signal line on the substrate 100.
[0057] As shown in Figure 2B, the orthographic boundary of the trench layer 108 on the substrate 100 may just overlap with a portion of the orthographic edge of the first signal line and not extend beyond the orthographic edge of the first signal line.
[0058] For example, the orthographic boundary of the trench layer 108 on the substrate 100 does not extend beyond the orthographic projection of the gate electrode 113 on the substrate 100.
[0059] In one embodiment, as shown in Figures 3A and 3B, the orthographic projection of the trench structure on the substrate 100 has a ring shape, and the orthographic projection of the gate electrode 113 on the substrate 100 includes a third portion 130 located inside the ring shape and a fourth portion 140 located outside the ring shape. Referring to Figure 1N, the insulating dielectric layer 114 may also include a portion located inside the ring shape, and the insulating dielectric layer 114 is positioned vertically between the electrode 113 and the connection portion 118.
[0060] In one embodiment, as shown in Figures 3C to 3F, the orthographic projection of the trench structure on the substrate 100 includes a plurality of fifth portions 150, and the gate electrode 113 includes a sixth portion 160 surrounding each of the fifth portions 150, with the sixth portions 160 in the gate electrode 113 being integrally formed.
[0061] Specifically, as shown in Figures 3D, 3E, and 3F, the orthographic projection of the fifth portion 150 on the substrate 100 is rod-shaped and parallel to each other, or as shown in Figure 3C, the orthographic projection of the fifth portion 150 on the substrate 100 is ring-shaped, and the gate electrode 113 further includes a seventh portion 170 located inside the ring shape.
[0062] In one embodiment, as shown in Figures 3E and 3F, the orthographic projection of the trench structure on the substrate 100 has a rectangular shape.
[0063] Exemplary, the orthographic projection on the trench structure substrate 100 is entirely inside the orthographic projection of the gate electrode 113 and at least partially inside the orthographic projection of the first electrode.
[0064] Forming a trench structure prior to the gate electrode results in good crystallinity, which in turn improves electrical properties. Furthermore, if the orthographic projection of the trench structure on the substrate 100 has multiple bar shapes, the control area of ββthe gate electrode can be increased, the trench area can be increased, leakage can be reduced, and the operating current can be improved. Alternatively, if the orthographic projection of the trench structure on the substrate 100 has a ring shape, a uniform current distribution can be obtained. Moreover, if the orthographic projection of the trench structure on the substrate 100 has multiple ring shapes, it is possible to increase the control area of ββthe gate electrode and the trench area while simultaneously obtaining a uniform current distribution. In some embodiments not shown, the orthographic projection of the trench structure on the substrate further has multiple solid circles or multiple rectangles. The present application does not limit the specific shape of the orthographic projection on the substrate 100 of the fifth part 150.
[0065] In one embodiment, the semiconductor device of the present invention may be connected to a memory structure above it to constitute a memory. Taking a 1T1C cell structure as an example, when it is necessary to read information stored in a cell structure, a high potential can be applied to the word line of the cell. The potential state of the capacitor of the cell is reflected in the corresponding bit line, which is connected to a read / write drive circuit. The read / write drive circuit reads the potential state of the capacitor, and the information can be read. Alternatively, when the read / write drive circuit outputs a high or low potential, the capacitor is charged or discharged, and the information is written.
[0066] The above is an introduction to the semiconductor device of this application. A complete semiconductor device may include other components, but a detailed explanation is omitted here.
[0067] As described above, in the semiconductor device of this application, the trench layer has superior crystallinity, and the trench layer can have various shapes and structures, and is no longer limited to a circular shape. Therefore, the trench area can be increased, which contributes to reducing leakage and increasing operating current, and ultimately improves the electrical performance of the semiconductor device.
[0068] The method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to Figures 1A to 4. Figures 1A to 1N show schematic cross-sectional views along a first direction and along a second direction of a device obtained by sequentially carrying out the method for manufacturing a semiconductor device according to the embodiment of the present application. Figures 2A to 2G show schematic top views of a device obtained by sequentially carrying out the method for manufacturing a semiconductor device according to the embodiment of the present application. Figures 3A to 3F show schematic orthographic projections of a semiconductor device according to the embodiment of the present application. Figure 4 shows a flowchart of the method for manufacturing a semiconductor device according to the embodiment of the present application. Exemplarily, a schematic cross-section of a semiconductor device along the first direction is shown in Figure 1A to 1N (a), and a schematic cross-section of a semiconductor device along the second direction is shown in Figure 1A to 1N (b). The first direction only needs to intersect with the second direction; for example, the first direction may be perpendicular to the second direction.
[0069] As an example, as shown in Figure 4, the method for manufacturing a semiconductor device according to the present invention includes the following steps.
[0070] First, step S1 is performed to provide the substrate 100 as shown in Figure 1A.
[0071] The semiconductor device of the present invention may be any suitable type of device known to those skilled in the art, and in this embodiment, the technical solution of the present invention will be described and illustrated mainly using the case where the semiconductor device is a DRAM as an example.
[0072] In one embodiment, the substrate 100 is a substrate in which at least its surface is superficially insulated from the first electrode. The substrate 100 may be an insulating substrate as a whole, a composite substrate including a surface insulating layer and a semiconductor substrate, or a transistor or the like may be formed on the semiconductor substrate. While several examples of the substrate 100 are described herein, any material / structure that can be used as a substrate is included in the spirit and scope of this application.
[0073] Next, process S2 is performed, in which the first electrode, trench layer, gate insulating layer, and gate electrode are sequentially formed on the substrate 100, and the second electrode is formed on the substrate 100. The trench layer extends vertically and is connected between the first electrode and the second electrode. The gate insulating layer is positioned between the gate electrode and the trench layer.
[0074] In one embodiment, as shown in Figures 1A and 2A, a first electrode is formed first. The first electrode includes a conductive layer 101 and a lower contact portion 102 located on the side of the conductive layer away from the substrate 100. Exemplarily, the conductive layer 101 is made of a material including, but not limited to, tungsten, polysilicon, doped polysilicon, tantalum nitride, tantalum, copper, etc. Exemplarily, the lower contact portion 102 is provided corresponding to the conductive layer 101, and the material of the lower contact portion 102 includes, but is not limited to, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, doped polysilicon, etc. Exemplarily, the conductive layer 101 and the lower contact portion 102 may be formed using deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc., and this application is not limited thereto.
[0075] In one embodiment, the method of the present application further includes the step of forming a first signal line. The first signal line is formed simultaneously with the first electrode, and the orthographic projection of the first electrode on the substrate 100 lies within the orthographic projection of the first signal line on the substrate 100. Exemplarily, the first signal line is formed integrally with the first electrode, extends in a first horizontal direction, and the first signal line is a bit line (BL). Exemplarily, the edge of the orthographic projection of the first electrode on the substrate 100 coincides with the edge of the orthographic projection of the first signal line.
[0076] Furthermore, the process may include forming an insulating layer between the first electrodes and making the surface of the insulating layer coplanar with the first electrodes. The insulating layer is formed as part of the substrate 100.
[0077] In one embodiment, the formation of the trench layer is started after the first electrode is formed. Specifically, as shown in Figures 1B to 1E and Figure 2B, the trench layer 108 is formed as follows.
[0078] First, as shown in Figure 1B, a semiconductor material layer 103 is formed on the first electrode. The semiconductor material layer 103 covers the surface of the first electrode and the substrate 100. Exemplarily, after forming the semiconductor material layer 103, the method of the present invention further includes a step of heat treatment to reduce the impedance between the semiconductor material layer 103 and the lower contact portion 102. The heat treatment step can also change the crystallinity of the semiconductor material layer 103. For example, if the semiconductor material layer 103 contains amorphous silicon, the heat treatment step can be performed to convert amorphous silicon to crystalline silicon. This heat treatment can be performed by various heat treatment processes known in the art, such as rapid thermal annealing. Since the semiconductor material layer 103 for forming the trench layer 108 is formed before the gate electrode, this heat treatment may improve its crystallinity.
[0079] Next, as shown in Figure 1D, a first patterned mask layer 107 is formed on the semiconductor material layer 103.
[0080] Taking the formation of a ring-shaped trench layer 108 as an example, as shown in Figures 1C and 1D, the formation of the first patterning mask layer 107 involves sequentially forming a first dielectric layer 105 and a second dielectric layer 106 on the semiconductor material layer 103, forming a plurality of via holes exposed to the semiconductor material layer 103 in the first dielectric layer 105, and covering the bottom and side walls of the via holes and the surface of the first dielectric layer 105 with the second dielectric layer 106. Subsequently, the second dielectric layer 106 is removed from the bottom of the vias and the surface of the first dielectric layer 105, and the second dielectric layer 106 placed on the side walls of the vias is retained as the first patterning mask layer 107, while the first dielectric layer 105 is removed. However, this is not limited to the above, as long as a ring-shaped first patterning mask layer 107 can be formed.
[0081] Exemplary, the horizontal thickness of the formed trench layer 108 can be defined by defining the horizontal thickness of the first patterning mask layer 107, that is, by controlling the deposition thickness of the second dielectric layer 106. Exemplary, the first dielectric layer 105 and the second dielectric layer 106 may be made of conventional insulating materials such as silicon oxide, silicon nitride, or silicon oxide nitride, as long as it is ensured that both have an appropriate etching selectivity ratio, and the present invention is not limited thereto.
[0082] Next, as shown in Figure 1E, the semiconductor material layer 103 is etched using the first patterning mask layer 107 as a mask to form a trench layer 108. Exemplarily, various etching processes commonly used in the art can be used to etch the semiconductor material layer 103 using the first patterning mask layer 107 as a mask, and this application is not limited thereto. It is understood that by defining the shape of the first patterning mask layer 107, the shape of the formed trench layer 108 can be defined; that is, the trench layer 108 has the same shape as the orthographic projection of the first patterning mask layer 107 in orthographic projection on the substrate 100.
[0083] In one embodiment, as shown in Figures 3A to 3F, the orthographic projection of the first patterning mask layer 107 on the substrate 100 overlaps with the orthographic projection of the trench layer 108 on the substrate 100, and the orthographic projection of the trench layer 108 on the substrate 100 may include at least one portion that constitutes an annular or rectangular shape in the orthographic projection of the trench layer 108 on the substrate 100, and / or the orthographic projection has a plurality of parallel bar shapes. That is, the orthographic projection of the first patterning mask layer 107 on the substrate 100 may have at least one portion, and the orthographic projection of this portion on the substrate 100 is composed of an annular or rectangular shape, and / or the orthographic projection of the first patterning mask layer 107 on the substrate 100 has a plurality of parallel bar shapes.
[0084] In one embodiment, the boundary of the orthographic projection of the first patterned mask layer 107 on the substrate 100 may extend beyond the orthographic projection of the first signal line on the substrate 100; that is, the orthographic projection of the first patterned mask layer 107 on the substrate 100 may be at least partially within the orthographic projection of the first signal line on the substrate 100.
[0085] In one embodiment, as shown in Figure 2B, the orthographic boundary of the ring-shaped first patterned mask layer 107 on the substrate 100 partially overlaps with the orthographic edge of the first signal line on the substrate 100, that is, the orthographic boundary of the ring-shaped trench layer 108 on the substrate 100 partially overlaps with the orthographic edge of the first signal line.
[0086] To make it easier to understand, in the prior art, the gate is etched to form a trench hole, and then a gate insulating layer and a trench layer are sequentially formed within the trench hole. To reduce defects on the etched bottom surface of the trench hole, the bottom surface of the trench hole is usually positioned entirely within the signal line. As a result, the trench width becomes smaller, and the electrical characteristics deteriorate. In the present invention, by forming the trench layer first, followed by the gate insulating layer and the gate electrode, the trench width can be further increased, making it possible for the boundary of the trench layer to overlap with or even extend beyond the signal line, thereby improving the electrical performance of the semiconductor device, i.e., the transistor.
[0087] In one embodiment, as shown in Figures 1B to 1E, the process of forming the second electrode includes the steps of forming a contact material layer 104 on the semiconductor material layer 103 before forming the first patterning mask layer 107, and forming an upper contact portion 109 by patterning the contact material layer 104 while etching the semiconductor material layer 103 using the first patterning mask layer 107 as a mask, with the upper contact portion 109 constituting the second electrode. Exemplarily, the material of the upper contact portion 109 includes, but is not limited to, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, doped polysilicon, etc.
[0088] In one embodiment, the method of the present invention further includes a step of performing a heat treatment after forming a contact material layer 104 on the semiconductor material layer 103, which enables a reduction in the impedance between the semiconductor material layer 103 and the contact material layer 104. Exemplarily, the heat treatment does not have to be performed after the semiconductor material layer 103 is formed on the lower contact portion 102, and the heat treatment may be performed after the contact material layer 104 is formed in order to simultaneously reduce the impedance between the semiconductor material layer 103 and the contact material layer 104, and between the semiconductor material layer 103 and the lower contact portion 102, and to improve the crystallinity of the semiconductor material layer 103.
[0089] In one embodiment, the present invention performs a heat treatment process after the semiconductor material layer 103 is formed (if a contact material layer 104 is formed, the heat treatment process is performed after the contact material layer 104 is formed). The trench layer 108 of the present invention has better crystallinity in the upper contact portion 109, the lower contact portion 102, and between the upper contact portion 109 and the lower contact portion 102 compared to related technologies in which a trench layer is formed by filling holes obtained by etching the WL control layer with trench material and then performing a heat treatment process. The trench layer 108 of the present invention can lower the impedance between the upper contact portion 109 and the lower contact portion 102, have better crystallinity, and consequently improve the electrical performance of the device.
[0090] In one embodiment, the present invention first forms a semiconductor material layer 103, and then etches the semiconductor material layer 103 to obtain a trench layer 108. This allows for improvements in the shape and structure of the trench layer 108. The trench layer 108 is no longer limited to a circular shape, and can be made into, for example, multiple elongated stripes. This increases the trench area, reduces leakage, improves the operating current, and ultimately improves the electrical performance of the device.
[0091] In one embodiment, the step of forming the gate insulating layer 115 and the gate electrode 113 after forming the trench layer 108 includes the following steps.
[0092] First, as shown in Figures 1F and 2C, a gate insulating material layer 110 is formed. The gate insulating material layer 110 covers the trench layer 108, the upper contact portion 109, the first electrode, and the first signal line. Exemplarily, the gate insulating material layer 110 may be formed using deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and this application is not limited thereto. Exemplarily, the material for the gate insulating material layer 110 may include, but is not limited to, silicon oxide or silicon nitride.
[0093] For example, the first insulating layer 116 is formed simultaneously with the gate insulating layer 115.
[0094] Next, as shown in Figure 1G, a gate electrode material layer 111 is formed. The gate electrode material layer 111 covers the gate insulating material layer 110. Exemplarily, the gate electrode material layer 111 may be formed using a film deposition method commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc., and this application is not limited thereto.
[0095] Next, as shown in Figures 1J and 2E, the gate electrode material layer 111 is pattern-etched to form the gate electrode 113. At this time, the surface of the gate electrode 113 away from the substrate 100 may be lower than the surface of the trench layer 108. Specifically, in forming the gate electrode 113, first, as shown in Figure 1H, a portion of the gate electrode material layer 111 is removed by back etching to lower the surface of the gate electrode material layer 111 away from the substrate 100 than the surface of the trench layer 108. Next, as shown in Figures 1I and 2D, a second patterning mask layer 112 is formed on the gate electrode material layer 111, and the gate electrode 113 is patterned using the second patterning mask layer 112. Exemplary materials for the gate electrode 113 include, but are not limited to, tungsten, polysilicon, doped polysilicon, tantalum nitride, tantalum, and copper.
[0096] Next, as shown in Figure 1K, an insulating dielectric layer 114 is formed. The insulating dielectric layer 114 covers the gate insulating material layer 110 and the gate electrode 113. Exemplarily, the insulating dielectric layer 114 may be made of a conventional insulating material such as silicon oxide, silicon nitride, or silicon oxide nitride, but the present invention is not limited thereto.
[0097] Finally, as shown in Figures 1L and 2F, a portion of the insulating dielectric layer 114 and a portion of the gate insulating material layer 110 are removed to expose the upper contact portion 109, and the gate insulating material layer located on the gate electrode 113 side adjacent to the trench layer 108 is formed as the gate insulating layer 115. In one embodiment, the removal process is chemical mechanical polishing (CMP), and the polishing ends at the upper contact portion 109, or the polishing also removes a portion of the thickness of the upper contact portion 109. In this application, there are no particular restrictions on the removal process. By providing the upper contact portion, damage to the trench layer 108 near the second electrode due to the manufacturing process and its impact on electrical properties are avoided.
[0098] In one embodiment, the orthographic projection of the first patterned mask layer 107 on the substrate 100 has a ring shape, and the gate electrode 113 includes a portion located inside the ring shape and a portion located outside the ring shape. Alternatively, the first patterned mask layer 107 includes multiple portions, and the gate electrode surrounds each of such portions. Specifically, since the orthographic projection of the first patterned mask layer 107 on the substrate 100 is the same as the orthographic projection of the trench layer 108 on the substrate 100, the orthographic projection of the trench layer 108 on the substrate 100 can be used to represent the orthographic projection of the first patterned mask layer 107 on the substrate 100.
[0099] In one embodiment, as shown in Figure 3A, the orthographic projection of the trench layer 108 on the substrate 100 has a ring shape, and the orthographic projection of the gate electrode 113 on the substrate 100 includes a third portion 130 located inside the ring shape and a fourth portion 140 located outside the ring shape.
[0100] In one embodiment, as shown in Figures 3D to 3F, the orthographic projection of the trench layer 108 on the substrate 100 includes a plurality of fifth portions 150, and the gate electrode 113 includes a sixth portion 160 surrounding each of the fifth portions 150, with the sixth portions 160 in one gate electrode 113 being integrally formed. Specifically, as shown in Figures 3D, 3E, and 3F, the orthographic projection of the fifth portions 150 on the substrate 100 is rod-shaped and parallel to each other, or as shown in Figure 3C, the orthographic projection of the fifth portions 150 on the substrate 100 is ring-shaped, and the gate electrode 113 further includes a seventh portion 170 positioned inside the ring shape. Exemplarily, the orthographic projection of the trench structure on the substrate 100 is entirely inside the orthographic projection of the gate electrode 113 and at least partially inside the orthographic projection of the first electrode.
[0101] In one embodiment, the step of forming the second electrode includes, as shown in Figures 1N and 2G, exposing the upper contact portion 109 and then forming a connection portion 118 at the end of the upper contact portion 109 away from the trench layer 108, so that the second electrode further comprises the connection portion 118. Specifically, the step of forming the connection portion 118 includes first depositing the material to be used to form the connection portion 118 onto the upper contact portion 109 and the insulating dielectric layer 114, as shown in Figure 1M. Exemplarily, as shown in Figure 2G, the shape of the connection portion 118 may be circular, and depending on the actual need, the shape of the connection portion 118 may be rectangular or elongated. Exemplarily, connection portions 118 above different trench layers 108 are provided independently, and the connection portions 118 may be used to increase the contact area and reduce resistance. Exemplarily, the connection portions 118 are independently connected to the memory structure above, for example, in the case of a 1T1C cell structure, each of the connection portions 118 may be connected to a capacitor. Exemplary, the semiconductor device of the present application is not limited to being applied to a 1T1C structure, but may also be applied to other cell structures (e.g., 1T3C, 2T0C, etc.) of memory, and the present application is not limited thereto. Exemplary, the first electrode may correspond to the source electrode of a transistor, the gate electrode 113 may correspond to the gate electrode of a transistor, and the second electrode may function as the drain electrode of a transistor, or another film layer may be formed on the second electrode to function as the drain electrode of a transistor, or a film layer that functions as the drain electrode of a transistor may not be formed, and the capacitor may be directly connected by the second electrode (connection portion 118 on the second electrode) (exemplifying the 1T1C cell structure).
[0102] Furthermore, in one embodiment, the semiconductor device of the present invention includes a memory structure arranged on a second electrode and electrically connected to the second electrode to form a memory cell, and an array of memory cells may be arranged to form a memory. In the case of a 1T1C unit structure, for example, when it is necessary to read information stored in a certain cell structure, a high potential is applied to the word line of the cell, the potential state of the capacitor of the cell is reflected in the corresponding bit line, and the corresponding bit line is connected to a read / write drive circuit, and the read / write drive circuit reads the potential state of the capacitor to complete the reading of the information. Alternatively, the read / write drive circuit outputs a high or low potential to charge or discharge the capacitor to complete the writing of the information.
[0103] The main steps for manufacturing the semiconductor device of this application have been described above, but the manufacture of a complete semiconductor device may include other steps not described herein. The above steps are merely illustrative, and the order of the above steps can be adjusted without contradiction.
[0104] As described above, the semiconductor device manufacturing method of the present invention improves the crystallinity of the trench layer by accelerating the formation of the trench layer and then forming the gate electrode. At the same time, it improves the shape and structure of the trench layer. The trench layer is no longer limited to a circular shape, and the area of ββthe trench can be increased, which helps to reduce leakage and increase the operating current, thereby improving the electrical performance of the semiconductor device.
[0105] While this specification describes several embodiments, those skilled in the art should understand that several other modifications and embodiments can be envisioned, all of which fall within the spirit and scope of the idea disclosed herein. More specifically, within the scope of the disclosure, the accompanying drawings, and the accompanying claims, various modifications and changes can be made to the arrangement and / or components of the subject matter combination arrangement. In addition to modifications and changes to the components and / or arrangement, the use of interchangeable means is an obvious choice for those skilled in the art. [Explanation of symbols]
[0106] 100 circuit boards 101 Conductor layer 102 Lower contact area 103 Semiconductor material layer 104 Contact material layer 105 First Dielectric Layer 106 Second Dielectric Layer 107 First Patterned Mask Layer 108 Trench Layer 109 Upper contact part 110 Gate insulating material layer 111 Guard plate material layer 112 Second Patterned Mask Layer 113 gate 114 Insulating dielectric layer 115 Gate Insulation Layer 116 First insulating layer 117 Material layer 118 Connection part 122 First signal line 130 Part 3 140 Part 4 150 Part 5 160 Part 6 170 Part 7
Claims
1. A semiconductor device, The system comprises a substrate and a semiconductor module disposed on the substrate, The semiconductor module comprises a trench structure and a first electrode, a gate electrode, and a second electrode that are sequentially stacked at intervals along the vertical direction. The trench structure comprises a trench layer and a gate insulating layer. The trench structure extends through the gate electrode in the vertical direction and is connected between the first electrode and the second electrode. The gate insulating layer is disposed between the gate electrode and the trench layer in a semiconductor device.
2. The semiconductor device further comprises a first insulating layer, The first insulating layer is provided in the same layer as the gate insulating layer and extends horizontally between the first electrode and the gate electrode. The semiconductor device according to claim 1.
3. The semiconductor device according to claim 2, wherein the first insulating layer is in contact with the first electrode.
4. The semiconductor device according to claim 2, wherein the first insulating layer is in contact with the gate electrode.
5. The semiconductor device according to claim 1, wherein the pitch between the end of the trench layer connected to the second electrode and the gate electrode is smaller than the pitch between the end of the gate insulating layer in contact with the second electrode and the gate electrode.
6. The second electrode has a first portion that contacts the trench layer and a second portion that is positioned on the side of the first portion away from the trench layer. The semiconductor device further comprises an insulating dielectric layer, The insulating dielectric layer is disposed between the second portion and the gate electrode. The orthographic projection of the insulating dielectric layer on the substrate does not overlap with the orthographic projection of the trench structure on the substrate. The semiconductor device according to claim 5.
7. The semiconductor device further comprises a first signal line, The first signal line is formed integrally with the first electrode and extends in the first horizontal direction. The orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first signal line on the substrate. The semiconductor device according to claim 1.
8. The boundary of the orthographic projection of the trench layer on the substrate extends beyond the orthographic projection of the first signal line on the substrate, or The orthographic boundary of the trench layer on the substrate partially overlaps with the orthographic edge of the first signal line on the substrate and does not extend beyond the orthographic projection of the first signal line. The semiconductor device according to claim 7.
9. The orthographic projection of the trench structure on the substrate has a ring shape, The orthographic projection of the gate electrode on the substrate has a third portion located within the ring shape and a fourth portion located outside the ring shape. The semiconductor device according to claim 1.
10. The orthographic projection of the trench structure on the substrate has a plurality of fifth portions, The gate electrode has a sixth portion surrounding each of the fifth portions, and the sixth portion of the gate electrode is integrally formed. The semiconductor device according to claim 1.
11. The orthographic projection of the fifth portion on the substrate is rod-shaped, parallel to each other, or The orthographic projection of the fifth portion on the substrate is ring-shaped, and the gate electrode further comprises a seventh portion located inside the ring shape. The semiconductor device according to claim 10.
12. The first electrode includes a first contact material layer and a conductor layer. The first contact material layer is disposed between the conductor layer and the trench layer. The second electrode includes a second contact material layer. The semiconductor device according to claim 1.
13. A method for manufacturing a semiconductor device, The process of preparing the circuit board, The process involves forming a first electrode, a trench layer, a gate insulating layer, and a gate electrode on the substrate in this order. The steps include forming a second electrode on the substrate, Includes, The trench layer extends vertically and is connected between the first electrode and the second electrode. The gate insulating layer is disposed between the gate electrode and the trench layer. Manufacturing method.
14. The step of forming the trench layer is: A step of forming a semiconductor material layer on the first electrode, A step of forming a first patterned mask layer on the semiconductor material layer, To form the trench layer, the process involves etching the semiconductor material layer using the first patterned mask layer as a mask, The manufacturing method according to claim 13, including
15. The first patterned mask layer includes at least one portion, The orthographic projection of the portion on the substrate includes a ring shape or a rectangular shape, and / or The orthographic projection of the first patterned mask layer on the substrate includes a plurality of parallel bar shapes, The manufacturing method according to claim 14.
16. The process of forming the two adjacent electrodes is as follows: Before forming the first patterned mask layer, a step of forming a contact material layer on the semiconductor material layer, The semiconductor material layer is etched using the first patterning mask layer as a mask, and at the same time, the contact material layer is patterned to form an upper contact portion. Includes, The second electrode includes the upper contact portion, The manufacturing method according to claim 14.
17. The aforementioned manufacturing method further includes, A step of forming a first signal line, wherein the first signal line is formed simultaneously with the first electrode, and the orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first signal line on the substrate. The steps for forming the gate insulating layer and the gate electrode are as follows: A step of forming a gate insulating material layer, wherein the gate insulating material layer covers the trench layer, the upper contact portion, the first electrode, and the first signal line. A step of forming a gate electrode material layer, wherein the gate electrode material layer covers the gate insulating material layer, A step of pattern etching the gate electrode material layer to form the gate electrode, wherein the surface of the gate electrode away from the substrate is lower than the trench layer. A step of forming an insulating dielectric layer, wherein the insulating dielectric layer covers the gate insulating material layer and the gate electrode. A step of removing a portion of the insulating dielectric layer and a portion of the gate insulating material layer to expose the upper contact portion, and forming the gate insulating material layer located on the gate electrode side adjacent to the trench layer as the gate insulating layer, The manufacturing method according to claim 16, further comprising:
18. The step of forming the second electrode further includes, after exposing the upper contact portion, forming a connection portion at one end of the upper contact portion away from the trench layer, The second electrode further comprises the connection portion, The manufacturing method according to claim 17.
19. In the orthographic projection on the substrate, The first patterned mask layer has a ring shape, and the gate electrode includes a portion located inside the ring shape and a portion located outside the ring shape, or The first patterned mask layer includes a plurality of parts, and the gate electrode surrounds each of the parts. The manufacturing method according to claim 14.
20. The manufacturing method further includes the step of forming a first signal line, The first signal line is formed simultaneously with the first electrode, The orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first signal line on the substrate. The boundary of the orthographic projection of the first patterned mask layer on the substrate does not extend beyond the orthographic projection of the first signal line on the substrate, or partially overlaps with the edge of the orthographic projection of the first signal line and does not extend beyond the orthographic projection of the first signal line. The manufacturing method according to claim 14.
21. The first electrode comprises a conductive layer and a lower contact portion located on the side of the conductive layer away from the substrate. The manufacturing method further includes a step of heat treatment after forming the semiconductor material layer to enable a reduction in impedance between the semiconductor material layer and the lower contact portion. The manufacturing method according to claim 14.
22. The manufacturing method according to claim 16, further comprising the step of forming the contact material layer on the semiconductor material layer and then heat-treating it to enable a reduction in impedance between the semiconductor material layer and the contact material layer.