Semiconductor device and method for manufacturing the same

Abstract

The present invention provides semiconductor devices and methods for manufacturing the same. [Solution] The semiconductor device of the present invention includes a substrate, a channel layer having a fin shape that protrudes perpendicularly from the substrate, an external gate electrode provided on both sides and the top surface of the channel layer, and an internal gate electrode provided on the bottom surface of the channel layer. The internal gate electrode contains a different material from the external gate electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In a semiconductor device such as a FinFET (Fin Field Effect Transistor), a channel is formed in a fin shape protruding vertically from a substrate, and a gate electrode surrounds three sides of the channel. Such a semiconductor device having a three-dimensional shape has high performance and can achieve a high integration density.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing the same.

Means for Solving the Problems

[0004] To solve the above problems, in one aspect of the present invention, there is provided a semiconductor device including a substrate, a channel layer having a fin shape protruding perpendicularly to the substrate, an external gate electrode provided on both side surfaces and the upper surface of the channel layer, and an internal gate electrode provided on the lower surface of the channel layer, wherein the internal gate electrode includes a substance different from that of the external gate electrode.

[0005] The internal gate electrode may include a substance having an etching selectivity with respect to the external gate electrode.

[0006] The internal gate electrode and the external gate electrode may each include a metal, a metal nitride, a metal oxide, or a highly doped poly silicon.

[0007] The external gate electrode may include a first conductive layer provided on the channel layer and a second conductive layer provided on the first conductive layer.

[0008] The channel layer may include a group IV semiconductor, a group III-V semiconductor compound, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor, a quantum dot, or an organic semiconductor.

[0009] The internal gate electrode may include an internal conductive layer containing a different material from the external gate electrode, and barrier layers provided on the upper and lower surfaces of the internal conductive layer, respectively.

[0010] In another aspect of the present invention, a semiconductor element is provided comprising a first unit element and a second unit element arranged spaced apart from each other on a substrate, wherein each of the first unit element and the second unit element includes a channel layer having a fin shape protruding perpendicularly from the substrate, an external gate electrode provided on both sides and the top surface of the channel layer, and an internal gate electrode provided on the bottom surface of the channel layer, wherein the internal gate electrode contains a conductive material different from that of the external gate electrode.

[0011] The internal gate electrode may contain a material that exhibits etching selectivity with respect to the external gate electrode.

[0012] The external gate electrode of the first unit element may be configured to have a different thickness from the external gate electrode of the second unit element.

[0013] The external gate electrode may include a first conductive layer provided on the channel layer and a second conductive layer provided on the first conductive layer.

[0014] The first conductive layer of the first unit element may be configured to have a different thickness from the first conductive layer of the second unit element.

[0015] The internal gate electrode and the external gate electrode may each contain a metal, a metal nitride, a metal oxide, or polysilicon doped to a high concentration.

[0016] The channel layer may include a group IV semiconductor, a group III-V semiconductor compound, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor, a quantum dot, or an organic semiconductor.

[0017] The internal gate electrode may include an internal conductive layer containing a different material from the external gate electrode, and barrier layers provided on the upper and lower surfaces of the internal conductive layer, respectively.

[0018] In yet another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising the steps of: forming a first channel layer and a second channel layer having a first through-hole and a second through-hole formed at the bottom thereof, extending perpendicularly with respect to a substrate; forming a first internal gate electrode and a second internal gate electrode filling the first through-hole and the second through-hole; forming a first external gate material layer on the substrate so as to cover the first channel layer and the first internal gate electrode and the second channel layer and the second internal gate electrode; selectively etching and removing the first external gate material layer covering the first channel layer and the first internal gate electrode; and forming a second external gate material layer on the first channel layer and the first internal gate electrode and the first external gate material layer covering the second channel layer and the second internal gate electrode, wherein the first external gate electrode is formed on the first channel layer and the first internal gate electrode, and the second external gate electrode is formed on the second channel layer and the second internal gate electrode, and the first internal gate electrode and the second internal gate electrode are made of a different material from the first external gate electrode and the second external gate electrode.

[0019] The second external gate electrode may be formed to have a different thickness from the first external gate electrode.

[0020] The first and second through holes may each be formed in a direction parallel to the surface of the substrate.

[0021] The step of forming the first internal gate electrode and the second internal gate electrode may include forming an internal gate material layer on the first channel layer and the second channel layer so as to fill the first through hole and the second through hole, and etching and removing the internal gate material layer so that only the internal gate material layer remains inside the first through hole and the second through hole.

[0022] The internal gate material layer may include a material having an etching selectivity with respect to the first external gate material layer.

[0023] The first internal gate electrode and the second internal gate electrode may include an internal conductive layer containing a material different from that of the first external gate electrode and the second external gate electrode, and barrier layers formed on the upper surface and the lower surface of the internal conductive layer, respectively.

Brief Description of the Drawings

[0024] [Figure 1] It is a perspective view schematically showing a semiconductor element according to an exemplary embodiment. [Figure 2] It is a cross-sectional view taken along the line I-I' of FIG. 1. [Figure 3] It is a cross-sectional view of a semiconductor element according to another exemplary embodiment. [Figure 4] It is a cross-sectional view of a semiconductor element according to still another exemplary embodiment. [Figure 5] It is a cross-sectional view of a semiconductor element according to still another exemplary embodiment. [Figure 6] It is a cross-sectional view of a semiconductor element according to still another exemplary embodiment. [Figure 7A] It is a drawing for explaining a manufacturing method of a semiconductor element according to an exemplary embodiment. [Figure 7B] It is a drawing for explaining a manufacturing method of a semiconductor element according to an exemplary embodiment. [Figure 7C] It is a drawing for explaining a manufacturing method of a semiconductor element according to an exemplary embodiment. [Figure 7D]These are drawings illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 7E] These are drawings illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 7F] These are drawings illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 7G] These are drawings illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8A] This is a diagram illustrating a semiconductor device manufacturing method using comparative examples. [Figure 8B] This is a diagram illustrating a semiconductor device manufacturing method using comparative examples. [Figure 8C] This is a diagram illustrating a semiconductor device manufacturing method using comparative examples. [Figure 9A] These are drawings illustrating a method for manufacturing semiconductor devices according to other exemplary embodiments. [Figure 9B] These are drawings illustrating a method for manufacturing semiconductor devices according to other exemplary embodiments. [Figure 9C] These are drawings illustrating a method for manufacturing semiconductor devices according to other exemplary embodiments. [Figure 9D] These are drawings illustrating a method for manufacturing semiconductor devices according to other exemplary embodiments. [Figure 9E] These are drawings illustrating a method for manufacturing semiconductor devices according to other exemplary embodiments. [Figure 9F] These are drawings illustrating a method for manufacturing semiconductor devices according to other exemplary embodiments. [Figure 9G] These are drawings illustrating a method for manufacturing semiconductor devices according to other exemplary embodiments. [Figure 9H] These are drawings illustrating a method for manufacturing semiconductor devices according to other exemplary embodiments. [Modes for carrying out the invention]

[0025] The following exemplary embodiments will be described in detail with reference to the attached drawings. In the following drawings, similar reference numerals refer to similar components, and the size of each component in the drawings is exaggerated for clarity and convenience of explanation. On the other hand, the embodiments described below are merely illustrative, and various modifications are possible from these embodiments.

[0026] In the following, "top" or "above" may include not only things that are directly above, below, to the left, or to the right in contact, but also things that are above, below, to the left, or to the right without contact. A singular expression includes multiple expressions unless the context clearly indicates otherwise. Also, when a part "contains" a component, this means that it does not exclude other components, but rather includes other components, unless otherwise specified.

[0027] The use of the term "the foregoing" and similar referential terms may apply to both singular and plural nouns. Unless otherwise stated, the steps constituting a method may be performed in any order, and are not necessarily limited to the order in which they are stated.

[0028] Furthermore, terms such as "...part" and "module" used in the specification refer to a unit that processes at least one function or operation, which may be implemented in hardware or software, or in combination with hardware and software.

[0029] The connections between the components shown in the drawings, or the connecting members, are illustrative examples of functional and / or physical or circuit connections, and in actual devices, they may be represented by interchangeable or additional diverse functional, physical, or circuit connections.

[0030] Any use of examples or illustrative terms is solely for the purpose of illustrating the technical idea, and the scope of the invention is not limited by such examples or illustrative terms unless limited by the claims.

[0031] Figure 1 is a schematic perspective view of a semiconductor device 100 according to an exemplary embodiment. Figure 2 is a cross-sectional view taken along the line I-I' in Figure 1. The semiconductor device 100 shown in Figures 1 and 2 functions as a FinFET (Fin Field Effect Transistor).

[0032] Referring to Figures 1 and 2, a substrate 110 is provided. The substrate may include a variety of materials. For example, the substrate 110 may include a semiconductor material layer 111. The semiconductor material layer 111 may include a group IV semiconductor such as Si, Ge, SiGe, or a group III-V semiconductor compound. The semiconductor material layer 111 may also include, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor material (2D semiconductor material), a quantum dot, or an organic semiconductor. However, this is merely illustrative. The semiconductor material layer 111 may include a p-type dopant or an n-type dopant. The substrate 110 may further include an insulating material layer 112. The insulating material layer 112 may include, for example, silicon oxide, but is not limited to this.

[0033] The above describes the case where the substrate 110 includes a semiconductor material layer 111 and an insulating material layer 112, but the substrate 110 can also include a variety of other materials. For example, the substrate 110 may include a glass substrate or an SOI (semiconductor-on-insulator) substrate.

[0034] A channel layer 120 is provided on the substrate 110. The channel layer 120 may have a fin shape that protrudes from the upper surface of the substrate 110. The channel layer 120 has a length in the x-axis direction, a width in the y-axis direction, and a height in the z-axis direction.

[0035] The portions of the channel layer 120 in the longitudinal direction (x-axis direction) function as source 121 and drain 122, and the intermediate portion of the channel layer 120 between source 121 and drain 122 functions as a channel. The channel layer 120 may contain a semiconductor material. The channel layer 120 may contain, but is not limited to, the semiconductor material that constitutes the substrate 110. The channel layer 120 may contain, for example, a group IV semiconductor such as Si, Ge, SiGe, or a group III-V semiconductor compound. The channel layer 120 may contain, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor material, a quantum dot, or an organic semiconductor. Here, oxide semiconductors include, for example, InGaZnO, two-dimensional semiconductor materials include, for example, TMD (transition metal dichalcogenide), and quantum dots may include colloidal quantum dots (colloidal QD), nanocrystal structures, etc. However, this is merely illustrative. The channel layer 120 may further contain a dopant, which may include a p-type dopant or an n-type dopant.

[0036] A gate electrode 130 is provided so as to surround the channel of the channel layer 120. Here, the gate electrode 130 is provided so as to surround all four sides of the channel layer 120. The gate electrode 130 may include an external gate electrode 131 and an internal gate electrode 132. The external gate electrode 131 is provided so as to cover the top surface of the channel layer 120 and both sides of the channel layer 120 in the width direction of the channel layer 120. The internal gate electrode 132 is provided so as to cover the bottom surface of the channel layer 120. The internal gate electrode 132 is provided between the bottom surface of the channel layer 120 and the top surface of the substrate 110. On the other hand, although not shown in the drawings, a gate insulating layer is provided between the external gate electrode 131 and the channel layer 120 and between the internal gate electrode 132 and the channel layer 120.

[0037] The external gate electrode 131 may include, for example, a metal, a metal nitride, a metal oxide, or a combination thereof. Metals may include, for example, ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), platinum (Pt), etc. Metal nitrides may include, for example, titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), or tungsten nitride (WN). Metal oxides may include, for example, platinum oxide (PtO), iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenium oxide (SrRu3), barium strontium ruthenium oxide ((Ba,Sr)RuO3), calcium ruthenium oxide (CaRuO3), or lanthanum strontium cobalt oxide ((La,Sr)CoO3). The external gate electrode 131 may also contain highly doped polysilicon. Such an external gate electrode 131 may have a single-layer laminated structure. On the other hand, as will be described later, the external gate electrode 131 may have a laminated structure of multiple material layers.

[0038] The internal gate electrode 132 may contain a different material than the external gate electrode 131. Specifically, the internal gate electrode 132 may contain a material that exhibits etching selectivity with respect to the external gate electrode 131. Like the external gate electrode 131, the internal gate electrode 132 may contain, for example, a metal, a metal nitride, a metal oxide, or a combination thereof, or highly doped polysilicon. However, it is not limited to these.

[0039] According to an exemplary embodiment, the external gate electrode 131 is provided so as to cover both sides and the top surface of the channel layer 120, and the internal gate electrode 132 is provided so as to cover the bottom surface of the channel layer 120, thereby realizing a semiconductor element 100 in which the gate electrode 130 surrounds all four sides of the channel layer 120. In this way, by providing the internal gate electrode 132 on the bottom surface of the channel layer 120 in addition to the external gate electrode 131, leakage current generated from the bottom surface of the channel layer 120 can be further controlled. Furthermore, due to the fin shape of the channel layer 120, the internal gate electrode 132 provided on the bottom surface of the channel layer 120 has less influence on the channel layer 120 compared to the external gate electrode 131, so even if the internal gate electrode 132 is made of a different material than the external gate electrode 131, a stable threshold voltage can be achieved. In addition, as in the semiconductor manufacturing process described later, by forming the internal gate electrode 132 with a material that is etching selective to the external gate electrode 131, the problem of organic matter from the etching mask remaining between the substrate 110 and the channel layer 120 can be suppressed.

[0040] Figure 3 is a cross-sectional view of the semiconductor element 200 according to another exemplary embodiment. The semiconductor element 200 shown in Figure 3 functions as a FinFET array containing multiple FinFETs. Figure 3 exemplifies the case where the semiconductor element 200 contains two FinFETs. The following description will focus on the differences from the embodiments described above.

[0041] Referring to Figure 3, the semiconductor device 200 includes first and second unit elements 250a and 250b provided spaced apart from each other on the substrate 110. The first and second unit elements 250a and 250b each function as a FinFET. The first and second unit elements 250a and 250b may be configured to have different threshold voltages.

[0042] The first unit element 250a includes a first channel layer 220a provided on the substrate 110 and a first gate electrode provided so as to surround the first channel layer 220a. The first gate electrode includes a first external gate electrode 231a provided on both sides and the top surface of the first channel layer 220a and a first internal gate electrode 232a provided on the bottom surface of the first channel layer 220a. The substrate 110, the first channel layer 220a, the first external gate electrode 231a, and the first internal gate electrode 232a are the same as the substrate 110, channel layer 120, external gate electrode 131, and internal gate electrode 132 shown in Figure 2, so their description is omitted.

[0043] The second unit element 250b includes a second channel layer 220b provided on the substrate 110 and a second gate electrode provided so as to cover the second channel layer 220b. The second gate electrode includes a second external gate electrode 231b provided on both sides and the top surface of the second channel layer 220b and a second internal gate electrode 232b provided on the bottom surface of the second channel layer 220b. The second channel layer 220b and the second internal gate electrode 232b are identical to the first channel layer 220a and the first internal gate electrode 232a, respectively. The second external gate electrode 231b may contain the same material as the first external gate electrode 231a.

[0044] The second external gate electrode 231b may have a different thickness from the first external gate electrode 231a. For example, the second external gate electrode 231b may be thicker than the first external gate electrode 231a. In this way, by forming the first and second external gate electrodes 231a and 231b with different thicknesses and diffusing an elemental material that adjusts the work function into the first and second external gate electrodes 231a and 231b, the first and second external gate electrodes 231a and 231b may be configured to have different threshold voltages.

[0045] Figure 4 is a cross-sectional view of a semiconductor element 300 according to yet another exemplary embodiment. The following description will focus on the differences from the embodiments described above.

[0046] Referring to Figure 4, the first unit element 350a includes a first channel layer 320a provided on the substrate 110 and a first gate electrode provided so as to surround the first channel layer 320a. The first gate electrode includes a first external gate electrode 331a provided on both sides and the top surface of the first channel layer 320a, and a first internal gate electrode 332a provided on the bottom surface of the first channel layer 320a. The first external gate electrode 331a includes a first conductive layer 331a' provided on the first channel layer 320a and a second conductive layer 331a'' provided on the first conductive layer 331a'. Here, the first conductive layer 331a' of the first external gate electrode 331a is the same as the first external gate electrode 231a in Figure 3. The second conductive layer 331a'' of the first external gate electrode 331a contains a different material from the first conductive layer 331a' of the first external gate electrode 331a.

[0047] The second unit element 350b includes a second channel layer 320b provided on the substrate 110 and a second gate electrode provided so as to surround the second channel layer 320b. The second gate electrode includes a second external gate electrode 331b provided on both sides and the top surface of the second channel layer 320b and a second internal gate electrode 332b provided on the bottom surface of the second channel layer 320b. The second channel layer 320b and the second internal gate electrode 332b are identical to the first channel layer 320a and the first internal gate electrode 332a, respectively.

[0048] The second external gate electrode 331b includes a first conductive layer 331b' provided on the second channel layer 320b and a second conductive layer 331b'' provided on the first conductive layer 331b'. Here, the first conductive layer 331b' of the second external gate electrode 331b is the same as the second external gate electrode 231b in Figure 3. Therefore, the first conductive layer 331b' of the second external gate electrode 331b may have a different thickness from the first conductive layer 331a' of the first external gate electrode 331a.

[0049] The second conductive layer 331b'' of the second external gate electrode 331b is identical to the second conductive layer 331a'' of the first external gate electrode 331a. Therefore, the second conductive layer 331b'' of the second external gate electrode 331b may have the same thickness as the second conductive layer 331a'' of the first external gate electrode 331a. Furthermore, the second conductive layer 331b'' of the second external gate electrode 331b contains a different material from the first conductive layer 331b' of the second external gate electrode 331b. The second conductive layers 331a'' and 331b'' of the first and second external gates 331a and 331b may contain a material that modulates the work function (e.g., AI).

[0050] In this embodiment, the first conductive layer 331a' of the first external gate electrode 331a and the first conductive layer 331b' of the second external gate electrode 331b can be formed with different thicknesses, while the second conductive layer 331a'' of the first external gate electrode 331a and the second conductive layer 331b'' of the second external gate electrode 331b can be formed with the same thickness. Here, if the elemental material that adjusts the work function within the second conductive layers 331a'',331b'', diffuses into the first conductive layer 331a' of the first external gate electrode 331a and the first conductive layer 331b' of the second external gate electrode 331b, the difference in thickness of the first conductive layers 331a'' and 331b'' can cause the first external gate electrode 331a and the second external gate electrode 331b to be configured to have different threshold voltages.

[0051] Figure 5 is a cross-sectional view of a semiconductor element 400 according to yet another exemplary embodiment. The semiconductor element 400 shown in Figure 5 functions as a FinFET. The following description will focus on the differences from the embodiments described above.

[0052] Referring to Figure 5, the substrate 110 is provided with a channel layer 420. The channel layer 420 may have a fin shape protruding from the upper surface of the substrate 110. The channel layer 420 has a length in the x-axis direction, a width in the y-axis direction, and a height in the z-axis direction. The channel layer 420 may contain a semiconductor material. The channel layer 420 may contain, for example, a group IV semiconductor such as Si, Ge, SiGe, or a group III-V semiconductor compound. The channel layer 420 may contain, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor material, a quantum dot, or an organic semiconductor. However, this is merely illustrative. The channel layer 420 may further contain a p-type dopant or an n-type dopant.

[0053] A gate electrode is provided so as to surround the channel layer 420. Here, the gate electrode is provided so as to surround all four sides of the channel layer 420. The gate electrode may include an external gate electrode 431 and an internal gate electrode 432. The external gate electrode 431 is provided so as to cover the top surface and both sides of the channel layer 420. The internal gate electrode 432 is provided so as to cover the bottom surface of the channel layer 420. The internal gate electrode 432 is provided between the bottom surface of the channel layer 420 and the top surface of the substrate 110. On the other hand, although not shown in the drawings, a gate insulating layer is provided between the external gate electrode 431 and the channel layer 420, and between the internal gate electrode 432 and the channel layer 420.

[0054] The external gate electrode 431 may contain, for example, a metal, a metal nitride, a metal oxide, or a combination thereof, or polysilicon doped to a high concentration. Such an external gate electrode 431 may have a single-layer laminated structure. Alternatively, the external gate electrode 431 may have a multiple-layer laminated structure.

[0055] The internal gate electrode 432 includes an internal conductive layer 432' and barrier layers 432'' provided on the upper and lower surfaces of the internal conductive layer 432', respectively. Here, the internal conductive layer 432' may contain a different material than that of the external gate electrode 431. Specifically, the internal conductive layer 432' may contain a material that has etching selectivity with respect to the external gate electrode 431. The internal conductive layer 432' may, like the external gate electrode 431, contain, for example, a metal, a metal nitride, a metal oxide, or a combination thereof, or polysilicon doped to a high concentration. However, it is not limited to these.

[0056] The barrier layer 432" may contain a substance that suppresses the diffusion of material within the internal conductive layer 432' to the outside. The barrier layer 432" may contain a substance different from that of the internal conductive layer 432'. The barrier layer 432" may contain a substance different from that of the external gate electrode 431, or it may contain the same substance as the external gate electrode 431. For example, if the internal conductive layer 432' contains tungsten (W), the barrier layer 432" may contain titanium nitride (TiN). However, this embodiment is not limited thereto.

[0057] Figure 6 is a cross-sectional view of the semiconductor element 500 according to yet another exemplary embodiment. The semiconductor element 500 shown in Figure 6 functions as a FinFET array including multiple FinFETs. Figure 6 exemplifies the case where the semiconductor element 500 includes two FinFETs. The following description will focus on the differences from the embodiments described above.

[0058] Referring to Figure 6, the semiconductor element 500 includes first and second unit elements 550a and 550b provided spaced apart from each other on the substrate 110. The first and second unit elements 550a and 550b each function as a FinFET. The first and second unit elements 550a and 550b may be configured to have different threshold voltages.

[0059] The first unit element 550a includes a first channel layer 520a provided on the substrate 110 and a first gate electrode provided so as to surround the first channel layer 520a. The first gate electrode includes a first external gate electrode 531a provided on both sides and the top surface of the first channel layer 520a and a first internal gate electrode 532a provided on the bottom surface of the first channel layer 520a. Here, the first internal gate electrode 532a includes a first internal conductive layer 532a' and a first barrier layer 532a'' provided on the top and bottom surfaces of the first internal conductive layer 532a', respectively. The first channel layer 520a, the first external gate electrode 531a, and the first internal gate electrode 532a are the same as the channel layer 420, external gate electrode 431, and internal gate electrode 432 shown in Figure 5, so their explanation is omitted.

[0060] The second unit element 550b includes a second channel layer 520b provided on the substrate 110 and a second gate electrode provided so as to surround the second channel layer 520b. The second gate electrode includes a second external gate electrode 531b provided on both sides and the top surface of the second channel layer 520b and a second internal gate electrode 532b provided on the bottom surface of the second channel layer 520b. Here, the second internal gate electrode 532b includes a second internal conductive layer 532b' and a second barrier layer 532b'' provided on the top and bottom surfaces of the second internal conductive layer 532b', respectively. The second channel layer 520b and the second internal gate electrode 532b are identical to the first channel layer 520a and the first internal gate electrode 532a, respectively. The second external gate electrode 531b may contain the same material as the first external gate electrode 531a.

[0061] The second external gate electrode 531b may have a different thickness from the first external gate electrode 531a. For example, the second external gate electrode 531b is thicker than the first external gate electrode 531a. In this way, by forming the first and second external gate electrodes 531a and 531b with different thicknesses and diffusing an elemental material that adjusts the work function into the first and second external gate electrodes 531a and 531b, the first and second external gate electrodes 531a and 531b can be configured to have different threshold voltages. On the other hand, each of the first and second external gate electrodes 531a and 531b may include a first conductive layer and a second conductive layer provided on the first conductive layer, similar to those shown in Figure 4.

[0062] Figures 7A to 7F are diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. Figures 7A to 7F show an exemplary method for manufacturing the semiconductor device 200 shown in Figure 3.

[0063] Referring to Figure 7A, first and second channel layers 220a and 220b are formed perpendicular to the substrate 110. The substrate 110 may include a semiconductor material layer 111. The semiconductor material layer 111 may include a group IV semiconductor such as Si, Ge, SiGe, or a group III-V semiconductor compound. The semiconductor material layer 111 may also include, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor material, a quantum dot, or an organic semiconductor. However, this is merely illustrative. The semiconductor material layer 111 may include a p-type dopant or an n-type dopant. The substrate 110 may further include an insulating material layer 112. The insulating material layer 112 may include, for example, silicon oxide, but is not limited to this.

[0064] The first and second channel layers 220a and 220b may each be formed in a fin shape protruding from the upper surface of the substrate 110. The first and second channel layers 220a and 220b may contain the same material as the semiconductor material layer 111 of the substrate 110. For example, the first and second channel layers 220a and 220b may contain a group IV semiconductor such as Si, Ge, or SiGe, or a group III-V semiconductor compound. The first and second channel layers 220a and 220b may also contain, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor material, a quantum dot, or an organic semiconductor. The first and second channel layers 220a and 220b may also contain a p-type dopant or an n-type dopant. Such first and second channel layers 220a and 220b may be formed by etching the semiconductor material layer 111 constituting the substrate 110 into a predetermined shape.

[0065] Next, first and second through-holes h1 and h2 are formed in the first and second channel layers 220a and 220b, respectively. The first and second through-holes h1 and h2 may be formed through the first and second channel layers 220a and 220b in a direction parallel to the surface of the substrate 110 (y-axis direction). Here, the first through-hole h1 may be formed between the upper surface of the substrate 110 and the lower surface of the first channel layer 220a, and the second through-hole h2 may be formed between the upper surface of the substrate 110 and the lower surface of the second channel layer 220b.

[0066] Referring to Figure 7B, the first and second channel layers 220a, 220b and the substrate 110 are formed to fill the first and second through holes h1, h2. The internal gate material layer 232' may include, for example, a metal, a metal nitride, a metal oxide, or a combination thereof. Metals may include, for example, ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), platinum (Pt), etc. Metal nitrides may include, for example, titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), or tungsten nitride (WN), etc. The metal oxides may include, for example, platinum oxide (PtO), iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenium oxide (SrRu3), barium strontium ruthenium oxide ((Ba,Sr)RuO3), calcium ruthenium oxide (CaRuO3), or lanthanum strontium cobalt oxide ((La,Sr)CoO3). The internal gate material layer 232' may contain highly doped polysilicon. The internal gate material layer 232' may contain a material that has etching selectivity with respect to the first external gate material layer (231' in Figure 7), which will be described later.

[0067] Referring to Figure 7C, the internal gate material layer 232' is partially etched so that it remains only inside the first and second through holes h1 and h2. This allows for the formation of a first internal gate electrode 232a to fill the first through hole h1 and a second internal gate electrode 232b to fill the second through hole h2.

[0068] Referring to Figure 7D, a first outer gate material layer 231' is formed to cover the first channel layer 220a and the first internal gate electrode 232a, and the second channel layer 220b and the second internal gate electrode 232b. Here, the first outer gate material layer 231' may contain a different material from the internal gate material layer 232'. Specifically, the first outer gate material layer 231' may contain a material that has etching selectivity with respect to the internal gate material layer 232'. The first outer gate material layer 231' may, for example, contain a metal, a metal nitride, a metal oxide, or a combination thereof, or polysilicon doped to a high concentration. However, it is not limited to these.

[0069] Referring to Figure 7E, only the first external gate material layer 231' covering the first channel layer 220a and the first internal gate electrode 232a is selectively etched and removed. Specifically, an etching mask M is formed to cover the first external gate material layer 231' formed on the second channel layer 220b and the second internal gate electrode 232b through patterning. Here, the etching mask M includes, but is not limited to, silicon-based or carbon-based organic materials. Next, the etching mask M is used to selectively etch only the first external gate material layer 231' covering the first channel layer 220a and the first internal gate electrode 232a. Then, referring to Figure 7F, the etching mask M formed on the first external gate material layer 231' covering the second channel layer 220b and the second internal gate electrode 232b is removed.

[0070] Referring to Figure 7G, a second external gate material layer (not shown) is formed to cover the structure shown in Figure 7F. The second external gate material layer may contain the same material as the first external gate material layer 231'. The second external gate material layer may be formed to cover the first channel layer 220a and the first internal gate electrode 232a, and the first external gate material layer 231' formed on the second channel layer 220b and the second internal gate electrode 232b. Here, the second external gate material layer covering the first channel layer 220a and the first internal gate electrode 232a functions as the first external gate electrode 231a. The first external gate material layer 231' and the second external gate material layer covering the second channel layer 220b and the second internal gate electrode 232b constitute the second external gate electrode 231b. Therefore, the second external gate electrode 231b may be formed thicker than the first external gate electrode 231a. In this way, a semiconductor element 200 can be fabricated, which includes first and second unit elements 250a and 250b arranged on a substrate 110 at a distance from each other. On the other hand, conductive layers (not shown) containing elemental material for adjusting the work function may be further formed on the first and second external gate electrodes 231a and 231b.

[0071] Figures 8A to 8C are diagrams illustrating a semiconductor device manufacturing method using comparative examples. Figures 8A to 8C exemplify problems that arise in the semiconductor device manufacturing process when the internal gate electrode and the external gate electrode are made of the same gate material layer.

[0072] Referring to Figure 8A, after forming fin-shaped first and second channel layers 220a and 220b that extend perpendicularly to the substrate 110, first and second through-holes are formed in the first and second channel layers 220a and 220b, respectively. Next, a gate material layer 31' is formed on the first and second channel layers 220a and 220b and the substrate 110. Here, the gate material layer 31' may be formed to surround the four sides of the first and second channel layers 220a and 220b, respectively. Here, it is desirable that the gate material layer 31' be formed to fill the first and second through-holes, but due to the process, there is a possibility that an empty gap will occur between the gate material layer 31' formed on the lower surface of the first and second channel layers 220a and 220b and the substrate 110.

[0073] Referring to Figure 8B, only the gate material layer 31' on the first channel layer 220a is selectively etched and removed. Specifically, an etching mask M is formed to cover the gate material layer 31' formed on the second channel layer 220b through patterning. Here, the etching mask M includes, but is not limited to, silicon-based or carbon-based organic materials. Next, the etching mask M is used to selectively etch only the gate material layer 31' covering the first channel layer 220a.

[0074] Referring to Figure 8C, the etching mask M formed on the gate material layer 31' covering the second channel layer 220b is removed. However, during this etching mask M removal process, a problem arises in which the organic material M' of the etching mask M that fills the gap between the gate material layer 31' formed on the underside of the second channel layer 220b and the substrate 110 remains.

[0075] Figures 9A to 9H are drawings illustrating a method for manufacturing a semiconductor device according to another exemplary embodiment. Figures 9A to 9H show an exemplary method for manufacturing the semiconductor device 500 shown in Figure 6.

[0076] Referring to Figure 9A, after forming fin-shaped first and second channel layers 520a and 520b that extend perpendicularly to the substrate 110, first and second through-holes are formed in the first and second channel layers 520a and 520b, respectively. The first and second through-holes may be formed by penetrating the first and second channel layers 520a and 520b in a direction parallel to the surface of the substrate 110. Next, a barrier material layer 532' is formed on the surfaces of the first and second channel layers 520a and 520b and on the upper surface of the substrate 110. The barrier material layer 532' may be formed to surround the four sides of each of the first and second channel layers 520a and 520b and cover the upper surface of the substrate 110. The barrier material layer 532' may contain a material that suppresses the diffusion of the internal conductive material layer (532") in Figure 9B, which will be described later.

[0077] Referring to Figure 9B, an internal conductive material layer 532'' is formed on the first and second channel layers 520a, 520b and the barrier material layer 532' formed on the substrate 110. Here, the internal conductive material layer 532'' may contain a different material from the barrier material layer 532'. Furthermore, the internal conductive material layer 532'' may contain a material that has etching selectivity with respect to the first external gate material layer 531', which will be described later. The internal conductive material layer 532'' may contain, for example, a metal, a metal nitride, a metal oxide, or a combination thereof, or polysilicon doped to a high concentration.

[0078] The internal conductive material layer 532” may be formed to fill the space between the first and second channel layers 520a, 520b and the substrate 110. As a result, the space between the first and second channel layers 520a, 520b and the substrate 110 may be filled with the internal conductive material layer 532” and the barrier material layers 532’ formed on the upper and lower surfaces of the internal conductive material layer 532” respectively.

[0079] Referring to Figure 9C, the internal conductive material layer 532" is partially etched so that it remains only between the first and second channel layers 520a, 520b and the substrate 110. Then, referring to Figure 9D, the barrier material layer 532' is partially etched so that it remains only between the first and second channel layers 520a, 520b and the substrate 110. As a result, the first internal gate electrode 532a can be formed between the lower surface of the first channel layer 520a and the upper surface of the substrate 110. The first internal gate electrode 532a includes the first internal conductive layer 532a' and the first barrier layer 532a'' provided on the upper and lower surfaces of the first internal conductive layer 532a', respectively. A second internal gate electrode 532b may be formed between the lower surface of the second channel layer 520b and the upper surface of the substrate 110. The second internal gate electrode 532b includes the second internal conductive layer 532b' and the second barrier layer 532b'' provided on the upper and lower surfaces of the second internal conductive layer 532b', respectively.

[0080] Referring to Figure 9E, a first external gate material layer 531' is formed to cover the first channel layer 520a and the first internal gate electrode 532a, and the second channel layer 520b and the second internal gate electrode 532b. Here, the first external gate material layer 531' may contain a different material from the internal conductive material layer 532" described above. Specifically, the first external gate material layer 531' may contain a material that has etching selectivity with respect to the internal conductive material layer 532". The first external gate material layer 531' may, for example, contain a metal, a metal nitride, a metal oxide, or a combination thereof, or polysilicon doped to a high concentration. However, it is not limited to these.

[0081] Referring to Figure 9F, only the first external gate material layer 531' covering the first channel layer 520a and the first internal gate electrode 532a is selectively etched and removed. Specifically, an etching mask M is formed by patterning to cover the first external gate material layer 531' formed on the second channel layer 520b and the second internal gate electrode 532b. Here, the etching mask M includes, but is not limited to, silicon-based or carbon-based organic materials. Next, the etching mask M is used to selectively etch only the first external gate material layer 531' covering the first channel layer 520a and the first internal gate electrode 532a. Then, referring to Figure 9G, the etching mask M formed on the first external gate material layer 531' covering the second channel layer 520b and the second internal gate electrode 532b is removed.

[0082] Referring to Figure 9H, a second external gate material layer (not shown) is formed to cover the structure shown in Figure 9G. The second external gate material layer may contain the same material as the first external gate material layer 531'. The second external gate material layer may be formed to cover the first channel layer 520a and the first internal gate electrode 532a, and the first external gate material layer 531' formed on the second channel layer 520b and the second internal gate electrode 532b. Here, the second external gate material layer covering the first channel layer 520a and the first internal gate electrode 532a functions as the first external gate electrode 531a. The first external gate material layer 531' and the second external gate material layer covering the second channel layer 520b and the second internal gate electrode 532b constitute the second external gate electrode 531b. Therefore, the second external gate electrode 531b may be formed thicker than the first external gate electrode 531a. In this way, a semiconductor element 500 can be fabricated, which includes first and second unit elements 550a and 550b arranged on a substrate 110 at a distance from each other. On the other hand, conductive layers (not shown) containing elemental material for adjusting the work function may be further formed on the first and second external gate electrodes 531a and 531b.

[0083] According to the exemplary embodiments described above, by providing an external gate electrode so as to cover both sides and the top surface of the channel layer, and an internal gate electrode so as to cover the bottom surface of the channel layer, a semiconductor device can be realized in which the gate electrode surrounds all four sides of the channel layer. In this way, by providing an internal gate electrode on the bottom surface of the channel layer in addition to the external gate electrode, leakage current generated from the bottom surface of the channel layer can be further controlled. Furthermore, due to the fin shape of the channel layer, the internal gate electrode provided on the bottom surface of the channel layer has less influence on the channel layer than the external gate electrode, so a stable threshold voltage can be achieved even if the internal gate electrode is made of a different material than the external gate electrode. In addition, in the semiconductor manufacturing process, by forming the internal gate electrode with a material that is etching selective compared to the external gate electrode, the problem of organic matter from the etching mask remaining between the substrate and the channel layer can be suppressed. The embodiments described above are merely exemplary, and various modifications are possible for those with ordinary knowledge in the field. [Explanation of Symbols]

[0084] 100 semiconductor devices 110 circuit boards 111 Semiconductor material layer 112 Insulating material layer 120 channel layer 121 Source 122 drain 130 gates 131 External gate electrode 132 Internal gate electrode 200 semiconductor elements 220a First channel layer 220b Second channel layer 231' First outer gate material layer 231a First external gate electrode 231b Second external gate electrode 232' Inner Gate Material Layer 232a First internal gate electrode 232b Second internal gate 250a First Unit Element 250b Second unit element 300 semiconductor elements 320a First channel layer 320b Second channel layer 331a First external gate electrode 331b Second external gate electrode 332a First internal gate 332b Second Inner Geothermal Region 350a First Unit Element 350b Second unit element 400 semiconductor elements 420 channel layer 431 External gate electrode 432 Internal gate electrode 500 semiconductor elements 520a First channel layer 520b Second channel layer 531a First external gate electrode 531b Second external gate electrode 532 Internal conductive material layer 532a First internal gate electrode 532b Second internal gate electrode 550a First Unit Element 550b Second unit element

Claims

1. circuit board and A channel layer having a fin shape that protrudes perpendicularly to the substrate, External gate electrodes are provided on both sides and the top surface of the channel layer, The channel layer includes an internal gate electrode provided on the lower surface of the channel layer, The internal gate electrode is a semiconductor element containing a different material from the external gate electrode.

2. The semiconductor device according to claim 1, wherein the internal gate electrode contains a material having etching selectivity with respect to the external gate electrode.

3. The semiconductor device according to claim 1, wherein the internal gate electrode and the external gate electrode each comprise a metal, a metal nitride, a metal oxide, or highly doped polysilicon.

4. The semiconductor device according to claim 1, wherein the external gate electrode includes a first conductive layer provided on the channel layer and a second conductive layer provided on the first conductive layer.

5. The semiconductor device according to claim 1, wherein the channel layer includes a group IV semiconductor, a group III-V semiconductor compound, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor, a quantum dot, or an organic semiconductor.

6. The semiconductor element according to claim 1, wherein the internal gate electrode includes an internal conductive layer containing a material different from that of the external gate electrode, and barrier layers provided on the upper and lower surfaces of the internal conductive layer, respectively.

7. It includes a first unit element and a second unit element arranged on a substrate at a distance from each other, Each of the first unit element and the second unit element is, A channel layer having a fin shape that protrudes perpendicularly to the substrate, External gate electrodes are provided on both sides and the top surface of the channel layer, The channel layer includes an internal gate electrode provided on the lower surface of the channel layer, The internal gate electrode contains a conductive material different from that of the external gate electrode, making it a semiconductor device.

8. The semiconductor device according to claim 7, wherein the internal gate electrode contains a material that is etching selective with respect to the external gate electrode.

9. The semiconductor element according to claim 7, wherein the external gate electrode of the first unit element is configured to have a different thickness from the external gate electrode of the second unit element.

10. The semiconductor device according to claim 7, wherein the external gate electrode includes a first conductive layer provided on the channel layer and a second conductive layer provided on the first conductive layer.

11. The semiconductor element according to claim 10, wherein the first conductive layer of the first unit element is configured to have a different thickness from the first conductive layer of the second unit element.

12. The semiconductor device according to claim 7, wherein the internal gate electrode and the external gate electrode each comprise a metal, a metal nitride, a metal oxide, or highly doped polysilicon.

13. The semiconductor device according to claim 7, wherein the channel layer includes a group IV semiconductor, a group III-V semiconductor compound, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor, a quantum dot, or an organic semiconductor.

14. The semiconductor element according to claim 7, wherein the internal gate electrode includes an internal conductive layer containing a material different from that of the external gate electrode, and barrier layers provided on the upper and lower surfaces of the internal conductive layer, respectively.

15. The steps include forming a first channel layer and a second channel layer, each having a first through-hole and a second through-hole formed at the bottom, so as to extend perpendicularly to the substrate, The steps include forming a first internal gate electrode and a second internal gate electrode that fill the first through hole and the second through hole, The steps include forming a first outer gate material layer on the substrate so as to cover the first channel layer and the first inner gate electrode, and the second channel layer and the second inner gate electrode, The steps include selectively etching and removing the first channel layer and the first outer gate material layer covering the first inner gate electrode, The process includes the step of forming a second outer gate material layer on the first outer gate material layer covering the first channel layer and the first inner gate electrode, and the second channel layer and the second inner gate electrode, A first external gate electrode is formed on the first channel layer and the first internal gate electrode, and a second external gate electrode is formed on the second channel layer and the second internal gate electrode. A method for manufacturing a semiconductor device, wherein the first internal gate electrode and the second internal gate electrode contain materials different from the first external gate electrode and the second external gate electrode.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the second external gate electrode is formed to have a different thickness from the first external gate electrode.

17. The method for manufacturing a semiconductor element according to claim 15, wherein the first through hole and the second through hole are each formed in a direction parallel to the surface of the substrate.

18. The step of forming the first internal gate electrode and the second internal gate electrode is: The steps include forming an internal gate material layer in the first channel layer and the second channel layer so as to fill the first through hole and the second through hole, A method for manufacturing a semiconductor device according to claim 15, comprising the step of etching and removing the internal gate material layer such that the internal gate material layer remains only inside the first through hole and the second through hole.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the internal gate material layer contains a material that is etching selective with respect to the first external gate material layer.

20. The method for manufacturing a semiconductor device according to claim 15, wherein the first internal gate electrode and the second internal gate electrode each include an internal conductive layer containing a material different from that of the first external gate electrode and the second external gate electrode, and barrier layers formed on the upper and lower surfaces, respectively, of the internal conductive layer.

Images