Solid-state image sensor and imaging device

Abstract

The present invention provides a solid-state image sensor and imaging device that enable an expanded dynamic range while improving the signal-to-noise ratio during high-sensitivity readout. [Solution] In the solid-state image sensor 4, each of the multiple pixel blocks BL is provided corresponding to a photoelectric conversion unit PD, a first node Pa, and one photoelectric conversion unit PD, and includes one transfer switch TX for transferring charge from the photoelectric conversion unit PD to the first node Pa, two first switch units SWA for electrically connecting and disconnecting the first node Pa of one pixel block BL and the first node Pa of another pixel block BL, and two second nodes Pb corresponding to these two first nodes Pa, respectively, a second switch unit SWB for electrically connecting and disconnecting the two second nodes Pb, and two third switch units RST for supplying a predetermined potential VDD to the two second nodes Pb, respectively.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device and an imaging apparatus using the same.

Background Art

[0002] Patent Document 1 below discloses a solid-state imaging device including a plurality of pixels, at least two of which each include (a) a photodetector, (b) a charge-voltage conversion region forming a floating capacitance portion, and (c) an input portion to an amplifier, and a connection switch that selectively connects the charge-voltage conversion regions to each other.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the conventional solid-state imaging device, by turning on the connection switch to connect the charge-voltage conversion regions to each other, the saturation electron number in the entire connected charge-voltage conversion region is increased, so that the dynamic range can be expanded.

[0005] Further, in the conventional solid-state imaging device, by turning off the connection switch to disconnect the charge-voltage conversion region from other charge-voltage conversion regions, the charge-voltage conversion capacitance becomes smaller and the charge-voltage conversion coefficient becomes larger, so that the SN ratio at the time of high-sensitivity readout becomes higher.

[0006] However, in the conventional solid-state imaging device, even when the connection switch is turned off, the SN ratio at the time of high-sensitivity readout could not be significantly increased.

[0007] This invention has been made in view of these circumstances, and aims to provide a solid-state image sensor that can expand the dynamic range and improve the signal-to-noise ratio during high-sensitivity readout, and an imaging device using the same. [Means for solving the problem]

[0008] To solve the aforementioned problems, the following embodiments are presented. The solid-state image sensor according to the first embodiment comprises a plurality of pixel blocks having one photoelectric conversion unit, a first node, and one transfer switch provided in correspondence with the one photoelectric conversion unit for transferring charge from the photoelectric conversion unit to the first node; two second nodes corresponding to the first node of one of the pixel blocks and the first node of another pixel block, respectively; two first switch units that electrically connect and disconnect the first node of one of the pixel blocks and the two second nodes, respectively; a second switch unit that electrically connects and disconnects the two second nodes; and two third switch units that supply a predetermined potential to the two second nodes, respectively.

[0009] The aforementioned pixel block may have only one photoelectric conversion unit and consist of one pixel, or it may have two or more photoelectric conversion units and consist of multiple pixels. This also applies to each of the embodiments described later.

[0010] In the second embodiment, the solid-state image sensor is such that, in the first embodiment, each pixel block has a plurality of photoelectric conversion units and transfer switches.

[0011] A solid-state image sensor according to a third embodiment includes a control unit that controls each of the first and third switch units, such that, in the first or second embodiment, the first switch unit that electrically connects and disconnects the first node of one pixel block and the corresponding second node is turned on only when the potential of the first node of one pixel block is reset, and the third switch unit that supplies the predetermined potential to the second node corresponding to the first node of one pixel block is turned on at least when the potential of the first node of one pixel block is reset.

[0012] In the fourth embodiment of the solid-state image sensor, the control unit controls the first switch unit, the second switch unit, and the third switch unit so that in the second operating mode, the first switch unit which electrically connects and disconnects the first node of one pixel block and the corresponding second node is turned on, the second switch unit is turned off, and the third switch unit which supplies the predetermined potential to the second node corresponding to the first node of one pixel block is turned on only when the potential of the first node of one pixel block is reset.

[0013] In the fifth embodiment of the solid-state image sensor, in the third or fourth embodiment, the control unit controls the first switch unit, the second switch unit, and the third switch unit so that in the third operating mode, the first switch unit which electrically connects and disconnects the first node of one pixel block and the corresponding second node is turned on, the second switch unit is turned on, and the third switch unit which supplies the predetermined potential to the second node corresponding to the first node of one pixel block is turned on only when the potential of the first node of one pixel block is reset.

[0014] The solid-state image sensor according to the sixth embodiment comprises, in the first or second embodiment, three or more first switch units that electrically connect and disconnect the electrical connections between the first nodes of three or more pixel blocks among the plurality of pixel blocks and three or more second nodes corresponding to these three or more first nodes, the three or more second nodes are connected in a daisy-chain manner by the plurality of second switch units, and the solid-state image sensor comprises three or more third switch units that supply the predetermined potential to the three or more second nodes.

[0015] A solid-state image sensor according to the seventh embodiment includes a control unit that controls each of the first and third switch units, such that in the first operating mode, the first switch unit, which electrically connects and disconnects the first node of one of the three or more pixel blocks and the corresponding second node thereto, is turned on only when the potential of the first node of one of the three or more pixel blocks is reset, and the third switch unit, which supplies the predetermined potential to the second node corresponding to the first node of one of the three or more pixel blocks, is turned on at least when the potential of the first node of one of the three or more pixel blocks is reset.

[0016] In the eighth embodiment of the solid-state image sensor, in the seventh embodiment, the control unit controls the first switch unit, the second switch unit, and the third switch unit so that in the second operating mode, the first switch unit which electrically connects and disconnects the first node of one of the three or more pixel blocks and the corresponding second node is turned on, the second switch unit which is electrically connected to the second node corresponding to the first node of one of the three or more pixel blocks is turned off, and the third switch unit which supplies the predetermined potential to the second node corresponding to the first node of one of the three or more pixel blocks is turned on only when the potential of the first node of one of the three or more pixel blocks is reset.

[0017] In the ninth embodiment of the solid-state image sensor, in the seventh or eighth embodiment, the control unit controls each of the first, second, and third switch units such that in the third operating mode, the first switch unit which electrically connects and disconnects the first node of one of the three or more pixel blocks and the corresponding second node is turned on, the second switch unit which is electrically connected to the second node corresponding to the first node of one of the three or more pixel blocks is turned on, and the third switch unit which supplies the predetermined potential to the second node corresponding to the first node of one of the three or more pixel blocks is turned on only when the potential of the first node of one of the three or more pixel blocks is reset.

[0018] The imaging device according to the tenth embodiment is equipped with a solid-state image sensor according to any of the first to ninth embodiments.

[0019] The imaging device according to the 11th aspect includes a solid-state imaging device according to the 3rd, 4th, 5th, 7th, 8th, or 9th aspect, and control means for switching each of the operation modes according to a set value of the ISO sensitivity.

Advantages of the Invention

[0020] According to the present invention, it is possible to provide a solid-state imaging device capable of expanding the dynamic range and improving the SN ratio at the time of high-sensitivity reading, and an imaging device using the same.

Brief Description of the Drawings

[0021] [Figure 1] It is a schematic block diagram schematically showing an electronic camera according to the first embodiment of the present invention. [Figure 2] It is a circuit diagram showing a schematic configuration of the solid-state imaging device in FIG. 1. [Figure 3] It is a circuit diagram showing an enlarged view of the vicinity of four pixel blocks in FIG. 1. [Figure 4] It is a schematic plan view schematically showing the vicinity of three pixel blocks in FIG. 3. [Figure 5] It is a schematic plan view showing an enlarged view of the vicinity of one pixel block in FIG. 4. [Figure 6] It is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 2. [Figure 7] It is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 2. [Figure 8] It is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2. [Figure 9] It is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2. [Figure 10] It is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2. [Figure 11] It is a circuit diagram showing the vicinity of three pixel blocks of a solid-state imaging device according to a comparative example. [Figure 12]This is a schematic plan view illustrating the vicinity of the three pixel blocks shown in Figure 9. [Figure 13] This is a circuit diagram showing the schematic configuration of a solid-state image sensor for an electronic camera according to a second embodiment of the present invention. [Modes for carrying out the invention]

[0022] The solid-state image sensor and imaging device according to the present invention will be described below with reference to the drawings.

[0023] [First Embodiment] Figure 1 is a schematic block diagram illustrating an electronic camera 1 according to a first embodiment of the present invention.

[0024] The electronic camera 1 according to this embodiment is configured as, for example, a single-lens reflex digital camera, but the imaging device according to the present invention is not limited to this and can be applied to various imaging devices such as other electronic cameras such as compact cameras, electronic cameras mounted on mobile phones, and video cameras that capture video.

[0025] An imaging lens 2 is attached to the electronic camera 1. The focus and aperture of this imaging lens 2 are driven by the lens control unit 3. The imaging surface of the solid-state image sensor 4 is positioned in the image space of this imaging lens 2.

[0026] The solid-state image sensor 4 is driven by commands from the imaging control unit 5 and outputs a digital image signal. During normal shooting (still image shooting), the imaging control unit 5 controls the solid-state image sensor 4 to perform a predetermined readout operation after, for example, a so-called global reset in which all pixels are reset simultaneously, followed by exposure with a mechanical shutter (not shown). In electronic viewfinder mode or during video recording, the imaging control unit 5 controls the solid-state image sensor 4 to perform a predetermined readout operation while, for example, performing a so-called rolling electronic shutter. In these cases, the imaging control unit 5 controls the solid-state image sensor 4 to perform the readout operation of each operating mode, as described later, according to the ISO sensitivity setting. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation, and white balance processing on the digital image signal output from the solid-state image sensor 4. The image signal after processing by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. Bus 8 is also connected to the lens control unit 3, image processing control unit 5, CPU 9, display unit 10 such as an LCD display panel, recording unit 11, image compression unit 12, and image processing unit 13. The CPU 9 is connected to an operation unit 14 such as a shutter release button. The operation unit 14 allows the ISO sensitivity to be set. A recording medium 11a is detachably attached to the recording unit 11.

[0027] The CPU 9 in the electronic camera 1 drives the image processing unit 5 accordingly when instructed by the operation unit 14 to switch to electronic viewfinder mode, video recording, or normal shooting (still image shooting). At this time, the lens control unit 3 adjusts the focus and aperture as appropriate. The solid-state image sensor 4 is driven by the command of the image processing unit 5 and outputs a digital image signal. The digital image signal from the solid-state image sensor 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. When in electronic viewfinder mode, the CPU 9 displays the image signal on the display unit 10, and when shooting video, it records the image signal on the recording medium 11a. In the case of normal shooting (still image shooting), after the digital image signal from the solid-state image sensor 4 has been processed by the digital signal processing unit 6 and stored in the memory 7, the CPU 9 performs the necessary processing in the image processing unit 13 and image compression unit 12 based on the command of the operation unit 14, and outputs the processed signal to the recording unit 11 for recording on the recording medium 11a.

[0028] Figure 2 is a circuit diagram showing the schematic configuration of the solid-state image sensor 4 in Figure 1. Figure 3 is a circuit diagram showing a magnified view of the vicinity of four pixel blocks BL arranged sequentially in the column direction in Figure 2. Figure 4 is a schematic plan view schematically showing the vicinity of three pixel blocks BL in Figure 3. Figure 5 is a schematic plan view showing a magnified view of the vicinity of one pixel block BL in Figure 4. In this embodiment, the solid-state image sensor 4 is configured as a CMOS type solid-state image sensor, but it is not limited to this, and may be configured as, for example, another XY address type solid-state image sensor.

[0029] As shown in Figures 2 to 4, the solid-state image sensor 4 is arranged in a two-dimensional matrix with N rows and M columns, and comprises a pixel block BL having two pixels PX (PXA, PXB), a first transistor SWA as a first switch unit that electrically connects and disconnects a first node Pa and its corresponding second node Pb (described later), a second transistor SWB as a second switch unit that electrically connects and disconnects two second nodes Pb, and a third switch that supplies a power supply voltage VDD as a predetermined potential to the second nodes Pb. The circuit includes a reset transistor RST as a control unit, a vertical scanning circuit 21, control lines 22-27 provided for each row of the pixel block BL, a plurality of (M) vertical signal lines 28 provided for each column of pixels PX (each column of the pixel block BL) to receive signals from the corresponding column's pixels PX (pixel block BL), a constant current source 29 provided for each vertical signal line 28, a column amplifier 30, a CDS circuit (correlated double sampling circuit) 31 and an A / D converter 32 provided for each vertical signal line 28, and a horizontal readout circuit 33.

[0030] Furthermore, an analog amplifier or a so-called switched-capacitor amplifier may be used as the column amplifier 30. Also, the column amplifier 30 is not necessarily required.

[0031] For the sake of visual representation, Figure 2 shows M=2, but the number of columns M can actually be any number. Similarly, the number of rows N is not limited. When distinguishing pixel blocks BL by row, the j-th row pixel block BL is denoted by the code BL(j). This also applies to other elements and the control signals described later. Figures 2 and 3 show the n-1 to n+2 rows of pixel blocks BL(n-1) to BL(n+2) spanning four rows.

[0032] In the drawings, the lower pixels in the pixel block BL in Figures 2 and 3 are designated as PXA, and the upper pixels in Figures 2 and 3 are designated as PXB to distinguish between them. However, when explaining without distinguishing between them, both may be designated as PX. Similarly, in the drawings, the photodiode of pixel PXA is designated as PDA, and the photodiode of pixel PXB is designated as PDB to distinguish between them. However, when explaining without distinguishing between them, both may be designated as PD. Likewise, the transfer transistor of pixel PXA is designated as TXA, and the transfer transistor of pixel PXB is designated as TXB to distinguish between them. However, when explaining without distinguishing between them, both may be designated as TX. In this embodiment, the photodiodes PD of pixel PX are arranged in a two-dimensional matrix with 2N rows and M columns.

[0033] In this embodiment, each pixel PX has a photodiode PD as a photoelectric conversion unit that generates and stores a signal charge corresponding to incident light, and a transfer transistor TX as a transfer switch that transfers charge from the photodiode PD to the first node Pa.

[0034] In this embodiment, multiple pixels PX form pixel blocks BL for every two pixels PX (PXA, PXB) in which photodiodes PD are sequentially arranged in the column direction. As shown in Figures 2 and 3, for each pixel block BL, the two pixels PX (PXA, PXB) belonging to that pixel block BL share a set of first nodes Pa, amplification transistors AMP and selection transistors SEL. A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa and a reference potential, and the charge transferred to the first node Pa is converted into a voltage by this capacitance. The amplification transistor AMP constitutes an amplification unit that outputs a signal corresponding to the potential of the first node Pa. The selection transistor SEL constitutes a selection unit for selecting the pixel block BL. The photodiodes PD and transfer transistors TX are not shared by the two pixels PX (PXA, PXB), but are provided for each pixel PX. In Figures 2 and 3, n indicates a row of pixel block BL. For example, the first pixel block BL is formed by the first pixel PX(PXA) and the second pixel PX(PXB), and the second pixel block BL is formed by the third pixel PX(PXA) and the fourth pixel PX(PXB).

[0035] For example, in pixel block BL(n), the transfer transistor TXA(n) transfers charge from photodiode PDA(n) to the first node Pa(n), and the transfer transistor TXB(n) transfers charge from photodiode PDB(n) to the first node Pa(n). A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa(n) and a reference potential, and this capacitance converts the charge transferred to the first node Pa(n) into a voltage. The amplification transistor AMP(n) outputs a signal corresponding to the potential of the first node Pa(n). These points are similar for other rows of pixel block BL.

[0036] In this invention, for example, a pixel block BL may be configured for every three or more pixels PX in which photodiodes PD are sequentially arranged in the column direction.

[0037] Although not shown in the drawings, in this embodiment, multiple types of color filters, each transmitting light of a different color component, are arranged in a predetermined color arrangement (e.g., a Bayer array) on the light-incident side of the photodiode PD of each pixel PX. The pixel PX outputs an electrical signal corresponding to each color through color separation by the color filters.

[0038] The first transistor SWA(n) constitutes a first switch that electrically connects and disconnects the first node Pa(n) and the corresponding second node Pb(n). While such a first switch can be constructed by combining switches such as multiple transistors, it is preferable to construct it with a single first transistor SWA(n) as in this embodiment to simplify the structure. These points also apply to other first transistor SWAs.

[0039] Each second transistor SWB constitutes a second switch section that electrically connects and disconnects the second node Pb corresponding to the first node Pa of one pixel block BL and the second node Pb corresponding to the first node Pa of the other pixel block BL for each pair of adjacent pixel blocks BL in the column direction. In this embodiment, the first nodes Pa of three or more pixel blocks BL are connected in a daisy-chain manner by multiple second switch sections. While the second switch section described above can be constructed by combining switches such as multiple transistors, it is preferable to construct it with a single second transistor SWB as in this embodiment in order to simplify the structure.

[0040] For example, the second transistor SWB(n) is provided to electrically connect and disconnect the second node Pb(n) corresponding to the first node Pa(n) of the pixel block BL(n) in the nth row and the second node Pb(n-1) corresponding to the first node Pa(n-1) of the pixel block BL(n-1) in the (n-1) row. This is also true for other second transistors SWB.

[0041] The reset transistor RST(n) constitutes a third switch section that supplies a power supply voltage VDD as a predetermined potential to the second node Pb(n). While such a third switch section can be constructed by combining switches such as multiple transistors, it is preferable to construct it with a single reset transistor RST(n) as in this embodiment to simplify the structure. These points also apply to other reset transistors RST.

[0042] In Figures 2 and 3, VDD is the power supply potential. In this embodiment, transistors TXA, TXB, AMP, RST, SEL, SWA, and SWB are all nMOS transistors.

[0043] The gate of the transfer transistor TXA is commonly connected to control line 26 for each row, to which the control signal φTXA is supplied from the vertical scanning circuit 21. The gate of the transfer transistor TXB is commonly connected to control line 25 for each row, to which the control signal φTXB is supplied from the vertical scanning circuit 21. The gate of the reset transistor RST is commonly connected to control line 24 for each row, to which the control signal φRST is supplied from the vertical scanning circuit 21. The gate of the selection transistor SEL is commonly connected to control line 23 for each row, to which the control signal φSEL is supplied from the vertical scanning circuit 21. The gate of the first transistor SWA is commonly connected to control line 22 for each row, to which the control signal φSWA is supplied from the vertical scanning circuit 21. The gate of the second transistor SWB is commonly connected to control line 27 for each row, to which the control signal φSWB is supplied from the vertical scanning circuit 21. For example, the gate of the transfer transistor TXA(n) is supplied with the control signal φTXA(n), the gate of the transfer transistor TXB(n) is supplied with the control signal φTXB(n), the gate of the reset transistor RST(n) is supplied with the control signal φRST(n), the gate of the selection transistor SEL(n) is supplied with the control signal φSEL(n), the gate of the first transistor SWA(n) is supplied with the control signal φSWA(n), and the gate of the second transistor SWB(n) is supplied with the control signal φSWB(n).

[0044] Each transistor TXA, TXB, RST, SEL, SWA, and SWB turns on when the corresponding control signals φTXA, φTXB, φRST, φSEL, φSWA, and φSWB are at a high level (H) and turns off when they are at a low level (L).

[0045] The vertical scanning circuit 21, under the control of the imaging control unit 5 in Figure 1, outputs control signals φTXA, φTXB, φRST, φSEL, φSWA, and φSWB for each row of the pixel block BL, controlling the pixel block BL, the first transistor SWA, and the second transistor SWB to realize still image readout operations, video readout operations, etc. In this control, for example, depending on the ISO sensitivity setting, readout operations for each operation mode described later are performed. Through this control, each vertical signal line 28 is supplied with the signal (analog signal) of the pixel PX of the corresponding column.

[0046] In this embodiment, the vertical scanning circuit 21 is configured as a control unit that switches between the various operating modes described later in accordance with commands (control signals) from the imaging control unit 5 in Figure 1.

[0047] The signals read out on the vertical signal line 28 are amplified by the column amplifier 30 for each column, and then processed in the CDS circuit 31 to obtain the difference between the optical signal (a signal containing optical information converted photoelectrically by the pixel PX) and the dark signal (a difference signal containing noise components to be subtracted from the optical signal). After this, the signals are converted into digital signals by the A / D converter 32, and these digital signals are held in the A / D converter 32. The digital image signals held in each A / D converter 32 are horizontally scanned by the horizontal readout circuit 33, converted to a predetermined signal format as needed, and output to the outside (digital signal processing unit 6 in Figure 1).

[0048] The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in Figure 1. When φDARKC is at a high level (H), it samples the output signal of the column amplifier 30 as a dark signal. Simultaneously, under the control of the imaging control unit 5 in Figure 1, it receives an optical signal sampling signal φSIGC from the timing generation circuit. When φSIGC is at a high level (H), it samples the output signal of the column amplifier 30 as an optical signal. The CDS circuit 31 then outputs a signal corresponding to the difference between the sampled dark signal and the optical signal, based on the clock or pulse from the timing generation circuit. A known configuration can be used for such a CDS circuit 31.

[0049] Here, the structure of the pixel block BL will be explained with reference to Figures 4 and 5. In reality, color filters and microlenses are placed above the photodiode PD, but these are omitted in Figures 4 and 5. Note that the layout of power lines, ground lines, and control lines 22-27, etc., is omitted in Figures 4 and 5.

[0050] In this embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and each element of the pixel block BL, such as a photodiode PD, is arranged in the P-type well. In Figure 5, reference numerals 41 to 50 indicate N-type impurity diffusion regions that are part of the aforementioned transistors. Reference numerals 61 to 67 indicate the gate electrodes of each transistor made of polysilicon. The diffusion regions 42 and 50 are regions to which the power supply voltage VDD is applied by power supply lines (not shown).

[0051] The photodiodes PDA(n) and PDB(n) are embedded photodiodes consisting of an N-type charge storage layer (not shown) provided in the P-type well and a P-type depletion prevention layer (not shown) arranged on its surface. The photodiodes PDA(n) and PDB(n) convert incident light into photoelectric energy and store the resulting charge in their charge storage layer.

[0052] The transfer transistor TXA(n) is an nMOS transistor with the charge storage layer of photodiode PDA(n) as the source, the diffusion region 41 as the drain, and the gate electrode 61 as the gate. The transfer transistor TXB(n) is an nMOS transistor with the charge storage layer of photodiode PDB(n) as the source, the diffusion region 41 as the drain, and the gate electrode 62 as the gate. The diffusion region 41 is provided between photodiode PDA(n) and photodiode PDB(n). The diffusion region 41 is used as both the drain of the transfer transistor TXA(n) and the drain of the transfer transistor TXB(n). The gate electrode 61 of the transfer transistor TXA(n) is located on the photodiode PDA(n) side of the diffusion region 41. The gate electrode 62 of the transfer transistor TXB(n) is located on the photodiode PDB(n) side of the diffusion region 41.

[0053] The amplification transistor AMP(n) is an nMOS transistor with diffusion region 42 as the drain, diffusion region 43 as the source, and gate electrode 63 as the gate. The selection transistor SEL(n) is an nMOS transistor with diffusion region 43 as the drain, diffusion region 44 as the source, and gate electrode 64 as the gate. Diffusion region 44 is connected to the vertical signal line 28.

[0054] The first transistor SWA(n) is an nMOS transistor with diffusion region 45 as the source, diffusion region 46 as the drain, and gate electrode 65 as the gate. The second transistor SWB(n) is an nMOS transistor with diffusion region 47 as the drain, diffusion region 48 as the source, and gate electrode 66 as the gate. The reset transistor RST(n) is an nMOS transistor with diffusion region 49 as the source, diffusion region 50 as the drain, and gate electrode 67 as the gate.

[0055] The gate electrode 63 and diffusion regions 41 and 45 of the pixel block BL(n) are electrically connected and conductive to each other by the wiring 71(n). In this embodiment, the first node Pa(n) corresponds to the wiring 71(n) and the entire area that is electrically connected to it and conductive.

[0056] The drain diffusion region 46 of the first transistor SWA(n), the drain diffusion region 47 of the second transistor SWB(n), the source diffusion region 49 of the reset transistor RST(n), and the source diffusion region 48 of the second transistor SWB(n+1) are electrically connected and conduction between them by the wiring 72(n). The second node Pb(n) corresponds to the wiring 72(n) and the entire area that is electrically connected to it and conduction. These points are also true for the other first transistors SWA, the other second transistors SWB, and the other reset transistors RST.

[0057] The structure of pixel blocks BL other than the nth row is the same as the structure of the nth row pixel block BL(n) described above. The structure of the first transistor SWA other than the first transistor SWA(n) is the same as the structure of the first transistor SWA(n) described above. The structure of the linked transistor SWB other than the second transistor SWB(n) is the same as the structure of the linked transistor SWB(n) described above. The structure of the reset transistor RST other than the reset transistor RST(n) is the same as the structure of the reset transistor RST(n) described above.

[0058] In Figures 2 to 5, CC(n) is the capacitance between the first node Pa(n) and the reference potential when the first transistor SWA(n) is off. Let the capacitance value of CC(n) be Cfd1. CD(n) is the capacitance between the wiring 72(n) and the reference potential when the first transistor SWA(n), the second transistors SWB(n), SWB(n+1), and the reset transistor RST(n) are off. Let the capacitance value of CD(n) be Cfd2. These points are also true for the other first transistors SWA, the other second transistors SWB, and the other reset transistors RST.

[0059] Capacitance CC(n) is composed of the capacitance of the drain diffusion region 41 of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region of the first transistor SWA(n), the capacitance of the gate electrode 63 of the amplification transistor AMP(n), and the wiring capacitance of the wiring 71(n). The sum of these capacitance values ​​is the capacitance value Cfd1 of capacitance CC(n). This is the same for the other rows of pixel block BL. Note that the drain diffusion region 47 of the second transistor SWB(n) and the source diffusion region 49 of the reset transistor RST(n) are not components of capacitance CC(n), so the capacitance value Cfd1 of capacitance CC(n) is smaller accordingly.

[0060] Here, let Csw be the channel capacitance value of both the first transistor SWA and the second transistor SWB when they are ON. Typically, the capacitance value Csw is smaller than the capacitance values ​​Cfd1 and Cfd2.

[0061] Now, focusing on the pixel block BL(n), when the first transistor SWA(n) is turned off (i.e., none of the on-state transistors among each first transistor SWA and each second transistor SWB are electrically connected to the first node Pa(n)), the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential becomes capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1. This state corresponds to the state of the first node Pa(n) other than during reset in period T2 in Figure 6, which shows the first operating mode described later (the state during the period when φSWA(n) is L in period T2 in Figure 6).

[0062] Furthermore, focusing on the pixel block BL(n), when the first transistor SWA(n) is turned on, unless all the on-state transistors among the first transistors SWA and each of the second transistors SWB, except for the first transistor SWA(n), are electrically connected to the first node Pa(n) (specifically, if the second transistors SWB(n) and SWB(n+1) are off), the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential is the capacitance CC(n) plus the capacitance CD(n) and the channel capacitance of the first transistor SWA(n) when it is on. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1+Cfd2+Csw≈Cfd1+Cfd2. This state corresponds to the state during period T2 in Figure 7, which shows the second operating mode described later.

[0063] Furthermore, focusing on the pixel block BL(n), when the first transistor SWA(n) and the second transistor SWB(n+1) are turned on, unless the on-state transistors of each of the first transistor SWA and each of the second transistor SWB, other than transistors SWA(n) and SWB(n+1), are electrically connected to the first node Pa(n) (specifically, if transistors SWB(n), SWA(n+1), and SWB(n+2) are off), the charge-voltage conversion capacitance of the first node Pa(n) will be the capacitance CC(n) plus the on-state channel capacitances of capacitances CD(n), CD(n+1), and transistors SWA(n) and SWB(n+1). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1+2×Cfd2+2×Csw≈Cfd1+2×Cfd2. This state corresponds to the state during period T2 in Figure 8, which shows the operation mode of the 3A described later.

[0064] Furthermore, focusing on the pixel block BL(n), when the first transistors SWA(n), SWA(n+1) and the second transistor SWB(n+1) are turned on, unless the on-state transistors of each of the first transistors SWA and each of the second transistors SWB, other than transistors SWA(n), SWA(n+1), and SWB(n+1), are electrically connected to the first node Pa(n) (specifically, if transistors SWB(n) and SWB(n+2) are off), the charge-voltage conversion capacitance of the first node Pa(n) will be the capacitance CC(n) plus the on-state channel capacitances of the transistors SWA(n), SWA(n+1), and SWB(n+1). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is 2×Cfd1+2×Cfd2+3×Csw≈2×Cfd1+2×Cfd2. This state corresponds to the state during period T2 in Figure 9, which shows the operation mode of the third B described later.

[0065] Furthermore, focusing on the pixel block BL(n), when the first transistor SWA(n) and the second transistors SWB(n+1) and SWB(n+2) are turned on, unless the on-state transistors of each of the first transistor SWA and each of the second transistors SWB, other than transistors SWA(n), SWB(n+1), and SWB(n+2), are electrically connected to the first node Pa(n) (specifically, if transistors SWA(n+1), SWA(n+2), SWB(n), and SWB(n+3) are off), the charge-voltage conversion capacitance of the first node Pa(n) will be the capacitance CC(n) plus the capacitance CD(n), capacitance CD(n+1), capacitance CD(n+2), and the channel capacitance of transistors SWA(n), SWB(n+1), and SWB(n+2) when they are on. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1 + 3 × Cfd2 + 3 × Csw ≈ Cfd1 + 3 × Cfd2. This state corresponds to the state during period T2 in Figure 10, which shows the operating mode of the third C described later.

[0066] Thus, if there are no on-state transistors electrically connected to the first node Pa(n) among each first transistor SWA and each second transistor SWB, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes the minimum capacitance value Cfd1, and the charge-voltage conversion coefficient due to that capacitance becomes large, thus enabling reading with the best signal-to-noise ratio.

[0067] On the other hand, by increasing the number of on-state transistors electrically connected to the first node Pa(n) among each first transistor SWA and each second transistor SWB to one or more desired numbers, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) can be increased to a desired value, allowing for the handling of large signal charge amounts and thus expanding the saturation electron number. This expands the dynamic range.

[0068] The above describes the first node Pa(n) of pixel block BL(n), but the same applies to the first node Pa of other pixel blocks BL.

[0069] Figure 6 is a timing chart showing the first operating mode of the solid-state image sensor 4 shown in Figure 2. This first operating mode is an example of an operation in which each pixel block BL is selected row by row, and when there are no ON-state transistors electrically connected to the first node Pa of the selected pixel block BL (i.e., the charge-voltage conversion capacitance of the first node Pa is minimized), the transfer transistors TXA and TXB of the selected pixel block BL are sequentially turned ON, and the signals of each photodiode PDA and PDB of the selected pixel block BL are sequentially read out row by row. In the example shown in Figure 6, the signals of all pixels PXA and PXB are read out, but this is not limited to this, and for example, decimal readout, in which pixel rows are read out, may also be performed. This point is also true for the examples shown in Figures 7 to 10, which will be described later.

[0070] Figure 6 shows the process where the pixel block BL(n-1) in the (n-1)th row is selected during period T1, the pixel block BL(n) in the (n)th row is selected during period T2, and the pixel block BL(n+1) in the (n+1)th row is selected during period T3. Since the behavior is the same regardless of which row's pixel block BL is selected, only the behavior when the pixel block BL(n) in the (n)th row is selected will be explained here.

[0071] Before the start of period T2, the exposure of photodiodes PDA(n) and PDB(n) has already been completed for a predetermined exposure period. This exposure is performed by a mechanical shutter (not shown) after a so-called global reset, which simultaneously resets all pixels, during normal shooting (still image shooting), and by a so-called rolling electronic shutter operation, such as in electronic viewfinder mode or during video recording. Immediately before the start of period T2, all transistors SEL, RST, TXA, TXB, SWA, and SWB are turned off.

[0072] During period T2, the φSEL(n) of the nth row is set to H, the selection transistor SEL(n) of the pixel block BL(n) of the nth row is turned on, and the pixel block BL(n) of the nth row is selected. Also during period T2, the φRST(n) of the nth row is set to H, and the reset transistor RST(n) is turned on. However, the reset transistor RST(n) does not necessarily need to be turned on for the entire period T2; φRST(n) may be set to H only when the first node Pa(n) is reset (i.e., during the H period of φSWA(n) in Figure 6).

[0073] Immediately after the start of period T2, for a certain period (when the first node Pa(n) is reset), φSWA(n) is set to H, and the first transistor SWA(n) in the nth row is temporarily turned on. At this time, φRST(n) is set to H and the reset transistor RST(n) is turned on, so the potential of the first node Pa(n) is temporarily reset to the power supply potential VDD via the ON reset transistor RST(n) and the ON first transistor SWA(n).

[0074] Subsequently, when the first transistor SWA(n) is turned off, there are no on-state transistors electrically connected to the first node Pa(n) of the selected pixel block BL(n) from among the transistors SWA and SWB. Therefore, as mentioned above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1, which is the minimum value.

[0075] During period T2, from time t1 onwards for a certain period, the dark signal sampling signal φDARKC is set to H, and the potential appearing at the first node Pa(n) is amplified by the nth row amplification transistor AMP(n), then passes through the selection transistor SEL(n) and the vertical signal line 28, and is further amplified by the column amplifier 30. This signal is then sampled as a dark signal by the CDS circuit 31.

[0076] During period T2, from a certain point in time t2 onward, φTXA(n) is set to H, turning on the nth row transfer transistor TXA(n). As a result, the signal charge accumulated in the photodiode PDA(n) of the nth row pixel block BL(n) is transferred to the charge-voltage conversion capacitor of the first node Pa(n). The potential of the first node Pa(n), excluding noise components, is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n).

[0077] At a subsequent time point t3 during period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa(n) is amplified by the nth row amplification transistor AMP(n), then passes through the selection transistor SEL(n) and the vertical signal line 28, and is further amplified by the column amplifier 30. This signal is then sampled as an optical signal by the CDS circuit 31.

[0078] Subsequently, after φSIGC becomes low, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled over a certain period from time t1 and the optical signal sampled over a certain period from time t3. The A / D converter 32 converts this difference-corresponding signal into a digital signal and holds it. The digital image signals held by each A / D converter 32 are horizontally scanned by the horizontal readout circuit 33 and output as digital image signals to the outside (digital signal processing unit 6 in Figure 1).

[0079] Then, from time t4 during period T2, for a certain period (when the first node Pa(n) is reset), φSWA(n) is set to H, and the first transistor SWA(n) in the nth row is temporarily turned on. At this time, since φSEL(n) is set to H and the reset transistor RST(n) is turned on, the potential of the first node Pa(n) is temporarily reset to the power supply potential VDD via the ON reset transistor RST(n) and the ON first transistor SWA(n).

[0080] Subsequently, when the first transistor SWA(n) is turned off, there are no on-state transistors electrically connected to the first node Pa(n) of the selected pixel block BL(n) from among the transistors SWA and SWB. Therefore, as mentioned above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1, which is the minimum value.

[0081] During period T2, from time t5 onwards, for a certain period, the dark signal sampling signal φDARKC is set to H, and the potential appearing at the first node Pa(n) is amplified by the nth row amplification transistor AMP(n), then passes through the selection transistor SEL(n) and the vertical signal line 28, and is further amplified by the column amplifier 30. This signal is then sampled as a dark signal by the CDS circuit 31.

[0082] During period T2, from time t6 onwards, for a certain period, φTXB(n) is set to H, turning on the nth row transfer transistor TXB(n). As a result, the signal charge accumulated in the photodiode PDB(n) of the nth row pixel block BL(n) is transferred to the charge-voltage conversion capacitor of the first node Pa(n). The potential of the first node Pa(n), excluding noise components, is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n).

[0083] At time point t7 during period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa(n) is amplified by the nth row amplification transistor AMP(n), then passes through the selection transistor SEL(n) and the vertical signal line 28, and is further amplified by the column amplifier 30. This signal is then sampled as an optical signal by the CDS circuit 31.

[0084] Subsequently, after φSIGC becomes low, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled over a certain period from time t5 and the optical signal sampled over a certain period from time t7. The A / D converter 32 converts this difference-corresponding signal into a digital signal and holds it. The digital image signals held by each A / D converter 32 are horizontally scanned by the horizontal readout circuit 33 and output as digital image signals to the outside (digital signal processing unit 6 in Figure 1).

[0085] Thus, in the first operating mode, since there are no ON-state transistors electrically connected to the first node Pa of the selected pixel block BL from among the transistors SWA and SWB, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL is minimized, and the charge-voltage conversion coefficient due to that capacitance becomes larger, enabling readout with the best signal-to-noise ratio. For example, when the ISO sensitivity setting is at its highest value, the imaging control unit 5 is commanded to perform the first operating mode.

[0086] Figure 7 is a timing chart showing the second operating mode of the solid-state image sensor 4 shown in Figure 2. This second operating mode is an example of an operation in which each pixel block BL is selected row by row, and with one of the first transistors SWA and second transistors SWB in the ON state, transistor SWA is electrically connected to the first node Pa of the selected pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are sequentially turned ON, and the signals of each photodiode PDA and PDB of the selected pixel block BL are sequentially read out row by row.

[0087] Figure 7, like Figure 6, shows a situation where the pixel block BL(n-1) in the (n-1)th row is selected during period T1, the pixel block BL(n) in the (n)th row is selected during period T2, and the pixel block BL(n+1) in the (n+1)th row is selected during period T3. The differences between the second operating mode shown in Figure 7 and the first operating mode shown in Figure 6 are explained below.

[0088] In the second operating mode shown in Figure 7, during the period T2 in which the nth row pixel block BL(n) is selected, φSWA(n) is set to H, while φSWB(n) and φSWB(n+1) are set to L, turning on the first transistor SWA(n) and turning off the second transistors SWB(n) and φSWB(n+1). As a result, during period T2, the first transistor SW (in this case, the first transistor SWA(n)) which is in the ON state of one of the transistors SWA and SWB, is electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as mentioned above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1+Cfd2+Csw≈Cfd1+Cfd2, which is, so to speak, one step larger than in the first operating mode shown in Figure 6.

[0089] In the second operating mode shown in Figure 7, φSWA(n) is set to H and the first transistor SWA(n) is turned on, while φRST(n) is set to H and the reset transistor RST(n) is turned on only when the first node Pa(n) is reset (for a certain period immediately after the start of period T2 and for a certain period from time t4 during period T2). This ensures that the potential of the first node Pa(n) is properly reset.

[0090] Here, we have described the period T2 during which the pixel block BL(n) in the nth row is selected, but the same applies to the periods during which other pixel blocks BL are selected.

[0091] Thus, in the second operating mode, the first transistor SWA, which is in the ON state of one of the transistors SWA, SWB, is electrically connected to the first node Pa of the selected pixel block BL. As a result, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by one step, and the saturation electron number at the charge-voltage conversion capacitance of the first node Pa can be expanded by one step. This expands the dynamic range by one step. For example, when the ISO sensitivity setting is one step lower than the highest value, the imaging control unit 5 is commanded to perform the second operating mode.

[0092] Figure 8 is a timing chart showing the operation mode 3A of the solid-state image sensor 4 shown in Figure 2. Operation mode 3A is one of the third operation modes. This third operation mode is an example of an operation in which each pixel block BL is selected row by row, the first transistor SWA which electrically connects and disconnects the first node Pa of the selected pixel block BL and its corresponding second node Pb is turned on, the second transistor SWB which is electrically connected to the second node Pb corresponding to the first node Pa of the selected pixel block BL is turned on, and the reset transistor RST which supplies the power supply potential VDD to the second node Pb corresponding to the first node Pa of the selected pixel block BL is turned on only when the first node Pa of the selected pixel block BL is reset, and the transfer transistors TXA and TXB of the selected pixel block BL are sequentially turned on, and the signals of each photodiode PDA and PDB of the selected pixel block BL are sequentially read row by row. The third operating mode A is an example of operation in which, in the third operating mode, one first transistor SWA and one second transistor SWB are electrically connected to the first node Pa of the selected pixel block BL, with the transistor SWA in the ON state.

[0093] Figure 8, like Figure 6, shows a situation in which the pixel block BL(n-1) in the (n-1)th row is selected during period T1, the pixel block BL(n) in the (n)th row is selected during period T2, and the pixel block BL(n+1) in the (n+1)th row is selected during period T3. The differences between the operation mode 3A shown in Figure 8 and the first operation mode shown in Figure 6 are explained below.

[0094] In the third operating mode A shown in Figure 8, during the period T2 in which the nth row pixel block BL(n) is selected, φSWA(n) and φSWB(n+1) are set to H, while φSWA(n+1), φSWB(n), and φSWB(n+2) are set to L. The first transistor SWA(n) and the second transistor SWB(n+1) are turned on, while the first transistor SWA(n+1) and the second transistors SWB(n) and SWB(n+2) are turned off. As a result, during the period T2, the first transistor SWA (here, the first transistor SWA(n)) and the second transistor SWB (here, the second transistor SWB(n+1)) which are both in the ON state are electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as mentioned above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1 + Cfd2 + Csw ≈ Cfd1 + Cfd2, which is, so to speak, two steps larger than the first operating mode shown in Figure 6.

[0095] In the third operating mode A shown in Figure 8, φSWA(n) is set to H and the first transistor SWA(n) is turned on, while φRST(n) is set to H and the reset transistor RST(n) is turned on only when the first node Pa(n) is reset (for a certain period immediately after the start of period T2 and for a certain period from time t4 during period T2). This ensures that the potential of the first node Pa(n) is properly reset. This also applies to the third operating mode B shown in Figure 9 and the third operating mode C shown in Figure 10, which will be described later.

[0096] Here, we have described the period T2 during which the pixel block BL(n) in the nth row is selected, but the same applies to the periods during which other pixel blocks BL are selected.

[0097] Thus, in the third operating mode, one of the transistors SWA and SWB, the first transistor SWA, is in the ON state, and the second transistor SWB, also in the ON state, is electrically connected to the first node Pa of the selected pixel block BL. As a result, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by two steps, and the saturation electron number at the charge-voltage conversion capacitance of the first node Pa can be increased by two steps. This allows the dynamic range to be increased by two steps. For example, when the ISO sensitivity setting is two steps lower than the highest value, the imaging control unit 5 is commanded to perform the third operating mode A.

[0098] Figure 9 is a timing chart showing the operation mode 3B of the solid-state image sensor 4 shown in Figure 2. This operation mode 3B is an example of the operation in the third operation mode in which two first transistors SWA and one second transistor SWB, both in the ON state, are electrically connected to the first node Pa of the selected pixel block BL.

[0099] Figure 9, like Figure 4, shows a situation where the pixel block BL(n-1) in the (n-1)th row is selected in period T1, the pixel block BL(n) in the (n)th row is selected in period T2, and the pixel block BL(n+1) in the (n+1)th row is selected in period T3. The differences between the third operation mode shown in Figure 9 and the first operation mode shown in Figure 4 are explained below.

[0100] In the third operating mode shown in Figure 9, during the period T2 in which the nth row pixel block BL(n) is selected, φSWA(n), φSWA(n+1) and φSWB(n+1) are set to H, while φSWB(n) and φSWB(n+2) are set to L. This turns on the first transistor SWA(n), SWA(n+1) and the second transistor SWB(n+1), while turning off the second transistor SWB(n) and SWB(n+2). As a result, during the period T2, the first transistor SWA (here, the first transistor SWA(n), SWA(n+1)) with two on-state transistors and the second transistor SWB (here, the second transistor SWB(n+1)) with one on-state transistor are electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as mentioned above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is 2×Cfd1+2×Cfd2+3×Csw≈2×Cfd1+2×Cfd2, which is, so to speak, three steps larger than the first operating mode shown in Figure 6.

[0101] Here, we have described the period T2 during which the pixel block BL(n) in the nth row is selected, but the same applies to the periods during which other pixel blocks BL are selected.

[0102] Thus, in the third operating mode, the first transistor SWA, with two transistors in the ON state, and the second transistor SWB, with one transistor in the ON state, are electrically connected to the first node Pa of the selected pixel block BL. As a result, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by three steps, and the saturation electron number at the charge-voltage conversion capacitance of the first node Pa can be expanded by three steps. This expands the dynamic range by three steps. For example, when the ISO sensitivity setting is three steps lower than the highest value, the imaging control unit 5 is commanded to perform the third operating mode.

[0103] Figure 10 is a timing chart showing the operation mode of the third C of the solid-state image sensor 4 shown in Figure 2. This third C operation mode is an example of an operation in which each pixel block BL is sequentially selected row by row, and with one of the first transistors SWA and two of the second transistors SWB electrically connected to the first node Pa of the selected pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are sequentially turned on, and the signals of each photodiode PDA and PDB of the selected pixel block BL are sequentially read out row by row.

[0104] Figure 10, like Figure 6, shows a situation in which the pixel block BL(n-1) in the (n-1)th row is selected during period T1, the pixel block BL(n) in the (n)th row is selected during period T2, and the pixel block BL(n+1) in the (n+1)th row is selected during period T3. The differences between the third operation mode shown in Figure 10 and the first operation mode shown in Figure 4 are explained below.

[0105] In the third C operating mode shown in Figure 10, during the period T2 in which the nth row pixel block BL(n) is selected, φSWA(n) and φSWB(n+1), φSWB(n+2) are set to H, while φSWA(n+1), φSWA(n+2), φSWB(n), φSWB(n+3) are set to L, the first transistor SWA(n) and the second transistors SWB(n+1), SWB(n+2) are turned on, while the first transistors SWA(n+1), SWA(n+2) and the second transistors SWB(n), SWB(n+3) are turned off. As a result, during period T2, one of the transistors SWA and SWB, the first transistor SWA (here, the first transistor SWA(n)), and the two on-state second transistors SWB (here, the second transistors SWB(n+1), SWB(n+2)), are electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as mentioned above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1+3×Cfd2+3×Csw≈Cfd1+3×Cfd2, which is, so to speak, three steps larger than the first operating mode shown in Figure 4.

[0106] Here, we have described the period T2 during which the pixel block BL(n) in the nth row is selected, but the same applies to the periods during which other pixel blocks BL are selected.

[0107] Thus, in the third operating mode, the first transistor SWA, with one transistor SWA and SWB in the ON state, and the second transistor SWB, with both transistors in the ON state, are electrically connected to the first node Pa of the selected pixel block BL. As a result, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by three steps, and the saturation electron number at the charge-voltage conversion capacitance of the first node Pa can be expanded by three steps. This expands the dynamic range by three steps. For example, when the ISO sensitivity setting is three steps lower than the highest value, the imaging control unit 5 is commanded to perform the second operating mode.

[0108] Here, a comparative solid-state image sensor to be compared with the solid-state image sensor 4 in this embodiment will be described. Figure 11 is a circuit diagram showing the vicinity of the three pixel blocks BL of this comparative solid-state image sensor, and corresponds to Figure 3. Figure 12 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in Figure 11, and corresponds to Figures 4 and 5. In Figures 11 and 12, elements that are the same as or corresponding to the elements in Figures 3, 4 and 5 are denoted by the same reference numerals, and redundant explanations are omitted. Note that in Figure 12, the diffusion region and gate electrode are not denoted by reference numerals, but their reference numerals are the same as in Figure 5, so please refer to Figure 5 as needed.

[0109] The differences between this comparative example and this embodiment are described below. In this comparative example, the first and second transistors SWA, SWB and wirings 71, 72 are removed, and instead, a first connected transistor SWa, a second connected transistor SWb and wirings 97, 98 are provided. Also, in this comparative example, a node P corresponding to the first node Pa exists, but a node corresponding to the second node Pb does not exist. Furthermore, in this embodiment, the source of the reset transistor RST is connected to the second node Pb and not to the first node Pa, whereas in this comparative example, the source of the reset transistor RST is connected to node P.

[0110] In this comparative example, for each pair of pixel blocks BL adjacent to each other in the column direction, a first connected transistor SWa and a second connected transistor SWb are provided in series between the node P of one pixel block BL and the node P of the other pixel block BL. For example, a first connected transistor SWa(n) and a second connected transistor SWb(n) are provided in series between node P(n) of the pixel block BL(n) in row n and node P(n+1) of the pixel block BL in row n+1.

[0111] In this comparative example, the gate electrode of the amplification transistor AMP(n) of pixel block BL(n), the drain diffusion regions of the transfer transistors TXA(n) and TXB(n), the source diffusion region of the first linked transistor SWa(n), the drain diffusion region of the second linked transistor SWb(n-1), and the source diffusion region of the reset transistor RST(n) are electrically connected and conduction is maintained by wiring 97(n). Node P(n) corresponds to wiring 97(n) and the entire area electrically connected to it and conducting. This is also true for the other pixel blocks BL.

[0112] In this comparative example, the two connected transistors SWa and SWb, which are arranged in series between each pair of nodes P, are connected by wiring 98. For example, the drain diffusion region of the first connected transistor SWa(n) and the source diffusion region of the second connected transistor SWb(n) are electrically connected by wiring 98(n).

[0113] In Figures 11 and 12, CA(n) is the capacitance between node P(n) and the reference potential when the connected transistors SWa(n) and SWb(n-1) are off. Let Cfd1' be the capacitance value of capacitance CA(n). CB(n) indicates the capacitance between wiring 72(n) and the reference potential when the connected transistors SWa(n) and SWb(n) are off. These points are similar for the other rows of pixel block BL.

[0114] Capacitance CA(n) is composed of the capacitances of the drain diffusion regions of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region of the reset transistor RST(n), the capacitance of the source diffusion region of the first linked transistor SWa(n), the capacitance of the drain diffusion region of the second linked transistor SWb(n-1), the capacitance of the gate electrode of the amplification transistor AMP(n), and the wiring capacitance of wiring 97(n). The sum of these capacitance values ​​is the capacitance value Cfd1' of capacitance CA(n). This is also true for the other rows of pixel block BL.

[0115] In contrast, the capacitance CC(n) in this embodiment, as described above, is composed of the capacitance of the drain diffusion region 41 of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region of the first transistor SWA(n), the capacitance of the gate electrode of the amplification transistor AMP(n), and the wiring capacitance of the wiring 71(n), and the sum of these capacitance values ​​is the capacitance value Cfd1 of the capacitance CC(n).

[0116] Therefore, the capacitance value Cfd1 of capacitance CC(n) in this embodiment is smaller than the capacitance value Cfd1' of capacitance CA(n) in this comparative example by the amount of the capacitance of the drain diffusion region of the second connected transistor SWb(n-1) and the capacitance of the source diffusion region of the reset transistor RST(n) (i.e., by the amount of two transistor diffusion capacitances).

[0117] In this comparative example, focusing on pixel block BL(n), when both connected transistors SWa(n) and SWb(n-1) are turned off, the capacitance (charge-voltage conversion capacitance) between node P(n) and the reference potential becomes capacitance CA(n). The capacitance value of node P(n) becomes the minimum Cfd1', and the charge-voltage conversion coefficient due to this capacitance becomes large, enabling readout with the best signal-to-noise ratio. Furthermore, in this comparative example, by increasing the number of ON-state connected transistors electrically connected to node P(n) among each connected transistor SWa and SWb to one or more desired numbers, the capacitance value of node P(n) can be increased to a desired value, allowing for the handling of large signal charge amounts and thus expanding the saturation electron number. This expands the dynamic range.

[0118] As mentioned above, the minimum capacitance value Cfd1 of the charge-voltage conversion capacitance of the first node Pa(n) in this embodiment is two transistor diffusion capacitances smaller than the minimum capacitance value Cfd1' of the charge-voltage conversion capacitance of node P(n) in this comparative example. Therefore, according to this embodiment, the charge-voltage conversion coefficient becomes even larger compared to this comparative example, and a higher signal-to-noise ratio (SNR) can be read out.

[0119] In this embodiment, a second transistor SWB is provided between every two adjacent second nodes Pb in the column direction, but the present invention is not necessarily limited to this. For example, a second transistor SWB may not be provided between r (where r is an integer of 2 or more) second nodes Pb arranged in the column direction and the second node Pb adjacent to that second node Pb on the lower side in the figure, and the connection between them may always be left open. In this case, the smaller the number of r, the smaller the maximum number of the predetermined number in the second operating mode, and the degree of dynamic range expansion decreases, but the signal-to-noise ratio during high-sensitivity readout can be improved compared to the comparative example. Also, for example, a second transistor SWB may not be provided between s (where s is an integer of 1 or more) second nodes Pb arranged in the column direction and the second node Pb adjacent to that second node Pb on the lower side in the figure, and the connection between them may be electrically short-circuited. Furthermore, for example, a second transistor SWB may be provided only between a second node Pb that is spaced u times (where u is an integer greater than or equal to 1) in the column direction and the second node Pb that is adjacent to that second node Pb on the lower side in the figure, while the second node Pb that is not spaced u times in the column direction and the second node Pb that is adjacent to that second node Pb on the lower side in the figure may be electrically short-circuited.

[0120] In this embodiment, by providing an adjustment capacitor in the wiring 72, the capacitance value of capacitance CD may be set to a value within ±20% of the capacitance value of capacitance CC, or to a value within ±10% of the capacitance value of capacitance CC. These points also apply to the second embodiment described later.

[0121] The operation examples shown in Figures 6 to 10 were examples of operations in which the signal charge of the photodiode PD of each pixel PX is read out without mixing it with the signal charge of the photodiode PD of other pixels PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be read out mixed with the signal charge of the photodiode PD of other pixels PX of the same color.

[0122] For example, by turning on the first transistors SWA(n-1), SWA(n), SWA(n+1) and the second transistors SWB(n), SWB(n+1) to connect the first nodes Pa(n-1), Pa(n), Pa(n+1) to each other, and simultaneously turning on TXA(n-1), TXA(n), TXA(n+1), the signal charges of the photodiodes PDA(n-1), PDA(n), PDA(n-1) of the three pixels PXA(n-1), PXA(n), PXA(n-1) of the same color, assuming a Bayer array, are averaged at the first nodes Pa(n-1), Pa(n), Pa(n+1) to which they are connected, thereby realizing the function of mixed readout of three pixels of the same color. In this case, by turning off the second transistors SWB(n-2) and SWB(n+2) and minimizing the number of ON-state first or second transistors electrically connected to the first nodes Pa(n-1), Pa(n), and Pa(n+1), the charge-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), and Pa(n+1) is minimized, enabling the best signal-to-noise ratio for mixed readout of three pixels of the same color. On the other hand, if, in addition to the first transistors SWA(n-1), SWA(n), SWA(n+1) and the second transistors SWB(n), SWB(n+1), one or more on-state transistors from each of the first transistors SWA and each of the second transistors SWB are electrically connected to the first nodes Pa(n-1), Pa(n), Pa(n+1), the charge-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), Pa(n+1) will increase in proportion to the number of such connections, thereby expanding the dynamic range of the same-color three-pixel mixed readout.

[0123] [Second Embodiment] Figure 13 is a circuit diagram showing the schematic configuration of a solid-state image sensor 84 of an electronic camera according to a second embodiment of the present invention, and corresponds to Figure 2. In Figure 13, elements that are the same as or corresponding to elements in Figure 2 are denoted by the same reference numerals, and redundant explanations are omitted.

[0124] The difference between this embodiment and the first embodiment is that, in this embodiment, the photodiode PDB and transfer transistor TXB are removed in each pixel block BL compared to the first embodiment, and each pixel block BL becomes a pixel PXA. However, in this embodiment, the column density of the photodiode PDA is twice that of the first embodiment and is the same as the column density of the entire photodiode PDA and PDB in the fourth embodiment. In this embodiment, n represents both a row of pixel block BL and a row of pixel PXA.

[0125] In other words, in the first embodiment, each pixel block BL is composed of two pixels PX (PXA, PXB), whereas in this embodiment, each pixel block BL is composed of one pixel PX (PXA). Furthermore, in the first embodiment, the two pixels PX (PXA, PXB) belonging to the pixel block BL share one set of first nodes Pa, amplification transistor AMP, reset transistor RST, and selection transistor SEL, whereas in this embodiment, each pixel PX (PXA only in this embodiment) has its own set of first nodes Pa, amplification transistor AMP, reset transistor RST, and selection transistor SEL.

[0126] Basically, the description of the first embodiment above can be adapted to describe this embodiment by replacing the pixel block BL with the pixel PXA. Therefore, a detailed description of this embodiment is omitted here.

[0127] This embodiment also provides the same advantages as the first embodiment.

[0128] Although various embodiments and variations of the present invention have been described above, the present invention is not limited thereto. [Explanation of Symbols]

[0129] 4. Solid-state image sensor BL Pixel Block PX pixels PD photodiode TXA, TXB transfer transistors Pa 1st node Pb Second Node AMP (amplifying transistor) SWA First Transistor SWB Second Transistor RST Reset Transistor (Third Transistor)

Claims

1. A first photoelectric conversion unit that converts light into electric charge, A second photoelectric conversion unit that converts light into electric charge, A first transfer transistor that transfers the charge converted by the first photoelectric conversion unit, A second transfer transistor that transfers the charge converted in the second photoelectric conversion unit, A first diffusion unit where the charge transferred from the first photoelectric conversion unit by the first transfer transistor and the charge transferred from the second photoelectric conversion unit by the second transfer transistor are stored, A first transistor electrically connected to the first diffusion section, A first reset transistor is electrically connected to a first supply unit to which a predetermined voltage is supplied, A first amplification transistor having a gate portion electrically connected to the first diffusion portion and Equipped with, The gate portion of the first transfer transistor and the gate portion of the second transfer transistor are arranged such that the direction in which the charge converted in the first photoelectric conversion unit is transferred from the first photoelectric conversion unit to the first diffusion unit is different from the direction in which the charge converted in the second photoelectric conversion unit is transferred from the second photoelectric conversion unit to the first diffusion unit. The first transistor and the first reset transistor are connected in series by a first connection path that electrically connects the first diffusion unit and the first supply unit. The gate portion of the first amplification transistor is positioned further away from the first diffusion portion than the gate portion of the first transistor. Image sensor.

2. In the image sensor according to claim 1, The gate width of the first transistor is smaller than the gate width of the first amplification transistor. stomach, Image sensor.

3. In the image sensor according to claim 1 or claim 2, The gate length of the first transistor is smaller than the gate length of the first amplification transistor. Image sensor.

4. In the image sensor according to any one of claims 1 to 3, An image sensor comprising a first selection transistor electrically connected to the first amplification transistor.

5. In the image sensor according to claim 4, The gate width of the first amplification transistor is greater than the gate width of the first selection transistor. Image sensor.

6. In the image sensor according to claim 4 or claim 5, The gate length of the first amplification transistor is greater than the gate length of the first selection transistor. Image sensor.

7. In the image sensor according to any one of claims 4 to 6, The first amplification transistor is formed using at least a portion of the diffusion portion that forms the first selection transistor. Image sensor.

8. In the image sensor according to any one of claims 4 to 7, The first amplification transistor and the first selection transistor are formed by sharing at least a portion of one diffusion section, Image sensor.

9. In the image sensor according to any one of claims 4 to 8, Either the drain portion of the first amplification transistor or the source portion of the first amplification transistor is formed using at least a portion of the diffusion portion that forms either the drain portion of the first selection transistor or the source portion of the first selection transistor. Image sensor.

10. In the image sensor according to any one of claims 4 to 9, Either the drain portion of the first amplification transistor or the source portion of the first amplification transistor forms either the drain portion of the first selection transistor or the source portion of the first selection transistor. Image sensor.

11. In the image sensor according to any one of claims 1 to 10, The gate portion of the first transfer transistor and the gate portion of the second transfer transistor are arranged such that the direction in which the charge converted in the first photoelectric conversion unit is transferred from the first photoelectric conversion unit to the first diffusion unit is opposite to the direction in which the charge converted in the second photoelectric conversion unit is transferred from the second photoelectric conversion unit to the first diffusion unit. Image sensor.

12. In the image sensor according to any one of claims 1 to 11, The gate portion of the first reset transistor is positioned in the first connection path at a location further away from the first diffusion portion than the gate portion of the first transistor. Image sensor.

13. In the image sensor according to any one of claims 1 to 12, The gate portion of the first transistor and the gate portion of the first reset transistor are arranged in the first connection path such that they move away from the first diffusion portion in the order of the gate portion of the first transistor and the gate portion of the first reset transistor. Image sensor.

14. In the image sensor according to any one of claims 1 to 13, The gate width of the first transistor is smaller than the gate width of the first transfer transistor. Image sensor.

15. In the image sensor according to claim 14, The gate width of the first reset transistor is smaller than the gate width of the first transfer transistor. Image sensor.

16. In the image sensor according to any one of claims 1 to 13, The gate width of the first reset transistor is smaller than the gate width of the first transfer transistor. Image sensor.

17. In the image sensor according to any one of claims 1 to 16, The first diffusion unit and the first transistor are electrically connected via wiring. Image sensor.

18. In the image sensor according to any one of claims 1 to 17, The first transistor and the first reset transistor are electrically connected via wiring. Image sensor.

19. In the image sensor according to any one of claims 1 to 18, The second photoelectric conversion unit is located next to the first photoelectric conversion unit. Image sensor.

20. In the image sensor according to claim 19, The second photoelectric conversion unit is arranged next to the first photoelectric conversion unit in the row direction. Image sensor.

21. In the image sensor according to any one of claims 1 to 20, The first diffusion unit accumulates charge transferred from three or more photoelectric conversion units, including the first photoelectric conversion unit and the second photoelectric conversion unit. Image sensor.

22. In the image sensor according to any one of claims 1 to 21, The first connection path is configured to include three or more transistors, including the first transistor and the first reset transistor. Image sensor.

23. In the image sensor according to claim 22, The three or more transistors arranged in the first connection path are connected in series. Image sensor.

24. In the image sensor according to any one of claims 1 to 23, An image sensor comprising a control unit that controls the timing such that a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor are different timings.

25. In the image sensor according to claim 24, The control unit controls the first transistor to turn off at the first timing. Image sensor.

26. In the image sensor according to claim 24 or claim 25, The control unit controls the first transistor to turn off at the second timing. Image sensor.

27. In the image sensor according to claim 24, The control unit controls the first transistor to turn on at the first timing. Image sensor.

28. In the image sensor according to claim 24 or claim 25, The control unit controls the first transistor to turn on at the second timing. Image sensor.

29. In the image sensor according to any one of claims 1 to 23, A third photoelectric conversion unit that converts light into electric charge, A third transfer transistor that transfers the charge converted in the third photoelectric conversion unit, A second diffusion unit where the charge transferred from the third photoelectric conversion unit by the third transfer transistor is accumulated, The second transistor is electrically connected to the second diffusion section and Equipped with, The first transistor and the second transistor are connected in series by a second connection path that electrically connects the first diffusion section and the second diffusion section. Image sensor.

30. In the image sensor according to claim 29, The first transistor and the second transistor are arranged in the second connection path such that the length from the first diffusion portion to the first transistor is shorter than the length from the first transistor to the second transistor. Image sensor.

31. In the image sensor according to claim 30, The first transistor and the second transistor are arranged in the second connection path such that the length from the first diffusion portion to the gate portion of the first transistor is shorter than the length from the gate portion of the first transistor to the gate portion of the second transistor. Image sensor.

32. In the image sensor according to any one of claims 29 to 31, The first transistor and the second transistor are arranged in the second connection path such that the length from the second diffusion portion to the second transistor is shorter than the length from the second transistor to the first transistor. Image sensor.

33. In the image sensor according to claim 32, The first transistor and the second transistor are arranged in the second connection path such that the length from the second diffusion portion to the gate portion of the second transistor is shorter than the length from the gate portion of the second transistor to the gate portion of the first transistor. Image sensor.

34. In the image sensor according to any one of claims 29 to 33, The first transistor and the second transistor are electrically connected via wiring. Image sensor.

35. In the image sensor according to any one of claims 29 to 34, The second connection path is arranged to have three or more transistors, including the first transistor and the second transistor. Image sensor.

36. In the image sensor according to claim 35, The three or more transistors arranged in the second connection path are connected in series. Image sensor.

37. In the image sensor according to any one of claims 29 to 36, It includes a second reset transistor that is electrically connected to a second supply unit to which a predetermined voltage is supplied, The second transistor and the second reset transistor are connected in series by a third connection path that electrically connects the second diffusion unit and the second supply unit. Image sensor.

38. In the image sensor according to any one of claims 29 to 37, The third photoelectric conversion unit is positioned next to either the first photoelectric conversion unit or the second photoelectric conversion unit. Image sensor.

39. In the image sensor according to claim 38, The third photoelectric conversion unit is positioned in the row direction next to either the first photoelectric conversion unit or the second photoelectric conversion unit. Image sensor.

40. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor to be different timings. The control unit controls the first transistor and the second transistor to be turned off at the first timing, and controls the first transistor and the second transistor to be turned off at the second timing. Image sensor.

41. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor to be different timings. The control unit controls the first transistor to be ON and the second transistor to be OFF at the first timing, and controls the first transistor to be OFF and the second transistor to be ON at the second timing. Image sensor.

42. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor to be different timings. The control unit controls the first transistor to be ON and the second transistor to be ON at the first timing, and controls the first transistor to be ON and the second transistor to be ON at the second timing. Image sensor.

43. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of the transfer of charge from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and the timing of the transfer of charge from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor to a first timing that is different from the timing of the transfer of charge from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor. The control unit controls the first transistor and the second transistor to be turned off at the first timing, and controls the first transistor and the second transistor to be turned off at the second timing. Image sensor.

44. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of the transfer of charge from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and the timing of the transfer of charge from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor to a first timing that is different from the timing of the transfer of charge from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor. The control unit controls the first transistor to be ON and the second transistor to be OFF at the first timing, and controls the first transistor to be OFF and the second transistor to be ON at the second timing. Image sensor.

45. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of the transfer of charge from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and the timing of the transfer of charge from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor to a first timing that is different from the timing of the transfer of charge from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor. The control unit controls the first transistor to be ON and the second transistor to be ON at the first timing, and controls the first transistor to be ON and the second transistor to be ON at the second timing. Image sensor.

46. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor to be different timings. The control unit executes either a first mode in which it controls the first transistor to be turned off at the first timing and the second transistor to be turned off at the second timing, or a second mode in which it controls the first transistor to be turned on and the second transistor to be turned off at the first timing and the first transistor to be turned off and the second transistor to be turned on at the second timing. Image sensor.

47. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor to be different timings. The control unit executes either a first mode in which, at the first timing, the first transistor is turned off and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned off; or a second mode in which, at the first timing, the first transistor is turned on and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned on. Image sensor.

48. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor to be different timings. The control unit executes either a first mode in which it controls the first transistor to be turned off at the first timing and the second transistor to be turned off at the second timing, or a second mode in which it controls the first transistor to be turned on and the second transistor to be turned on at the first timing and the first transistor to be turned on and the second transistor to be turned on at the second timing. Image sensor.

49. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor to be different timings. The control unit executes either a first mode in which, at the first timing, the first transistor is turned off and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned off; or a second mode in which, at the first timing, the first transistor is turned on and the second transistor is turned on, and at the second timing, the first transistor is turned on and the second transistor is turned on. Image sensor.

50. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor to be different timings. The control unit executes either a first mode in which, at the first timing, the first transistor is turned on and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned on; or a second mode in which, at the first timing, the first transistor is turned on and the second transistor is turned on, and at the second timing, the first transistor is turned on and the second transistor is turned on. Image sensor.

51. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor to be different timings. The control unit executes one of the following modes: a first mode in which the first transistor is controlled to be turned off at the first timing and the second transistor is controlled to be turned off at the second timing; a second mode in which the first transistor is controlled to be turned on and the second transistor is turned off at the first timing and the first transistor is turned off and the second transistor is turned on at the second timing; and a third mode in which the first transistor is controlled to be turned on and the second transistor is turned on at the first timing and the first transistor is turned on and the second transistor is turned on at the second timing. Image sensor.

52. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of a first timing in which charge is transferred from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and a second timing in which charge is transferred from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor to be different timings. The control unit executes one of the following modes: a first mode in which, at the first timing, the first transistor is turned off and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned off; a second mode in which, at the first timing, the first transistor is turned on and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned on; and a third mode in which, at the first timing, the first transistor is turned on and the second transistor is turned on, and at the second timing, the first transistor is turned on and the second transistor is turned on. Image sensor.

53. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of the transfer of charge from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and the timing of the transfer of charge from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor to a first timing that is different from the timing of the transfer of charge from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor. The control unit executes either a first mode in which it controls the first transistor to be turned off at the first timing and the second transistor to be turned off at the second timing, or a second mode in which it controls the first transistor to be turned on and the second transistor to be turned off at the first timing and the first transistor to be turned off and the second transistor to be turned on at the second timing. Image sensor.

54. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of the transfer of charge from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and the timing of the transfer of charge from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor to a first timing that is different from the timing of the transfer of charge from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor. The control unit executes either a first mode in which, at the first timing, the first transistor is turned off and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned off; or a second mode in which, at the first timing, the first transistor is turned on and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned on. Image sensor.

55. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of the transfer of charge from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and the timing of the transfer of charge from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor to a first timing that is different from the timing of the transfer of charge from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor. The control unit executes either a first mode in which it controls the first transistor to be turned off at the first timing and the second transistor to be turned off at the second timing, or a second mode in which it controls the first transistor to be turned on and the second transistor to be turned on at the first timing and the first transistor to be turned on and the second transistor to be turned on at the second timing. Image sensor.

56. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of the transfer of charge from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and the timing of the transfer of charge from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor to a first timing that is different from the timing of the transfer of charge from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor. The control unit executes either a first mode in which, at the first timing, the first transistor is turned off and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned off; or a second mode in which, at the first timing, the first transistor is turned on and the second transistor is turned on, and at the second timing, the first transistor is turned on and the second transistor is turned on. Image sensor.

57. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of the transfer of charge from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and the timing of the transfer of charge from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor to a first timing that is different from the timing of the transfer of charge from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor. The control unit executes either a first mode in which, at the first timing, the first transistor is turned on and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned on; or a second mode in which, at the first timing, the first transistor is turned on and the second transistor is turned on, and at the second timing, the first transistor is turned on and the second transistor is turned on. Image sensor.

58. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of the transfer of charge from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and the timing of the transfer of charge from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor to a first timing that is different from the timing of the transfer of charge from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor. The control unit executes one of the following modes: a first mode in which the first transistor is controlled to be turned off at the first timing and the second transistor is controlled to be turned off at the second timing; a second mode in which the first transistor is controlled to be turned on and the second transistor is turned off at the first timing and the first transistor is turned off and the second transistor is turned on at the second timing; and a third mode in which the first transistor is controlled to be turned on and the second transistor is turned on at the first timing and the first transistor is turned on and the second transistor is turned on at the second timing. Image sensor.

59. In the image sensor according to any one of claims 29 to 39, The device includes a control unit that controls the timing of the transfer of charge from the first photoelectric conversion unit to the first diffusion unit by the first transfer transistor and the timing of the transfer of charge from the second photoelectric conversion unit to the first diffusion unit by the second transfer transistor to a first timing that is different from the timing of the transfer of charge from the third photoelectric conversion unit to the second diffusion unit by the third transfer transistor. The control unit executes one of the following modes: a first mode in which, at the first timing, the first transistor is turned off and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned off; a second mode in which, at the first timing, the first transistor is turned on and the second transistor is turned off, and at the second timing, the first transistor is turned off and the second transistor is turned on; and a third mode in which, at the first timing, the first transistor is turned on and the second transistor is turned on, and at the second timing, the first transistor is turned on and the second transistor is turned on. Image sensor.

60. An imaging device comprising an image sensor according to any one of claims 1 to 59.

61. In the imaging device according to claim 60, An imaging device comprising an imaging control unit that controls the image sensor.

62. In the imaging device according to claim 61, The imaging control unit controls the operation of the first transistor. Imaging device.

63. In the imaging device according to claim 62, The imaging control unit controls the operation of the first transistor based on the set ISO sensitivity. Imaging device.

64. An imaging device comprising an image sensor according to any one of claims 29 to 59.

65. In the imaging device according to claim 64, An imaging device comprising an imaging control unit that controls the image sensor.

66. In the imaging device according to claim 65, The imaging control unit controls the operation of the first transistor and the operation of the second transistor. Imaging device.

67. In the imaging device according to claim 66, The imaging control unit controls the operation of the first transistor and the operation of the second transistor based on the set ISO sensitivity. Imaging device.

68. In the imaging device according to any one of claims 60 to 67, An imaging device comprising a drive unit for driving a photographic lens that emits light to the aforementioned image sensor.

69. In the imaging device according to claim 68, An imaging device equipped with the aforementioned photographic lens.

Images