Semiconductor equipment

Abstract

To provide a semiconductor device that ensures a wide operating area. [Solution] The semiconductor device 1 includes a semiconductor layer 10, an active region 3 provided in the semiconductor layer, a non-active region 4 provided in the semiconductor layer outside the active region, a gate structure formed on the main surface, an insulating layer 61 formed on the main surface to cover the gate structure, a gate main electrode 50 disposed on the insulating layer and electrically connected to the gate structure, and a gate pad electrode 70 disposed on the gate main electrode to be connected to the gate main electrode, and including a connection portion connected to the gate main electrode with a first area in a plan view and an electrode surface 73 having a second area exceeding the first area in a plan view, wherein the active region includes a plurality of divided regions provided in the semiconductor layer at intervals in a plan view, and the gate pad electrode includes a portion that overlaps with the portion located between the plurality of divided regions in the non-active region in a plan view.

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application No. 2020-082750, filed with the Japan Patent Office on 8 May 2020, and the full disclosure of this application is incorporated herein by reference. The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a gate pad electrically connected to the gate electrode of an IGBT. Patent Document 2 discloses technology relating to a vertical semiconductor device comprising a semiconductor layer made of SiC. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-4864 [Patent Document 2] Japanese Patent Publication No. 2012-79945 [Overview of the project] [Problems that the invention aims to solve]

[0004] The semiconductor device described in Patent Document 1 includes a gate pad for supplying power to the gate electrode. Since wire bonding is performed on the gate pad, it needs to be of a certain size or larger. However, the area directly beneath the gate pad is an inactive region where it cannot function as a transistor. Therefore, when the pad size is ensured, there is a problem in that the operating region (active region) where the transistor can function becomes smaller.

[0005] Therefore, one embodiment of the present invention provides a semiconductor device that can secure a wide operating area. [Means for solving the problem]

[0006] One embodiment of the present invention provides a semiconductor device including a vertical transistor, comprising: a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and mainly composed of SiC; a control electrode of the vertical transistor provided on the first main surface; a first main electrode of the vertical transistor provided on the first main surface at a distance from the control electrode; a second main electrode of the vertical transistor provided on the second main surface; a first electrode covering a part of the first main surface; a second electrode provided at a distance from the first electrode in a plan view; and a first electrode pad overlapping the first electrode in a plan view and electrically connected to the first electrode, wherein the first electrode is smaller than the first electrode pad in a plan view.

[0007] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor layer having a main surface and mainly composed of SiC; a gate structure formed on the main surface; an insulating layer formed on the main surface so as to cover the gate structure; a gate main electrode disposed on the insulating layer and electrically connected to the gate structure; and a gate pad electrode disposed on the gate main electrode so as to be connected to the gate main electrode and including a connection portion connected to the gate main electrode with a first area in a plan view, and an electrode surface having a second area exceeding the first area in a plan view.

[0008] One embodiment of the present invention provides a semiconductor device including a semiconductor layer having a main surface, an active region provided in the semiconductor layer, a non-active region provided in a region outside the active region in the semiconductor layer, a plurality of gate structures formed in the active region, an insulating layer formed on the main surface so as to cover the plurality of gate structures, a gate main electrode disposed on the insulating layer so as to be electrically connected to the plurality of gate structures and overlapping the non-active region in a plan view, and a gate pad electrode disposed above the gate main electrode so as to be electrically connected to the gate main electrode and overlapping the active region and the non-active region in a plan view. The semiconductor device may further include a current conduction electrode disposed on the insulating layer at a distance from the gate main electrode. The gate pad electrode may be disposed above the gate main electrode and the current conduction electrode.

[0009] The above-described or further other objects, features, and effects of the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0010] [Figure 1] FIG. 1 is a cross-sectional view showing a vertical transistor included in a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1. [Figure 3] FIG. 3 is a plan view of the semiconductor device shown in FIG. 1. [Figure 4] FIG. 4 is a plan view taken along line IV-IV shown in FIG. 2. [Figure 5] FIG. 5 is a plan view taken along line V-V shown in FIG. 2. <{ [Figure 6A] FIG. 6A is a cross-sectional view showing a step of a manufacturing method of the semiconductor device shown in FIG. 1. [Figure 6B] FIG. 6B is a cross-sectional view showing a step after FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view showing a step after FIG. 6B. [Figure 6D] Figure 6D is a cross-sectional view showing a process after Figure 6C. [Figure 6E] Figure 6E is a cross-sectional view showing a process after Figure 6D. [Figure 6F] Figure 6F is a cross-sectional view showing a process after Figure 6E. [Figure 6G] Figure 6G is a cross-sectional view showing a process after Figure 6F. [Figure 6H] Figure 6H is a cross-sectional view showing a process after Figure 6G. [Figure 7] Figure 7 is a cross-sectional view of the semiconductor device according to the second embodiment. [Figure 8] Figure 8 is a plan view of the semiconductor device shown in Figure 7. [Figure 9] Figure 9 is a plan view along the line IX-IX shown in Figure 7. [Figure 10] Figure 10 is a plan view showing a modified example of the semiconductor device according to the second embodiment. [Figure 11] Figure 11 is a plan view showing the top surface of the electrodes of the semiconductor device shown in Figure 10. [Figure 12] Figure 12 is a cross-sectional view showing the main parts of the semiconductor device according to the third embodiment. [Figure 13] Figure 13 is a plan view of the semiconductor device shown in Figure 12. [Figure 14] Figure 14 is a plan view along the line XIV-XIV shown in Figure 12. [Figure 15] Figure 15 is a plan view showing a modified example of the semiconductor device according to the third embodiment. [Figure 16] Figure 16 is a plan view showing the top surface of the electrodes of the semiconductor device shown in Figure 15. [Figure 17] Figure 17 is a rear view showing an example of a semiconductor package according to the fourth embodiment. [Figure 18] Figure 18 is a front view showing the internal structure of the semiconductor package shown in Figure 17. [Figure 19] Figure 19 is a front view showing another example of a semiconductor package according to the fourth embodiment. [Figure 20]Figure 20 is a cross-sectional view showing the main parts of a semiconductor device according to the first modified example of each of the embodiments described above. [Figure 21] Figure 21 is a cross-sectional view showing the main parts of a semiconductor device according to a second modified example of each of the embodiments described above. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be specifically described below with reference to the attached drawings. The embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, arrangement positions of components, connection configurations of components, steps, and the order of steps shown in the following embodiments are examples and are not intended to limit the present invention. Components in the following embodiments that are not described in an independent claim will be described as optional components.

[0012] Each attached drawing is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale in the attached drawings may not necessarily match. In the attached drawings, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified.

[0013] In this specification, terms describing relationships between elements, such as perpendicular and orthogonal, and terms describing the shapes of elements, such as rectangles and cuboids, as well as numerical ranges, are not expressions that represent only strict meanings, but rather expressions that include substantially equivalent ranges. For example, in the shape of a polygon or polygonal prism, the vertices may be rounded.

[0014] In this specification, the terms "upper" and "lower" do not refer to the absolute spatial directions of upward (vertically upward) and downward (vertically downward), but rather are used as terms defined by the relative positional relationship based on the stacking order in a stacked configuration. Specifically, the first main surface side of one semiconductor layer is referred to as the upper side (upper), and the second main surface side of the other is referred to as the lower side (lower). In actual use of a semiconductor device (vertical transistor), the first main surface side may be the lower side (lower), and the second main surface side may be the upper side (upper). Alternatively, the semiconductor device (vertical transistor) may be used in an orientation where the first and second main surfaces are inclined or perpendicular to the horizontal plane.

[0015] Furthermore, the terms “above” and “below” apply when two components are spaced apart from each other with another component interposed between them, as well as when two components are placed in close proximity to each other.

[0016] In this specification and in the drawings, the x, y, and z axes represent the three axes of a three-dimensional Cartesian coordinate system. In this specification, "stack direction" means the direction perpendicular to the main surface of the semiconductor layer. In addition, "plan view" means the view from a direction perpendicular to the first main surface of the semiconductor layer.

[0017] Figure 1 is a cross-sectional view showing a vertical transistor 2 included in the semiconductor device 1 according to the first embodiment. In Figure 1, for the sake of readability, the cross-section of the semiconductor layer 10 is not shaded.

[0018] The semiconductor device 1 shown in Figure 1 is an example of a switching device and includes a vertical transistor 2. The vertical transistor 2 is, for example, a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor). As shown in Figure 1, the semiconductor device 1 includes a semiconductor layer 10, a gate electrode 20, a source electrode 30, and a drain electrode 40.

[0019] The semiconductor device 1 includes a semiconductor layer 10 mainly composed of SiC (silicon carbide) as an example of a wide-bandgap semiconductor. Specifically, the semiconductor layer 10 is an n-type SiC semiconductor layer containing a SiC single crystal. The SiC single crystal is, for example, a 4H-SiC single crystal. The 4H-SiC single crystal has an off-angle tilted at an angle of 10° or less with respect to the [11-20] direction from the (0001) plane. The off-angle may be 0° or more and 4° or less. The off-angle may be greater than 0° and less than 4°. The off-angle is set, for example, to 2° or 4°, or in the range of 2°±0.2° or 4°±0.4°.

[0020] In this embodiment, the semiconductor layer 10 is formed in the shape of a rectangular parallelepiped chip. The semiconductor layer 10 has a first main surface 11 on one side and a second main surface 12 on the other side. In this embodiment, the semiconductor layer 10 has a semiconductor substrate 13 and an epitaxial layer 14. The semiconductor substrate 13 is n + It is formed as a drain region of type n - It is formed as a drain drift region of type [type].

[0021] The semiconductor substrate 13 contains a SiC single crystal. The lower surface of the semiconductor substrate 13 is the second main surface 12. The second main surface 12 is the carbon surface (000-1) surface where the carbon of the SiC crystal is exposed. The epitaxial layer 14 is laminated on the upper surface of the semiconductor substrate 13 and contains an n - This is a SiC semiconductor layer of a specific type. The upper surface of the epitaxial layer 14 is the first main surface 11. The first main surface 11 is the silicon surface (0001) where the silicon of the SiC crystal is exposed.

[0022] The n-type impurity concentration of the semiconductor substrate 13 is, for example, 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3The following holds. In this specification, "impurity concentration" means the peak value of the impurity concentration. The n-type impurity concentration of the epitaxial layer 14 is lower than the n-type impurity concentration of the semiconductor substrate 13. The n-type impurity concentration of the epitaxial layer 14 is, for example, 1.0×10 15 cm -3 or more and 1.0×10 17 cm -3 or less.

[0023] The thickness of the semiconductor substrate 13 is, for example, 1 μm or more and less than 1000 μm. The thickness of the semiconductor substrate 13 may be 5 μm or more. The thickness of the semiconductor substrate 13 may be 25 μm or more. The thickness of the semiconductor substrate 13 may be 50 μm or more. The thickness of the semiconductor substrate 13 may be 100 μm or more.

[0024] The thickness of the semiconductor substrate 13 may be 700 μm or less. The thickness of the semiconductor substrate 13 may be 500 μm or less. The thickness of the semiconductor substrate 13 may be 400 μm or less. The thickness of the semiconductor substrate 13 may be 300 μm or less. The thickness of the semiconductor substrate 13 may be 250 μm or less. The thickness of the semiconductor substrate 13 may be 200 μm or less. The thickness of the semiconductor substrate 13 may be 150 μm or less. The thickness of the semiconductor substrate 13 may be 100 μm or less. In the vertical transistor 2, current flows in the thickness direction (i.e., the stacking direction) of the semiconductor substrate 13. Therefore, by reducing the thickness of the semiconductor substrate 13, reduction of the resistance value due to shortening of the current path can be realized.

[0025] The thickness of the epitaxial layer 14 is, for example, 1 μm or more and 100 μm or less. The thickness of the epitaxial layer 14 may be 5 μm or more. The thickness of the epitaxial layer 14 may be 10 μm or more. The thickness of the epitaxial layer 14 may be 50 μm or less. The thickness of the epitaxial layer 14 may be 40 μm or less. The thickness of the epitaxial layer 14 may be 30 μm or less. The thickness of the epitaxial layer 14 may be 20 μm or less. The thickness of the epitaxial layer 14 may be 15 μm or less. The thickness of the epitaxial layer 14 may be 10 μm or less.

[0026] The semiconductor device 1 includes a plurality of trench gate structures 21 and a plurality of trench source structures 31 formed on the first main surface 11 of the semiconductor layer 10. The trench gate structures 21 and trench source structures 31 are arranged alternately one by one along the x-axis in a plan view, forming a stripe structure. In Figure 1, only the area where one trench gate structure 21 is sandwiched between two trench source structures 31 is shown.

[0027] Both the trench gate structure 21 and the trench source structure 31 are formed in a strip shape extending along the y-axis direction. For example, the x-axis direction is the [11-20] direction and the y-axis direction is the [1-100] direction. The x-axis direction may also be the [-1100] direction ([1-100] direction). In this case, the y-axis direction may also be the [11-20] direction. The distance between the trench gate structure 21 and the trench source structure 31 is, for example, 0.3 μm or more and 1.0 μm or less.

[0028] The trench gate structure 21 includes a gate trench 22, a gate insulating layer 23, and a gate electrode 20, as shown in Figure 1. The gate trench 22 is formed by excavating the first main surface 11 of the semiconductor layer 10 toward the second main surface 12. The gate trench 22 has a rectangular cross-sectional shape in the xz section and is a groove-shaped recessed portion that extends in a band-like manner along the y-axis direction.

[0029] The gate trench 22 may have a length on the order of millimeters in the longitudinal direction (y-axis direction). For example, the gate trench 22 may have a length of 1 mm or more and 10 mm or less. The length of the gate trench 22 may be 2 mm or more and 5 mm or less. The total length of one or more gate trenches 22 per unit area may be 0.5 μm / μm² or more and 0.75 μm / μm² or less.

[0030] The gate insulating layer 23 is provided in a film-like manner along the side walls 22a and bottom wall 22b of the gate trench 22. The gate insulating layer 23 defines a concave space inside the gate trench 22. The gate insulating layer 23 contains, for example, silicon oxide. The gate insulating layer 23 may contain at least one of the following: impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0031] The thickness of the gate insulating layer 23 is, for example, 0.01 μm or more and 0.5 μm or less. The thickness of the gate insulating layer 23 may be uniform or may vary depending on the location. For example, the gate insulating layer 23 includes a side wall portion 23a and a bottom wall portion 23b. The side wall portion 23a is formed along the side wall 22a of the gate trench 22. The bottom wall portion 23b is formed along the bottom wall 22b of the gate trench 22.

[0032] The thickness of the bottom wall portion 23b may be greater than the thickness of the side wall portion 23a. For example, the thickness of the bottom wall portion 23b is 0.01 μm or more and 0.2 μm or less. For example, the thickness of the side wall portion 23a is 0.05 μm or more and 0.5 μm or less. The gate insulating layer 23 may also include an upper surface portion formed on the upper surface of the first main surface 11 outside the gate trench 22. The thickness of the upper surface portion may be greater than the thickness of the side wall portion 23a.

[0033] The gate electrode 20 is an example of a control electrode for the vertical transistor 2. The gate electrode 20 is embedded in the gate trench 22. A gate insulating layer 23 is provided between the gate electrode 20 and the side walls 22a and bottom wall 22b of the gate trench 22. In other words, the gate electrode 20 is embedded in a concave space partitioned by the gate insulating layer 23. The gate electrode 20 is, for example, a conductive layer containing conductive polysilicon. The gate electrode 20 may contain at least one of the following: a metal such as titanium, nickel, copper, aluminum, silver, gold, or tungsten, or a conductive metal nitride such as titanium nitride.

[0034] The width of the trench gate structure 21 is, for example, between 0.2 μm and 2.0 μm. For example, the width of the trench gate structure 21 may be about 0.4 μm. The depth of the trench gate structure 21 is, for example, between 0.5 μm and 3.0 μm. For example, the depth of the trench gate structure 21 may be about 1.0 μm.

[0035] The aspect ratio of the trench gate structure 21 is, for example, between 0.25 and 15.0. The aspect ratio of the trench gate structure 21 is defined by the ratio of the depth (length in the z-axis direction) of the trench gate structure 21 to the width (length in the x-axis direction) of the trench gate structure 21. In this configuration, the aspect ratio of the trench gate structure 21 is the same as the aspect ratio of the gate trench 22.

[0036] The trench source structure 31, as shown in Figure 1, includes a source trench 32, a deep well region 15, a barrier forming layer 33, and a source electrode 30. The source trench 32 is formed by excavating the first main surface 11 of the semiconductor layer 10 toward the second main surface 12. The source trench 32 has a rectangular cross-sectional shape in the xz cross-section and is a groove-like recess extending in a band shape along the y-axis direction. In this configuration, the source trench 32 is deeper than the gate trench 22. That is, the bottom wall 32b of the source trench 32 is located toward the second main surface 12 than the bottom wall 22b of the gate trench 22.

[0037] The deep well region 15 is formed in the semiconductor layer 10 in a region along the source trench 32. The deep well region 15 is also called the breakdown voltage holding region. The deep well region 15 is p - This is a type of semiconductor region. The p-type impurity concentration in the deep well region 15 is, for example, 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm -3 The following is true: The p-type impurity concentration in the deep well region 15 is higher than, for example, the n-type impurity concentration in the epitaxial layer 14.

[0038] The deep well region 15 includes a sidewall portion 15a along the sidewall 32a of the source trench 32, and a bottom wall portion 15b along the bottom wall 32b of the source trench 32. The thickness (length in the z-axis direction) of the bottom wall portion 15b is, for example, greater than or equal to the thickness (length in the x-axis direction) of the sidewall portion 15a. At least a portion of the bottom wall portion 15b may be located within the semiconductor substrate 13.

[0039] The source electrode 30 is an example of the first main electrode of the vertical transistor 2. The source electrode 30 is embedded in the source trench 32. The source electrode 30 is, for example, a conductive layer containing conductive polysilicon. The source electrode 30 may be n-type polysilicon doped with n-type impurities, or p-type polysilicon doped with p-type impurities. The source electrode 30 may contain at least one of the following: metals such as titanium, nickel, copper, aluminum, silver, gold, tungsten, or conductive metal nitrides such as titanium nitride. The source electrode 30 may be formed from the same material as the gate electrode 20. In this case, the source electrode 30 and the gate electrode 20 are formed in the same process.

[0040] The barrier-forming layer 33 is interposed between the source electrode 30 and the source trench 32. The barrier-forming layer 33 is formed as a film along the side walls 32a and bottom wall 32b of the source trench 32 between the source electrode 30 and the source trench 32. In other words, the source electrode 30 is embedded in a concave space partitioned by the barrier-forming layer 33. The barrier-forming layer 33 partitions the concave space within the source trench 32. The barrier-forming layer 33 is formed using a different material than the source electrode 30. The barrier-forming layer 33 has a higher potential barrier than the potential barrier between the source electrode 30 and the deep well region 15.

[0041] The barrier-forming layer 33 may be an insulating barrier-forming layer. In this case, the barrier-forming layer 33 contains at least one of the following: impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The barrier-forming layer 33 may be formed using the same material as the gate insulating layer 23. In this case, the barrier-forming layer 33 may have the same film thickness as the gate insulating layer 23. For example, the barrier-forming layer 33 and the gate insulating layer 23 may be formed of silicon oxide. In this case, the barrier-forming layer 33 and the gate insulating layer 23 are formed simultaneously by a thermal oxidation treatment method.

[0042] The barrier-forming layer 33 may be a conductive barrier-forming layer. In this case, the barrier-forming layer 33 contains at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0043] The width of the trench source structure 31 is, for example, 0.6 μm to 2.4 μm. As an example, the width of the trench source structure 31 may be about 0.8 μm. The depth of the trench source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall portion 15b of the deep well region 15. The depth of the trench source structure 31 is, for example, 1.5 μm to 11 μm. As an example, the depth of the trench source structure 31 may be about 2.5 μm.

[0044] The aspect ratio of the trench source structure 31 is greater than the aspect ratio of the trench gate structure 21. The aspect ratio of the trench source structure 31 is defined by the ratio of the depth (length in the z-axis direction) of the trench source structure 31 to the width (length in the x-axis direction) of the trench source structure 31. In this configuration, the width of the trench source structure 31 is the sum of the width of the source trench 32 and the width of the side wall portions 15a of the deep well regions 15 located on both sides of the source trench 32. For example, the aspect ratio of the trench source structure 31 is between 1.5 and 4.0. By increasing the depth of the trench source structure 31, the pressure-resistant holding effect of the superjunction (SJ) structure can be enhanced.

[0045] As shown in Figure 1, the semiconductor device 1 includes a body region 16, a source region 17, and a contact region 18 formed on the epitaxial layer 14 of the semiconductor layer 10, respectively. The aforementioned deep well region 15, body region 16, source region 17, and contact region 18 may be considered as components of the epitaxial layer 14.

[0046] The body region 16 is provided on the surface portion of the first main surface 11 of the semiconductor layer 10. - This is a semiconductor region of type 16. In a plan view, the body region 16 is formed in the region between the gate trench 22 and the source trench 32. In a plan view, the body region 16 is formed in a strip shape extending along the y-axis. The body region 16 is connected to the deep well region 15.

[0047] The p-type impurity concentration in body region 16 is, for example, 1.0 × 10⁻⁶. 16 cm -3 The above 1.0 × 10 19 cm -3 The following applies: The p-type impurity concentration in the body region 16 may be equal to that of the impurity region in the deep well region 15. The p-type impurity concentration in the body region 16 may be higher than that of the deep well region 15.

[0048] The source region 17 is provided in the body region 16 on the surface portion of the first main surface 11 of the semiconductor layer 10 n + This is a semiconductor region of type 2. The source region 17 is located in the region along the gate trench 22. The source region 17 is in contact with the gate insulating layer 23 and faces the gate electrode 20 across the gate insulating layer 23. Specifically, the source region 17 is in contact with the side wall portion 23a of the gate insulating layer 23. The source region 17 may also be in contact with the upper surface portion of the gate insulating layer 23.

[0049] The source region 17 is formed in a band shape extending along the y-axis in a plan view. The width (length in the x-axis direction) of the source region 17 is, for example, 0.2 μm or more and 0.6 μm or less. As an example, the width of the source region 17 may be about 0.4 μm. The n-type impurity concentration in the source region 17 is, for example, 1.0 × 10⁻⁶ 18 cm -3 The above 1.0 × 10 21 cm -3 The following applies:

[0050] The contact region 18 is provided on the surface portion of the first main surface 11 of the semiconductor layer 10. + This is a semiconductor region of the type. The contact region 18 may be considered as part of the body region 16 (high-concentration region). The contact region 18 is formed in a region along the source trench 32. The contact region 18 is in contact with the barrier forming layer 33 and faces the source electrode 30 across the barrier forming layer 33. The contact region 18 is electrically connected to the body region 16. The contact area 18 is electrically connected to the source area 17.

[0051] The contact region 18 is formed in a band shape extending along the y-axis in a plan view. The width (length in the x-axis direction) of the contact region 18 is, for example, 0.1 μm or more and 0.4 μm or less. As an example, the width of the contact region 18 may be about 0.2 μm. The p-type impurity concentration in the contact region 18 is, for example, 1.0 × 10⁻⁶ 18 cm -3 The above 1.0 × 10 21cm -3 The following applies:

[0052] The semiconductor device 1 includes a drain electrode 40 connected to the second main surface 12 of the semiconductor layer 10. The drain electrode 40 is an example of the second main electrode of the semiconductor device 1 (vertical transistor 2). The drain electrode 40 may contain at least one of titanium, nickel, copper, aluminum, gold, or silver. For example, the drain electrode 40 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in order from the second main surface 12 of the semiconductor layer 10.

[0053] The drain electrode 40 may have a four-layer structure including a Ti layer, an AlCu layer, a Ni layer, and an Au layer stacked in order from the second main surface 12 of the semiconductor layer 10. The AlCu layer is an alloy layer of aluminum and copper. The drain electrode 40 may have a four-layer structure including a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer stacked in order from the second main surface 12 of the semiconductor layer 10. The AlSiCu layer is an alloy layer of aluminum, silicon, and copper. The drain electrode 40 may include a single-layer structure having a TiN layer instead of a Ti layer, or a stacked structure having a Ti layer and a TiN layer.

[0054] In the semiconductor device 1 configured as described above, the ON state, in which drain current flows, and the OFF state, in which no drain current flows, can be switched depending on the gate voltage applied to the gate electrode 20 of the vertical transistor 2. The gate voltage is, for example, a voltage of 10V to 50V. As an example, the gate voltage may be 30V. The source voltage applied to the source electrode 30 is, for example, a reference voltage such as the ground voltage (0V). The drain voltage applied to the drain electrode 40 is equal to or greater than the source voltage. The drain voltage is, for example, 0V to 10000V. The drain voltage may be 1000V or more.

[0055] When a gate voltage is applied to the gate electrode 20, p -A channel is formed in the portion of the body region 16 of the type that is in contact with the gate insulating layer 23. This creates a current path between the source electrode 30 and the drain electrode 40 through the channel in the body region 16. The current path connects the contact region 18, the source region 17, the channel in the body region 16, the epitaxial layer 14, and the semiconductor substrate 13 between the source electrode 30 and the drain electrode 40.

[0056] The drain electrode 40 may be at a higher potential than the source electrode 30. In this case, the drain current flows from the drain electrode 40 towards the source electrode 30. That is, the drain current flows through the drain electrode 40, the semiconductor substrate 13, the epitaxial layer 14, the channel of the body region 16, the source region 17, and the contact region 18 in that order to the source electrode 30. In this way, the drain current flows along the thickness direction of the semiconductor device 1.

[0057] In this configuration, the pn junction (pn junction) is p - Type deep well regions 15 and n - It is formed between the epitaxial layers 14 of type . When the vertical transistor 2 is ON, the source voltage is passed through the source electrode 30 p - A drain voltage higher than the source voltage is applied to the deep well region 15 of the type n through the drain electrode 40. - It is applied to the epitaxial layer 14 of the type.

[0058] In other words, a reverse bias voltage is applied to the pn junction between the deep well region 15 and the epitaxial layer 14. Consequently, the depletion layer spreads from the interface between the deep well region 15 and the epitaxial layer 14 toward the drain electrode 40. This increases the breakdown voltage of the vertical transistor 2.

[0059] Next, a pad structure for supplying a predetermined voltage to the gate electrode 20 and the source electrode 30 will be described. Figure 2 is a cross-sectional view of the semiconductor device 1 shown in Figure 1. Figure 3 is a plan view of the semiconductor device 1 shown in Figure 1. Specifically, Figure 2 is a cross-sectional view along the line II-II shown in Figure 3. In Figure 2, the specific configuration of the semiconductor layer 10 shown in Figure 1 is omitted. Also, in Figure 2, the shading representing the cross-section of the semiconductor layer 10 is not applied.

[0060] As shown in Figures 2 and 3, the semiconductor device 1 includes a main surface gate electrode 50, a main surface source electrode 55, an insulating layer 60, a gate pad 70, a source pad 75, and a mold layer 80. The pad structure is provided above the first main surface 11 of the semiconductor layer 10.

[0061] Figure 4 is a plan view along the line IV-IV shown in Figure 2. Specifically, Figure 4 is a plan view of the semiconductor device 1 as seen from the positive z-axis side, looking through the gate pad 70, source pad 75, and mold layer 80 shown in Figure 3. For example, the positive z-axis side is the side of the first main surface 11, assuming that the second main surface 12 (or the surface of the drain electrode 40) is located on the xy plane where z=0. Specifically, Figure 5 is a plan view of the semiconductor device 1 as seen from the positive z-axis side, looking through the main surface gate electrode 50, main surface source electrode 55, and insulating layer 60 shown in Figure 4, as well as the gate pad 70, source pad 75, and mold layer 80 shown in Figure 3.

[0062] As shown in Figures 3 to 5, the semiconductor layer 10 (semiconductor device 1) has a rectangular planar shape. In planar view, the length of one side of the semiconductor layer 10 (semiconductor device 1) is, for example, 1 mm or more and 10 mm or less. In planar view, the length of one side of the semiconductor layer 10 (semiconductor device 1) may be 2 mm or more and 5 mm or less.

[0063] The semiconductor device 1 includes an active region 3 and an inactive region 4 (outer region). The active region 3 is shown by a dashed line in Figures 3 and 5. The active region 3 is the main region through which the drain current of the vertical transistor 2 flows. In other words, the active region 3 is the operating region of the vertical transistor 2. Specifically, the active region 3 roughly coincides with the region covered by the main surface source electrode 55.

[0064] In this embodiment, the active region 3 is separated in a plan view into a region on one side (left side of the paper) in the x-axis direction of the semiconductor layer 10 and a region on the other side (right side of the paper) in the x-axis direction. In the active region 3, the planar area of ​​one side (left side of the paper) may differ from the planar area of ​​the other side (right side of the paper). In this embodiment, an example is shown in which the planar area of ​​one side (left side of the paper) is less than the planar area of ​​the other side (right side of the paper).

[0065] As shown in Figure 5, the active region 3 includes multiple gate electrodes 20 (trench gate structures 21) and multiple source electrodes 30 (trench source structures 31). In Figure 5, the multiple gate electrodes 20 and multiple source electrodes 30 are schematically illustrated to the extent that the number of gate electrodes 20 and source electrodes 30 can be counted. However, the actual number of gate electrodes 20 and source electrodes 30 is far greater than the number shown.

[0066] The inactive region 4 is the region that does not operate as the vertical transistor 2. The inactive region 4 is a frame-shaped (ring-shaped) region surrounding the active region 3. In this configuration, the inactive region 4 separates the active region 3 into one side (left side of the paper) and the other side (right side of the paper). In other words, in a plan view, the inactive region 4 surrounds one side (left side of the paper) of the active region 3.

[0067] As shown in Figure 5, the inactive region 4 is provided with the gate finger portion 20b, which will be described later. In the examples shown in Figures 3 to 5, the active region 3 is divided into two by the inactive region 4, but the active region 3 may be a single, undivided region. The shape and arrangement of the active region 3 can be adjusted as appropriate by the layout of the gate finger portion 20b.

[0068] As shown in Figure 4, the active region 3 includes the region covered by the main surface source electrode 55. As shown in Figure 3, the active region 3 includes a portion of the region covered by the gate pad 70. The region covered by the main surface gate electrode 50 is included in the inactive region 4 and is not included in the active region 3.

[0069] The main surface gate electrode 50 is an example of a first electrode that covers a portion of the first main surface 11. The main surface gate electrode 50 includes, for example, at least one of the following: conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, or a metal nitride such as titanium nitride. The main surface gate electrode 50 may be formed using the same material as the gate electrode 20.

[0070] The main surface gate electrode 50 is electrically connected to the gate electrode 20. As shown in Figure 2, the main surface gate electrode 50 is provided in a line on the insulating layer 60 (specifically, the lower insulating layer 61), which will be described later. The main surface gate electrode 50 is connected to the gate electrode 20 (not shown in Figure 2) via a via conductor that penetrates the insulating layer 60 (specifically, the lower insulating layer 61).

[0071] As shown in Figure 4, the main surface gate electrode 50 includes a power receiving section 50a, a power supply section 50b, and a connection section 50c. The power receiving section 50a of the main surface gate electrode 50 is located in the inner part of the first main surface 11 in a plan view. Specifically, the power receiving section 50a is located in a plan view on the region between the region on one side (left side of the paper) and the region on the other side (right side of the paper) of the active region 3 within the inactive region 4.

[0072] The power receiving section 50a is located directly below the gate pad 70 (described later) and is connected to the gate pad 70 (specifically, the columnar section 71 described later). In a plan view, the portion of the main surface gate electrode 50 that overlaps with the columnar section 71 corresponds to the power receiving section 50a. In a plan view, the power receiving section 50a of the main surface gate electrode 50 is smaller than the gate pad 70. The plan view shape of the power receiving section 50a (the plan view shape of the columnar section 71) is, for example, a square or a rectangle. The length of one side of the power receiving section 50a is between 5 μm and 50 μm. As an example, the plan view shape of the power receiving section 50a may be a square of about 20 μm × 20 μm.

[0073] The power supply section 50b is a portion that extends along the outer periphery of the semiconductor layer 10 (the periphery of the first main surface 11) in a plan view. In the example shown in Figure 4, the power supply section 50b extends along the x-axis direction of the semiconductor layer 10. In this configuration, two power supply sections 50b are provided so as to sandwich the inner portion of the first main surface 11 from the positive and negative sides in the y-axis direction in a plan view. The power supply section 50b may also be provided around the entire circumference of the semiconductor layer 10 so as to surround the inner portion of the first main surface 11 (for example, the main surface source electrode 55 described later).

[0074] The connection section 50c is the part connected to the power receiving section 50a and the power supply section 50b. In the example shown in Figure 4, the connection section 50c is drawn out from the power receiving section 50a to the positive and negative sides in the y-axis direction, respectively, and extends to the power supply section 50b. The area where the power receiving section 50a, the power supply section 50b, and the connection section 50c are provided becomes an inactive area 4. For this reason, it is desirable that the power receiving section 50a, the power supply section 50b, and the connection section 50c be made as small as possible.

[0075] In this configuration, the main surface gate electrode 50 is electrically connected to each of the multiple gate electrodes 20 via the power supply section 50b. Specifically, a through-hole is provided in the insulating layer 60 (specifically, the lower insulating layer 61 described later) located directly below the power supply section 50b, and the power supply section 50b is connected to the gate finger section 20b (see Figure 5) described later via this through-hole.

[0076] As shown in Figure 5, the multiple gate electrodes 20 (trench gate structure 21) are formed in an elongated shape extending in the y-axis direction. The multiple gate electrodes 20 may be divided into a positive side portion and a negative side portion in the central part in the y-axis direction.

[0077] As shown in Figure 5, the semiconductor device 1 includes gate finger portions 20b formed on the semiconductor layer 10 (first main surface 11) so as to be electrically connected to a plurality of gate electrodes 20. Specifically, the gate finger portions 20b are interposed between the semiconductor layer 10 (first main surface 11) and the insulating layer 60 described later. In a plan view, the gate finger portions 20b extend in the x-axis direction along the periphery of the first main surface 11 (outer circumference of the semiconductor device 1).

[0078] In this configuration, two gate finger portions 20b are provided so as to sandwich the multiple gate electrodes 20 from the positive and negative sides in the y-axis direction when viewed from above. The gate finger portions 20b are connected to both ends of the multiple gate electrodes 20 in the y-axis direction. The gate finger portions 20b may also be connected to only one end of the multiple gate electrodes 20 in the y-axis direction. The aforementioned power supply portion 50b is connected to the gate finger portions 20b via through holes provided in the insulating layer 60 (specifically, the lower insulating layer 61 described later).

[0079] The main surface source electrode 55 is an example of a second electrode that covers a portion of the first main surface 11. In a plan view, the main surface source electrode 55 is provided at a distance from the main surface gate electrode 50. For example, in a plan view, the main surface source electrode 55 is formed over almost the entire area of ​​the first main surface 11 of the semiconductor layer 10 (semiconductor device 1), excluding the area where the main surface gate electrode 50 is provided and the area surrounding that area. In a plan view, the main surface source electrode 55 is larger than the main surface gate electrode 50.

[0080] The main surface source electrode 55 specifically includes a first portion positioned on one side (left side of the paper) of the active region 3, and a second portion separated from the first portion and positioned on the other side (right side of the paper) of the active region 3. The planar area of ​​the second portion is larger than the first planar area of ​​the first portion. The sum of the planar areas of the first and second portions is larger than the planar area of ​​the main surface gate electrode 50.

[0081] The main surface source electrode 55 includes, for example, at least one of the following: conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, or a metal nitride such as titanium nitride. The main surface source electrode 55 may be formed using the same material as the source electrode 30. The main surface source electrode 55 may also be formed using the same material as the main surface gate electrode 50. In this case, the main surface gate electrode 50 and the main surface source electrode 55 can be formed in the same process.

[0082] Multiple source electrodes 30 are provided directly below the main surface source electrode 55, and the main surface source electrode 55 is electrically connected to the source electrodes 30. Therefore, as shown in Figure 1, the main surface source electrode 55 is directly connected to the upper surfaces of each of the multiple source electrodes 30. As shown in Figure 2, the area below the main surface source electrode 55 is the active region 3, and the MOSFET structure shown in Figure 1 is periodically formed in the active region 3.

[0083] The main surface source electrode 55 has an area of ​​50% or more of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the main surface source electrode 55 has an area of ​​70% or more of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. On the other hand, the main surface gate electrode 50 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the main surface gate electrode 50 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view.

[0084] The main surface source electrode 55 is located in a region that includes the center of the semiconductor layer 10 (first main surface 11) in a plan view. The main surface gate electrode 50 is located in a region that avoids the main surface source electrode 55. The main surface gate electrode 50 may also be located in a region that includes the center of the semiconductor layer 10 (first main surface 11). In this case, the main surface source electrode 55 may be arranged to surround the main surface gate electrode 50.

[0085] The insulating layer 60 includes a lower insulating layer 61, a side insulating layer 62, an upper insulating layer 63, and an end insulating layer 65, as shown in Figure 2. In Figure 4, the unshaded portion around the main surface gate electrode 50 corresponds to the side insulating layer 62 and the end insulating layer 65. The lower insulating layer 61 is an interlayer insulating film and is provided on the first main surface 11. Specifically, the lower insulating layer 61 covers multiple trench gate structures 21 collectively. As shown in Figure 1, the lower insulating layer 61 is provided to prevent contact between the main surface source electrode 55 and the gate electrode 20.

[0086] The lower insulating layer 61 has a plurality of source contact holes 61b. A portion of the main surface source electrode 55 is embedded in the plurality of source contact holes 61b. As a result, the main surface source electrode 55 is electrically connected to the plurality of source electrodes 30 within the plurality of source contact holes 61b.

[0087] Although not shown in Figure 2, as described above, the lower insulating layer 61 is provided with a through-hole for connecting the power supply portion 50b (see Figure 4) of the main surface gate electrode 50 to the gate finger portion 20b (see Figure 5). A portion of the power supply portion 50b is embedded in the through-hole of the lower insulating layer 61. The power supply portion 50b is connected to the gate finger portion 20b within the through-hole. As a result, the main surface gate electrode 50 is electrically connected to the gate electrode 20.

[0088] The side insulating layer 62 is formed on the lower insulating layer 61 and is provided to prevent contact between the main surface gate electrode 50 and the main surface source electrode 55. As shown in Figure 4, the side insulating layer 62 is provided so as to surround the main surface gate electrode 50.

[0089] The upper insulating layer 63 is formed on the upper surface 56 of the main surface source electrode 55. Specifically, the upper insulating layer 63 covers the portion of the main surface gate electrode 50 along the current receiving portion 50a on the main surface source electrode 55. The upper insulating layer 63 covers a portion of the current receiving portion 50a such that the upper surface 52 of the current receiving portion 50a is partially exposed. In other words, the upper insulating layer 63 has through holes 64 that expose the upper surface 52 of the current receiving portion 50a. As shown in Figure 2, a portion of the upper insulating layer 63 overlaps the current receiving portion 50a from above the lower insulating layer 61.

[0090] More specifically, the upper insulating layer 63 includes a flat portion 63a, a first end portion 63b, and a second end portion 63c. The flat portion 63a is provided on the upper surface 56 of the main surface source electrode 55 and has a substantially uniform thickness. A portion of the flat portion 63a is also provided on the upper surface 52 of the power receiving portion 50a.

[0091] The first end portion 63b is provided on the upper surface 52 of the current receiving portion 50a of the main surface gate electrode 50. The second end portion 63c is provided on the upper surface 56 of the main surface source electrode 55. The first end portion 63b and the second end portion 63c are each portions having non-uniform thickness. The first end portion 63b and the second end portion 63c are each inclined, for example, so that their thickness decreases gradually. The first end portion 63b and the second end portion 63c may have inclined surfaces with a constant inclination angle, or they may have curved surfaces that are convex or concave.

[0092] In a plan view, the size and shape of the through-hole 64 are approximately the same as the size and shape of the current-receiving portion 50a of the main surface gate electrode 50. Specifically, in a plan view, the size of the through-hole 64 is smaller than the current-receiving portion 50a because a portion of the upper insulating layer 63 overlaps the current-receiving portion 50a.

[0093] The end insulating layer 65 is provided on the first main surface 11 along the outer circumference of the main surface source electrode 55. For example, the end insulating layer 65 is formed in an annular shape so as to cover the entire circumference of the main surface source electrode 55 in a plan view. As shown in Figure 2, the end insulating layer 65 has a portion that overlaps the lower insulating layer 61 and an electrode covering portion that overlaps the main surface source electrode 55 (upper surface 56).

[0094] The electrode covering portion of the end insulating layer 65 has a flat portion 65a and an end portion 65b. The flat portion 65a is a portion with substantially uniform thickness. The end portion 65b is a portion with non-uniform thickness. The end portion 65b is inclined, for example, so that its thickness decreases gradually. The end portion 65b may have an inclined surface with a constant inclination angle, or it may have a curved surface that is convex or concave. The end insulating layer 65 may cover the power supply portion 50b of the main surface gate electrode 50 shown in Figure 4.

[0095] The lower insulating layer 61 mainly comprises, for example, silicon oxide or silicon nitride. The lower insulating layer 61, the side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as examples of silicon oxide.

[0096] The side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may each contain a photosensitive resin. The side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may each be made of an organic material such as polyimide or PBO (polybenzoxazole). The thickness of the upper insulating layer 63 and the end insulating layer 65 is, for example, 3 μm or more and 20 μm or less. The thickness of the upper insulating layer 63 and the end insulating layer 65 may preferably be 5 μm or more and 15 μm or less. The thickness of the upper insulating layer 63 and the end insulating layer 65 may more preferably be 5 μm or more and 10 μm or less. The lower insulating layer 61, the side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may be formed of the same insulating material (for example, an inorganic insulating material such as silicon oxide or silicon nitride).

[0097] The gate pad 70 is an example of a first electrode pad. In a plan view, the gate pad 70 overlaps the main surface gate electrode 50 and is electrically connected to the main surface gate electrode 50. The gate pad 70 completely covers the current receiving portion 50a of the main surface gate electrode 50. That is, in a plan view, the current receiving portion 50a of the main surface gate electrode 50 is located inside the gate pad 70.

[0098] In a plan view, the gate pad 70 overlaps with a portion of the main surface source electrode 55. In other words, a portion of the main surface source electrode 55 is located directly beneath the gate pad 70. In this configuration, since the main surface source electrode 55 is extended to the region that overlaps with the gate pad 70 in a plan view, a portion of the region where the gate pad 70 overlaps with the main surface source electrode 55 can be used as the active region 3. This allows for securing a larger area for the active region 3 while maintaining the area of ​​the gate pad 70.

[0099] As shown in Figure 2, the gate pad 70 includes a columnar portion 71 and a wide portion 72. The columnar portion 71 is an example of a first conductive layer provided on the main surface gate electrode 50. The columnar portion 71 extends columnarly in the direction normal to the upper surface 52 of the current receiving portion 50a of the main surface gate electrode 50 (in the z-axis direction).

[0100] The columnar portion 71 covers the upper surface 52 of the power receiving section 50a. The columnar portion 71 further covers a portion of the flat section 63a and the first end portion 63b of the upper insulating layer 63. The height (length in the z-axis direction) of the columnar portion 71 is greater than (longer than) the thickness (length in the z-axis direction) of the upper insulating layer 63. Specifically, the height of the columnar portion 71 is greater than (longer than) the maximum thickness of the portion of the upper insulating layer 63 located on the power receiving section 50a. As a result, the highest point of the columnar portion 71 is higher than the highest point of the upper insulating layer 63.

[0101] The columnar portion 71 has a side surface 74 that extends vertically or substantially vertically. The side surface 74 does not necessarily have to extend in a straight line in cross-sectional view, but may extend in a curved or uneven manner. The side surface 74 is located above the region where the power receiving portion 50a and the upper insulating layer 63 overlap in plan view. Specifically, the side surface 74 is located on the flat portion 63a of the upper insulating layer 63. In other words, the columnar portion 71 covers the power receiving portion 50a and the upper insulating layer 63. By positioning the side surface 74 on the flat portion 63a, the columnar portion 71 can be formed more stably compared to when it is positioned on the first end portion 63b, which has relatively large variations in thickness.

[0102] The wide portion 72 is an example of a second conductive layer provided at the upper end of the columnar portion 71. The wide portion 72 is a portion that is an enlargement of the size of the upper end of the columnar portion 71 in the xy plane. In plan view, the size and shape of the wide portion 72 match the size and shape of the gate pad 70 in plan view. In plan view, the wide portion 72 is larger than the columnar portion 71. In plan view, the columnar portion 71 is located inside the wide portion 72.

[0103] In a plan view, the contour of the wide portion 72 is formed at a constant distance from the contour of the columnar portion 71 toward the peripheral edge of the semiconductor layer 10. In a plan view, the wide portion 72 (gate pad 70) overlaps with a part of the active region 3 and the inactive region 4. In other words, in a plan view, the wide portion 72 (gate pad 70) overlaps with the trench gate structure 21 and the trench source structure 31.

[0104] The wide portion 72 has an upper surface 73 that is used for electrical connection between the semiconductor device 1 (vertical transistor 2) and other circuits. In this configuration, the upper surface 73 of the wide portion 72 is formed in an island shape in plan view and is connected to a power supply circuit that supplies the gate voltage. That is, in this configuration, the gate pad 70 is not formed in a line shape, unlike the main gate electrode 50. For example, a metal wire is connected to the upper surface 73 of the wide portion 72 by wire bonding. The metal wire includes at least one of the metals, such as aluminum, copper, or gold. In this configuration, an aluminum wire is wedge-bonded to the gate pad (upper surface 73 of the wide portion 72).

[0105] For wire bonding to be performed properly, the wide portion 72 must be of a certain size or larger. The plan view shape of the wide portion 72 is, for example, a square. In this case, the size of the wide portion 72 may be, for example, 800 μm × 800 μm or more and 1 mm × 1 mm or less. In this case, the orientation of the connection of the metal wire to the wide portion 72 can be any direction. Of course, the size of the wide portion 72 may be larger than 1 mm × 1 mm. Also, the plan view shape of the wide portion 72 may be a rectangle. In this case, the size of the wide portion 72 may be 400 μm × 800 μm or more.

[0106] In a plan view, the area of ​​the wide portion 72 (i.e., the area of ​​the gate pad 70) is larger than the area of ​​the power receiving portion 50a of the main surface gate electrode 50. In other words, in a plan view, the connection area of ​​the connection between the main surface gate electrode 50 and the gate pad 70 is less than the area of ​​the upper surface 73 of the gate pad 70. The area of ​​the wide portion 72 is between 200 and 40,000 times the area of ​​the power receiving portion 50a. The area of ​​the wide portion 72 may be 400 times or more the area of ​​the power receiving portion 50a. For example, the area of ​​the wide portion 72 may be about 2,500 times the area of ​​the power receiving portion 50a.

[0107] The columnar portion 71 contains a metallic material such as copper or a copper alloy with copper as the main component. The wide portion 72 contains a metallic material such as copper or a copper alloy with copper as the main component. The wide portion 72 is formed, for example, using the same conductive material as the columnar portion 71. The wide portion 72 may be formed from a different conductive material than the columnar portion 71.

[0108] The height (length in the z-axis direction) of the gate pad 70 is the sum of the height (length in the z-axis direction) of the columnar portion 71 and the thickness (length in the z-axis direction) of the wide portion 72. The height of the gate pad 70 is, for example, greater than 0 mm and less than or equal to 1 mm (for example, between several tens of micrometers and several hundred micrometers). As shown in Figure 2, the height of the columnar portion 71 is greater (longer) than the thickness of the wide portion 72. The height of the columnar portion 71 may be less than or equal to the thickness of the wide portion 72.

[0109] In a plan view, the source pad 75 overlaps with the main surface source electrode 55 and is electrically connected to the main surface source electrode 55. The source pad 75 is provided on the main surface source electrode 55. The source pad 75 extends in a thick plate shape in the direction normal to the upper surface 56 of the main surface source electrode 55 (in the z-axis direction). In a plan view, the area of ​​the source pad 75 is smaller than the area of ​​the main surface source electrode 55.

[0110] The source pad 75 covers the upper surface 56 of the main surface source electrode 55. The source pad 75 also covers a portion of the flat portion 63a and the second end portion 63c of the upper insulating layer 63. Furthermore, the source pad 75 covers a portion of the flat portion 65a and the end portion 65b of the end insulating layer 65. The thickness (length in the z-axis direction) of the source pad 75 is greater (longer) than the thickness (length in the z-axis direction) of the upper insulating layer 63 and the end insulating layer 65, respectively.

[0111] Specifically, the thickness of the source pad 75 is greater (longer) than the maximum thickness of the upper insulating layer 63 located on the main surface source electrode 55, and the maximum thickness of the end insulating layer 65 located on the main surface source electrode 55. As a result, the top of the source pad 75 is higher than the top of the upper insulating layer 63 and the top of the end insulating layer 65.

[0112] The source pad 75 has a side surface 77 that extends vertically or substantially vertically. The side surface 77 does not necessarily have to extend in a straight line in cross-sectional view, but may extend in a curved or uneven manner. The side surface 77 is located in a region where the main surface source electrode 55 and the upper insulating layer 63 overlap in a plan view, or in a region where the main surface source electrode 55 and the end insulating layer 65 overlap in a plan view.

[0113] Specifically, the side surface 77 is located on the flat portion 63a of the upper insulating layer 63, or on the flat portion 65a of the end insulating layer 65. In other words, the source pad 75 is in contact with the main surface source electrode 55 and the upper insulating layer 63, or with the main surface source electrode 55 and the end insulating layer 65. In this configuration, the source pad 75 is in contact with the main surface source electrode 55, the upper insulating layer 63, and the end insulating layer 65. This allows the source pad 75 to be formed stably, similar to the case of the columnar portion 71.

[0114] The source pad 75 has a top surface 76 that is used for electrical connection between the semiconductor device 1 (vertical transistor 2) and other circuits. In this configuration, the top surface 76 of the source pad 75 is connected to a power supply circuit that supplies the source voltage. For example, a metal wire is connected to the top surface 76 of the source pad 75 by wire bonding. The metal wire includes at least one of the metals, such as aluminum, copper, or gold. In this configuration, an aluminum wire is wedge-bonded to the source pad 75.

[0115] The source pad 75 is spaced apart from the gate pad 70 in a plan view. This prevents short circuits caused by contact between the source pad 75 and the gate pad 70. The source pad 75 is made of a conductive material. Specifically, the source pad 75 includes metallic materials such as copper or copper alloys. For example, the source pad 75 is made of the same material as the gate pad 70. In this case, the source pad 75 can be formed using the same process as the gate pad 70. The source pad 75 may also be made of a different material than the gate pad 70.

[0116] The source pad 75 has an area of ​​50% or more of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the source pad 75 has an area of ​​70% or more of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. On the other hand, the gate pad 70 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the gate pad 70 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view.

[0117] The source pad 75 is located in a region that includes the center of the semiconductor layer 10 (first main surface 11) in a plan view. The gate pad 70 is located in a region that avoids the source pad 75. The gate pad 70 may also be located in a region that includes the center of the semiconductor layer 10 (first main surface 11). In this case, the source pad 75 may be located so as to surround the gate pad 70.

[0118] The semiconductor device 1 includes a mold layer 80 filled between the source pad 75 and the gate pad 70. Specifically, the mold layer 80 fills the space between the gate pad 70 and the source pad 75. The mold layer 80 also covers the upper insulating layer 63 and the end insulating layer 65. Furthermore, the mold layer 80 is provided in an annular shape along the outer periphery of the semiconductor layer 10 (the periphery of the first main surface 11) in a plan view.

[0119] The mold layer 80 is formed of an insulating material. The mold layer 80 may also contain a thermosetting resin. For example, the mold layer 80 may contain an epoxy resin. For example, the mold layer 80 may contain an epoxy resin containing carbon, glass fibers, etc. The thickness (length in the z-axis direction) of the mold layer 80 is, for example, greater than 0 mm and less than or equal to 1 mm (for example, more than several tens of micrometers and less than or equal to several hundred micrometers). The thickness of the mold layer 80 may be greater than the thickness of the semiconductor layer 10.

[0120] In this configuration, the mold layer 80 has an upper surface 81 that is flush with the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75. That is, no steps are formed at the boundaries between the upper surface 73 of the gate pad 70, the upper surface 76 of the source pad 75, and the upper surface 81 of the mold layer 80. In this case, the upper surface 73 of the gate pad 70 may be a ground surface. The upper surface 76 of the source pad 75 may also be a ground surface. The upper surface 81 of the mold layer 80 may also be a ground surface. In other words, the upper surface 81 of the mold layer 80 may form a single ground surface with the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75.

[0121] The following describes a method for manufacturing the semiconductor device 1 according to the first embodiment. Figures 6A to 6G are cross-sectional views showing one step in the manufacturing process of the semiconductor device shown in Figure 1. The following description will focus particularly on the manufacturing method of the upper structure of the semiconductor layer 10. Known methods can be used for forming the trench gate structure 21, the trench source structure 31, and each well region (each semiconductor region) in the semiconductor layer 10.

[0122] First, as shown in Figure 6A, the lower insulating layer 61 is formed on the first main surface 11 of the semiconductor layer 10 (semiconductor wafer). The lower insulating layer 61 has a plurality of source contact holes 61b. For example, in this process, first, an insulating film containing silicon oxide or the like is deposited by plasma CVD (Chemical Vapor Deposition). Next, a portion of the deposited insulating film is removed by photolithography and etching. This forms the lower insulating layer 61 having a plurality of source contact holes 61b.

[0123] Next, as shown in Figure 6B, the main surface gate electrode 50 and the main surface source electrode 55 are formed. For example, in this process, first, a metal film is deposited over the entire surface of the first main surface 11 so as to cover the lower insulating layer 61 by vapor deposition or sputtering. Next, a portion of the deposited metal film is removed by photolithography and etching. This patterns the metal film, forming the main surface gate electrode 50 and the main surface source electrode 55. The main surface gate electrode 50 and the main surface source electrode 55 may be formed by repeating a metal film deposition process using different materials and a patterning process of the said metal film.

[0124] Next, as shown in Figure 6C, a side insulating layer 62, an upper insulating layer 63, and an end insulating layer 65 are formed. The upper insulating layer 63 has through holes 64. For example, this process includes a coating process and an exposure and development process. In the coating process, a liquid photosensitive resin material, which will form each insulating layer, is applied to the upper surface 52 of the main surface gate electrode 50 and the upper surface 56 of the main surface source electrode 55 by a spin coating method. In the exposure and development process, after the photosensitive resin material is cured by exposure, any unwanted portions of the photosensitive resin material are removed by an ashing method or a wet etching method. This forms the side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65.

[0125] Next, as shown in Figure 6D, the columnar portion 71 is formed on the current receiving portion 50a of the main surface gate electrode 50, and the lower source pad 75a is formed on the main surface source electrode 55. For example, in this step, a metal plating layer is selectively formed on at least a portion of the main surface gate electrode 50 that is not covered by the upper insulating layer 63, and on at least a portion of the main surface source electrode 55 that is not covered by the upper insulating layer 63, by electroplating or electroless plating.

[0126] A portion of the metal plating layer is also formed on the flat portion 63a, the first end portion 63b, and the second end portion 63c of the upper insulating layer 63. Furthermore, a portion of the metal plating layer is also formed on the flat portion 65a and the end portion 65b of the end insulating layer 65. The portion of the metal plating layer located on the current receiving portion 50a of the main gate electrode 50, and the portion located on the flat portion 63a and the first end portion 63b of the upper insulating layer 63, is formed as a columnar portion 71, which is part of the gate pad 70. The portion of the metal plating layer located on the main source electrode 55, and the portion located on the second end portion 63c of the upper insulating layer 63 and the end insulating layer 65, is formed as a lower source pad 75a, which is part of the source pad 75.

[0127] Next, as shown in Figure 6E, the lower mold layer 80a is formed. For example, this process includes a film formation step, a curing step, and a thinning step. In the film formation step, a liquid resin material (for example, epoxy resin as an example of a thermosetting resin) that will form the lower mold layer 80a is coated or printed over the entire surface of the first main surface 11 of the semiconductor layer 10. In this step, the resin material covers the entire columnar portion 71 and the lower source pad 75a. The resin material also fills the space between the columnar portion 71 and the lower source pad 75a.

[0128] In the curing process, the applied or printed resin material is cured by heating. In the thinning process, the resin material is ground until the columnar portion 71 and the lower source pad 75a are exposed. As a result, the upper surface of the columnar portion 71, the upper surface of the lower mold layer 80a, and the upper surface of the lower source pad 75a are made flush, as shown in Figure 6E.

[0129] Next, as shown in Figure 6F, the gate wiring layer 72b and the source wiring layer 75b are formed. The gate wiring layer 72b and the source wiring layer 75b are formed, for example, using the same material as the columnar portion 71 and the lower source pad 75a. In a plan view, the gate wiring layer 72b has the same size and shape as the wide portion 72 of the gate pad 70. In a plan view, the source wiring layer 75b has the same size and shape as the lower source pad 75a. The gate wiring layer 72b and the source wiring layer 75b function as seed wiring, which will be the starting point for film formation in the next plating process.

[0130] Next, as shown in Figure 6G, the wide portion 72a of the gate pad 70 is formed on the gate wiring layer 72b, and the upper source pad 75c of the source pad 75 is formed on the source wiring layer 75b. For example, in this step, a metal plating layer is selectively formed only on the upper surface of the gate wiring layer 72b and the upper surface of the source wiring layer 75b by electroplating or electroless plating.

[0131] Next, the upper mold layer 80b is formed, as shown in Figure 6H. For example, this step includes a film formation step, a curing step, and a thinning step. In the film formation step, for example, the entire wide portion 72a and the entire upper source pad 75c are covered with a resin material (for example, epoxy resin as an example of a thermosetting resin) by coating or printing.

[0132] In the curing process, the applied or printed resin material is cured by heating. In the thinning process, the resin material is ground until the wide portion 72a and the upper source pad 75c are exposed. As a result, the upper surface of the wide portion 72a, the upper surface of the upper mold layer 80b, and the upper surface of the upper source pad 75c are made flush, as shown in Figure 6H.

[0133] As a result, as shown in Figure 6H, the wide portion 72 of the gate pad 70 is formed by the gate wiring layer 72b and the wide portion 72a. The source pad 75 is formed by the lower source pad 75a, the source wiring layer 75b, and the upper source pad 75c. The mold layer 80 is composed of the lower mold layer 80a and the upper mold layer 80b.

[0134] As described above, the gate pad 70 and source pad 75 are formed by a two-stage plating process. In Figure 2 and other figures mentioned above, the specific layer structure of the gate pad 70, source pad 75, and mold layer 80 is not illustrated or explained. The explanation of the specific layer structure of the gate pad 70, source pad 75, and mold layer 80 also applies to Figure 2 and other figures mentioned above.

[0135] Next, the semiconductor layer 10 is thinned by polishing the second main surface 12a of the semiconductor layer 10. Then, a drain electrode 40 is formed on the second main surface 12 by vapor deposition or sputtering. After that, the semiconductor layer 10 and other components are selectively cut together with the mold layer 80 to manufacture the semiconductor device 1 shown in Figure 2.

[0136] The method for manufacturing the semiconductor device 1 is merely an example and is not limited to the method described above. For example, the gate pad 70 and source pad 75 may be formed by a film deposition method other than plating.

[0137] As described above, the semiconductor device 1 according to the first embodiment is a semiconductor device including a vertical transistor 2. The semiconductor device 1 includes a semiconductor layer 10, a vertical transistor 2, a gate electrode 20, a source electrode 30, a drain electrode 40, a main surface gate electrode 50, a main surface source electrode 55, and a gate pad 70.

[0138] The semiconductor layer 10 has a first main surface 11 and a second main surface 12 opposite to the first main surface 11, and mainly contains SiC. The vertical transistor 2 is provided on the first main surface 11. The gate electrode 20 is provided on the first main surface 11 as the gate electrode of the vertical transistor 2. The source electrode 30 is provided on the first main surface 11 at a distance from the gate electrode 20 as the source electrode of the vertical transistor 2.

[0139] The drain electrode 40 is provided on the second main surface 12 as the drain electrode of the vertical transistor 2. The main surface gate electrode 50 covers a portion of the first main surface 11. The main surface source electrode 55 is provided at a distance from the main surface gate electrode 50 in a plan view. The gate pad 70 overlaps the main surface gate electrode 50 in a plan view and is electrically connected to the main surface gate electrode 50. The main surface gate electrode 50 is smaller than the gate pad 70 in a plan view. For example, the main surface gate electrode 50 is electrically connected to the gate electrode 20. The main surface source electrode 55 is electrically connected to the source electrode 30.

[0140] If the main surface gate electrode 50 is used as an electrode pad for wire bonding instead of the gate pad 70, the main surface gate electrode 50 needs to be formed to the same size as the wide portion 72 of the gate pad 70. In this case, the region of the semiconductor layer 10 covered by the main surface gate electrode 50 is formed as an inactive region 4.

[0141] Therefore, the size of the inactive region 4 becomes the same size as the main surface gate electrode 50, which is formed to be the same size as the wide portion 72, so the active region 3 becomes smaller. In other words, the size of the inactive region 4 becomes significantly larger than the size of the inactive region 4 of the semiconductor device 1 according to this configuration. As a result, the active region 3 becomes smaller, making it difficult to effectively utilize the semiconductor layer 10, and miniaturization and cost reduction become difficult.

[0142] In contrast, according to the semiconductor device 1 of this form, a gate pad 70 (wide portion 72) connected to the main surface gate electrode 50 is provided, and wire bonding is performed to the gate pad 70 (wide portion 72). Therefore, while reducing the size of the main surface gate electrode 50, a gate pad 70 of sufficient size for proper wire bonding can be secured. As a result, the main surface gate electrode 50 can be reduced in size, and the area not covered by the main surface gate electrode 50 can be expanded and utilized as the active area 3. Thus, a semiconductor device 1 that can secure a wide operating area is realized.

[0143] For example, in a plan view, the gate pad 70 overlaps with a portion of the main surface source electrode 55. This allows the area directly below the wide portion 72 to be used as the active region 3. Furthermore, the main surface source electrode 55, located directly below the wide portion 72 of the gate pad 70, makes it easy to secure electrical connections to multiple source electrodes 30.

[0144] The second embodiment is described below. The second embodiment mainly differs from the first embodiment in that the semiconductor device further includes an electrode for current sensing and an electrode pad connected to the current sensing electrode, and the current sensing electrode is smaller than the electrode pad. The following description will focus on the differences from the first embodiment, and the descriptions of the common points will be omitted or simplified.

[0145] Figure 7 is a cross-sectional view of the semiconductor device 101 according to the second embodiment. Figure 8 is a plan view of the semiconductor device 101 shown in Figure 7. Figure 9 is a plan view of the electrode top surface of the semiconductor device 101 along the line IX-IX in Figure 7. Specifically, Figure 7 shows a cross-section along the line VII-VII in Figure 8. Specifically, Figure 9 is a plan view of the semiconductor device 101 as seen from the positive side of the z-axis, with a view through the gate pad 70, source pad 75, current sensing pad 170, and mold layer 80 shown in Figure 8. Although not shown in Figure 7, the semiconductor device 101 includes a vertical transistor 2 that conducts current in the thickness direction of the semiconductor layer 10, similar to the first embodiment.

[0146] As shown in Figures 7 to 9, the semiconductor device 101 includes a main surface gate electrode 50, a main surface source electrode 55, and a current sensing electrode 150. In the second embodiment, the main surface gate electrode 50 and the main surface source electrode 55 differ in arrangement or shape from those in the first embodiment, but their configurations are substantially the same as those in the first embodiment. Therefore, a description of the main surface gate electrode 50 and the main surface source electrode 55 in the second embodiment is omitted.

[0147] The current sensing electrode 150 is an example of a third electrode. In a plan view, the current sensing electrode 150 is positioned at a distance from the main surface gate electrode 50 and the main surface source electrode 55. In this embodiment, in a plan view, the current sensing electrode 150 is positioned in the region demarcated by the main surface gate electrode 50 and the main surface source electrode 55. The current sensing electrode 150 corresponds to a portion of the main surface source electrode 55 separated from the first embodiment.

[0148] The current sensing electrode 150 includes, for example, at least one of the following: conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, or a metal nitride such as titanium nitride. The current sensing electrode 150 is formed from, for example, the same material as the main surface gate electrode 50 and the main surface source electrode 55.

[0149] The current sensing electrode 150 is electrically connected to N (N-numer) source electrodes 30 out of a plurality of source electrodes 30 provided on the first main surface 11 of the semiconductor layer 10. N is a natural number. For example, N is 10 or less. The vertical transistor 2 included in the semiconductor device 101 can pass a drain current from the drain electrode 40 provided on the second main surface 12 of the semiconductor layer 10 to the plurality of source electrodes 30 provided on the first main surface 11 of the semiconductor layer 10. The current sensing electrode 150 is an electrode for extracting the current (one component of the drain current) flowing through N of the plurality of source electrodes 30. The N source electrodes 30 are used to detect the current (drain current) flowing through the vertical transistor 2.

[0150] As shown in Figure 7, the current sensing electrode 150 is provided on the lower insulating layer 61. The current sensing electrode 150 is electrically connected to one or more source electrodes 30 via one or more source contact holes 61b provided in the lower insulating layer 61. For example, the number of source contact holes 61b corresponds to N. In other words, by adjusting the number of source contact holes 61b, the number N of source electrodes 30 to which the current sensing electrode 150 is connected can be adjusted.

[0151] The main surface source electrode 55 is electrically connected to M source electrodes 30 out of a plurality of source electrodes 30. M is a natural number greater than N. For example, M is between 100 and 10,000 times N. Therefore, the current sensing electrode 150 connected to the N source electrodes 30 carries a current between 1 / 10,000 and 1 / 100 of the current flowing through the main surface source electrode 55.

[0152] This allows the current flowing through the current sensing electrode 150 to be reduced even if a large drain current flows between the drain electrode 40 and the multiple source electrodes 30 of the semiconductor device 101 due to some factor. For example, the maximum amount of current flowing through the current sensing electrode 150 can be limited to about 1A. This makes it possible to detect an increase in current within the detection range using the current sensing electrode 150. In other words, the increase or decrease in drain current can be indirectly detected within the detection range of the current sensing electrode 150.

[0153] The current sensing electrode 150 is smaller than the current sensing pad 170 in a plan view. The plan view shape of the current sensing electrode 150 is, for example, a square or a rectangle. The length of one side of the current sensing electrode 150 is between 5 μm and 50 μm. As an example, the current sensing electrode 150 may have a square plan view shape and a size of approximately 20 μm × 20 μm. As shown in Figure 9, the size of the current sensing electrode 150 is the same as the size of the current receiving portion 50a of the main surface gate electrode 50. The size of the current sensing electrode 150 may be smaller than the size of the current receiving portion 50a. The size of the current sensing electrode 150 may be larger than the size of the current receiving portion 50a.

[0154] The current sensing electrode 150 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the current sensing electrode 150 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11). In a plan view, the current sensing electrode 150 is positioned in a region that avoids the main surface source electrode 55 and the main surface gate electrode 50. The current sensing electrode 150 may be positioned in a region that includes the center of the semiconductor layer 10. In this case, the main surface source electrode 55 may be positioned to surround the current sensing electrode 150.

[0155] As shown in Figures 7 and 8, the semiconductor device 101 includes a gate pad 70, a source pad 75, and a current sensing pad 170. The gate pad 70 and source pad 75 in the second embodiment differ in arrangement or shape from those in the first embodiment, but their configurations are substantially the same as those in the first embodiment. Therefore, a description of the gate pad 70 and source pad 75 in the second embodiment is omitted.

[0156] The current sensing pad 170 is an example of a second electrode pad. In a plan view, the current sensing pad 170 overlaps with the current sensing electrode 150 and is electrically connected to the current sensing electrode 150. In the semiconductor device 101 according to this configuration, the current sensing pad 170 connected to the current sensing electrode 150 has the same configuration as the gate pad 70.

[0157] Specifically, as shown in Figure 7, the current sensing pad 170 includes a columnar portion 171 and a wide portion 172. The columnar portion 171 is an example of a first conductive layer provided on the current sensing electrode 150. The columnar portion 171 extends columnarly in the direction normal to the upper surface 152 of the current sensing electrode 150 (in the z-axis direction). The columnar portion 171 is connected to the current sensing electrode 150 via a through hole 164 provided in the upper insulating layer 63.

[0158] The columnar portion 171 covers the upper surface 152 of the current sensing electrode 150. The columnar portion 171 further covers a portion of the flat portion 63a and the first end portion 63b of the upper insulating layer 63. The height (length in the z-axis direction) of the columnar portion 171 is greater than (longer than) the thickness (length in the z-axis direction) of the upper insulating layer 63. Specifically, the height of the columnar portion 171 is greater than (longer than) the maximum thickness of the portion of the upper insulating layer 63 located on the current sensing electrode 150. As a result, the highest point of the columnar portion 171 is higher than the highest point of the upper insulating layer 63.

[0159] The columnar portion 171 has a side surface 174 that extends vertically or substantially vertically. The side surface 174 does not necessarily have to extend in a straight line in cross-sectional view, but may extend in a curved or uneven manner. The side surface 174 is located above the region where the current sensing electrode 150 and the upper insulating layer 63 overlap in plan view. Specifically, the side surface 174 is located on the flat portion 63a of the upper insulating layer 63. In other words, the columnar portion 171 covers the current sensing electrode 150 and the upper insulating layer 63. This allows the columnar portion 171 to be formed stably, similar to the columnar portion 71 according to the first embodiment.

[0160] The wide portion 172 is an example of a second conductive layer provided at the upper end of the columnar portion 171. The wide portion 172 is a portion obtained by expanding the size of the upper end of the columnar portion 171 in the xy plane. The size and shape of the wide portion 172 in plan view match the size and shape of the current sensing pad 170 in plan view. The wide portion 172 has an upper surface 173 that is used for electrical connection between the semiconductor device 101 (vertical transistor 2) and other circuits.

[0161] In this configuration, the upper surface 173 of the wide portion 172 is connected to a control circuit that controls the semiconductor device 101 (vertical transistor 2) based on the detected current. For example, a metal wire is connected to the upper surface 173 of the wide portion 172 by wire bonding. The metal wire includes at least one of the metals, such as aluminum, copper, or gold. In this configuration, an aluminum wire is wedge-bonded to the current sensing pad 170 (upper surface 173 of the wide portion 172).

[0162] For wire bonding to be performed properly, the wide portion 172 must be of a certain size or larger. The plan view shape of the wide portion 172 is, for example, a square. In this case, the size of the wide portion 172 may be between 800 μm × 800 μm and 1 mm × 1 mm. In this case, the orientation of the connection of the metal wire to the wide portion 172 can be any direction. The size of the wide portion 172 may be larger than 1 mm × 1 mm.

[0163] The plan view shape of the wide portion 172 may be rectangular. In this case, the size of the wide portion 172 may be 400 μm × 800 μm or larger. The size of the wide portion 172 is the same as the size of the wide portion 72 of the gate pad 70. The size of the wide portion 172 may be smaller than the size of the wide portion 72. The size of the wide portion 172 may be larger than the size of the wide portion 72.

[0164] In a plan view, the area of ​​the wide portion 172 (i.e., the area of ​​the current sensing pad 170) is larger than the area of ​​the current sensing electrode 150. The area of ​​the wide portion 172 is between 200 and 40,000 times the area of ​​the current sensing electrode 150. The area of ​​the wide portion 172 may be 400 times or more the area of ​​the current sensing electrode 150. For example, the area of ​​the wide portion 172 may be approximately 2,500 times the area of ​​the current sensing electrode 150.

[0165] The columnar portion 171 contains a metallic material such as copper or a copper alloy with copper as the main component. The wide portion 172 contains a metallic material such as copper or a copper alloy with copper as the main component. The wide portion 172 is formed, for example, using the same conductive material as the columnar portion 171. The wide portion 172 may be formed using a different conductive material than the columnar portion 171. The current sensing pad 170 is formed, for example, using the same material as the gate pad 70 and the source pad 75. This allows the current sensing pad 170, the gate pad 70, and the source pad 75 to be formed in the same process.

[0166] The height (length in the z-axis direction) of the current sensing pad 170 is the sum of the height (length in the z-axis direction) of the columnar portion 171 and the thickness (length in the z-axis direction) of the wide portion 172. The height of the current sensing pad 170 is, for example, greater than 0 mm and less than or equal to 1 mm (for example, between several tens of μm and several hundred μm). As shown in Figure 7, the height of the columnar portion 171 is greater (longer) than the thickness of the wide portion 172. The height of the columnar portion 171 may be less than or equal to the thickness of the wide portion 172.

[0167] The current sensing pad 170 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the current sensing pad 170 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. The current sensing pad 170 is also positioned in a region that avoids the gate pad 70 and the source pad 75. The current sensing pad 170 may also be positioned in a region that includes the center of the semiconductor layer 10 (first main surface 11). In this case, the source pad 75 may be positioned to surround the current sensing pad 170.

[0168] In this configuration, as shown in Figure 7, the semiconductor device 101 includes an active region 103 and an inactive region 104. The active region 103 is the main region through which the drain current of the vertical transistor 2 flows. In a plan view, the active region 103 is the region that overlaps with the main surface source electrode 55. The active region 103 does not include any region that overlaps with either the main surface gate electrode 50 or the current sensing electrode 150. On the other hand, a portion of the region that overlaps with the gate pad 70 and the current sensing pad 170 in a plan view is included in the active region 103.

[0169] The inactive region 104 is the region that does not operate as the vertical transistor 2. In a plan view, the inactive region 104 is the region other than the active region 103. As shown in Figure 7, the inactive region 104 includes the current sensing region 102. In a plan view, the current sensing region 102 is the region that overlaps with the current sensing electrode 150. In this configuration, the region that overlaps with the main surface gate electrode 50 or the current sensing electrode 150 in a plan view is included in the inactive region 104.

[0170] Specifically, in a plan view, the current sensing pad 170 overlaps with a portion of the main surface source electrode 55. In other words, a portion of the main surface source electrode 55 is located directly beneath the current sensing pad 170. In this configuration, since the main surface source electrode 55 is extended to the area that overlaps with the current sensing pad 170 in a plan view, a portion of the area where the current sensing pad 170 overlaps with the main surface source electrode 55 can be used as the active area 103. This allows for securing a larger area for the active area 103 while maintaining the area of ​​the current sensing pad 170.

[0171] As described above, the semiconductor device 101 according to the second embodiment further includes a plurality of source electrodes 30, a current sensing electrode 150, and a current sensing pad 170. The plurality of source electrodes 30 are arranged with space between them in a plan view. The current sensing electrode 150 is provided with space between it and the main surface gate electrode 50 and the main surface source electrode 55 in a plan view, and is electrically connected to N (N is a natural number) source electrodes 30. The current sensing pad 170 overlaps the current sensing electrode 150 in a plan view and is electrically connected to the current sensing electrode 150. The main surface source electrode 55 is electrically connected to M (M is a natural number greater than N) source electrodes 30. In a plan view, the current sensing electrode 150 is smaller than the current sensing pad 170.

[0172] As described above, the number N of source electrodes 30 to which the current sensing electrode 150 is connected (i.e., source electrodes 30 included in the current sensing region 102) may be, for example, 10 or less. In contrast, as shown in Figure 7, the number of source electrodes 30 included in the area 105 directly below the wide portion 172 of the current sensing pad 170 is far greater than 10.

[0173] Therefore, if the current sensing electrode 150 is used as an electrode pad for wire bonding instead of the current sensing pad 170, the current sensing electrode 150 needs to be formed to the same size as the wide portion 172 of the current sensing pad 170. In this case, the area 105 directly below the wide portion 172 of the current sensing pad 170 is formed as an inactive region 104.

[0174] Therefore, the size of the inactive region 104 becomes the same size as the current sensing electrode 150, which is formed to be the same size as the wide portion 172, resulting in a smaller active region 103. In other words, the size of the inactive region 104 becomes significantly larger than the size of the inactive region 104 of the semiconductor device 101 according to this configuration. As a result, the active region 103 becomes smaller, making it difficult to effectively utilize the semiconductor layer 10, thus hindering miniaturization and cost reduction.

[0175] In contrast, according to the semiconductor device 101 of this form, a current sensing pad 170 (wide portion 172) connected to the current sensing electrode 150 is provided, and wire bonding is performed on the current sensing pad 170 (wide portion 172). Therefore, while making the current sensing electrode 150 smaller, it is possible to secure a current sensing pad 170 that is large enough to properly perform wire bonding. Also, since the current sensing electrode 150 can be reduced in size, the area not covered by the current sensing electrode 150 can be expanded and used as the active area 103. Thus, a semiconductor device 101 that can secure a wide operating area is realized.

[0176] The method for manufacturing the semiconductor device 101 according to this embodiment is the same as the method for manufacturing the semiconductor device 1 according to the first embodiment. Specifically, the semiconductor device 101 can be manufactured by adjusting the shapes in each of the following steps: the patterning step for the main surface gate electrode 50, the main surface source electrode 55, and the current sensing electrode 150; the patterning step for the insulating layer 60; and the patterning step for the gate pad 70, the source pad 75, and the current sensing pad 170.

[0177] In this embodiment of the semiconductor device 101, an example was described in which the gate pad 70 has the same configuration as the current sensing pad 170, but the gate pad 70 may have the same configuration as the source pad 75.

[0178] Figure 10 is a plan view of a modified example of the semiconductor device 101 according to the second embodiment (hereinafter referred to as semiconductor device 101a). Figure 11 is a plan view of the upper electrode surface of the semiconductor device 101a shown in Figure 10. Figures 10 and 11 correspond to Figures 8 and 9 of the second embodiment, respectively.

[0179] In the modified semiconductor device 101a, the main surface gate electrode 50A and the gate pad 70a have the same size and shape in a plan view. That is, in a plan view, the main surface gate electrode 50A is larger than the power receiving portion 50a of the main surface gate electrode 50 according to the second embodiment. The current sensing electrode 150 and the current sensing pad 170 are the same as in the second embodiment. That is, the modified semiconductor device 101a includes the current sensing electrode 150 as an example of a first electrode, and the current sensing pad 170 as an example of a first electrode pad.

[0180] Thus, in the modified semiconductor device 101a, a configuration that increases the area in a plan view (specifically, the current sensing pad 170) is applied only to the current sensing electrode 150. This makes it possible to make the current sensing electrode 150 smaller than the current sensing pad 170 while still securing the area of ​​the pad for electrical connection to the current sensing electrode 150. Therefore, a portion of the area overlapping with the current sensing pad 170 in a plan view can be effectively used as the active area. Thus, a wider operating area can be secured.

[0181] The third embodiment is described below. In the third embodiment, the semiconductor device further includes a diode having electrodes and an electrode pad connected to the electrodes of the diode, the main difference from the first embodiment being that the electrodes of the diode are smaller than the electrode pad. The following description will focus on the differences from the first embodiment, and the descriptions of the commonalities will be omitted or simplified.

[0182] Figure 12 is a cross-sectional view showing the main part of the semiconductor device 201 according to the third embodiment. Figure 13 is a plan view of the semiconductor device 201 shown in Figure 12. Figure 14 is a plan view along the line XIV-XIV shown in Figure 12. Specifically, Figure 12 shows a cross-section along the line XII-XII in Figure 13. Specifically, Figure 14 is a plan view of the semiconductor device 201 as seen from the positive side of the z-axis, with a transparent view through the gate pad 70, source pad 75, anode electrode pad 270, cathode electrode pad 275, and mold layer 80 shown in Figure 13.

[0183] As shown in Figure 12, the semiconductor device 201 includes a diode 290 provided on the first main surface 11 of the semiconductor layer 10. In this embodiment, the diode 290 is a pn diode and includes a p-type semiconductor layer 291 and an n-type semiconductor layer 292. For example, the p-type semiconductor layer 291 contains polysilicon doped with p-type impurities, and the n-type semiconductor layer 292 contains polysilicon doped with n-type impurities. The p-type semiconductor layer 291 and the n-type semiconductor layer 292 are in contact with each other and constitute a pn diode having a pn junction.

[0184] The diode 290 is provided in a recess 293 located in the first main surface 11 of the semiconductor layer 10. The recess 293 is formed by excavating the first main surface 11 of the semiconductor layer 10 toward the second main surface 12. For example, the recess 293 has the same depth as the gate trench 22. The recess 293 can be formed in the same process as the gate trench 22.

[0185] The recess 293 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the recess 293 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. The recess 293 is provided in a region that avoids the main surface source electrode 55 and the main surface gate electrode 50 in a plan view. The recess 293 may be provided in a region that includes the center position of the semiconductor layer 10 (first main surface 11). In this case, the main surface source electrode 55 may be arranged to surround the recess 293.

[0186] The semiconductor device 201 includes an insulating layer 223 formed to cover the bottom and side walls of the recess 293. The insulating layer 223 is interposed between the semiconductor layer 10 and the diode 290. That is, the diode 290 is provided on the insulating layer 223. The insulating layer 223 includes, for example, silicon oxide. The insulating layer 223 may include at least one of impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The insulating layer 223 includes, for example, the same material as the gate insulating layer 23 and has the same thickness as the gate insulating layer 23. This allows the insulating layer 223 to be formed in the same process as the gate insulating layer 23.

[0187] The semiconductor layer 10 does not necessarily have to have either the recess 293 or the insulating layer 223, or both. The diode 290 may be provided on the first main surface 11 of the semiconductor layer 10. In this case, the diode 290 may be placed on the insulating layer 223 that covers the first main surface 11.

[0188] The diode 290 includes an anode electrode 250 and a cathode electrode 255. The temperature of the semiconductor device 201 can be detected by the magnitude of the voltage between the anode electrode 250 and the cathode electrode 255. In other words, the diode 290 is used as a temperature sensor (thermosensitive diode).

[0189] The anode electrode 250 is electrically connected to the p-type semiconductor layer 291. The anode electrode 250 includes, for example, at least one of the following: conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, or a metal nitride such as titanium nitride.

[0190] The cathode electrode 255 is electrically connected to the n-type semiconductor layer 292. As shown in Figure 14, the cathode electrode 255 is spaced apart from the anode electrode 250 in a plan view. In this configuration, the lower insulating layer 61 is provided between the cathode electrode 255 and the anode electrode 250. Furthermore, the anode electrode 250 and the cathode electrode 255 are spaced apart from the main surface gate electrode 50 and the main surface source electrode 55, respectively, in a plan view.

[0191] As shown in Figure 14, the main surface gate electrode 50 and main surface source electrode 55 in the third embodiment differ in arrangement and shape from those in the first embodiment, but their configurations are substantially the same as those in the first embodiment. Therefore, a description of the main surface gate electrode 50 and main surface source electrode 55 in the third embodiment is omitted.

[0192] The cathode electrode 255 includes, for example, at least one of the following: conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, or a metal nitride such as titanium nitride. The cathode electrode 255 may be formed using the same material as the anode electrode 250.

[0193] As shown in Figures 12 and 13, the semiconductor device 201 includes a gate pad 70, a source pad 75, an anode electrode pad 270, and a cathode electrode pad 275. The gate pad 70 and source pad 75 in the third embodiment differ in their arrangement and shape from those in the first embodiment, but their configurations are substantially the same as those in the first embodiment. Therefore, a description of the gate pad 70 and source pad 75 in the third embodiment is omitted.

[0194] In a plan view, the anode electrode pad 270 overlaps with the anode electrode 250 and is electrically connected to the anode electrode 250. In the semiconductor device 201 according to this embodiment, the anode electrode pad 270 connected to the anode electrode 250 has the same configuration as the gate pad 70.

[0195] Specifically, as shown in Figure 12, the anode electrode pad 270 includes a columnar portion 271 and a wide portion 272. The columnar portion 271 is an example of a first conductive layer provided on the anode electrode 250. The columnar portion 271 extends columnarly in the direction normal to the upper surface 251 of the anode electrode 250 (in the z-axis direction).

[0196] The wide portion 272 is an example of a second conductive layer provided at the upper end of the columnar portion 271. The wide portion 272 is a portion obtained by expanding the size of the upper end of the columnar portion 271 in the xy plane. The size and shape of the wide portion 272 in plan view correspond to the size and shape of the anode electrode pad 270 in plan view. The wide portion 272 has an upper surface 273 that is used for electrical connection between the semiconductor device 201 (diode 290) and other circuits.

[0197] In this configuration, the upper surface 273 of the wide portion 272 is connected to a voltmeter or the like for detecting the voltages of the anode electrode 250 and the cathode electrode 255. For example, a metal wire is connected to the upper surface 273 of the wide portion 272 by wire bonding. The metal wire includes at least one of the metals, such as aluminum, copper, or gold. In this configuration, an aluminum wire is wedge-bonded to the anode electrode pad 270 (upper surface 273 of the wide portion 272).

[0198] For wire bonding to be performed properly, the wide portion 272 must be of a certain size or larger. The shape and size of the wide portion 272 in plan view are, for example, the same as the shape and size of the wide portion 72 of the gate pad 70 in plan view. At least one of the shape and size of the wide portion 272 in plan view may differ from the shape and size of the wide portion 72 in plan view.

[0199] In a plan view, the area of ​​the wide portion 272 (i.e., the area of ​​the anode electrode pad 270) is larger than the area of ​​the anode electrode 250. The area of ​​the wide portion 272 may be between 200 and 40,000 times the area of ​​the anode electrode 250. The area of ​​the wide portion 272 may be 400 times or more the area of ​​the anode electrode 250. For example, the area of ​​the wide portion 272 may be about 2,500 times the area of ​​the anode electrode 250.

[0200] The columnar portion 271 includes a metallic material such as copper or a copper alloy with copper as the main component. The wide portion 272 also includes a metallic material such as copper or a copper alloy with copper as the main component. The wide portion 272 is formed, for example, using the same conductive material as the columnar portion 271. The wide portion 272 may be formed using a different conductive material than the columnar portion 271.

[0201] The height (length in the z-axis direction) of the anode electrode pad 270 is the sum of the height (length in the z-axis direction) of the columnar portion 271 and the thickness (length in the z-axis direction) of the wide portion 272. The height of the anode electrode pad 270 is, for example, greater than 0 mm and less than or equal to 1 mm (for example, between several tens of μm and several hundred μm). As shown in Figure 12, the height of the columnar portion 271 is greater (longer) than the thickness of the wide portion 272. The height of the columnar portion 271 may be less than or equal to the thickness of the wide portion 272.

[0202] In a plan view, the cathode electrode pad 275 overlaps with the cathode electrode 255 and is electrically connected to the cathode electrode 255. In the semiconductor device 201 according to this embodiment, the cathode electrode pad 275 connected to the cathode electrode 255 has the same configuration as the gate pad 70 and the anode electrode pad 270.

[0203] Specifically, as shown in Figure 12, the cathode electrode pad 275 includes a columnar portion 276 and a wide portion 277. The columnar portion 276 is an example of a first conductive layer provided on the cathode electrode 255. The columnar portion 276 extends columnarly in the direction normal to the upper surface 256 of the cathode electrode 255 (in the z-axis direction).

[0204] The wide portion 277 is an example of a second conductive layer provided at the upper end of the columnar portion 276. The wide portion 277 is the portion obtained by expanding the size of the upper end of the columnar portion 276 in the xy plane. The size and shape of the wide portion 277 in plan view correspond to the size and shape of the cathode electrode pad 275 in plan view.

[0205] The wide portion 277 has an upper surface 278 that is used for electrical connection between the semiconductor device 201 (diode 290) and other circuits. In this configuration, the upper surface 278 of the wide portion 277 is connected to a voltmeter or the like that detects the voltages of the anode electrode 250 and the cathode electrode 255. For example, a metal wire is connected to the upper surface 278 of the wide portion 277 by wire bonding.

[0206] Regarding shape and material, the columnar portion 276 and wide portion 277 of the cathode electrode pad 275 are the same as the columnar portion 276 and wide portion 277 of the anode electrode pad 270, respectively. Therefore, a description of the shape and material of the cathode electrode pad 275 is omitted.

[0207] The anode electrode pad 270 and cathode electrode pad 275 are formed using, for example, the same material as the gate pad 70 and source pad 75. This allows the anode electrode pad 270, cathode electrode pad 275, gate pad 70, and source pad 75 to be formed in the same process.

[0208] The semiconductor device 201 may include an insulating layer (not shown) that covers a portion of the upper surface 251 of the anode electrode 250 and a portion of the upper surface 256 of the cathode electrode 255. The insulating layer is made of an organic material such as polyimide or PBO. In this case, the side surfaces of the columnar portion 271 of the anode electrode pad 270 and the side surfaces of the columnar portion 276 of the cathode electrode pad 275 may be provided on the flat portion of the insulating layer, similar to the side surface 74 of the columnar portion 71 in the first embodiment.

[0209] The anode electrode pad 270 and the cathode electrode pad 275 each have an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the anode electrode pad 270 and the cathode electrode pad 275 have an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view.

[0210] Furthermore, the anode electrode pad 270 and the cathode electrode pad 275 are arranged in a region that avoids the gate pad 70 and the source pad 75. One of the anode electrode pad 270 and the cathode electrode pad 275 may be arranged in a region that includes the center of the semiconductor layer 10 (first main surface 11), and the source pad 75 may be arranged to surround the anode electrode pad 270 and the cathode electrode pad 275.

[0211] In this configuration, as shown in Figure 12, the semiconductor device 201 includes an active region 203 and an inactive region 204. The active region 203 is the main region through which the drain current of the vertical transistor 2 flows. In a plan view, the active region 203 is the region that overlaps with the main surface source electrode 55. The active region 203 does not include any region that overlaps with either the main surface gate electrode 50 or the recess 293. Part of the region that overlaps with the gate pad 70, anode electrode pad 270, and cathode electrode pad 275 in a plan view is included in the active region 103.

[0212] The inactive region 204 is the region that does not operate as a vertical transistor 2. In a plan view, the inactive region 204 is the region other than the active region 203. As shown in Figure 12, a diode 290 is formed in the inactive region 204. In this configuration, the region that overlaps with the main surface gate electrode 50 or the recess 293 in a plan view is included in the inactive region 204.

[0213] Specifically, the anode electrode pad 270 and the cathode electrode pad 275 overlap a portion of the main surface source electrode 55 in a plan view. In other words, a portion of the main surface source electrode 55 is located directly below the anode electrode pad 270 and directly below the cathode electrode pad 275, respectively. In this configuration, the main surface source electrode 55 is extended to a region that overlaps with the anode electrode pad 270 or the cathode electrode pad 275 in a plan view.

[0214] Therefore, a portion of the area where the main surface source electrode 55 and the anode electrode pad 270 overlap, or a portion of the area where the main surface source electrode 55 and the cathode electrode pad 275 overlap, can be used as the active region 203. This allows for securing a larger area for the active region 203 while maintaining the area of ​​the anode electrode pad 270 and the cathode electrode pad 275.

[0215] As described above, the semiconductor device 201 according to this embodiment includes a diode 290, an anode electrode pad 270, and a cathode electrode pad 275. The diode 290 includes an anode electrode 250 and a cathode electrode 255 and is provided on the first main surface 11. The anode electrode pad 270 overlaps the anode electrode 250 in a plan view and is electrically connected to the anode electrode 250. The cathode electrode pad 275 overlaps the cathode electrode 255 in a plan view and is electrically connected to the cathode electrode 255. The anode electrode 250 is smaller than the anode electrode pad 270 in a plan view. The cathode electrode 255 is smaller than the cathode electrode pad 275 in a plan view.

[0216] If the anode electrode 250 is used as an electrode pad for wire bonding instead of the anode electrode pad 270, the anode electrode 250 needs to be the same size as the wide portion 272. On the other hand, if the cathode electrode 255 is used as an electrode pad for wire bonding instead of the cathode electrode pad 275, the cathode electrode 255 needs to be the same size as the wide portion 277.

[0217] In these cases, the region covered by the anode electrode 250 and the cathode electrode 255 is formed as an inactive region 204. Therefore, the size of the inactive region becomes the same size as the anode electrode 250 and the cathode electrode 255, which are formed to be the same size as the wide portion 272 and the wide portion 277, resulting in a smaller active region 203. In other words, the size of the inactive region becomes significantly larger than the size of the inactive region 204 of the semiconductor device 201 according to this configuration. As a result, the semiconductor layer 10 cannot be used effectively, making miniaturization and cost reduction difficult.

[0218] In contrast, according to the semiconductor device 201 of this form, an anode electrode pad 270 (wide portion 272) connected to the anode electrode 250 is provided, and a cathode electrode pad 275 (wide portion 277) connected to the cathode electrode 255 is provided. Wire bonding is performed on the anode electrode pad 270 (wide portion 272) and the cathode electrode pad 275 (wide portion 277), respectively.

[0219] Therefore, while reducing the size of the anode electrode 250 and cathode electrode 255, it is possible to secure anode electrode pads 270 and cathode electrode pads 275 that are each large enough to perform wire bonding properly. Furthermore, since the anode electrode 250 and cathode electrode 255 can be reduced in size, the area not covered by the anode electrode 250 or cathode electrode 255 can be expanded and utilized as the active area 203. In this way, a semiconductor device 201 with a wide operating area is realized.

[0220] The method for manufacturing the semiconductor device 201 according to this embodiment is the same as the method for manufacturing the semiconductor device 1 according to the first embodiment. Specifically, the semiconductor device 201 can be manufactured by adjusting the shapes in each of the following steps: the patterning step of the main surface gate electrode 50, the main surface source electrode 55, the anode electrode 250 and the cathode electrode 255, the patterning step of the insulating layer 60, and the patterning step of the gate pad 70, the source pad 75, the anode electrode pad 270 and the cathode electrode pad 275.

[0221] In this embodiment of the semiconductor device 201, an example was described in which the gate pad 70 has the same configuration as the anode electrode pad 270 and the cathode electrode pad 275, but the gate pad 70 may also have the same configuration as the source pad 75.

[0222] Figure 15 is a plan view of a modified example of the semiconductor device 201 according to the third embodiment (hereinafter referred to as semiconductor device 201a). Figure 16 is a plan view showing the top surface of the electrodes of the semiconductor device 201a shown in Figure 15. Figures 15 and 16 correspond to Figures 13 and 14 of the third embodiment, respectively.

[0223] In the modified semiconductor device 201a, the main gate electrode 50A and the gate pad 70a have the same size and shape in a plan view. In other words, in a plan view, the main gate electrode 50A is larger than the power receiving portion 50a of the main gate electrode 50 according to the third embodiment.

[0224] The anode electrode 250, cathode electrode 255, anode electrode pad 270, and cathode electrode pad 275 are the same as in the third embodiment. That is, the modified semiconductor device 201a includes an anode electrode 250 as an example of a first electrode and an anode electrode pad 270 as an example of a first electrode pad. The modified semiconductor device 201a includes a cathode electrode 255 as an example of a second electrode and a cathode electrode pad 275 as an example of a second electrode pad.

[0225] Thus, in the modified semiconductor device 201a, a configuration is applied that increases the area in a plan view only for the anode electrode 250 and the cathode electrode 255 (specifically, the anode electrode pad 270 and the cathode electrode pad 275). In other words, while securing the area of ​​the pads for electrical connection to the anode electrode 250 and the cathode electrode 255, the anode electrode 250 can be made smaller than the anode electrode pad 270, and the cathode electrode 255 can be made smaller than the cathode electrode pad 275.

[0226] This allows a portion of the area overlapping the anode electrode pad 270 or cathode electrode pad 275 in a plan view to be expanded and effectively utilized as the active area. Therefore, a wider operating area can be secured.

[0227] Either the anode electrode pad 270 or the cathode electrode pad 275 may have the same configuration as the source pad 75. For example, the anode electrode 250 and the anode electrode pad 270 may have the same shape and size in a plan view. The cathode electrode 255 and the cathode electrode pad 275 may have the same shape and size in a plan view.

[0228] Hereinafter, a semiconductor package having a semiconductor device will be described as a fourth embodiment. Figure 17 is a rear view showing an example of a semiconductor package 300 according to the fourth embodiment. Figure 18 is a front view showing the internal structure of the semiconductor package 300 shown in Figure 17.

[0229] As shown in Figures 17 and 18, the semiconductor package 300 is a so-called TO (Transistor Outline) type semiconductor package. The semiconductor package 300 includes a package body 301, terminals 302d, 302g, 302s, bonding wires 303g, bonding wires 303s, and semiconductor device 1.

[0230] The package body 301 is rectangular in shape. The package body 301 contains the semiconductor device 1. In other words, the package body 301 is a encapsulant that seals the semiconductor device 1. The package body 301 may contain epoxy resin. The package body 301 is formed from an epoxy resin containing, for example, carbon, glass fibers, etc.

[0231] Each of the terminals 302d, 302g, and 302s protrudes from the bottom of the package body 301 and is arranged in a row along the bottom of the package body 301. The terminals 302d, 302g, and 302s are formed of, for example, aluminum, but may be formed of other metallic materials such as copper.

[0232] Inside the package body 301, the gate pad 70 of the semiconductor device 1 is electrically connected to the terminal 302g by bonding wire 303g or the like. The source pad 75 of the semiconductor device 1 is electrically connected to the terminal 302s by bonding wire 303s or the like. The drain electrode 40 of the semiconductor device 1 is bonded to the wide portion of the terminal 302d located inside the package body 301 by solder or a sintered layer made of silver or copper.

[0233] The semiconductor package 300 may include semiconductor devices 101, 101a, 201, or 201a instead of semiconductor device 1. In this case, the package body 301 may further include terminals to which the current sensing pad 170 of semiconductor device 101 is connected. The package body 301 may also further include a plurality of terminals to which the anode electrode pad 270 and cathode electrode pad 275 of semiconductor device 201 are connected, respectively.

[0234] In summary, by including semiconductor devices 1, 101, 101a, 201, or 201a, the semiconductor package 300 can secure a wider operating area than when it includes a general semiconductor device.

[0235] The following describes other examples of the semiconductor package shown in Figure 17. Figure 19 is a front view showing another example of the semiconductor package 300 according to the fourth embodiment (hereinafter referred to as semiconductor package 400). The semiconductor package 400 shown in Figure 19 is a so-called DIP (Dual In-line Package) type semiconductor package. The semiconductor package 400 includes a package body 401, a plurality of terminals 402, and a semiconductor device 1.

[0236] The package body 401 is rectangular in shape. The package body 401 contains the semiconductor device 1. In other words, the package body 401 is a encapsulant that seals the semiconductor device 1. The package body 401 may contain epoxy resin. The package body 401 is formed from an epoxy resin containing, for example, carbon, glass fibers, etc.

[0237] Multiple terminals 402 protrude from the long side of the package body 401 and are arranged in a line along the long side of the package body 401. The multiple terminals 402 are formed of, for example, aluminum, but may be formed of other metallic materials such as copper.

[0238] Inside the package body 401, the gate pad 70, source pad 75, and drain electrode 40 of the semiconductor device 1 are electrically connected to the corresponding terminals 402 by bonding wires or the like. The semiconductor package 400 may contain multiple semiconductor devices 1. In other words, the package body 401 may contain multiple semiconductor devices 1.

[0239] The semiconductor package 400 may include semiconductor devices 101, 101a, 201, or 201a in place of or in addition to semiconductor device 1. In this case, within the package body 401, the current sensing pad 170 of semiconductor device 101, or the anode electrode pad 270 and cathode electrode pad 275 of semiconductor device 201, are electrically connected to the corresponding terminals 402 by bonding wires or the like.

[0240] In summary, by including semiconductor devices 1, 101, 101a, 201, or 201a, the semiconductor package 400 can secure a wider operating area than when it includes a general semiconductor device.

[0241] Figure 20 is a cross-sectional view showing the main parts of a semiconductor device 501 according to the first modified example of each embodiment described above. As described above, bonding wires are used for the electrical connection between the terminals of the semiconductor package 300 or 400 and the semiconductor devices 1, 101, 101a, 201 or 201a. If the bonding wire is made of aluminum, as shown in Figure 20, nickel layers may be formed on the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75, respectively, which are metal plating layers.

[0242] Figure 20 shows bonding wires 303g and 303s together as an example of bonding wires. As shown in Figure 20, the nickel layer 90 is an example of a metal layer formed from a different metal material than the metal material forming the gate pad 70 and source pad 75. The nickel layer 90 is a layer that mainly contains nickel. Specifically, the nickel layer 90 is a metal layer consisting of pure nickel.

[0243] Similarly, in the case of semiconductor devices 101, 101a, 201, or 201a, a nickel layer 90 may be provided on the upper surfaces of the current sensing pad 170, the anode electrode pad 270, and the cathode electrode pad 275.

[0244] Figure 21 is a cross-sectional view showing the main parts of a semiconductor device 601 according to a second modified example of each of the embodiments described above. As shown in Figure 21, the semiconductor device 601 may include a columnar portion 71 made of copper and a wide portion 672 made of nickel. The source pad 75 may include a lower source pad 75a made of copper and an upper source pad 675c made of nickel.

[0245] For example, the semiconductor device 601 shown in Figure 21 can be manufactured by performing a plating process using nickel instead of copper in the plating process shown in Figure 6G. In the example shown in Figure 21, the upper surface 73 of the wide portion 672, the upper surface 76 of the upper source pad 675c, and the upper surface 81 of the mold layer 80 are formed flush with each other.

[0246] In the example shown in Figure 20 or Figure 21, a layer other than the nickel layer may be formed on the outermost surface of the metal plating layer (specifically, the gate pad 70 and source pad 75) that forms the joint portion of the bonding wire made of aluminum. For example, a two-layer structure (i.e., a NiPd layer) including a nickel layer and a palladium layer provided on the nickel layer may be provided on the metal plating layer. Alternatively, a three-layer structure (e.g., a NiPdAu layer) may be formed on the upper surface of the two-layer structure, with another metal layer such as a gold (Au) layer formed thereon. The NiPd layer and NiPdAu layer are suitable not only when bonding wires are joined, but also when external terminals are joined by silver sintering.

[0247] The form of the semiconductor package including semiconductor devices 1, 101, 101a, 201, 201a, 501, or 601 is not limited to forms such as semiconductor package 300 and semiconductor package 400. The semiconductor package may be an SOP (Small Outline Package), QFN (Quad Flat Non-Lead Package), DFP (Dual Flat Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package). Furthermore, various similar semiconductor packages may be used as the semiconductor package.

[0248] Although semiconductor devices relating to one or more embodiments have been described above based on multiple embodiments, the present invention is not limited to these embodiments. Without departing from the spirit of the present invention, various modifications that can be conceived by those skilled in the art, as well as embodiments constructed by combinations of components from different embodiments, are also included within the scope of the present invention.

[0249] For example, in a plan view, the gate pad 70 may cover only a portion of the main surface gate electrode 50. In other words, the gate pad 70 does not have to completely cover the main surface gate electrode 50. Similar structures may be applied to the current sensing pad 170, the anode electrode pad 270, and the cathode electrode pad 275, respectively.

[0250] For example, in each embodiment, the conductivity type of each semiconductor region or semiconductor layer may be reversed. That is, an n-type semiconductor may be provided instead of a p-type semiconductor, and a p-type semiconductor may be provided instead of an n-type semiconductor.

[0251] For example, each mechanism, n + Instead of the type semiconductor substrate 13, p + A SiC semiconductor substrate of a certain type may be used. This allows the vertical transistor 2 to be formed as an IGBT (Insulated Gate Bipolar Transistor). In other words, a semiconductor device including an IGBT as a vertical transistor can be provided. In this case, the "source" of the MISFET is replaced with the "emitter" of the IGBT. Also, the "drain" of the MISFET is replaced with the "collector" of the IGBT. The emitter of the IGBT is an example of a first main electrode, and the collector of the IGBT is an example of a second main electrode. Even when the semiconductor device according to each embodiment includes an IGBT instead of a MISFET, it can achieve the same effects as described above.

[0252] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each item to the embodiments.

[0253] [A1] A method for manufacturing a semiconductor device (1, 101, 101a, 201, 201a) including a vertical transistor (2), comprising: a first step of forming a control electrode (20) and a first main electrode (30) of the vertical transistor (2) on the first main surface (11) of a semiconductor layer (10) having a first main surface (11) and a second main surface (12) opposite to the first main surface (11), and mainly composed of SiC, with a gap between them; and a part of the first main surface (11) A method for manufacturing semiconductor devices (1, 101, 101a, 201, 201a), comprising: a second step of forming one electrode (50, 250) and a first electrode (55, 255) spaced apart from each other; and a third step of forming a first electrode pad (70) electrically connected to the first electrode (50, 250) so as to overlap the first electrode (50, 250) in a plan view, wherein the first electrode (50, 250) is smaller than the first electrode pad (70) in a plan view.

[0254] [A2] A method for manufacturing a semiconductor device (1, 101, 101a, 201, 201a) according to A1, wherein the third step includes a fourth step of forming a first conductive layer (71) on the first electrodes (50, 250), a fifth step of forming an insulating layer (80) along the outer circumference of the first conductive layer (71) in a plan view, and a sixth step of forming a second conductive layer (72) larger than the first conductive layer (71) on the first conductive layer (71) and the insulating layer (80).

[0255] [A3] A method for manufacturing a semiconductor device (1, 101, 101a, 201, 201a) according to A2, wherein the sixth step is a seventh step of forming a wiring layer (72b) larger than the first conductive layer (71) on the first conductive layer (71) and the insulating layer (80), and an eighth step of selectively forming a metal plating layer (72a) on the wiring layer (72b).

[0256] [A4] The fifth step is to mold the first conductive layer (71) with a resin material (80b) so as to cover it, and then grind the molded resin material (80b) until the first conductive layer (71) is exposed to form the insulating layer (80), as described in A2 or A3, for the manufacturing of a semiconductor device (1, 101, 101a, 201, 201a).

[0257] [B1] A semiconductor device (1, 101, 101a, 201, 201a) including a vertical transistor (2), comprising a semiconductor layer (10) having a first main surface (11) and a second main surface (12) opposite to the first main surface (11), and mainly composed of SiC, a control electrode (20) of the vertical transistor (2) provided on the first main surface (11), a first main electrode (30) of the vertical transistor (2) provided on the first main surface (11) at a distance from the control electrode (20), and the second main surface (12) is provided with a second main electrode (40) of the vertical transistor (2), a first electrode (50, 250) covering a part of the first main surface (11), a first electrode (55, 255) provided at a distance from the first electrode (50, 250) in a plan view, and a first electrode pad (70) that overlaps with the first electrode (50, 250) in a plan view and is electrically connected to the first electrode (50, 250), wherein the first electrode (50, 250) is located on the first electrode pad (70) in a plan view. Smaller semiconductor devices (1, 10¹, 10¹a, 20¹, 20¹a).

[0258] [B2] The semiconductor device described in B1 (1, 101, 101a, 201, 201a), wherein the first electrode pad (70) overlaps with a portion of the first electrode (55, 255) in a plan view.

[0259] [B3] The semiconductor device (1, 101, 101a, 201, 201a) according to B1 or B2, wherein the first electrodes (50, 250) are electrically connected to the control electrode (20), and the first electrodes (55, 255) are electrically connected to the first main electrode (30).

[0260] [B4] Further, a plurality of the first main electrodes (30) arranged at intervals from each other in a plan view, a third electrode (150) provided at an interval from the first electrode (50, 250) and the first electrode (55, 255) in a plan view, and electrically connected to N (N is a natural number) of the first main electrodes (30), a second electrode pad (170) overlapping with the third electrode (150) in a plan view and electrically connected to the third electrode (150), wherein the first electrode (55, 255) is electrically connected to M (M is a natural number greater than N) of the first main electrodes (30), and the third electrode (150) is smaller than the second electrode pad (170) in a plan view, the semiconductor device (1, 101, 101a, 201, 201a) according to B3.

[0261] [B5] Further, including an anode electrode (250) and a cathode electrode (255), a diode (290) provided on the first main surface (11), an anode electrode pad (270) overlapping with the anode electrode (250) in a plan view and electrically connected to the anode electrode (250), and a cathode electrode pad (275) overlapping with the cathode electrode (255) in a plan view and electrically connected to the cathode electrode (255), wherein the anode electrode (250) is smaller than the anode electrode pad (270) in a plan view, and the cathode electrode (255) is smaller than the cathode electrode pad (275) in a plan view, the semiconductor device (1, 101, 101a, 201, 201a) according to B3 or B4.

[0262] [B6] Having a plurality of the first main electrodes (30), and the first electrode (50, 250) being electrically connected to one of the plurality of the first main electrodes (30), the semiconductor device (1, 101, 101a, 201, 201a) according to B1 or B2.

[0263] [B7] The semiconductor device (1, 101, 101a, 201, 201a) according to B1 or B2 further comprises a diode (290) provided on the first main surface (11) and a second electrode pad that overlaps the first electrode (55, 255) in a plan view and is electrically connected to the first electrode (55, 255), wherein the first electrode (50, 250) is the anode electrode (250) of the diode (290) and the first electrode (55, 255) is the cathode electrode (255) of the diode (290), and is smaller than the second electrode pad (170) in a plan view.

[0264] [C1] A semiconductor device (1, 101, 101a, 201, 201a) comprising: a semiconductor layer (10) having a main surface (11) and mainly composed of SiC; a gate structure (21) formed on the main surface (11); an insulating layer (61) formed on the main surface (11) so as to cover the gate structure (21); a gate main electrode (50) disposed on the insulating layer (61) and electrically connected to the gate structure (21); and a gate pad electrode (70) disposed on the gate main electrode (50) so as to be connected to the gate main electrode (50), and including a connection portion connected to the gate main electrode (50) with a first area in a plan view, and an electrode surface (73) having a second area exceeding the first area in a plan view.

[0265] [C2] The electrode surface (73) of the gate pad electrode (70) is exposed to the outside, as described in C1 (1, 101, 101a, 201, 201a).

[0266] [C3] The gate main electrode (50) is formed in a line shape on the insulating layer (61) in the semiconductor device described in C1 or C2 (1, 101, 101a, 201, 201a).

[0267] [C4] The semiconductor device according to any one of C1 to C3 (1, 101, 101a, 201, 201a), wherein the second area of ​​the electrode surface (73) exceeds the area of ​​the gate main electrode (50).

[0268] [C5] A semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C4, further comprising: active regions (3, 103, 203) provided in the semiconductor layer (10); and inactive regions (4, 104, 204) provided in the semiconductor layer (10) outside the active regions (3, 103, 203); wherein the gate structure (21) is formed in the active regions (3, 103, 203); the gate main electrode (50) is formed in the inactive regions (4, 104, 204) in a plan view; and the gate pad electrode (70) overlaps the active regions (3, 103, 203) and the inactive regions (4, 104, 204) in a plan view.

[0269] [C6] A semiconductor device according to any one of C1 to C5 (1, 101, 101a, 201, 201a), further comprising a current-conducting electrode (55) disposed on the insulating layer (61) at a distance from the gate main electrode (50).

[0270] [C7] The semiconductor device described in C6 (1, 101, 101a, 201, 201a) wherein the gate pad electrode (70) overlaps with a part of the current conduction electrode (55) in a plan view.

[0271] [C8] The semiconductor device according to C6 or C7 (1, 101, 101a, 201, 201a), further comprising a current-conducting pad electrode (75) disposed on the current-conducting electrode (55).

[0272] [C9] The current-conducting pad electrode (75) overlaps with a part of the gate main electrode (50) in a plan view, as described in C8 (1, 101, 101a, 201, 201a).

[0273] [C10] The semiconductor device according to C8 or C9 (1, 101, 101a, 201, 201a), wherein the current-conducting pad electrode (75) includes an electrode surface (76) having a third area that exceeds the second area of ​​the gate pad electrode (70) in a plan view.

[0274] [C11] A semiconductor device according to any one of C1 to C10 (1, 101, 101a, 201, 201a), further comprising a first resin layer (63, 65) that partially covers the gate main electrode (50) such that a part of the gate main electrode (50) is exposed on the insulating layer (61), and the gate pad electrode (70) is positioned on the portion of the gate main electrode (50) that is exposed from the first resin layer (63, 65).

[0275] [C12] The semiconductor device according to C11 (1, 101, 101a, 201, 201a), further comprising a second resin layer (80) that partially covers the first resin layer (63, 65) such that a portion of the gate main electrode (50) is exposed on the insulating layer (61), and the gate pad electrode (70) is positioned on the portion of the gate main electrode (50) that is exposed from the first resin layer (63, 65) and the second resin layer (80).

[0276] [C13] The semiconductor device (1, 101, 101a, 201, 201a) according to C12, wherein the first resin layer (63, 65) is made of a photosensitive resin layer and the second resin layer (80) is made of a thermosetting resin layer.

[0277] [C14] The gate structure (21) is a trench gate structure (21) as described in any one of C1 to C13 (1, 101, 101a, 201, 201a).

[0278] [C15] A semiconductor layer (10) having a main surface (11), active regions (3, 103, 203) provided on the semiconductor layer (10), inactive regions (4, 104, 204) provided in the semiconductor layer (10) outside the active regions (3, 103, 203), a plurality of gate structures (21) formed on the active regions (3, 103, 203), an insulating layer (61) formed on the main surface (11) so as to cover the plurality of gate structures (21), and a plurality of the gate structures A semiconductor device (1, 101, 101a, 201, 201a) includes a gate main electrode (50) disposed on the insulating layer (61) so as to be electrically connected to (21) and overlapping the inactive regions (4, 104, 204) in a plan view, and a gate pad electrode (70) disposed on the gate main electrode (50) so as to be electrically connected to the gate main electrode (50) and overlapping the active regions (3, 103, 203) and the inactive regions (4, 104, 204) in a plan view.

[0279] [C16] The gate main electrode (50) is a semiconductor device (1, 101, 101a, 201, 201a) as described in C15, which does not overlap the active region (3, 103, 203) in a plan view.

[0280] [C17] The semiconductor device (1, 101, 101a, 201, 201a) according to C15 or C16, wherein the gate pad electrode (70) includes a connecting portion connected to the gate main electrode (50) with a first area in a plan view, and an electrode surface (73) having a second area exceeding the first area in a plan view.

[0281] [C18] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C15 to C17, wherein the active regions (3, 103, 203) include a plurality of divided regions provided in the semiconductor layer (10) at intervals in a plan view, and the inactive regions (4, 104, 204) include portions located between the plurality of divided regions in the semiconductor layer (10) in a plan view.

[0282] [C19] The gate main electrode (50) includes a portion overlapping a portion located between the plurality of divided regions in the non-active region (4, 104, 204) in a plan view, and the gate pad electrode (70) includes a portion overlapping a portion located between the plurality of divided regions in the non-active region (4, 104, 204) in a plan view. The semiconductor device (1, 101, 101a, 201, 201a) according to C18.

[0283] [C20] The gate pad electrode (70) overlaps the plurality of divided regions in a plan view. The semiconductor device (1, 101, 101a, 201, 201a) according to C19.

[0284] [D1] A semiconductor device (1, 101, 101a, 201, 201a) including a semiconductor layer (10) having a main surface (11) and containing SiC as a main component, a diode structure (290, 291, 292) formed on the main surface (11), an insulating layer (61) formed on the main surface (11) so as to cover the diode structure (290, 291, 292), and a pair of polarity electrodes (250, 255) disposed on the insulating layer (61) and including a first polarity electrode (250 / 255) on one side and a second polarity electrode (255 / 250) on the other side that are electrically connected to the diode structure (290, 291, 292), and a first polarity pad electrode (270 / 275) disposed on the first polarity electrode (250 / 255) so as to be connected to the first polarity electrode (250 / 255), the first polarity pad electrode (270 / 275) including a first connection portion connected to the first polarity electrode (250 / 255) with a first area in a plan view and a first electrode surface (272 / 278) having a second area exceeding the first area in a plan view.

[0285] [D2] The second area of the first polarity pad electrode (270 / 275) exceeds the area of the first polarity electrode (250 / 255) in a plan view. The semiconductor device (1, 101, 101a, 201, 201a) according to D1.

[0286] [D3] A semiconductor device according to D1 or D2 (1, 101, 101a, 201, 201a), further comprising a second polar pad electrode (275 / 270) which is disposed on the second polar electrode (255 / 250) so as to be connected to the second polar electrode (255 / 250) and which is connected to the second polar electrode (255 / 250) in a third area in a plan view, and a second electrode surface (278 / 272) having a fourth area exceeding the third area.

[0287] [D4] The semiconductor device according to D3 (1, 101, 101a, 201, 201a), wherein the fourth area of ​​the second polar pad electrode (275 / 270) exceeds the area of ​​the second polar electrode (255 / 250) in a plan view.

[0288] [D5] The diode structure (290, 291, 292) includes a polysilicon layer, a first region (291 / 292) of a first conductivity type formed on the polysilicon layer, and a second region (292 / 291) of a second conductivity type formed on the polysilicon layer so as to form a pn junction with the first region (291 / 292), the first polar electrode (250 / 255) is electrically connected to the first region (291 / 292) of the diode structure (290, 291, 292), and the second polar electrode (255 / 250) is electrically connected to the second region (292 / 291) of the diode structure (290, 291, 292), the semiconductor device (1, 101, 101a, 201, 201a) according to any one of D1 to D4.

[0289] [D6] The semiconductor device (1, 101, 101a, 201, 201a) according to D5, further comprising a recess (293) formed in the main surface (11), wherein the diode structures (290, 291, 292) are arranged within the recess (293).

[0290] [D7] The semiconductor device (1, 101, 101a, 201, 201a) according to D6, wherein the diode structure (290, 291, 292) has an upper end located on the bottom wall side of the recess (293) with respect to the main surface (11).

[0291] [D8] A semiconductor device (1, 101, 101a, 201, 201a) according to any one of D1 to D7, further comprising: active regions (3, 103, 203) provided in the semiconductor layer (10); inactive regions (4, 104, 204) provided in the semiconductor layer (10) outside the active regions (3, 103, 203); and a gate structure (21) formed in the active regions (3, 103, 203).

[0292] [D9] The diode structures (290, 291, 292) are formed in the inactive regions (4, 104, 204) of the semiconductor device described in D8 (1, 101, 101a, 201, 201a).

[0293] [D10] The diode structure (290, 291, 292) is a semiconductor device (1, 101, 101a, 201, 201a) described in any one of D1 to D9 that functions as a temperature-sensitive diode.

[0294] [E1] A semiconductor device comprising: a semiconductor layer having a main surface and mainly composed of SiC; a gate structure formed on the main surface; an insulating layer formed on the main surface so as to cover the gate structure; a gate main electrode disposed on the insulating layer and electrically connected to the gate structure; a gate pad electrode disposed on the gate main electrode so as to be connected to the gate main electrode and including a connection portion connected to the gate main electrode with a first area in a plan view and an electrode surface having a second area exceeding the first area in a plan view; a current-conducting electrode disposed on the insulating layer at a distance from the gate main electrode; and a current-conducting pad electrode disposed on the current-conducting electrode, wherein the current-conducting pad electrode overlaps a part of the gate main electrode in a plan view.

[0295] [E2] The semiconductor device according to E1, wherein the electrode surface of the gate pad electrode is exposed to the outside.

[0296] [E3] The semiconductor device according to E1 or E2, wherein the gate main electrode is formed in a line shape on the insulating layer.

[0297] [E4] The semiconductor device according to any one of E1 to E3, wherein the second area of ​​the electrode surface exceeds the area of ​​the gate main electrode.

[0298] [E5] The semiconductor device according to any one of E1 to E4, further comprising an active region provided in the semiconductor layer and a non-active region provided in the semiconductor layer outside the active region, wherein the gate structure is formed in the active region, the gate main electrode is formed in the non-active region in a plan view, and the gate pad electrode overlaps the active region and the non-active region in a plan view.

[0299] [E6] The semiconductor device according to any one of E1 to E5, wherein the gate pad electrode overlaps a part of the current-conducting electrode in a plan view.

[0300] [E7] The semiconductor device according to any one of E1 to E6, wherein the current-conducting pad electrode includes an electrode surface having a third area that exceeds the second area of ​​the gate pad electrode in a plan view.

[0301] [E8] The semiconductor device according to any one of E1 to E7, wherein the gate structure consists of a trench gate structure.

[0302] [E9] The semiconductor device according to any one of E1 to E8, wherein the gate main electrode is formed in a line shape in a plan view.

[0303] [E10] The active region includes a plurality of divided regions provided in the semiconductor layer at intervals in a plan view, The semiconductor device according to E5, wherein the inactive region includes a portion located between a plurality of the divided regions in the semiconductor layer in a plan view.

[0304] [E11] The gate main electrode includes a portion that overlaps with the portion located between the plurality of division regions in the inactive region in a plan view, The semiconductor device according to E10, wherein the gate pad electrode includes a portion that overlaps with the portion located between the plurality of divided regions in the inactive region in a plan view.

[0305] [E12] The semiconductor device according to E10 or E11, wherein the gate pad electrode overlaps a plurality of the divided regions in a plan view.

[0306] [E13] The semiconductor device according to any one of E1 to E12, wherein at least one of the gate pad electrode and the current conduction pad electrode is made of copper or a copper alloy.

[0307] [E14] An active region provided in the semiconductor layer, The semiconductor layer further includes a non-active region provided in a region outside the active region, The gate structure includes a plurality of gate structures, Multiple gate structures are formed in the active region, The gate main electrode overlaps the inactive region in a plan view, The semiconductor device according to any one of E1 to E13, wherein the gate pad electrode overlaps the active region and the inactive region in a plan view.

[0308] [E15] In a plan view, the current-conducting pad electrode is arranged to surround the gate pad electrode, according to any one of E1 to E14.

[0309] [E16] The semiconductor device according to any one of E5, E10-E12, and E14, wherein, in a plan view, the area of ​​the first portion of the active region located in the region between the first edge of the semiconductor layer and the gate pad electrode is greater than the area of ​​the second portion of the active region located in the region between the second edge opposite the first edge of the semiconductor layer and the gate pad electrode.

[0310] [E17] A semiconductor device comprising: a semiconductor layer having a main surface; an active region provided in the semiconductor layer; a non-active region provided in the semiconductor layer outside the active region; a plurality of gate structures formed in the active region; an insulating layer formed on the main surface so as to cover the plurality of gate structures; a gate main electrode disposed on the insulating layer so as to be electrically connected to the plurality of gate structures and overlapping the non-active region in a plan view; and a gate pad electrode disposed on the gate main electrode so as to be electrically connected to the gate main electrode and overlapping the active region and the non-active region in a plan view, wherein the active region includes a plurality of divided regions provided in the semiconductor layer at intervals in a plan view; the non-active region includes a portion located between the plurality of divided regions in the semiconductor layer in a plan view; the gate main electrode includes a portion overlapping the portion located between the plurality of divided regions in the non-active region in a plan view; and the gate pad electrode includes a portion overlapping the portion located between the plurality of divided regions in the non-active region in a plan view.

[0311] [E18] The semiconductor device according to E17, wherein the gate main electrode is formed in a line shape in a plan view.

[0312] [E19] The semiconductor device according to E17 or E18, wherein the gate pad electrode includes a connecting portion connected to the gate main electrode with a first area in a plan view, and an electrode surface having a second area exceeding the first area in a plan view.

[0313] [E20] The semiconductor device according to any one of E17 to E19, wherein the gate pad electrode overlaps a plurality of the divided regions in a plan view.

[0314] [E21] The semiconductor device according to E19, wherein the electrode surface of the gate pad electrode is exposed to the outside.

[0315] [E22] The semiconductor device according to any one of E17 to E21, wherein the gate main electrode is formed in a line shape on the insulating layer.

[0316] [E23] The semiconductor device according to E19 or E21, wherein the second area of ​​the electrode surface exceeds the area of ​​the gate main electrode.

[0317] [E24] The semiconductor device according to any one of E19, E21, and E23, further comprising a current-conducting electrode disposed on the insulating layer at a distance from the gate main electrode.

[0318] [E25] The semiconductor device according to E24, wherein the gate pad electrode overlaps a portion of the current-conducting electrode in a plan view.

[0319] [E26] The semiconductor device according to E24 or E25, further comprising a current-conducting pad electrode disposed on the current-conducting electrode.

[0320] [E27] The semiconductor device according to E26, wherein the current-conducting pad electrode overlaps a part of the gate main electrode in a plan view.

[0321] [E28] The semiconductor device according to E26 or E27, wherein the current-conducting pad electrode includes an electrode surface having a third area that exceeds the second area of ​​the gate pad electrode in a plan view.

[0322] [E29] The semiconductor device according to any one of E17 to E28, wherein the gate structure consists of a trench gate structure.

[0323] [E30] The semiconductor device according to any one of E17 to E29, wherein at least one of the gate pad electrode and the current conduction pad electrode is made of copper or a copper alloy.

[0324] [E31] In a plan view, the current-conducting pad electrode is arranged to surround the gate pad electrode, as described in any one of E26 to E28 and E30.

[0325] [E32] In a plan view, the area of ​​the first portion of the active region located in the region between the first edge of the semiconductor layer and the gate pad electrode is greater than the area of ​​the second portion of the active region located in the region between the second edge opposite the first edge of the semiconductor layer and the gate pad electrode, according to any one of the items E17 to E31.

[0326] [F1] A semiconductor layer having a main surface, an active region provided in the semiconductor layer, a non-active region provided in the semiconductor layer outside the active region, a plurality of gate structures formed in the active region, an insulating layer formed on the main surface so as to cover the plurality of gate structures, a gate main electrode disposed on the insulating layer so as to be electrically connected to the plurality of gate structures and overlapping the non-active region in a plan view, a current-conducting electrode disposed on the insulating layer at a distance from the gate main electrode, and the gate main electrode and the current-conducting electrode so as to be electrically connected to the gate main electrode A semiconductor device comprising: a gate pad electrode positioned above and overlapping the active region and the inactive region in a plan view, wherein the active region comprises a plurality of divided regions provided in the semiconductor layer at intervals in a plan view, the inactive region comprises a portion located between the plurality of divided regions in the semiconductor layer in a plan view, the gate main electrode comprises a portion overlapping the portion located between the plurality of divided regions in the inactive region in a plan view, and the gate pad electrode comprises a portion overlapping the portion located between the plurality of divided regions in the inactive region in a plan view.

[0327] [F2] The semiconductor device according to F1, wherein the gate main electrode is formed in a line shape in a plan view.

[0328] [F3] The semiconductor device according to F1 or F2, wherein the gate pad electrode includes a connecting portion connected to the gate main electrode with a first area in a plan view, and an electrode surface having a second area exceeding the first area in a plan view.

[0329] [F4] The semiconductor device according to any one of F1 to F3, wherein the gate pad electrode overlaps a plurality of the divided regions in a plan view.

[0330] [F5] The semiconductor device according to F3, wherein the electrode surface of the gate pad electrode is exposed to the outside.

[0331] [F6] The semiconductor device according to any one of F1 to F5, wherein the gate main electrode is formed in a line shape on the insulating layer.

[0332] [F7] The semiconductor device according to F3 or F5, wherein the second area of ​​the electrode surface exceeds the area of ​​the gate main electrode.

[0333] [F8] The semiconductor device according to any one of F1 to F7, wherein the gate pad electrode overlaps a part of the current-conducting electrode in a plan view.

[0334] [F9] The semiconductor device according to F3 or F7, further comprising a current-conducting pad electrode disposed on the current-conducting electrode.

[0335] [F10] The semiconductor device according to F9, wherein the current-conducting pad electrode overlaps a part of the gate main electrode in a plan view.

[0336] [F11] The semiconductor device according to F9 or F10, wherein the current-conducting pad electrode includes an electrode surface having a third area that exceeds the second area of ​​the gate pad electrode in a plan view.

[0337] [F12] The semiconductor device according to any one of F1 to F11, wherein the gate structure consists of a trench gate structure.

[0338] [F13] The semiconductor device according to any one of F1 to F12, wherein at least one of the gate pad electrode and the current conduction pad electrode is made of copper or a copper alloy.

[0339] [F14] In a plan view, the current-conducting pad electrode is arranged to surround the gate pad electrode, as described in any one of F9 to F11 and F13.

[0340] [F15] In a plan view, the area of ​​the first portion of the active region located in the region between the first edge of the semiconductor layer and the gate pad electrode is greater than the area of ​​the second portion of the active region located in the region between the second edge opposite the first edge of the semiconductor layer and the gate pad electrode, according to any one of F1 to F14.

[0341] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents. The present invention has industrial applicability and can be used in semiconductor devices, semiconductor packages, and the like. [Explanation of Symbols]

[0342] 1 Semiconductor device 3 Active Area 4. Inactive areas 10 Semiconductor Layers 11. First main surface (main surface) 21 Trench gate structure (gate structure) 50 Main surface gate electrode (gate main electrode) 55 Main surface source electrode (current-conducting electrode) 61 Lower insulating layer (insulating layer) 62 Side insulating layer (first resin layer) 63 Upper insulating layer (first resin layer) 65 End insulation layer (first resin layer) 70 Gate pad (gate pad electrode) 73 Top surface of gate pad (electrode surface) 75 Source pad (source pad electrode) 76. Top surface (electrode surface) of the source pad 80. Mold layer (second resin layer) 101 Semiconductor Equipment 101a Semiconductor 201 Semiconductor Equipment 201a Semiconductor 250 Anode electrode (first polarity electrode) 255 Cathode electrode (second polarity electrode) 290 Diode (Diode Structure) 293 Recess

Claims

1. A semiconductor layer having a main surface and containing SiC as the main component, An active region provided in the semiconductor layer, In the semiconductor layer, an inactive region is provided in a region outside the active region, The gate structure formed on the main surface, An insulating layer formed on the main surface so as to cover the gate structure, A gate main electrode, which is placed on the insulating layer and electrically connected to the gate structure, A gate pad electrode is positioned on the gate main electrode so as to be connected to the gate main electrode, and includes a connecting portion connected to the gate main electrode with a first area in a plan view, and an electrode surface having a second area exceeding the first area in a plan view. Includes, The active region includes a plurality of divided regions provided in the semiconductor layer at intervals in a plan view, The gate pad electrode includes a portion that overlaps with a portion located between a plurality of divided regions in the inactive region in a plan view.

2. The semiconductor device according to claim 1, wherein the electrode surface of the gate pad electrode is exposed to the outside.

3. The semiconductor device according to claim 1 or 2, wherein the gate main electrode is formed in a line shape on the insulating layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second area of ​​the electrode surface exceeds the area of ​​the gate main electrode.

5. The gate structure is formed in the active region, and the gate main electrode is formed in the inactive region in a plan view. The semiconductor device according to any one of claims 1 to 4, wherein the gate pad electrode overlaps the active region and the inactive region in a plan view.

6. The semiconductor device according to any one of claims 1 to 5, further comprising a current-conducting electrode disposed on the insulating layer at a distance from the gate main electrode.

7. The semiconductor device according to claim 6, wherein the gate pad electrode overlaps a portion of the current-conducting electrode in a plan view.

8. The semiconductor device according to claim 6 or 7, further comprising a current-conducting pad electrode disposed on the current-conducting electrode.

9. The semiconductor device according to claim 8, wherein the current-conducting pad electrode overlaps a portion of the gate main electrode in a plan view.

10. The semiconductor device according to claim 8 or 9, wherein the current-conducting pad electrode includes an electrode surface having a third area exceeding the second area of ​​the gate pad electrode in a plan view.

11. The semiconductor device according to any one of claims 1 to 10, further comprising a first resin layer that partially covers the gate main electrode such that a portion of the gate main electrode is exposed on the insulating layer, wherein the gate pad electrode is disposed on the portion of the gate main electrode exposed from the first resin layer.

12. The present invention further includes a second resin layer that partially covers the first resin layer such that a portion of the gate main electrode is exposed on the insulating layer, The semiconductor device according to claim 11, wherein the gate pad electrode is arranged on the portion of the gate main electrode that is exposed from the first resin layer and the second resin layer.

13. The semiconductor device according to claim 12, wherein the first resin layer is made of a photosensitive resin layer and the second resin layer is made of a thermosetting resin layer.

14. The semiconductor device according to any one of claims 1 to 13, wherein the gate structure comprises a trench gate structure.

15. A semiconductor layer having a main surface, An active region provided in the semiconductor layer, In the semiconductor layer, an inactive region is provided in a region outside the active region, Multiple gate structures formed in the active region, An insulating layer formed on the main surface so as to cover a plurality of the gate structures, A gate main electrode is placed on the insulating layer so as to be electrically connected to a plurality of the gate structures, and in a plan view, it overlaps with the inactive region. Includes a gate pad electrode positioned on the gate main electrode so as to be electrically connected to the gate main electrode, and overlapping the active region and the inactive region in a plan view, The active region includes a plurality of divided regions provided in the semiconductor layer at intervals in a plan view, The gate pad electrode includes a portion that overlaps with a portion located between a plurality of divided regions in the inactive region in a plan view.

16. The semiconductor device according to claim 15, wherein the gate main electrode does not overlap the active region in a plan view.

17. The semiconductor device according to claim 15 or 16, wherein the gate pad electrode includes a connecting portion connected to the gate main electrode with a first area in a plan view, and an electrode surface having a second area exceeding the first area in a plan view.

18. The semiconductor device according to any one of claims 15 to 17, wherein the inactive region includes a portion located between a plurality of the divided regions in the semiconductor layer in a plan view.

19. The semiconductor device according to claim 15, wherein the gate main electrode includes a portion that overlaps with a portion located between a plurality of divided regions in the inactive region in a plan view.

20. The semiconductor device according to claim 19, wherein the gate pad electrode overlaps a plurality of the divided regions in a plan view.

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