Semiconductor equipment

Abstract

The objective is to provide a transistor using an oxide semiconductor with high on-characteristics. This shall be one of the high-performance semiconductor devices having transistors capable of high-speed response and high-speed drive. One of the challenges is to provide it. [Solution] In a transistor having an oxide semiconductor, oxygen vacancies are introduced into the oxide semiconductor layer. By introducing (adding) a causative factor, the resistance of the source and drain regions can be selectively reduced. By introducing an oxygen vacancy-inducing factor into the oxide semiconductor layer, It is possible to effectively form oxygen vacancies that function as regulators. The material can be selected from one or more of titanium, tungsten, and molybdenum. It is preferable to introduce the metal element using an ion implantation method.

Description

Technical Field

[0001] The present invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

[0002] In the present specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

Background Art

[0003] Techniques for forming a thin film transistor (TFT) using a semiconductor thin film formed on a substrate having an insulating surface have attracted attention. Electronic devices such as thin film transistors and electro-optical devices are widely applied. Silicon-based semiconductor materials are known as semiconductor thin films applicable to thin film transistors, but oxide semiconductors are attracting attention as other materials.

[0004] For transistors using an oxide semiconductor, higher electrical characteristics are required for application to more highly functional semiconductor devices. In a transistor using an oxide semiconductor, for the purpose of uniformity and high-speed operation, hydrogen or deuterium contained in the source electrode and the drain electrode is diffused into the oxide semiconductor layer, and a technique for reducing the resistance in the region of the oxide semiconductor layer in contact with the source electrode and the drain electrode has been reported (for example, see Patent Document 1).

[0005]

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] Improving the on-characteristics of transistors using oxide semiconductors will lead to high-speed response in semiconductor devices. Answer: This enables high-speed operation, allowing for the creation of more advanced semiconductor devices.

[0007] Therefore, one embodiment of the present invention provides a transistor using an oxide semiconductor having high on-characteristics. One of the challenges is to provide it.

[0008] Furthermore, one embodiment of the present invention is a high-performance device having a transistor capable of high-speed response and high-speed drive. One of the objectives is to provide semiconductor devices. [Means for solving the problem]

[0009] In a transistor having an oxide semiconductor layer, an oxygen vacancy inducer is introduced into the oxide semiconductor layer. It is added to selectively reduce the resistance of the source and drain regions. By introducing an oxygen vacancy inducer, oxygen that functions as a donor is introduced into the oxide semiconductor layer. Defects can be effectively formed. Therefore, oxygen vacancy inducers are beneficial for oxide semiconductors. These can be considered donor factors, and the oxide semiconductor layer becomes less resistive due to these donor factors.

[0010] The oxygen deficiency-inducing factors to be introduced include titanium (Ti), tungsten (W), and molybdenum. (Mo), aluminum (Al), cobalt (Co), zinc (Zn), indium (In The element is selected from one or more of the following: ), silicon (Si), and boron (B). This is preferable. Furthermore, hydrogen or nitrogen may also be added in addition to the oxygen deficiency inducing factors mentioned above. Furthermore, it is more preferable to use a metal element with high oxygen affinity as the oxygen vacancy inducer. In that case, it is preferable to use ions of the above-mentioned oxygen defect inducing factor alone, or hydrides, fluorides, or chlorides of the ions. It is preferable to use the ions.

[0011] The introduction of the oxygen defect inducing factor into the oxide semiconductor layer in this specification is carried out by selectively using an ion implantation method or a doping method on the formed oxide semiconductor layer. Further, heat treatment may be performed after the introduction process of the oxygen defect inducing factor. It is carried out by selectively using an ion implantation method or a doping method on the formed oxide semiconductor layer. Further, heat treatment may be performed after the introduction process of the oxygen defect inducing factor. Heat treatment may be performed after the introduction process.

[0012] One form of the configuration of the invention disclosed in this specification is an oxide semiconductor layer provided with a channel formation region, a source region containing an oxygen defect inducing factor, and a drain region on a substrate having an insulating surface, and a gate insulating layer on the oxide semiconductor layer, a gate electrode layer overlapping the channel formation region on the gate insulating layer, an insulating layer covering the gate insulating layer, the oxide semiconductor layer, and the gate electrode layer, and an insulating layer A semiconductor device having a source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region on the semiconductor device. and a gate electrode layer overlapping the channel formation region on the gate insulating layer, an insulating layer covering the gate insulating layer, the oxide semiconductor layer, and the gate electrode layer, and an insulating layer A semiconductor device having a source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region on the semiconductor device. A semiconductor device having a source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region.

[0013] Another form of the configuration of the invention disclosed in this specification is an oxide semiconductor layer provided with a channel formation region, a first region containing an oxygen defect inducing factor, and a second region containing an oxygen defect inducing factor on a substrate having an insulating surface, and a gate insulating layer on the oxide semiconductor layer, a gate electrode layer overlapping the channel formation region on the gate insulating layer, an insulating layer covering the gate insulating layer, the oxide semiconductor layer, and the gate electrode layer, and an insulating layer A semiconductor device having a source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region on the semiconductor device. and a gate electrode layer overlapping the channel formation region on the gate insulating layer, an insulating layer covering the gate insulating layer, the oxide semiconductor layer, and the gate electrode layer, and an insulating layer A semiconductor device having a source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region on the semiconductor device. A semiconductor device having a source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region, where the first region is the source region and the drain region, and the second region is provided between the channel formation region and the first region and has a higher resistance than the first region. A semiconductor device having a source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region, where the first region is the source region and the drain region,

[0014] Another form of the configuration of the invention disclosed in this specification is an oxide semiconductor on a substrate having an insulating surface layer is formed, a gate insulating layer is formed on the oxide semiconductor layer, and a gate electrode layer is formed on the gate insulating layer is formed, an oxygen defect inducing factor introduction process is performed on the oxide semiconductor layer, and selective oxygen defects are formed to form a channel formation region, a source region, and a drain region in the oxide semiconductor layer Then, an insulating layer covering the gate insulating layer, the oxide semiconductor layer, and the gate electrode layer is formed, and on the insulating layer a source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region are formed. This is a method for manufacturing a semiconductor device .

[0015] Another form of the configuration of the invention disclosed in this specification is an oxide semiconductor on a substrate having an insulating surface layer is formed, a gate insulating layer is formed on the oxide semiconductor layer, and a gate electrode layer is formed on the gate insulating layer is formed, an insulating layer covering the gate insulating layer, the oxide semiconductor layer, and the gate electrode layer is formed, and oxygen defect inducing factor introduction process is performed on the oxide semiconductor layer, and selective oxygen defects are formed to form a first region functioning as a source region and a drain region, a second region having a higher resistance than the first region, and a channel formation region, and on the insulating layer a source electrode layer electrically connected to the source region and a drain electrode layer electrically connected to the drain region are formed. This is a method for manufacturing a semiconductor device .

[0016] Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, they do not indicate specific names unique to the matters for specifying the invention in this specification .

Advantages of the Invention

[0017] ​​ By introducing oxygen vacancy-inducing factors into the oxide semiconductor layer, donors and This allows for the effective formation of oxygen vacancies that function in this way.

[0018] It has a source region and a drain region with reduced resistance due to the introduction of an oxygen deficiency-inducing factor. In a transistor having an oxide semiconductor layer, the relationship between the oxide semiconductor layer and the electrode layer Because the tact resistance can be reduced, the on-resistance is improved. Therefore, transistors with high electrical characteristics It becomes possible to use "ta".

[0019] Transistors with high electrical characteristics enable fast response and fast drive, therefore, such transistors By incorporating this feature, it becomes possible to create a highly functional semiconductor device. [Brief explanation of the drawing]

[0020] [Figure 1] A diagram illustrating a semiconductor device and one form of a method for manufacturing a semiconductor device. [Figure 2] A diagram illustrating a semiconductor device and one form of a method for manufacturing a semiconductor device. [Figure 3] A diagram illustrating a semiconductor device and one form of a method for manufacturing a semiconductor device. [Figure 4] A diagram illustrating a semiconductor device and one form of a method for manufacturing a semiconductor device. [Figure 5] A diagram illustrating one form of semiconductor device. [Figure 6] A diagram showing electronic equipment. [Figure 7] A diagram showing the relationship between the introduction depth and concentration of oxygen deficiency-inducing factors, calculated by theory. [Figure 8] A diagram showing the calculated density of states. [Figure 9] A diagram showing the structure calculated by a calculation. [Figure 10] A diagram showing the calculated density of states of atoms. [Figure 11]A diagram illustrating a semiconductor device and one form of a method for manufacturing a semiconductor device. [Figure 12] A diagram illustrating a semiconductor device and one form of a method for manufacturing a semiconductor device. [Figure 13] A diagram illustrating a semiconductor device and one form of a method for manufacturing a semiconductor device. [Modes for carrying out the invention]

[0021] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the form and details can be modified in various ways, as any person skilled in the art would know. This is easily understood. Furthermore, the present invention shall be interpreted as being limited to the contents of the embodiments described below. It's not something that can be done.

[0022] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method for manufacturing a semiconductor device will be explained using Figure 1. In this embodiment, a transistor is shown as an example of a semiconductor device.

[0023] Figures 1(A) to 1(D) show examples of transistors and methods for manufacturing transistors.

[0024] The transistor 410 shown in Figure 1(D) is one of the thin-film transistors with a top gate structure. Yes, it is also called a planar thin-film transistor.

[0025] The transistor 410 is located on a substrate 400 having an insulating surface, with an insulating layer 407 and a channel-type Composition region 413, source region 414a containing oxygen deficiency inducing factors, and containing oxygen deficiency inducing factors The oxide semiconductor layer 403 has a drain region 414b, and the gate insulating layer 402 It has a gate electrode layer 401 and

[0026] The oxide semiconductor layer 403, the gate insulating layer 402, and the gate electrode layer 401 are covered by an insulating layer 4 09 and insulating layer 411 are laminated, and via insulating layer 409 and insulating layer 411, Source electrode layer 405a and drain region 414b, respectively. The electrode layer 405b is provided in an electrically connected manner.

[0027] Source region 414a and drain region 414b are drained by the introduction of an oxygen deficiency-inducing factor. This is a low-resistance region where a nucleus is formed.

[0028] The following describes the process of fabricating a transistor 410 on a substrate 400, using Figures 1(A) to (D). Explain.

[0029] There are no major restrictions on the substrates that can be used for the substrate 400 having an insulating surface, however In both cases, it is necessary that the material has sufficient heat resistance to withstand subsequent heat treatment.

[0030] For example, when using a glass substrate, if the subsequent heat treatment temperature is high, distortion will occur. It is best to use a material with a heating point of 730°C or higher. For the glass substrate, for example, aluminosilicate Glass materials such as glass, aluminoborosilicate glass, and bariumborosilicate glass are used. It is included. Furthermore, it is more practical than boron oxide (B2O3) in heat-resistant glass. A glass substrate containing a large amount of um (BaO) may also be used.

[0031] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. A substrate made of edge material may also be used. Other materials such as crystallized glass can also be used. Plastic substrates and the like can also be used as appropriate.

[0032] An insulating layer 407, which will serve as the base film, is formed on the substrate 400. The insulating layer 407 is formed from the substrate 400 It has the function of preventing the diffusion of impurity elements, silicon nitride layer, silicon oxide layer, silicon nitride oxide Silicon layer, silicon oxide nitride layer, aluminum nitride layer, aluminum oxide layer, aluminum nitride oxide Laminated structure consisting of one or more films selected from an aluminum layer or an aluminum oxide nitride layer. It can be formed by the following method. The method for forming the insulating layer 407 is the plasma CVD method or Sputtering methods can be used for this. For example, as the insulating layer 407, silica oxide can be used. The layer can be formed by sputtering.

[0033] An oxide semiconductor film is formed on the insulating layer 407.

[0034] As oxide semiconductors used in oxide semiconductor films, In-Sn- is an oxide of a quaternary metal. Ga-Zn-O systems, and ternary metal oxides such as In-Ga-Zn-O systems and In-Sn- Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O Systems such as the Sn-Al-Zn-O system, and the In-Zn-O system, which is an oxide of a binary metal, and Sn-Z nO series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg-O series, In-Mg-O series In addition, in-O, sn-O, and Zn-O systems can be used. For example, In-Ga-Zn-O oxide semiconductors are oxides containing at least In, Ga, and Zn. Yes, and there are no particular restrictions on the composition ratio. Furthermore, elements other than In, Ga, and Zn may also be included. Furthermore, the oxide semiconductor film may also contain SiO2.

[0035] Furthermore, oxide semiconductor films are oxides represented by the chemical formula InMO3(ZnO)m (m>0). A semiconductor can be used. Here, M is selected from Ga, Al, Mn, and Co. This indicates one or more metallic elements. For example, M could be Ga, Ga and Al, Ga and Mn, Alternatively, there are Ga and Co, etc.

[0036] Oxide semiconductor films can be formed by sputtering. In this embodiment, Oxide semiconductors are produced by sputtering using an In-Ga-Zn-O oxide target. A film is deposited and processed into an island shape to form an oxide semiconductor layer 420 (see Figure 1(A)).

[0037] A gate insulating layer 402 is formed on the oxide semiconductor layer 420. The gate insulating layer 402 is made of plastic Using the Zuma CVD method or sputtering method, a silicon oxide layer, a silicon nitride layer, and an oxide layer are produced. Silicon nitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride layer, oxide A single layer or multiple layers of aluminum nitride, aluminum oxide nitride, or hafnium oxide are used. It can be formed by sputtering. For example, a silicon oxide film with a thickness of 100 nm can be formed using the sputtering method. A concrete layer can be formed to serve as the gate insulating layer 402.

[0038] The gate insulating layer 402 separates the silicon oxide layer and the silicon nitride layer from the oxide semiconductor layer 420 side. A layered structure can also be used. For example, the first gate insulating layer can be formed using a sputtering method. This forms a silicon oxide layer (SiOx (x>0)) with a thickness of 5 nm to 300 nm. A second gate insulating layer with a film thickness of 50 nm to 200 nm is placed on top of the first gate insulating layer. A silicon nitride layer (SiNy(y>0)) may be laminated. The thickness of the gate insulating layer 402 is The setting can be adjusted appropriately depending on the characteristics required for the thin-film transistor, ranging from 30nm to 400nm. Even something around m would be fine.

[0039] A gate electrode layer 401 is formed on the gate insulating layer 402 (see Figure 1(B)). The materials for layer 401 are molybdenum, titanium, chromium, tantalum, tungsten, and aluminum. Metal materials such as copper, neodymium, scandium, or alloy materials mainly composed of these materials are used. They can be formed as a single layer or by lamination.

[0040] For example, as a two-layer stacked structure of the gate electrode layer 401, molybdenum on an aluminum layer A two-layer laminated structure in which layers are stacked, or a two-layer structure in which a molybdenum layer is stacked on a copper layer, It has a two-layer structure in which a titanium nitride layer or tantalum nitride layer is laminated on a copper layer, and the titanium nitride layer and molybdenum A two-layer structure with a butene layer is preferable. As for a three-layer laminated structure, A stainless steel layer or tungsten nitride layer and an aluminum-silicon alloy or aluminum A structure consisting of a titanium alloy and a titanium nitride layer or titanium layer is preferred. Furthermore, a conductive film with light-transmitting properties can also be used to form the gate electrode layer. Examples of conductive films having this property include translucent conductive oxides.

[0041] Next, an oxygen vacancy inducer 421 is introduced into the oxide semiconductor layer 420, and the source region 414a, An oxide semiconductor layer 403 is formed, including a drain region 414b and a channel formation region 413. (See Figure 1(C)). For example, the acid contained in the source region 414a and the drain region 414b The concentration of elementary defect-inducing factor 421 is ≥ 1 × 10¹⁹ atoms / cm³ and ≥ 1 × 10²¹ atoms. It should be set to oms / cm3 or less.

[0042] Heat treatment (e.g., between 200°C and 600°C) is performed after the introduction of oxygen deficiency-inducing factor 421. You may do so.

[0043] In this specification, the concentration of oxygen vacancy inducers refers to the concentration of the oxygen vacancy inducer after the deposition of the oxide semiconductor layer and the subsequent introduction treatment. Therefore, this is the concentration of oxygen vacancy-inducing factors introduced, and is not included in processes other than the introduction process, such as during film formation. Elements that are the same as those that caused the oxygen deficiency are not considered.

[0044] Oxygen deficiency-inducing factors 421 include titanium (Ti), tungsten (W), and molybdenum ( Mo), aluminum (Al), cobalt (Co), zinc (Zn), indium (In) The system uses elements selected from one or more of silicon (Si) and boron (B). Furthermore, in addition to the oxygen deficiency inducing factors mentioned above, hydrogen, or nitrogen, can be used. That's good too.

[0045] By selectively introducing an oxygen vacancy-inducing factor 421 into the oxide semiconductor layer 420, It effectively induces oxygen deficiencies in the induction region. Since oxygen deficiencies function as donors, Oxide semiconductor having selectively low-resistance source region 414a and drain region 414b A body layer 403 can be formed.

[0046] In this embodiment, in the introduction process of the oxygen vacancy inducer 421, the gate electrode layer 401 is It is used as a mask. Therefore, in the oxide semiconductor layer 403, the gate electricity is self-aligned. The region overlapping with the polar layer 401 is a channel-forming region 41 where the oxygen deficiency-inducing factor 421 is not introduced. 3 is formed, while in the region that does not overlap with the gate electrode layer 401, the oxygen deficiency inducing factor 421 is introduced. The source region 414a and drain region 414b are formed. A mask is separately provided to cover at least the channel formation region of 420, and the oxygen deficiency-inducing factor 4 The introduction process of 21 may be performed. The mask is a registration by the photolithography process. You should use a stomat.

[0047] The effect of reducing resistance by forming oxygen vacancies in an oxide semiconductor layer was calculated using a computer. The results were verified. As the oxide semiconductor layer, an In-Ga-Zn-O based oxide semiconductor was used. The calculations were performed for the case where body material is used. Note that in the calculations, In-Ga-Zn The composition of the -O-based oxide semiconductor material was set to In:Ga:Zn:O=1:1:1:4.

[0048] First, using the melt-quench method with classical MD (molecular dynamics) calculations, In-G An amorphous structure of an α-Zn-O oxide semiconductor was prepared. Here, the total number of atoms is 84, densely packed. Calculations are being performed for structures with a concentration of 5.9 g / cm³. This includes metal-oxygen and oxygen-oxygen interactions. For the intervals between metals, a Born-Mayer-Huggins type potential is used. For this, we use a Lennard-Jones type potential and an NVT ensemble. The calculation was performed using Materials Explorer as the calculation program. Ta.

[0049] Subsequently, based on the structure obtained by the above classical MD calculation, density functional theory (DFT) was applied to it. First-principles calculations (quantum MD calculations) using the plane wave-pseudopotential method were performed to determine the structure as follows: The structure was optimized, and the density of states was determined. Furthermore, the structure was also analyzed for the structure obtained by removing one arbitrary oxygen atom. Optimization was performed and the density of states was calculated. The calculation program used was CASTEP, and the exchange correlation The GGA-PBE functional was used.

[0050] Figure 8 shows the density of states of the structure obtained from the above calculation results. Figure 8(A) shows the oxygen vacancies Figure 8(B) shows the density of states for a structure without oxygen vacancies, while Figure 8(B) shows the density of states for a structure with oxygen vacancies. Therefore, 0 (eV) represents the energy corresponding to the Fermi level. Figure 8(A) and Figure From 8(B), in a structure without oxygen defects, the Fermi level is located at the top of the valence band. In contrast, in structures with oxygen vacancies, the Fermi level is found to be located in the conduction band. In structures with elementary defects, the Fermi level exists in the conduction band, and therefore the number of electrons contributing to conduction This increases the resistance, resulting in a structure with low resistance (high conductivity).

[0051] Therefore, by selectively introducing oxygen vacancy-inducing factors into the oxide semiconductor layer, oxygen vacancies can be effectively induced. By doing so, a source region and drain region with reduced resistance are formed in the oxide semiconductor layer. It is possible.

[0052] Furthermore, it is preferable to use a metal element with high oxygen affinity as the oxygen deficiency inducing factor 421. Examples of metal elements with high oxygen affinity include titanium, aluminum, and manganese. Examples include magnesium, zirconium, and beryllium. Copper can also be used. stomach.

[0053] Next, regarding the effect of using metal elements with high oxygen affinity as oxygen deficiency inducers, This explanation is based on calculation results using a computer. Here, we will consider metal elements with high oxygen affinity. Titanium is used, and an In-Ga-Zn-O based oxide semiconductor material is used as the oxide semiconductor layer. While calculations are performed for the case of use, the disclosed embodiments of the invention are not limited thereto. Note that in the calculation, the composition of the In-Ga-Zn-O oxide semiconductor material is In:Ga: The ratio of Zn to O was set to 1:1:1:4.

[0054] By introducing metal elements with high oxygen affinity, the amorphous oxide semiconductor can be transformed into an oxygen-affinity We observed the movement of oxygen towards highly compatible metal elements.

[0055] As an oxide semiconductor, titanium (Ti) is added to the In-Ga-Zn-O based oxide semiconductor. Calculations were performed on the electronic state of the structure. The calculation model and conditions are shown below.

[0056] The structure of the Ti-containing In-Ga-Zn-O oxide semiconductor used in the calculations is shown in Figure 9. The structure is an In-Ga-Zn-O molecule with a stoichiometric composition, fabricated using first-principles molecular dynamics calculations. This structure incorporates Ti into a silicon oxide semiconductor. Black circles represent metal atoms, and white circles represent oxygen atoms. The large black circles represent Ti. The number of atoms is shown in Figure 9 for the In-Ga-Zn-O oxide semi-oxide containing Ti. In the conductive structure, there are 12 In, 12 Ga, and 12 Zn atoms, 48 ​​O atoms, and 1 Ti atom. .

[0057] The density of the In-Ga-Zn-O oxide semiconductor structure containing Ti is greater than that of amorphous In-Ga-Zn. -The experimental value for the O-based oxide semiconductor was fixed at 5.9 g / cm³. For this structure, the following calculation was performed. The calculations were performed under the specified conditions. The first-principles calculations were performed using CAS, a first-principles calculation software from Accelrys. Discard TEP.

[0058] The Ti-containing In-Ga-Zn-O oxide semiconductor structure in Figure 9 is 1 While the temperature is reduced from 500K to 300K, the number of particles (N), volume (V), and temperature (T) are Under specific conditions (NVT ensemble), the time step size is 1 fsec, and the number of steps is 2 at each temperature. Step 000, electron cutoff energy 260 eV, reciprocal lattice mesh (k points) We calculate using 1x1x1 and then, for that final structure, we further calculate the electron cutoff energy 4 At 20eV, a reciprocal grid mesh (k points) was set to 2x2x2 and a structural optimization calculation was performed, and energy This design provides a low-stability structure for ghee.

[0059] As shown in Figure 9, titanium is bonded to oxygen.

[0060] For the Ti-containing In-Ga-Zn-O oxide semiconductor structure shown in Figure 9, electron cutoff Under the conditions of an energy of 420 eV and a reciprocal lattice mesh (k-points) of 3 × 3 × 3, the electron state is dense. I calculated the degree.

[0061] Figure 10(A) shows the overall density of states in the In-Ga-Zn-O oxide semiconductor structure, Figure 1 The partial density of states of Ti in an In-Ga-Zn-O oxide semiconductor structure containing Ti in 0(B) is As shown in Figures 10(A) and 10(B), the horizontal axis represents energy and the vertical axis represents density of states. The energy origin represents the energy of the electron's maximum occupied level, as shown in Figure 10(B). When Ti is added to an In-Ga-Zn-O oxide semiconductor, electrons enter the lower end of the conduction band. You can understand that.

[0062] From the results above, when Ti is introduced into an In-Ga-Zn-O oxide semiconductor, When oxygen combines with it, the stoichiometric ratio deviates. As a result, oxygen becomes deficient. In amorphous In-Ga-Zn-O oxide semiconductors, oxygen vacancies act as electron donors. As a result, an excess of electrons occurs. Therefore, when introducing Ti, which readily bonds with oxygen... This causes an oxygen deficiency, leading to the generation of carriers.

[0063] In this way, by introducing a metal element with high oxygen affinity into the oxide semiconductor layer, its guiding In the input region, oxygen atoms move from the oxide semiconductor layer to the metal element, making the oxygen vacancies more effective. It can be confirmed that the number of oxygen deficiencies that function as donors increases. The application area will be made less resistive more efficiently.

[0064] It has a source region and a drain region with reduced resistance due to the introduction of an oxygen deficiency-inducing factor. In transistors having oxide semiconductors, the contact between the oxide semiconductor layer and the electrode layer Because the power resistance can be reduced, the on-characteristics (e.g., on-current and field-effect mobility) are improved. Therefore, it becomes possible to create a transistor with high electrical characteristics.

[0065] The process of introducing oxygen vacancy-inducing factors 421 into the oxide semiconductor layer 420 is performed on the deposited oxide semiconductor This is performed selectively on body layer 420 using ion implantation or doping methods. In this embodiment, oxygen Titanium is used as the defect-inducing factor 421 and implanted into the oxide semiconductor layer 420 by ion implantation. To be introduced. As for ion implantation methods, there is a method using liquefied titanium tetrachloride (TiCl4) gas. These methods include vaporizing solid sources.

[0066] Furthermore, in the oxygen vacancy induction process, the introduction conditions (acceleration energy, oxygen vacancy induction factor) Depending on the irradiation dose (injection amount or dose amount), the mask (in this embodiment, the gate electrode) may be used. Even in regions overlapping with layer 401), oxygen vacancy-inducing factors are present in a portion of the oxide semiconductor layer. This can happen. Therefore, the region where oxygen deficiency-inducing factors are introduced depends on the introduction conditions, the thickness of the mask, and other factors. The size can be controlled by setting it appropriately.

[0067] For example, regarding the introduction conditions in the process of introducing oxygen vacancy-inducing factors into an oxide semiconductor layer, T A software called RIM (Transport of Ion in Matter) The calculations were performed using TRIM, which calculates the ion implantation process using the Monte Carlo method. This is a suitable software. The model used in the calculations is a silicon oxide film as the insulating layer 407, and an oxide film. The semiconductor layer 420 is an amorphous In-Ga-Zn-O film (composition: InGaZnO4, density 6.2 g / cm³, film thickness 50 nm), silicon oxide film (density 2) as gate insulating layer 402. It is a stacked structure with a density of 0.2 g / cm³ and a film thickness of 100 nm, and the oxide semiconductor layer 420 has a gate insulating layer. The oxygen deficiency-inducing factor 421 was introduced by passing through layer 402. Titanium ions (Ti+) were used, and the ion implantation method was performed with a dose of 1 × 10¹⁵ cm⁻². It was introduced. Furthermore, the acceleration energy was set to three conditions: 100 keV, 150 keV, and 200 keV. I calculated it by placing it there.

[0068] Figure 7 shows the relationship between the introduction depth and concentration of oxygen deficiency-inducing factors, as calculated. In Figure 7, the horizontal axis is The graph shows the depth (nm) of the oxygen vacancy-inducing factor introduced from the surface of the oxide semiconductor layer 420, with the vertical axis representing the introduced factor. This is the concentration (atoms / cm3) of the oxygen deficiency-inducing factor. As shown in Figure 7, the accelerated energy Ghee was found in the oxide semiconductor layer 42 under all three conditions: 100 keV, 150 keV, and 200 keV. Approximately 1 × 10²⁰ atoms / cm³ of titanium ions, which are oxygen vacancy inducers, are introduced into the atmosphere. It can be confirmed that this has been done.

[0069] Therefore, in the above calculation model, the oxide semiconductor layer has a concentration of 1 × 10¹⁹ atoms / cm³. In order to form a source region and drain region of 1 × 10²¹ atoms / cm³ or less The conditions for introducing titanium ions are a dose of 1 × 10¹⁴ cm⁻² or more, and 1 × 10¹⁶ cm⁻². The acceleration energy should be between 100 keV and 200 keV.

[0070] An oxygen vacancy-inducing factor may also be introduced into the channel formation region 413 of the oxide semiconductor layer 403. In this case, an oxygen vacancy-inducing factor is introduced into the oxide semiconductor layer 420 before the formation of the gate electrode layer 401. The introduction process is performed. The introduction process for oxygen vacancy inducers is performed before processing the oxide semiconductor film into island shapes. It is permissible to do so. An oxygen vacancy inducer is also introduced into the channel formation region 413, and the oxygen vacancy is donated. - By reducing the resistance (for example, by making it an n-type transistor), the electrical characteristics of the transistor can be controlled more effectively. It can be controlled.

[0071] After introducing oxygen deficiency-inducing factors, heat treatment (e.g., between 200°C and 600°C) is performed. You can.

[0072] The concentration of the oxygen vacancy inducer contained in the channel formation region 413 is in the source region 414a and The concentration is lower than that of the drain region 414b. As in this embodiment, the source region 414a and The concentration of oxygen vacancy inducers in drain region 414b is 1 × 10¹⁹ atoms / C If the value is between m3 and 1 × 10²¹ atoms / cm3, for example, channel formation region 41 The concentration of 3 should be less than 1 × 10¹⁴ atoms / cm³.

[0073] Next, an insulating layer covering the oxide semiconductor layer 403, gate insulating layer 402, and gate electrode layer 401 Layers 409 and the insulating layer 411 are laminated together.

[0074] The insulating layer 409 and the insulating layer 411 are inorganic insulating films such as an oxide insulating layer or a nitride insulating layer. It can be suitably used. Furthermore, as a method for producing the insulating layer 409 and insulating layer 411, The razma CVD method or sputtering method can be used.

[0075] The insulating layer 409 is typically a silicon oxide film, a silicon oxide nitride film, or an aluminum oxide film. Alternatively, an inorganic insulating film such as an aluminum oxide nitride film can be used.

[0076] The insulating layer 411 consists of a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, and an aluminum nitride oxide film. Inorganic insulating films, such as aluminum films, can be used.

[0077] Furthermore, a planarizing insulating film is formed on the insulating layer 411 to reduce surface irregularities caused by the transistor. It may be done. As the planarizing insulating film, polyimide, acrylic, benzocyclobutene, Heat-resistant organic materials such as riamide and epoxy can be used. In addition to materials, low-dielectric materials (low-k materials), siloxane resins, and PSG (phosphorus glass) are also used. ), BPSG (Limboron glass), etc. can be used. A planar insulating film may be formed by stacking multiple insulating films. The formation method is not particularly limited and can be sputtering, SOG, or spin-coating depending on the material. Coating, dipping, spray coating, droplet ejection (inkjet, screen printing, offset) Set printing, etc.), doctor knife, roll coater, curtain coater, knife coater The following can be used.

[0078] Insulating layer 409 and insulating layer 411 have openings that reach the source region 414a and drain region 414b, respectively. (Contact holes) are formed. A conductive film is deposited in the opening and processed by etching. Source electrode layer 405 is in contact with and electrically connected to the drain region 414a and the drain region 414b. a. Form the drain electrode layer 405b (see Figure 1(D)). Transistor is formed through the above process. 410 can be manufactured.

[0079] Examples of conductive films used for the source electrode layer 405a and drain electrode layer 405b include Al Elements selected from Cr, Cu, Ta, Ti, Mo, and W, or elements of the above-mentioned elements as components. An alloy such as the above-mentioned alloy or an alloy film combining the aforementioned elements can be used. , Cr, Ta, Ti, Mo, W etc. on either the underside or upperside of a metal layer such as Cu, or on both sides. A configuration in which layers of high-melting-point metals are stacked is also possible. Furthermore, Si, Ti, Ta, W, Mo, C Elements such as r, Nd, Sc, and Y are added to prevent the formation of hillocks and whiskers on Al films. By using the added Al material, it is possible to improve heat resistance. Conductive nitride materials of the above metals, such as titanium, may also be used. Furthermore, the method for producing the conductive film is as follows: Therefore, methods such as vapor deposition or sputtering can be used.

[0080] Furthermore, the source electrode layer 405a and drain electrode layer 405b can be single-layer structures or two or more layers. A layered structure is also possible. For example, a single-layer structure of an aluminum film containing silicon, aluminum A two-layer structure in which a titanium film is stacked on top of a film, a Ti film and an aluminum film is layered on top of the Ti film. Examples include a three-layer structure in which layers are stacked and then a Ti film is deposited on top of them.

[0081] Furthermore, source electrode layer 405a, drain electrode layer 405b (wiring formed from the same layer) The conductive film (including the layer) may be formed from a conductive metal oxide. Examples of oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO2). ), indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO), zinc oxide alloy (In2O3-ZnO) or silicon in the aforementioned metal oxide material Alternatively, a product containing silicon oxide can be used.

[0082] As described above, the source region 414a and the dome, which have been made less resistant by introducing an oxygen deficiency-inducing factor, The transistor 410 having an oxide semiconductor having a rain region 414b is an oxide semiconductor The contact resistance between layer 403 and the source electrode layer 405a and drain electrode layer 405b is reduced. Therefore, the on-state characteristics are improved. As a result, it is possible to create a transistor with high electrical characteristics. This is the result.

[0083] Transistors with high electrical characteristics enable fast response and fast drive, therefore, such transistors By incorporating this feature, it becomes possible to create a highly functional semiconductor device.

[0084] (Embodiment 2) In this embodiment, one form of a semiconductor device and a method for manufacturing a semiconductor device is shown in Figures 2 and 3. This will be explained. In this embodiment, a transistor is shown as an example of a semiconductor device. In the transistor shown in state 1, between the channel formation region and the source region or drain region The structure has a region containing oxygen deficiency-inducing factors at a lower concentration than the source region and the drain region. Therefore, the same parts or parts having similar functions as in the above embodiment, and the process, This can be done in the same manner as described above, and repeated explanations will be omitted. I will omit the detailed explanation.

[0085] Figures 2(A) to 2(D) and Figures 3(A) to 3(D) show transistors and transistors. An example of how to make a ta is shown.

[0086] The transistor 440 shown in Figure 2(D) is one of the thin-film transistors with a top gate structure. Yes, it is also called a planar thin-film transistor.

[0087] Transistor 440 has an insulating layer 407 and a channel formed on a substrate 400 having an insulating surface. Region 413, containing low-concentration oxygen deficiency-inducing factors Regions 415a, 415b, oxygen deficiency-inducing factors A source region 414a containing an oxygen deficiency inducing factor is provided. It has an oxide semiconductor layer 433, a gate insulating layer 402, and a gate electrode layer 401.

[0088] The oxide semiconductor layer 433, the gate insulating layer 402, and the gate electrode layer 401 are covered by an insulating layer 4 09 and insulating layer 411 are laminated, and via insulating layer 409 and insulating layer 411, Source electrode layer 405a and drain region 414b, respectively. The electrode layer 405b is provided in an electrically connected manner.

[0089] Low-concentration oxygen deficiency-inducing factor-containing regions 415a, 415b, source region 414a, and drain Region 414b is a region containing oxygen deficiency inducing factors, and is a region containing low concentrations of oxygen deficiency inducing factors. Source region 414a and Dray have higher concentrations of oxygen deficiency-inducing factors than 415a and 415b. Region 414b can also be described as a region containing high-concentration oxygen deficiency-inducing factors. Therefore, this specification In this region, the source region 414a and the drain region are areas containing high-concentration oxygen deficiency-inducing factors. Region 414b is designated as the first region, while regions 415a and 415b, which contain low-concentration oxygen deficiency-inducing factors, are designated as the second region. It is also called the domain of 2.

[0090] Low-concentration oxygen deficiency-inducing factor-containing regions 415a, 415b, source region 414a, and slave region Region 414b is a low-resistance region where a donor is formed by an oxygen deficiency-inducing factor. Low-concentration oxygen deficiency-inducing factor-containing regions 415a and 415b are high-concentration oxygen deficiency-inducing factor-containing regions Oxygen deficiency inducing factors contained in the source region 414a and the drain region 414b Because the concentration is low, the resistance is higher than that of the source and drain regions.

[0091] Therefore, in the oxide semiconductor layer 433 of transistor 440, channel formation region 413 , low-concentration oxygen deficiency-inducing factor-containing regions 415a and 415b, source region 414a and Dre The resistance decreases in the order of region 414b.

[0092] The transistor 440 is fabricated on the substrate 400 using Figures 2(A) to 2(D) below. Let me explain the process.

[0093] As shown in Figure 1(B) of Embodiment 1, an island-shaped layer is provided on the substrate 400 on which the insulating layer 407 is provided. An oxide semiconductor layer 420, a gate insulating layer 402, and a gate electrode layer 401 are formed (Figure 2(A)).

[0094] Region corresponding to the channel formation region of oxide semiconductor layer 420 (overlaps with gate electrode layer 401) The region may also be treated to introduce oxygen deficiency-inducing factors, thereby including them in the sample. In this case, an oxygen vacancy-inducing factor is introduced into the oxide semiconductor layer 420 before the formation of the gate electrode layer 401. The input process is performed. The introduction of oxygen vacancy-inducing factors is carried out before processing the oxide semiconductor film into island-like structures. Alternatively, an oxygen deficiency-inducing factor can be introduced into the channel formation region, and the oxygen deficiency can be used as a donor. By making it resistive (e.g., n-type), the electrical characteristics of the transistor can be controlled more effectively. It is possible.

[0095] After introducing oxygen deficiency-inducing factors, heat treatment (e.g., between 200°C and 600°C) is performed. You can.

[0096] Next, an insulating layer covering the oxide semiconductor layer 420, gate insulating layer 402, and gate electrode layer 401. Forms 409 (see Figure 2(B)).

[0097] Next, an oxygen vacancy inducer 434 is introduced into the oxide semiconductor layer 420, and a low-concentration oxygen vacancy inducer Child-containing regions 415a, 415b, source region 414a, drain region 414b, channel An oxide semiconductor layer 433 including the formation region 413 is formed (see Figure 2(C)). For example, The concentrations of oxygen deficiency-inducing factor 434 in the drain region 414a and drain region 414b are: The ideal value is between 1 × 10¹⁹ atoms / cm³ and 1 × 10²¹ atoms / cm³. The low-concentration oxygen deficiency-inducing factor-containing regions 415a and 415b are the source region 414a and the drain region. The concentration should be lower than that of region 414b, for example, region 41 containing low-concentration oxygen deficiency-inducing factor. The concentration of oxygen deficiency-inducing factor 434 in 5a and 415b is 1 × 10¹⁸ atoms / Approximately cm³ should suffice.

[0098] Heat treatment (e.g., between 200°C and 600°C) is performed after the introduction of oxygen deficiency-inducing factor 434. You may do so.

[0099] Examples of oxygen deficiency-inducing factors 434 include titanium (Ti), tungsten (W), and molybdenum ( Mo), aluminum (Al), cobalt (Co), zinc (Zn), indium (In) The system uses elements selected from one or more of silicon (Si) and boron (B). Furthermore, in addition to the oxygen deficiency inducing factors mentioned above, hydrogen, or nitrogen, can be used. This is also acceptable. Furthermore, if a metal element with high oxygen affinity is used as the oxygen deficiency inducing factor 434, More preferable.

[0100] By selectively introducing an oxygen vacancy-inducing factor 434 into the oxide semiconductor layer 420, It effectively induces oxygen deficiencies in the induction region. Since oxygen deficiencies function as donors, Selectively low-resistance low-concentration oxygen deficiency-inducing factor-containing regions 415a, 415b, and source region An oxide semiconductor layer 433 having 414a and a drain region 414b can be formed. ru.

[0101] Furthermore, a concentration distribution is established in the region where the oxygen deficiency-inducing factor is introduced, creating a high-resistance channel formation region and a low-resistance region. Between the resistive source region or drain region, there is a resistance higher than that of the source region and the drain region. Furthermore, regions 415a and 415b containing low-concentration oxygen deficiency-inducing factors have lower resistance than the channel-forming region. By having this feature, the oxide semiconductor layer 433 has a structure in which the conductivity changes in stages. Therefore, in order to suppress electric field concentration and prevent the application of localized high electric fields, the breakdown voltage of the transistor is improved. Furthermore, it is possible to provide high reliability to semiconductor devices.

[0102] In this embodiment, in the process of introducing the oxygen vacancy inducer 434, the gate electrode layer 401 is It is used as a mask. Therefore, in the oxide semiconductor layer 433, the gate electricity is self-aligned. The region overlapping with the polar layer 401 is the channel-forming region 41, where the oxygen deficiency-inducing factor 434 is not introduced. 3 is formed, while in the region that does not overlap with the gate electrode layer 401, the oxygen deficiency inducing factor 434 is introduced. The input source region 414a and drain region 414b are formed. The insulating layer 409 provided on the side of 01 also acts as a mask, so the gate electrode layer 401 and the side The introduction of the material into the oxide semiconductor layer 420, which overlaps with the insulating layer 409 provided therein, is inhibited. However, The area of ​​the oxide semiconductor layer 420 that overlaps with the insulating layer 409 provided on the side surface of the gate electrode layer 401 In the region (between the channel formation region 413 and the source region 414a or drain region 414b) This is due to the leakage of oxygen vacancy-inducing factor 434 introduced into the source or drain region. Since oxygen deficiency-inducing factor 434 is introduced, the low-concentration oxygen deficiency-inducing factor-containing region 415a, This becomes 415b.

[0103] The introduction of oxygen vacancy inducer 434 into the oxide semiconductor layer 420 results in the deposited oxide semiconductor layer This is performed selectively on 420 using ion implantation or doping methods.

[0104] Furthermore, in the oxygen vacancy induction process, the introduction conditions (acceleration energy, oxygen vacancy induction factor) Depending on the irradiation dose (injection amount or dose amount), the mask (in this embodiment, the gate electrode) may be used. Even in regions overlapping with layer 401), oxygen vacancy-inducing factors are present in a portion of the oxide semiconductor layer. This can happen. Therefore, the region where oxygen deficiency-inducing factors are introduced depends on the introduction conditions, the thickness of the mask, and other factors. The size can be controlled by setting it appropriately.

[0105] As in this embodiment, the insulating layer 409 is passed through to the source region 414a and the drain region 4 The low-concentration oxygen deficiency inducer is created by the wrap-around of oxygen deficiency inducer 434 introduced in 14b. When forming the containing regions 415a and 415b, the thickness of the insulating layer 409 and the acceleration energy By adjusting this, the channel length direction of the low-concentration oxygen deficiency-inducing factor-containing regions 415a and 415b Determine the width (for example, between 20 nm and 1 μm, typically between 20 nm and 200 nm). It is possible.

[0106] Figure 2 shows that a single oxygen deficiency-inducing factor introduction treatment results in a low-concentration oxygen deficiency-inducing factor-containing region 4. 15a, 415b, source region 414a, and drain region 414b are formed in a self-aligned manner. An example has been shown, but multiple oxygen deficiency-inducing factor introduction treatments may also be performed. Figure 3 shows two acid An example of introducing elementary defect-inducing factors is shown.

[0107] Similar to Figure 2(A), an island-shaped oxide semiconductor layer 42 is placed on a substrate 400 on which an insulating layer 407 is provided. A gate insulating layer 402 and a gate electrode layer 401 are formed (see Figure 3(A)).

[0108] Next, the oxide semiconductor layer 420 is masked with the gate electrode layer 401 as the oxygen vacancy inducer 43 0 is selectively introduced, and the channel-forming region 413, the oxygen deficiency-inducing factor-containing region 431a, 4 Forms 31b (see Figure 3(B)). For example, oxygen deficiency-inducing factor-containing regions 431a, 4 The concentration of oxygen deficiency-inducing factor 430 in 31b is approximately 1 × 10¹⁸ atoms / cm³. You can use degrees.

[0109] Next, the channel-forming region 413 and the oxygen deficiency-inducing factor-containing regions 431a and 431b are included. An insulating layer 409 is formed to cover the oxide semiconductor layer, the gate insulating layer 402, and the gate electrode layer 401. ru.

[0110] Next, in the oxygen vacancy inducing factor-containing regions 431a and 431b of the oxide semiconductor layer, oxygen vacancy inducing factors Sub-subordinate 432 is introduced, and low-concentration oxygen deficiency-inducing factor-containing regions 415a, 415b, and source region 4 The oxide semiconductor layer 433 includes 14a, a drain region 414b, and a channel formation region 413. Formed (see Figure 3(C)). For example, included in the source region 414a and drain region 414b The concentration of oxygen deficiency-inducing factor 432 present is greater than 1 × 10¹⁹ atoms / cm³. It should be 21 atoms / cm³ or less.

[0111] Heat treatment (e.g., between 200°C and 600°C) is performed after the introduction of oxygen deficiency-inducing factor 432. You may do so.

[0112] Furthermore, the insulating layer 409 provided on the side surface of the gate electrode layer 401 also acts as a mask, so the gate Oxygen into the oxide semiconductor layer 420 which overlaps with the electrode layer 401 and the insulating layer 409 provided on the side surface. The introduction of defect-inducing factor 432 is inhibited, and low-concentration oxygen defect-inducing factor-containing regions 415a, 41 It becomes 5b.

[0113] For oxygen vacancy inducing factors 430 and 432, the same materials as for oxygen vacancy inducing factor 434 were used. It is possible.

[0114] Furthermore, when introducing an oxygen vacancy-inducing factor into the channel formation region 413, the channel shape The concentration of oxygen deficiency-inducing factors contained in region 413 is determined in region 4, which contains low concentrations of oxygen deficiency-inducing factors. The concentrations in 15a, 415b, source region 414a, and drain region 414b are lower. As in the embodiment, oxygen vacancies are introduced in the source region 414a and the drain region 414b. The concentration of the causative factor is between 1 × 10¹⁹ atoms / cm³ and 1 × 10²¹ atoms / cm³. Below, the oxygen deficiency-inducing factors contained in the low-concentration oxygen deficiency-inducing factor-containing regions 415a and 415b If the concentration is around 1 × 10¹⁸ atoms / cm³, for example, channel formation region 41 The concentration of 3 should be less than 1 × 10¹⁴ atoms / cm³.

[0115] After completing the introduction process shown in Figure 3(C), an insulating layer 411 is formed on the insulating layer 409. 409 and the insulating layer 411 have openings (con) that reach the source region 414a and the drain region 414b. A tact hole is formed. A conductive film is deposited in the opening and processed by etching to form the source region. Source electrode layer 405a, which is in contact with drain region 414a and drain region 414b and electrically connected to them, The rain electrode layer 405b is formed (see Figure 3(D)). Transistor 440 is formed through the above process. It is possible to produce this.

[0116] As described above, the low-concentration oxygen deficiency-inducing factor, which has been made less resistant by introducing an oxygen deficiency-inducing factor, contains Regions 415a and 415b, and source region 414a which contains high-concentration oxygen deficiency-inducing factors. And the transistor 440 having an oxide semiconductor layer 433 having a drain region 414b Contact between oxide semiconductor layer 433 and source electrode layer 405a and drain electrode layer 405b Because the resistance can be reduced, the on-characteristics (e.g., on-current and field-effect mobility) are improved. Therefore, it becomes possible to create a transistor with high electrical characteristics.

[0117] Transistors with high electrical characteristics enable fast response and fast drive, therefore, such transistors By incorporating this feature, it becomes possible to create a highly functional semiconductor device.

[0118] Furthermore, by having an oxide semiconductor layer with gradually changing conductivity, the transistor's electrical conductivity... Because field concentration can be suppressed and the application of localized high electric fields can be prevented, the breakdown voltage of the transistor is improved, and semicircular This can provide high reliability to conductive devices.

[0119] (Embodiment 3) In this embodiment, another embodiment of a semiconductor device and a method for manufacturing a semiconductor device is shown in Figure 11. Explanation. In this embodiment, a transistor is shown as an example of a semiconductor device. Embodiment A transistor as shown in Embodiment 1 or Embodiment 2, and a process for forming the source electrode layer and the drain electrode layer. And an example with a different structure. Therefore, having the same parts or similar functions as the above embodiment. The parts and processes can be carried out in the same manner as in the embodiments described above, and repeated explanations will be omitted. Further detailed explanations of the same section will be omitted.

[0120] In Embodiments 1 and 2, the source electrode layer and the drain electrode layer are oxide semiconductor layers. Formed on an insulating layer provided above, the electrical connection with the oxide semiconductor layer is made through the insulating layer. An example of this process, which involves forming tact holes, is shown. In this embodiment, oxide semiconductors are used without an insulating layer. The source electrode layer and drain electrode layer are formed in direct contact with the conductor layer.

[0121] Figures 11(A) to 11(D) show examples of transistors and methods for manufacturing them. .

[0122] The transistor 510 shown in Figure 11(D) is a thin-film transistor with a top-gate structure. That is the case.

[0123] Transistor 510 has an insulating layer 507 and a channel formed on a substrate 500 having an insulating surface. Region 513, Regions 511a and 511b without oxygen deficiency inducers, and Region 511b containing oxygen deficiency inducers. An acid is provided with a source region 512a and a drain region 512b containing an oxygen vacancy inducer. Iridescent semiconductor layer 503, first source electrode layer 555a, first drain electrode layer 555b, The second source electrode layer 545a, the second drain electrode layer 545b, the gate insulating layer 502, and It has a gate electrode layer 501.

[0124] The source region 512a and drain region 512b are gate regions in the oxide semiconductor layer 503. Electrode layer 501, first source electrode layer 555a, first drain electrode layer 555b, second source - Region not covered by electrode layer 545a or second drain electrode layer 545b, and first Source electrode layer 555a, first drain electrode layer 555b, second source electrode layer 545a , or the surface portion of the oxide semiconductor layer 503 covered by the second drain electrode layer 545b It is formed in the source region 512a and the drain region 512b, which are oxygen vacancy induced This is a low-resistance region where the donor cell was formed by subunit 521.

[0125] On the other hand, in the oxide semiconductor layer 503, the first source electrode layer 555a, or the first drain An oxygen vacancy-inducing factor is provided near the interface with the electrode layer 555b and the insulating layer 507. The non-introduced regions 511a and 511b do not contain the oxygen deficiency-inducing factor 521.

[0126] Furthermore, the oxygen vacancy-inducing factor 521 is also introduced into the channel formation region 513 of the oxide semiconductor layer 503. It may be added. In this case, oxygen may be added to the oxide semiconductor layer 520 before the formation of the gate electrode layer 501. The defect-inducing factor 521 is introduced. The oxygen defect-inducing factor 521 is introduced in oxide semiconductors. This can be done before processing the body membrane into island-like structures. Oxygen deficiency-inducing factors also exist in the channel-forming region 513. When 521 is introduced, the oxygen vacancy inducer 521 is introduced throughout the oxide semiconductor layer 503. Therefore, the oxygen deficiency-inducing factor non-introduced regions 511a and 511b also have the same concentration as the channel-forming region. This will result in the inclusion of oxygen deficiency-inducing factor 521.

[0127] The oxygen deficiency-inducing factor 521 is also introduced into the channel formation region 513, and the oxygen deficiency is used as a donor. By reducing the resistance (for example, by making it an n-type transistor), the electrical characteristics of the transistor can be controlled more effectively. It is possible.

[0128] Heat treatment (e.g., between 200°C and 600°C) is performed after the introduction of oxygen deficiency-inducing factor 521. You may do so.

[0129] The concentration of the oxygen vacancy inducer contained in the channel formation region 513 is in the source region 512a and The concentration is lower than that of the drain region 512b. As in this embodiment, the source region 512a and The concentration of oxygen vacancy inducers in drain region 512b is 1 × 10¹⁹ atoms / C If the value is between m3 and 1 × 10²¹ atoms / cm3, for example, the channel formation region 51 The concentration of 3 should be less than 1 × 10¹⁴ atoms / cm³.

[0130] The transistor 510 is fabricated on the substrate 500 using Figures 11(A) to 11(D) below. I will explain the process.

[0131] An island-shaped oxide semiconductor layer 520 is provided on a substrate 500 on which an insulating layer 507 is provided, and oxidation The first source electrode layer 555a and the second source are in contact with one end of the material semiconductor layer 520. The electrode layer 545a is stacked and in contact with the other end of the oxide semiconductor layer 520, the first A stack of the drain electrode layer 555b and the second drain electrode layer 545b is formed.

[0132] The first source electrode layer 555a and the first drain electrode layer that are in contact with the oxide semiconductor layer 520 As the 555b, a metal nitride layer is used, and as the second source electrode layer 545a and the second drain It is preferable to use a metal layer for the electrode layer 545b. In the present embodiment, the first source A titanium nitride film is used for the electrode layer 555a and the first drain electrode layer 555b, and a titanium film is used for the second source electrode layer 545a and the second drain electrode layer 545b.

[0133] The first source electrode layer 555a, the first drain electrode layer 555b, the second source electrode layer 54 5a, and the second drain electrode layer 545b are thin conductive films.

[0134] An oxide semiconductor layer 520, a first source electrode layer 555a, a first drain electrode layer 555b, A gate insulating layer 50 2 is formed on the second source electrode layer 545a and the second drain electrode layer 545b, and a gate electrode layer 501 is formed on the gate insulating layer 502 (see FIG. 11(B)) .

[0135] Next, an oxygen defect inducing factor 521 is introduced into the oxide semiconductor layer 520, and an oxide semiconductor layer 503 including a source region 512a, a drain region 512b, a channel formation region 513, and an oxygen defect inducing factor non-introduced region 511a , 511b is formed (see FIG. 11(C)). For example, the concentration of the oxygen defect inducing factor 521 included in the source region 512a and the drain region 512b may be 1 ×1019 atoms / cm3 or more and 1×1021 atoms / cm3 or less.

[0136] After the introduction process of the oxygen defect inducing factor 521, a heat treatment (for example, 200°C or more and 600°C or less) It may be performed.

[0137] As the oxygen defect inducing factor 521, titanium (Ti), tungsten (W), molybdenum ( Mo), aluminum (Al), cobalt (Co), zinc (Zn), indium (In) , silicon (Si), boron (B), or an element selected from any one or more thereof can be used. Furthermore, in addition to the above oxygen defect inducing factor 521, hydrogen, or and nitrogen may be used. Note that as the oxygen defect inducing factor 521, it is more preferable to use a metal element with high oxygen affinity.

[0138] By selectively introducing the oxygen defect inducing factor 521 into the oxide semiconductor layer 520, oxygen defects are effectively induced in the introduced region. Since the oxygen defects function as donors, an oxide semiconductor layer 503 having selectively low-resistance source regions 512a and drain regions 512b can be formed.

[0139] In this embodiment, the introduction process of the oxygen defect inducing factor 521 into the oxide semiconductor layer 520 is performed using the gate electrode layer 501 as a mask, and passes through the gate insulating layer 502 and the first source electrode layer 55 5a, the first drain electrode layer 555b, the second source electrode layer 545a, and the second drain electrode layer 545b.

[0140] The region overlapping with the gate electrode layer 501 becomes the channel formation region 513 where the oxygen defect inducing factor 521 is not introduced.

[0141] The first source electrode layer 555a, the first drain electrode layer 555b, the second source electrode layer 54 5a, and the second drain electrode layer 545b are formed as conductive films with a thin film thickness, and the introduction conditions are controlled. As a result, the oxygen deficiency-inducing factor 521 is transferred to the first source electrode layer 555a and the first drain electrode layer Passing through 555b, the second source electrode layer 545a, and the second drain electrode layer 545b It can be introduced near the interface with the oxide semiconductor layer 520. Thus, as shown in Figure 11(C) The oxide semiconductor layer 503 and the first source electrode layer 555a, or the first drain electrode The source region 512 is also a region containing the oxygen vacancy inducer 521 near the interface with layer 555b. a. A drain region 512b can be formed. Therefore, the oxide semiconductor layer 503 and The first source electrode layer 555a or the first drain electrode layer 555b is a low-resistance source It can be connected via region 512a or drain region 512b.

[0142] On the other hand, the oxide that overlaps with the first source electrode layer 555a or the first drain electrode layer 555b In the semiconductor layer 503, an oxygen vacancy inducer 521 is introduced near the interface with the insulating layer 507. Regions 511a and 511b, where oxygen deficiency-inducing factors are not introduced, are formed. The defect-inducing factor non-introduced regions 511a, 511b and the channel-forming region 513 are subjected to the introduction process. It does not contain oxygen deficiency-inducing factors.

[0143] By following the above steps, transistor 510 can be manufactured.

[0144] The source region 512a and drain region were made less resistant by introducing the oxygen deficiency-inducing factor 521. By having region 512b, in the transistor 510 having an oxide semiconductor layer 503 This consists of an oxide semiconductor layer 503, a first source electrode layer 555a, and a first drain electrode layer 555 Because the contact resistance with b can be reduced, the on-characteristics (e.g., on-current and field-effect mobility) can be improved. ) is improved. Therefore, it becomes possible to obtain a transistor with high electrical characteristics.

[0145] A transistor with high electrical characteristics enables high-speed response and high-speed driving. By including such a transistor, it is possible to obtain a highly functional semiconductor device.

[0146] Also, as in Embodiment 2, between the channel formation region and the source region or the drain region, a structure having a region containing an oxygen defect inducing factor with a lower concentration than the source region and the drain region may be employed.

[0147] By having an oxide semiconductor layer with a stepwise change in conductivity, the electric field concentration in the transistor can be suppressed and the application of a local high electric field can be prevented. As a result, the breakdown voltage of the transistor is improved, and high reliability can be imparted to the semiconductor device.

[0148] This embodiment can be implemented in appropriate combination with other embodiments.

[0149] (Embodiment 4) This embodiment will be described in detail with reference to FIGS. 12 and FIG. 13, taking a transistor including an oxide semiconductor layer and a manufacturing method as examples. The same parts or parts having similar functions as those in the above embodiments, and the processes can be carried out in the same manner as in the above embodiments, and repeated descriptions are omitted. Also, detailed descriptions of the same locations are omitted.

[0150] Examples of the cross-sectional structures of the transistors are shown in FIGS. 12 and 13. The transistors 640 and 650 shown in FIGS. 12 and 13 are thin film transistors having the same top gate structure as the transistor 510 shown in FIG. 11.

[0151] The oxide semiconductor layer of this embodiment is an n-type impurity before the introduction of oxygen vacancy-inducing factors. Hydrogen is removed from the oxide semiconductor layer, and impurities other than the main components of the oxide semiconductor layer are kept to a minimum. By increasing the purity in such a way, it is made into true (type i), or true type. That is, By removing impurities such as hydrogen and water as much as possible, a highly purified intrinsic (type i) semiconductor or We're getting closer to that.

[0152] Furthermore, the above-mentioned highly purified oxide semiconductor layer contains extremely few (close to zero) carriers. The carrier concentration is less than 1 × 10¹⁴ / cm³, preferably less than 1 × 10¹² / cm³. More preferably, it is less than 1 × 10¹¹ / cm³.

[0153] Because there are very few carriers in the oxide semiconductor layer, the off-current can be kept low. The lower the current, the better.

[0154] Specifically, a transistor having the aforementioned oxide semiconductor layer has a channel width of 1 μm per The off-current should be set to 1 × 10⁴ zA / μm (1 × 10⁻¹⁷ A / μm) or less, and further It is possible to reduce this to 1 × 10³ zA / μm (1 × 10⁻¹⁸ A / μm) or less.

[0155] Furthermore, the resistance to the flow of off-current in a transistor can be expressed as off-resistivity. Resistivity is the resistivity of the channel formation region when the transistor is off, and off-resistivity is It can be calculated from the off-current.

[0156] The off-resistivity of the transistor comprising the oxide semiconductor layer of this embodiment is 1 × 10⁹ Ω·m The above is preferable, and more preferably 1 × 10¹⁰ Ω·m or more.

[0157] Furthermore, transistors 640 and 650, which are equipped with the aforementioned oxide semiconductor layer, have an on-current that depends on the temperature. Almost no activity is observed, and the off-current remains very small.

[0158] Hereinafter, using Figures 12(A) to 12(E), a transient is applied to a substrate 600 having an insulating surface. This explains the process for manufacturing the Sta640.

[0159] The substrate 600 can be a substrate similar to the substrate 400 shown in Embodiment 1. In this embodiment, a glass substrate is used as the substrate 600.

[0160] An insulating layer 607, which will serve as the base film, is formed on the substrate 600. The border layer 607 is a silicon oxide layer, a silicon oxide nitride layer, an aluminum oxide layer, or an oxide layer. It is preferable to use an oxide insulating layer such as an aluminum nitride layer. Method for forming the insulating layer 607 and For example, plasma CVD or sputtering can be used, but the insulating layer 60 To suppress the inclusion of hydrogen in 7, an insulating layer 607 is deposited using the sputtering method. It is preferable.

[0161] In this embodiment, a silicon oxide layer is formed as the insulating layer 607 by sputtering. The substrate 600 is transported to the processing room and spat with high-purity oxygen from which hydrogen and moisture have been removed. Tagas is introduced and a silicon semiconductor target is used to create an insulating layer 607 on the substrate 600. A silicon oxide layer is formed. The substrate 600 may be at room temperature or heated. .

[0162] For example, using quartz (preferably synthetic quartz), with a substrate temperature of 108°C, between the substrate and the target... Distance between terminals (TS distance) 60mm, pressure 0.4Pa, high-frequency power supply 1.5kW, oxygen and Under an argon atmosphere (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1), R A silicon oxide film will be deposited using the F sputtering method. The film thickness will be 100 nm. Instead of quartz (preferably synthetic quartz), a silicon target is used to form a silicon oxide film. It can be used as a target. Furthermore, oxygen or oxygen and... This is done using a mixed gas of argon and bisulfite.

[0163] In this case, it is preferable to form the insulating layer 607 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the insulating layer 607.

[0164] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The treatment chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms, such as O), are exhausted from the treatment chamber, the film is formed in the insulating layer 607. The concentration of impurities can be reduced.

[0165] Furthermore, the insulating layer 607 may also have a laminated structure, for example, a silicon nitride layer from the substrate 600 side, and a silicon nitride layer. Silicon oxide layer, aluminum nitride layer, or nitride insulating layer such as aluminum nitride oxide Alternatively, a laminated structure with the above-mentioned oxide insulating layer may be used.

[0166] For example, a spam containing high-purity nitrogen from which hydrogen and moisture have been removed between the silicon oxide layer and the substrate. A silicon nitride layer is deposited using a silicon target after introducing a tatta gas. Even if there is residual moisture in the processing chamber, similar to the silicon oxide layer, the silicon nitride layer is formed while removing residual moisture in the processing chamber. It is preferable to form a film. When forming a silicon nitride layer, the substrate may be heated during film formation. stomach.

[0167] When a silicon nitride layer and a silicon oxide layer are laminated as the insulating layer 607, the silicon nitride layer The silicon oxide layer and the silicon oxide layer are deposited in the same processing chamber using a common silicon target. This can be done. First, a sputtering gas containing nitrogen is introduced, and a silicon tape is installed in the processing chamber. A silicon nitride layer is formed using a GET, and then the sputtering gas is switched to an oxygen-containing gas. Then, using the same silicon target, a silicon oxide layer is formed. Silicon nitride layer and oxide Because the silicon layer can be formed continuously without exposure to the atmosphere, the silicon nitride layer surface This prevents impurities such as hydrogen and moisture from being adsorbed onto the surface.

[0168] Next, a film thickness of 2 nm to 200 nm, preferably 5 nm to 30 nm, is applied to the insulating layer 607. Forms oxide semiconductor films with a size of less than 1 nm.

[0169] Furthermore, before depositing the oxide semiconductor film by sputtering, argon gas is introduced. Reverse sputtering is performed to generate plasma, and powdery material adhering to the surface of the insulating layer 607 ( It is preferable to remove particles (also called debris). Reverse sputtering is a process that targets Without applying voltage to the substrate side, voltage is applied to the substrate side using an RF power supply under an argon atmosphere. This method modifies the surface by forming plasma near the plate. Note that instead of an argon atmosphere, Nitrogen, helium, oxygen, etc., may also be used.

[0170] The oxide semiconductor used as an oxide semiconductor film is an oxide of a quaternary metal, In-Sn-G α-Zn-O systems, and ternary metal oxides such as In-Ga-Zn-O and In-Sn-Z nO system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system Sn-Al-Zn-O system, and binary metal oxides such as In-Zn-O system and Sn-Zn -O system, Al-Zn-O system, Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system and In-O, Sn-O, and Zn-O systems can be used. The conductive film may contain SiO2. In this embodiment, the oxide semiconductor film is In-Ga - A film is deposited by sputtering using a Zn-O-based oxide target. Semiconductor films are fabricated under a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a noble gas (typically It can be formed by sputtering in an argon and oxygen atmosphere. ru.

[0171] For example, a target for fabricating oxide semiconductor films by sputtering is a composition As a ratio, In2O3:Ga2O3:ZnO = 1:1:1 [molar ratio] (i.e., I You can use n:Ga:Zn=1:1:0.5 (atom ratio). Also, there are other options. In:Ga:Zn=1:1:1 [atom ratio], or In:Ga:Zn=1:1:2 [ A target having a composition ratio of [atom ratio] may be used. The packing rate of the oxide target The packing density is 90% to 100%, preferably 95% to 99.9%. By using a crystalline target, the deposited oxide semiconductor film becomes a dense film.

[0172] The sputtering gas used when depositing oxide semiconductor films is hydrogen, water, hydroxyl groups, or hydrides. It is preferable to use a high-purity gas from which impurities have been removed.

[0173] The substrate is held in a processing chamber maintained under reduced pressure, and the substrate temperature is kept between 100°C and 600°C. The temperature should be between 200°C and 400°C. By depositing the film while heating the substrate, The concentration of impurities in the deposited oxide semiconductor film can be reduced. Damage caused by rinsing is reduced. And, while removing residual moisture in the processing chamber, hydrogen and moisture are removed. The removed sputtering gas is introduced, and the oxide semiconductor is placed on the substrate 600 using the target described above. A film is formed. To remove residual moisture in the processing chamber, an adsorption type such as a cryopump is used. It is preferable to use a vacuum pump. The processing chamber, which has been evacuated using a cryopump, for example , hydrogen, water (H2O), and other compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) Because (and other substances) are exhausted, the concentration of impurities contained in the oxide semiconductor film formed in the processing chamber It can be reduced.

[0174] An example of film deposition conditions is a distance of 100 mm between the substrate and the target, and a pressure of 0.6 Pa. The conditions applied are a DC power supply of 0.5kW and an oxygen atmosphere (oxygen flow rate ratio of 100%). It can be used. Furthermore, when using a pulsed DC power supply, powdery material (particulate matter) generated during film formation can be produced. This is preferable because it reduces debris (also called scum) and results in a more uniform film thickness distribution. The appropriate thickness varies depending on the oxide semiconductor material, so you should select the appropriate thickness according to the material. .

[0175] Next, the oxide semiconductor film is transformed into island-shaped oxide semiconductor layers 620 by a photolithography process. Process. Also, a resist mask for forming island-shaped oxide semiconductor layers 620 is ink. It may also be formed by the jet method. If the resist mask is formed by the inkjet method, photomask Because no screws are used, manufacturing costs can be reduced.

[0176] Note that etching of oxide semiconductor films here can be done by dry etching or wet etching. You can use either "gu" or "gu," and both are acceptable.

[0177] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, for example) Chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride ( CCl4, etc., are preferred.

[0178] Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (S)) F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and these gases can be mixed with noble gases such as helium (He) and argon (Ar). Gases with added sulfites, etc., can be used.

[0179] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. The desired processing shape can be etched. To that end, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) Adjust the amount of power used, the electrode temperature on the substrate, etc., as appropriate.

[0180] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, Ammonia Hydrogenated Water (31% hydrogen peroxide by weight: 28% ammonia by weight: water = 5:2:2) These can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0181] Furthermore, the etching solution after wet etching is washed away along with the etched material. The material is removed. The waste etching solution containing the removed material is purified, and the material contained in it is removed. It may be reused. Indium and other elements contained in the oxide semiconductor layer can be extracted from the waste liquid after etching. By recovering and reusing materials, resources can be used effectively and costs can be reduced. .

[0182] Etching conditions (etching) can be adjusted according to the material so that the desired processing shape can be etched. Adjust the solution, etching time, temperature, etc. as appropriate.

[0183] Next, the oxide semiconductor layer 620 is subjected to a first heat treatment. This first heat treatment causes acid The ion semiconductor layer 620 can be dehydrated or dehydrogenated. The temperature of the first heat treatment The temperature shall be between 400°C and 750°C, or between 400°C and the strain point of the substrate.

[0184] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. The device may include an apparatus that heats the object to be processed by radiation. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Angle) for Thermal Annealing devices, etc. A neal device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high pressure A device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas contains A Inert gases such as argon or nitrogen, which do not react with the material being treated by heat treatment, are used. A gaseous substance is used.

[0185] For example, as the first heat treatment, an inert gas heated to a high temperature of 650°C to 700°C The circuit board was moved inside and heated for several minutes, then moved again and heated to a high temperature in an inert solution. GRTA can be performed by extruding from a gas. Using GRTA allows for high-temperature heat treatment in a short time. It becomes possible.

[0186] In the first heat treatment, nitrogen or a noble gas such as helium, neon, or argon is used. It is preferable that it does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, Alternatively, the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably It is preferable to keep the concentration at 0.1 ppm or less.

[0187] Furthermore, the oxide semiconductor layer is heated as a dehydration or dehydrogenation heat treatment, and high purity is used in the same furnace. Oxygen gas, high-purity N2O gas, or ultra-dry air (with a dew point of -40°C or lower, preferably - Cooling may be performed by introducing a temperature of 60°C or lower. Oxygen gas or N2O gas, water, hydrogen, etc. It is preferable that it does not contain such substances. Alternatively, oxygen gas or N2O introduced into the heat treatment apparatus. The purity of the gas should be 6N (99.9999%) or higher, preferably 7N (99.99999%). The above (i.e., the impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably 0 ppm.) It is preferable to keep the concentration below 1 ppm. Removal of impurities by dehydration or dehydrogenation treatment. The oxygen, a main component material that makes up oxide semiconductors, which has decreased simultaneously due to the same process, is supplied. This process increases the purity of the oxide semiconductor layer 620 and makes it electrically i-type (intrinsic).

[0188] In this embodiment, the substrate 600 is introduced into an electric furnace, which is one of the heat treatment devices, and oxide semiconductor The body layer is subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere, and then exposed to air. This prevents the re-importation of water and hydrogen into the oxide semiconductor layer, thereby obtaining the oxide semiconductor layer 620. Thus, in order to dehydrate or dehydrogenate under an inert gas atmosphere such as nitrogen or a noble gas When heat treatment is performed, the oxide semiconductor layer 620 after heat treatment becomes n-type due to oxygen deficiency. This reduces resistance.

[0189] Furthermore, the oxide semiconductor layer 620 is affected by the conditions of the first heat treatment, or by the material of the oxide semiconductor layer. Therefore, crystallization may occur, resulting in a microcrystalline or polycrystalline film. Also, the first heat treatment Depending on the conditions or the material of the oxide semiconductor film, amorphous oxide semiconductors that do not contain crystalline components may be used. It can also form a conductive film. Furthermore, it is an oxide semiconductor in which microcrystalline regions are mixed within an amorphous oxide semiconductor. It can also form a semiconductor film.

[0190] Furthermore, the first heat treatment is performed on the oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer 620. It is also possible to do so. In that case, after the first heat treatment, remove the substrate from the heating device. The photolithography process is performed.

[0191] Using the oxide semiconductor layer 620 shown in this embodiment, a channel formation region and a source region or Between the drain region, there is an oxygen deficiency inducer with a lower concentration than the source region and the drain region. Transistors 640 and 650 having regions are shown in Figures 12(A) to 12(E) and 13( A) will be explained using Figure 13(C).

[0192] An oxide semiconductor layer 620 is formed on a substrate 600 on which an insulating layer 607 having an insulating surface is provided. This has been achieved (see Figure 12(A)).

[0193] In contact with one end of the oxide semiconductor layer 620, the first source electrode layer 625a and the second source electrode layer - A stack of electrode layers 635a is formed, and in contact with the other end of the oxide semiconductor layer 620, the first A stack of the first drain electrode layer 625b and the second drain electrode layer 635b is formed.

[0194] A first source electrode layer 625a and a first drain electrode layer 62 are in contact with the oxide semiconductor layer 620. 5b is a metal nitride layer, and the second source electrode layer 635a and the second drain electrode It is preferable to use a metal layer as the polar layer 635b. In this embodiment, the first source Titanium nitride films are used as the electrode layer 625a and the first drain electrode layer 625b, and the second saw The drain electrode layer 635a and the second drain electrode layer 635b consist of an aluminum film and titanium Lamination with a film is used.

[0195] Oxide semiconductor layer 620, first source electrode layer 625a, first drain electrode layer 625b, A gate insulating layer 60 is placed on the second source electrode layer 635a and the second drain electrode layer 635b. Forms 2.

[0196] The gate insulating layer 602 shall have a thickness of at least 1 nm, and shall be formed by sputtering or other methods. The insulating layer 602 can be formed using an appropriate method that prevents the incorporation of impurities such as water and hydrogen. Cut.

[0197] In this embodiment, a silicon oxide film with a thickness of 100 nm is used as the gate insulating layer 602. The film is deposited using the taring method. The substrate temperature during film deposition should be between room temperature and 300°C. In this embodiment, the temperature is set to 100°C. The silicon oxide film is deposited by sputtering. Under a noble gas (typically argon) atmosphere, under an oxygen atmosphere, or under a noble gas (typically argon) atmosphere This can be carried out in a gas and oxygen atmosphere. Furthermore, silicone oxide can be used as the target. A silicon target or a crystalline target can be used. For example, a silicon target Using a tweezers, silicon oxide is formed by sputtering under an oxygen and nitrogen atmosphere. The gate insulating layer 602, which is formed in contact with the oxide semiconductor layer 620, is resistant to moisture and It does not contain impurities such as hydrogen ions or hydroxyl groups, and blocks these from entering from the outside. These inorganic insulating films are typically used, such as silicon oxide films, silicon oxide nitride films, and aluminum oxide films. A nium film or an aluminum oxide nitride film is used.

[0198] In this case, the gate insulating layer 602 is formed while removing residual moisture in the processing chamber. Preferably, the oxide semiconductor layer 620 and the gate insulating layer 602 contain hydrogen, hydroxyl groups, or water. This is to prevent them from getting sick.

[0199] To remove residual moisture from the processing chamber, an adsorption-type vacuum pump such as a cryopump is used. It is preferable that they be present. The treatment chamber, which has been evacuated using a cryopump, is, for example, filled with hydrogen or water. Because compounds containing hydrogen atoms, such as H2O, are exhausted, the gate insulation of the film deposited in the processing chamber is affected. The concentration of impurities in the marginal layer 602 can be reduced.

[0200] Next, a second heat treatment (e.g., 200°C) is performed under an inert gas atmosphere or an oxygen gas atmosphere. The process is carried out at a temperature of 250°C to 400°C, preferably 250°C to 350°C. For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under gas pressure. After the second heat treatment, the oxide semiconductor With a portion of the body layer (including at least the channel-forming region) in contact with the gate insulating layer 602 It will be heated.

[0201] Through the above process, the oxide semiconductor layer after film formation is dehydrated or dehydrogenated. Heat treatment is performed to remove hydrogen, water, hydroxyl groups, or hydrides (also called hydrogen compounds), etc. The impurities are intentionally removed from the oxide semiconductor layer, and simultaneously reduced by the impurity removal process. It can supply oxygen, which is the main component material that makes up oxide semiconductors. That is, at least a portion of the oxide semiconductor layer including the channel formation region is purified and electrically charged It becomes type i (true) in terms of its energy.

[0202] In this embodiment, the oxide semiconductor layer 620 does not directly contact the gate insulating layer 602. The region overlapping with the first source electrode layer 625a or the first drain electrode layer 625b is as described above. Since oxygen is not supplied during the second heat treatment, the low resistance region of the n-type remains.

[0203] A gate electrode layer 601 is formed on the gate insulating layer 602 (see Figure 12(B)).

[0204] Furthermore, the region corresponding to the channel formation region of the oxide semiconductor layer 620 (gate electrode layer 601 and The oxygen deficiency-inducing factor can also be introduced into the overlapping region, and the oxygen deficiency-inducing factor can be included. i. In this case, oxygen vacancies are induced in the oxide semiconductor layer 620 before the formation of the gate electrode layer 601. The introduction process for the oxygen vacancy-inducing factor is performed before processing the oxide semiconductor film into island shapes. You can also go there. You can also introduce oxygen deficiency-inducing factors into the channel formation region and create an oxygen deficiency in the donor. By reducing the resistance (for example, by making it an n-type transistor), the electrical characteristics of the transistor can be controlled more effectively. It is possible.

[0205] After introducing oxygen deficiency-inducing factors, heat treatment (e.g., between 200°C and 600°C) is performed. It is also permissible. If an oxygen vacancy inducing factor is introduced before the first heat treatment, the heat treatment is the first It is preferable that this be combined with the heat treatment. For example, the introduction of an oxygen deficiency inducing factor and nitrogen By performing a heat treatment at a temperature between 200°C and 600°C under a controlled atmosphere, the oxide semiconductor layer is intrinsically transformed. This allows for lower resistance (n-type configuration).

[0206] The oxide semiconductor layer 620 in this embodiment is a highly purified oxide semiconductor layer, therefore acid The effect of introducing elementary defect-inducing factors becomes clearly apparent. Therefore, the oxygen defect-inducing factors included are Even in minute quantities, it is possible to effectively control the electrical characteristics of a transistor.

[0207] Next, the oxide semiconductor layer 620 is fitted with a gate electrode layer 601, a first source electrode layer 625a, and a first The drain electrode layer 625b, the second source electrode layer 635a, and the second drain electrode layer 6 Using 35b as a mask, the oxygen deficiency-inducing factor 630 is selectively introduced into the channel formation region 61 3. Regions containing oxygen deficiency-inducing factors 631a, 631b, Region without oxygen deficiency-inducing factors 611 a, 611b are formed (see Figure 12(C)). For example, oxygen deficiency-inducing factor-containing region 63 The concentration of oxygen deficiency-inducing factor 630 in 1a and 631b is 1 × 10¹⁸ atoms / Approximately cm³ should suffice.

[0208] By selectively introducing an oxygen vacancy-inducing factor 630 into the oxide semiconductor layer 620, It effectively induces oxygen deficiencies in the induction region. Since oxygen deficiencies function as donors, Oxide semiconductor having selectively low-resistance oxygen vacancy-inducing factor-containing regions 631a and 631b It can form a body layer.

[0209] In the region overlapping with the gate electrode layer 601, the oxygen vacancy inducer 630 is not introduced, and channel formation occurs. This becomes region 613.

[0210] In regions 611a and 611b where oxygen deficiency-inducing factors are not introduced, the oxygen deficiency-inducing factor 630 is introduced. However, dehydration or dehydrogenation can be performed under an inert gas atmosphere such as nitrogen or a noble gas. Because it has been converted to n-type by the first heat treatment, it is in the low-resistance region of n-type. Therefore, acid The ion semiconductor layer and the first source electrode layer 625a or the first drain electrode layer 625b are It can be connected via an n-type low-resistance region.

[0211] Next, channel-forming region 613, oxygen deficiency-inducing factor-containing regions 631a, 631b, oxygen Oxide semiconductor layer containing defect-inducing factor non-introduced regions 611a and 611b, first source electrode layer 625a, first drain electrode layer 625b, second source electrode layer 635a, second drain An insulating layer 609 is formed to cover the electrode layer 635b, the gate insulating layer 602, and the gate electrode layer 601. do.

[0212] Next, oxygen vacancy inducing factors are found in the oxygen vacancy inducing factors regions 631a and 631b of the oxide semiconductor layer. Sub-sub 14a, drain region 614b, channel formation region 613, oxygen deficiency-inducing factor non-introduced region An oxide semiconductor layer 633 containing 611a and 611b is formed (see Figure 12(D)). For example The concentration of the oxygen vacancy-inducing factor 632 contained in the source region 614a and the drain region 614b The degree should be between 1 × 10¹⁹ atoms / cm³ and 1 × 10²¹ atoms / cm³. Yes.

[0213] Furthermore, the insulating layer 609 provided on the side surface of the gate electrode layer 601 also acts as a mask, so the gate Oxygen into the oxide semiconductor layer 620 which overlaps with the electrode layer 601 and the insulating layer 609 provided on the side surface. The introduction of defect-inducing factor 632 is inhibited, and low-concentration oxygen defect-inducing factor-containing regions 615a, 61 This results in 5b. In particular, in this embodiment, because the thickness of the gate electrode layer 601 is thick, the oxide semi The introduction of the oxygen vacancy inducer 632 into the conductive layer 620 is further inhibited.

[0214] Furthermore, when introducing an oxygen vacancy-inducing factor into the channel-forming region 613, the channel shape The concentration of oxygen deficiency-inducing factors contained in region 613 is determined by the low-concentration oxygen deficiency-inducing factor-containing region 6 The concentrations in 15a, 615b, source region 614a, and drain region 614b should be lower. As in the embodiment, oxygen vacancies are introduced in the source region 614a and the drain region 614b. The concentration of the causative factor is between 1 × 10¹⁹ atoms / cm³ and 1 × 10²¹ atoms / cm³. Below, the oxygen deficiency-inducing factors contained in the low-concentration oxygen deficiency-inducing factor-containing regions 615a and 615b If the concentration is around 1 × 10¹⁸ atoms / cm³, for example, channel formation region 61 The concentration of 3 should be less than 1 × 10¹⁴ atoms / cm³.

[0215] The transistor 640 can be fabricated using the above process (see Figure 12(E)).

[0216] In the transistor 650 shown in Figure 13(C), the gate insulating layer overlaps with the gate electrode layer 601. The area outside the region has been removed, resulting in an island-shaped gate insulating layer 604. Therefore, the insulating layer 609 is Low-concentration oxygen vacancy-inducing factor-containing regions 615a, 615b, and source region of oxide semiconductor layer 633 Region 614a, drain region 614b, first source electrode layer 625a, first drain electrode Layer 625b, second source electrode layer 635a, second drain electrode layer 635b, and gate It is provided in contact with the electrode layer 601.

[0217] Similar to transistor 640, after proceeding to the step shown in Figure 12(C), the gate electrode layer 601 is formed As a mask, the gate insulating layer is etched to form island-shaped gate insulating layers 604 (Figure) 13(A)).

[0218] Furthermore, etching of the gate insulating layer forms oxygen vacancy-inducing factor-containing regions 631a and 631b. This may be done before introducing oxygen deficiency-inducing factors. In this case, the oxygen deficiency-inducing factors are exposed. It will be directly introduced into the oxide semiconductor layer 620.

[0219] Next, channel-forming region 613, oxygen deficiency-inducing factor-containing regions 631a, 631b, oxygen Oxide semiconductor layer containing defect-inducing factor non-introduced regions 611a and 611b, first source electrode layer 625a, first drain electrode layer 625b, second source electrode layer 635a, second drain An insulating layer 609 is formed to cover the electrode layer 635b, the gate insulating layer 604, and the gate electrode layer 601. In Figure 13, the oxygen vacancy-inducing factor-containing region 631 in the oxide semiconductor layer 633 is shown. Since the gate insulating layer on a, 631b has been removed, the insulating layer 609 is exposed and oxygen-deficient. It is formed in contact with the depression-inducing factor-containing regions 631a and 631b.

[0220] Next, oxygen vacancy inducing factors are found in the oxygen vacancy inducing factors regions 631a and 631b of the oxide semiconductor layer. Sub-636 is introduced, and the low-concentration oxygen deficiency-inducing factor-containing regions 615a, 615b, and source region 6 14a, drain region 614b, channel formation region 613, oxygen deficiency-inducing factor non-introduced region An oxide semiconductor layer 633 containing 611a and 611b is formed (see Figure 13(B)). For example The concentration of the oxygen vacancy inducer 636 contained in the source region 614a and the drain region 614b The degree should be between 1 × 10¹⁹ atoms / cm³ and 1 × 10²¹ atoms / cm³. Yes.

[0221] Furthermore, the insulating layer 609 provided on the side surface of the gate electrode layer 601 also acts as a mask, so the gate Oxygen into the oxide semiconductor layer 620 which overlaps with the electrode layer 601 and the insulating layer 609 provided on the side surface. The introduction of defect-inducing factor 636 is inhibited, and low-concentration oxygen defect-inducing factor-containing regions 615a, 61 This results in 5b. In particular, in this embodiment, the thickness of the gate electrode layer 601 is thick, and further gate Since an insulating layer 604 is also formed, oxygen vacancy inducer 636 to the oxide semiconductor layer 620 The introduction of this will be further hindered.

[0222] The transistor 650 can be manufactured using the above process.

[0223] The oxygen deficiency-inducing factors 630, 632, and 636 are titanium (Ti) and tungsten (W). ), molybdenum (Mo), aluminum (Al), cobalt (Co), zinc (Zn), i Select one or more from the following: ion (In), silicon (Si), or boron (B) The elements can be used. Furthermore, in addition to the oxygen vacancy inducing factors mentioned above, hydrogen, or Nitrogen may also be used. Note that the oxygen deficiency inducing factors 630, 632, and 636 are acid It is more preferable to use metal elements with high elementary affinity.

[0224] As described above, the low-concentration oxygen deficiency-inducing factor, which has been made less resistant by introducing an oxygen deficiency-inducing factor, contains Regions 615a and 615b, and source region 614a, which contains high-concentration oxygen deficiency-inducing factors. and a transistor 640 having an oxide semiconductor layer 633 having a drain region 614b, 650 consists of an oxide semiconductor layer 633, a first source electrode layer 625a, and a first drain electrode layer Because the contact resistance with 625b can be reduced, the on-characteristics (e.g., on-current and field effect) can be improved. Mobility improves. Therefore, it becomes possible to create a transistor with high electrical characteristics.

[0225] Transistors with high electrical characteristics enable fast response and fast drive, therefore, such transistors By incorporating this feature, it becomes possible to create a highly functional semiconductor device.

[0226] Furthermore, by having an oxide semiconductor layer with gradually changing conductivity, the transistor's electrical conductivity... Because field concentration can be suppressed and the application of localized high electric fields can be prevented, the breakdown voltage of the transistor is improved, and semicircular This can provide high reliability to conductive devices.

[0227] This embodiment can be implemented in appropriate combination with other embodiments.

[0228] (Embodiment 5) A semiconductor device and a method for manufacturing a semiconductor device will be explained using Figure 4. Note that Embodiment 1 and The parts and processes are the same as or have similar functions as those in Embodiment 2. Alternatively, the procedure can be carried out in the same manner as in Embodiment 2, and a repeated explanation will be omitted.

[0229] First, an insulating layer 407 is formed on the substrate 400. Then, a first oxidation is formed on the insulating layer 407. A material semiconductor layer is formed, and at least the surface of the first oxide semiconductor layer is subjected to a first heat treatment. The region containing the material is crystallized to form the first oxide semiconductor layer 450a (see Figure 4(A)). .

[0230] The first oxide semiconductor layer 450a formed on the insulating layer 407 is an oxide of a ternary metal. Using an oxide semiconductor material represented by the chemical formula InMXZnYOZ (Y=0.5~5), It is also acceptable to use such a material. Here, M can be gallium (Ga), aluminum (Al), or boron (B), etc. This represents one or more elements selected from the Group 13 elements. Note that it may also include Zn and O. The quantities are arbitrary and include the case where the content of M is zero (i.e., X=0). On the other hand, In and Z The content of n is not zero. In other words, the above notation includes In-Ga-Zn-O and In- It contains Zn-O, etc.

[0231] In addition, as the first oxide semiconductor layer 450a, In-Sn, an oxide of a quaternary metal, can also be used. -Ga-Zn-O systems, and ternary metal oxides such as In-Sn-Zn-O systems and Sn-Ga -Zn-O systems, Al-Ga-Zn-O systems, Sn-Al-Zn-O systems, and oxidation of binary metals The substances are Sn-Zn-O system, Al-Zn-O system, Zn-Mg-O system, Sn-Mg-O system, In-Mg-O systems, as well as In-O, Sn-O, and Zn-O systems, can also be used.

[0232] In this embodiment, the first oxide semiconductor layer 450a is made of an In-Ga-Zn-O based oxide. The material will be formed using a semiconductor target by sputtering.

[0233] The relative density of the oxide semiconductor in the oxide semiconductor target is 80% or more, preferably 95% or more. More preferably, it shall be 99.9% or higher. A high relative density oxide semiconductor target By using this method, a dense first oxide semiconductor layer 450a is formed. In terms of form, the first oxide semiconductor layer 450a is intentionally crystallized by subsequent heat treatment. Therefore, it is preferable to use an oxide semiconductor target that is prone to crystallization.

[0234] The formation atmosphere for the first oxide semiconductor layer 450a is a noble gas (typically argon) atmosphere. An oxygen atmosphere, or a mixed atmosphere of oxygen and a noble gas (typically argon), is preferable. It is suitable. Specifically, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides have been removed. It is preferable to use a high-purity gas atmosphere.

[0235] During the formation of the first oxide semiconductor layer 450a, for example, in a processing chamber held under reduced pressure The substrate is held in place, and the substrate temperature is maintained between 200°C and 600°C. Then, the residual in the processing chamber Sputtered gas, from which water and hydrogen have been removed while moisture is being removed, is introduced, and metal oxides are targeted. A first oxide semiconductor layer 450a is formed as a base. The first oxide semiconductor layer is formed while heating the substrate. By forming the conductive layer 450a, impurities contained in the first oxide semiconductor layer 450a are removed. This can reduce the amount of sputtering damage. Before, during, or after deposition of the semiconductor layer 450a, residual material remains in the sputtering apparatus. It is preferable to remove any remaining moisture. In order to remove residual moisture in the processing chamber, It is preferable to use an adsorption-type vacuum pump such as a cryopump. The exhausted processing chamber has had hydrogen and water removed, so the first oxide semiconductor layer 45 The impurity concentration of 0a can be reduced.

[0236] Furthermore, before depositing the first oxide semiconductor layer 450a, moisture remaining in the sputtering apparatus Preheating is recommended to remove these and other impurities. Methods include heating the inside of the bar under reduced pressure to between 200°C and 600°C, or heating while adding nitrogen or inertia. Methods include repeatedly introducing and exhausting a sterilizing gas. After the preheating process is complete, the substrate or... After cooling the puttering apparatus, the oxide semiconductor layer is deposited without exposure to the atmosphere. For the target coolant, it is better to use oil or grease rather than water. Nitrogen is introduced and exhausted without heating. Repeating this process will yield some results, but it is even better if done while heating.

[0237] The conditions for forming the first oxide semiconductor layer 450a include, for example, the relationship between the substrate and the target. The distance is 170 mm, the pressure is 0.4 Pa, the DC power is 0.5 kW, and the atmosphere is oxygen. Conditions such as ambient temperature can be applied. Furthermore, when using a pulsed DC power supply... This reduces dust (powdered or flake-like material formed during film formation) and also improves the uniformity of film thickness distribution. This is preferable because it results in a single unit. The thickness of the first oxide semiconductor layer 450a is 3 nm or more and 15 nm or less. It is preferable to set it to the lower side, and in this embodiment, it is set to 5 nm as an example. However, the acid to be applied The appropriate thickness varies depending on the semiconductor material and application, so the thickness depends on the material and application used. You can choose according to your needs and circumstances.

[0238] The temperature of the first heat treatment is 450°C to 850°C, preferably 550°C to 750°C. The following applies. The heating time shall be between 1 minute and 24 hours. In this embodiment, the first As a heat treatment, the product is subjected to a heat treatment at 700°C for 1 hour under a nitrogen atmosphere to dehydrate or dehydrogenate it. After the transformation is performed, the atmosphere is switched to an oxygen atmosphere to create the first oxide semiconductor layer 45 Oxygen is supplied to the interior of 0a. In addition, this first heat treatment causes the first oxide semiconductor layer 4 It can remove water (including hydroxyl groups) and hydrogen from 50a.

[0239] In the first heat treatment, nitrogen, oxygen, or helium, neon, argon, etc. It is preferable that the noble gas does not contain water, hydrogen, etc. Alternatively, it may be introduced into a heat treatment device. The purity of nitrogen, oxygen, or noble gases such as helium, neon, and argon is 6N (99.99%). 99% or higher, preferably 7N (99.99999% or higher), (i.e., impurity concentration of 1 pp) It is preferable that the concentration be less than or equal to m, preferably less than or equal to 0.1 ppm. Also, the concentration of H2O is 20 ppm. In ultra-dry air with a minimum of m of humidity, and more preferably in ultra-dry air with a H2O concentration of 1 ppm or less, A first heat treatment may be performed. This first heat treatment may result in the first oxide semiconductor Water (including hydroxyl groups) and hydrogen can be removed from layer 450a.

[0240] The first heat treatment results in a region having a crystalline region (non-single crystal region) in at least the surface region. A first oxide semiconductor layer 450a is formed. The crystalline region formed in the region including the surface is the surface It is formed by crystal growth from the surface inward. The crystalline region has an average thickness of 2n It is a plate-like crystal with a thickness of m or more and a thickness of 10 nm or less. Furthermore, the crystalline region is substantially perpendicular to the surface. This is a region having crystals in which the c-axis is oriented in the direction. Here, "approximately perpendicular" means -1 from the vertical direction. This refers to a state within 0° or within +10° from the vertical.

[0241] Furthermore, the heat treatment apparatus used for the first heat treatment is not particularly limited, and may include a heat source such as a resistance heating element. Devices that heat the object to be processed by heat conduction or thermal radiation can be used.

[0242] Next, on the first oxide semiconductor layer 450a having a crystalline region in at least the surface region, Then, a second oxide semiconductor layer 454 is formed (see Figure 4(B)).

[0243] The second oxide semiconductor layer 454, like the first oxide semiconductor layer 450a, is a quaternary metal. In-Sn-Ga-Zn-O oxides and In-Ga- ternary metal oxides Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O Al-Ga-Zn-O system, Sn-Al-Zn-O system, and binary metal oxides such as I n-Zn-O series, Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg Oxide semiconductors such as -O-based, In-Mg-O-based, In-O-based, Sn-O-based, and Zn-O-based. It can be formed using [this method].

[0244] Furthermore, the second oxide semiconductor layer 454 is made of the same main component material as the first oxide semiconductor layer 450a. Using materials, or materials with the same crystal structure and closely spaced lattice constants (mismatch of 1% or less). It is preferable that it has ), or it may be formed using materials with different main components.

[0245] When using materials with the same main component, the crystallization of the second oxide semiconductor layer 454 that is carried out later... This makes it easier to grow crystals using the crystalline region of the first oxide semiconductor layer 450a as a seed. Furthermore, because it can effectively increase the film thickness, it is suitable for applications such as power devices. Furthermore, if the main component material is the same, the interfacial properties such as adhesion and electrical properties will also be the same. It is good.

[0246] In this embodiment, the second oxide semiconductor layer 454 is made of an In-Ga-Zn-O based oxide semiconductor. The second oxide semiconductor layer 45 is formed by sputtering using a conductive target. The film deposition by the sputtering method of 4 is the sputtering of the first oxide semiconductor layer 450a described above. The process can be carried out in the same manner as with the ring deposition method. However, the thickness of the second oxide semiconductor layer 454 is It is preferable that the thickness of the first oxide semiconductor layer 450a is greater than the thickness of the first oxide semiconductor layer. The sum of the thicknesses of the monocrystalline semiconductor layer 450a and the second oxide semiconductor layer 454 is between 3 nm and 50 nm. It is preferable to form the second oxide semiconductor layer 454 in such a manner. The appropriate thickness varies depending on the oxide semiconductor material and application, so the thickness depends on the material used and You can choose according to your needs and preferences.

[0247] Next, the second oxide semiconductor layer 454 is subjected to a second heat treatment, and the first oxide semiconductor layer 45 Crystal growth is carried out using the crystalline region of 0a as a seed to form the second oxide semiconductor layer 450b. See Figure 4(C).

[0248] The temperature for the second heat treatment is 450°C to 850°C, preferably 600°C to 700°C. The following applies: The heating time for the second heat treatment shall be 1 minute or more and 400 hours or less, preferably 5 hours. The duration should be between 20 hours and 10 hours, with 10 hours being a typical example.

[0249] Furthermore, in the second heat treatment, nitrogen, oxygen, or helium, neon, argon, etc. It is preferable that the noble gas does not contain water, hydrogen, etc. Alternatively, it may be introduced into a heat treatment device. The purity of nitrogen, oxygen, or noble gases such as helium, neon, and argon is preferably 6N or higher. It is preferable that the N content be 7N or higher. Also, in ultra-dry air with H2O content of 20 ppm or less More preferably, the second heat treatment is performed in ultra-dry air containing 1 ppm or less of H2O. This is also good. This second heat treatment removes water (hydroxyl) from the second oxide semiconductor layer 450b. It can remove impurities (including the group) and hydrogen. Therefore, it reduces impurities and increases purity, i A first oxide semiconductor layer 450a that is typed or substantially i-typed and a second oxide semiconductor Layer 450b can be formed.

[0250] Furthermore, during the heating process of the second heat treatment, the inside of the furnace is filled with a nitrogen atmosphere, and during the cooling process, the inside of the furnace is filled with acid. The atmosphere can be switched as a primary atmosphere, and crystallization can be performed in a nitrogen atmosphere (this process involves dehydration). After the dehydrogenation process (which also includes dehydrogenation) is performed, the atmosphere is switched to an oxygen atmosphere to produce a second reaction. Oxygen can be supplied to the inside of the oxide semiconductor layer 450b.

[0251] In this way, by performing the second heat treatment, the second oxide semiconductor layer 454 and the first acid From the crystalline region formed at the interface of the oxide semiconductor layer 450a to the entire second oxide semiconductor layer 454 The second oxide semiconductor layer 450b can be formed by crystallizing the material. Heat treatment further enhances the orientation of the first oxide semiconductor layer 450, which consists of a crystalline layer with even higher orientation. It can be set to a.

[0252] For example, an In-Ga-Zn-O based oxide semiconductor material is used in the second oxide semiconductor layer 450b. When used, it is represented as InGaO3(ZnO)m (m>0, where m is not limited to a natural number). Crystals that are represented as In2Ga2ZnO7 (In:Ga:Zn:O=2:2:1:7) It may contain crystals such as the first. Such crystals, by a second heat treatment, have their c-axis changed to the first The oxide semiconductor layer 450a and the second oxide semiconductor layer 450b are positioned in a direction approximately perpendicular to their surfaces. It is oriented in such a way.

[0253] Here, the crystal described above contains either In, Ga, or Zn, and the a-axis is It can be understood as a stacked structure of layers parallel to the b-axis. In terms of the above crystal, it consists of a layer containing In and a layer that does not contain In (Ga). It has a structure in which layers (or layers containing Zn) are stacked in the c-axis direction.

[0254] In an In-Ga-Zn-O oxide semiconductor crystal, the a-axis of the In-containing layer is The conductivity in the direction parallel to the b-axis is good. This is because the In-Ga-Zn-O system acid In ionized semiconductor crystals, electrical conductivity is mainly controlled by In, and one In The 5s orbital of In overlaps with the 5s orbital of the adjacent In, thus shaping the carrier path. By being accomplished.

[0255] Furthermore, the first oxide semiconductor layer 450a has an amorphous region at the interface with the insulating layer 407. In the case of such a structure, by performing a second heat treatment, the surface of the first oxide semiconductor layer 450a Crystal growth is carried out from the crystalline region formed thereto toward the lower surface of the first oxide semiconductor layer. In some cases, the amorphous region may crystallize. Furthermore, the materials constituting the insulating layer 407 and the heat treatment Depending on the conditions, the amorphous region may remain.

[0256] The first oxide semiconductor layer 450a and the second oxide semiconductor layer 454 have oxide semiconductors with the same main component. When using a conductive material, as shown in Figure 4(C), the first oxide semiconductor layer 450a is crystallized. As a seed for growth, crystals grow upward toward the surface of the second oxide semiconductor layer 454, and the second An oxide semiconductor layer 450b is formed, and the first oxide semiconductor layer 450a and the second oxide The semiconductor layer 450b has the same crystal structure. Therefore, it is shown by the dotted line in Figure 4(C). However, the boundary between the first oxide semiconductor layer 450a and the second oxide semiconductor layer 450b cannot be determined. Therefore, the first oxide semiconductor layer 450a and the second oxide semiconductor layer 450b are considered to be the same layer. It is possible.

[0257] Furthermore, the heat treatment apparatus used for the second heat treatment shall be used under the same conditions as the first heat treatment. It is possible.

[0258] Next, the first oxide semiconductor layer 450a and The second oxide semiconductor layer 450b is processed into an island shape to form an island-shaped oxide semiconductor layer 450. (See Figure 4(D)).

[0259] Using the formed island-shaped oxide semiconductor layer 450, the fabrication method described in Embodiments 1 to 3 By combining these components, a transistor according to one aspect of the present invention can be formed.

[0260] As shown in this embodiment, the oxide semiconductor layer is deposited in two separate steps, and the heating treatment is performed in two separate steps. By performing this process, regardless of the material of the base material, such as oxides, nitrides, or metals, the film thickness can be adjusted. It is possible to obtain a crystalline region (non-single crystal region), that is, a crystalline region oriented perpendicular to the film surface along the c axis. Yes, it is possible. However, when using a typical silicon semiconductor, the crystal structure will collapse after ion implantation. As a result, the resistivity becomes significantly higher, so it was necessary to restore the crystallinity through heat treatment. In this embodiment as well, the oxide semiconductor in the region where the oxygen vacancy inducer is ion-implanted is The crystal structure collapses, resulting in an amorphous state. However, in oxide semiconductors, Even in a morphous state, if there are enough carriers, the necessary conductivity can be obtained, so Annealing is not required after injection.

[0261] Transistors using oxide semiconductor layers with crystalline regions have high field effect transfer This enables the realization of high on-characteristics such as high kinetic energy. Furthermore, it allows for the implementation of transistors with low off-current. It can be expressed.

[0262] This embodiment can be used in appropriate combination with other embodiments.

[0263] (Embodiment 6) The transistors shown as examples in Embodiments 1 to 5 above are used in the pixel section and further in the driving circuit. This allows for the fabrication of semiconductor devices (also called display devices) that have a display function. The transistors are integrated into the drive circuit, either partially or entirely, on the same substrate as the pixel section, and the system A Muon panel can be formed.

[0264] A display device having various display elements using the transistors shown as an example in Embodiments 1 to 5 It can provide a display element. The display element is a liquid crystal element (also called a liquid crystal display element), and it emits light. A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element is activated by current or voltage. This category includes elements whose brightness is controlled, specifically inorganic EL (Electrical LEDs). This includes Luminescence, organic EL, etc. Also, electronic inks, etc. Display media in which contrast changes due to the effect can also be applied.

[0265] In Figure 5(A), the pixel portion 4002 provided on the first substrate 4001 is surrounded by A sealing material 4005 is provided and sealed by the second substrate 4006. Figure 5( In A), the region surrounded by the sealing material 4005 on the first substrate 4001 and These are formed in different regions on a separately prepared substrate using a single-crystal semiconductor film or a polycrystalline semiconductor film. A scan line drive circuit 4004 and a signal line drive circuit 4003 are implemented. The signal line drive circuit 4003 and the scan line drive circuit 4004 or the pixel unit 4002 are supplied The various signals and potentials are transmitted via FPC (Flexible Printed Circuit). ) Supplied from 4018a and 4018b.

[0266] In Figures 5(B) and 5(C), the pixel portion 4002 is provided on the first substrate 4001. A sealing material 4005 is provided so as to surround the scan line drive circuit 4004. Furthermore, a second substrate 4006 is provided on the pixel section 4002 and the scan line driving circuit 4004. Therefore, the pixel section 4002 and the scan line driving circuit 4004 are connected to the first substrate 4001. The display element is sealed together with the material 4005 and the second substrate 4006. Figure 5 In (B) and Figure 5(C), the sealing material 4005 on the first substrate 4001 surrounds A single-crystal semiconductor film or polycrystalline semiconductor film is placed on a separately prepared substrate in a region different from the area where the film is being made. A signal line driving circuit 4003, formed from a conductive film, is implemented. (Figures 5(B) and 5(C)) In this case, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 and The various signals and potentials supplied to the pixel unit 4002 are supplied from the FPC 4018. .

[0267] Furthermore, in Figures 5(B) and 5(C), a signal line drive circuit 4003 is formed separately, and the first An example of implementation on board 4001 is shown, but the configuration is not limited to this. Scan line driving The circuit may be formed and implemented separately, or it may be part of the signal line drive circuit or part of the scan line drive circuit. It is also acceptable to form and implement only the relevant part separately.

[0268] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG(Ch ip On Glass) method, wire bonding method, or TAB (Tape A Methods such as utmost bonding can be used. Figure 5(A) shows C This is an example of implementing the signal line drive circuit 4003 and the scan line drive circuit 4004 using the OG method. Figure 5(B) shows an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 5(C) shows an example of implementing the signal line drive circuit 4003 using the COG method. This is an example of implementing the signal line drive circuit 4003 using the TAB method.

[0269] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. Includes modules with ICs and other components mounted on them.

[0270] In this specification, the term "display device" refers to an image display device, a display device, or an optical display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC or TAB tape. A module with TCP attached, a TAB tape, or a printed circuit board at the end of the TCP. An IC (integrated circuit) is directly mounted to the provided module or display element using the COG method. All modules that have been modified shall also be included in the display device.

[0271] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are, The device has multiple transistors, and examples of these transistors are shown in Embodiments 1 to 5. A transistor can be applied.

[0272] When using liquid crystal elements as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, and polymer liquid crystals are used. Crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. are used. Depending on the conditions, the cholesteric phase, smectic phase, cubic phase, chiral nematics This shows the cubic phase, isotropic phase, etc.

[0273] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so improving the temperature range is necessary. To achieve this, a liquid crystal composition containing several weight percent or more of a chiral agent is used in the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less. Furthermore, because it is optically isotropic, orientation processing is unnecessary, and it has low dependence on viewing angle. Since it is not necessary to provide a rubbing treatment, the rubbing treatment does not need to be performed. This prevents electrostatic discharge (ESD) damage, reducing defects and damage to liquid crystal displays during the manufacturing process. This makes it possible to improve the productivity of liquid crystal display devices. Transistors using a conductive layer are significantly affected by static electricity, which can drastically alter their electrical properties. There is a risk of it fluctuating and deviating from the design range. Therefore, transistors using oxide semiconductor layers Using a blue-phase liquid crystal material in a liquid crystal display device is more effective.

[0274] Furthermore, the resistivity of the liquid crystal material is 1 × 10⁹ Ω·cm or greater, preferably 1 × 10¹¹ The resistance is Ω·cm or greater, and more preferably 1 × 10¹² Ω·cm or greater. The resistivity values ​​in this document shall be those measured at 20°C.

[0275] The size of the retention capacitance provided in a liquid crystal display device depends on the regeneration of the transistors arranged in the pixel area. The capacity is set to hold the charge for a predetermined period, taking into account the current and other factors. This should be set considering the transistor's off-current, etc. Embodiment 4 and Embodiment By using a transistor having a high-purity oxide semiconductor layer as shown in 5, each pixel A storage container having a capacity of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacity. Providing sufficient quantity is enough.

[0276] LCD displays include TN (Twisted Nematic) mode and IPS (In-Place Printed Display). lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. Use modes such as UID Crystal.

[0277] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, It may also be used as a transmissive liquid crystal display device. Several vertical orientation modes are possible, For example, MVA (Multi-Domain Vertical Alignment) Mode, PVA (Patterned Vertical Alignment) mode ASV mode and other modes can be used.

[0278] Furthermore, it can also be applied to VA-type liquid crystal display devices. A VA-type liquid crystal display device is a liquid crystal display device. This is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. VA-type liquid crystal display devices are... This method aligns the liquid crystal molecules perpendicular to the panel surface when no voltage is applied. Furthermore, a pixel is divided into several subpixel regions, each in a different direction. This is called multi-domainization or multi-domain design, which is a method designed to defeat molecules. A method can be used.

[0279] Furthermore, in a display device, the black matrix (light-shielding layer), polarizing member, phase difference member, and reflector are used. Optical components (optical substrates) such as protective members are provided as appropriate. For example, polarizing substrates and phase difference substrates Circularly polarized light from a plate may be used. Also, backlights, sidelights, etc., may be used as light sources. It's okay to be there.

[0280] Furthermore, the display method used in the pixel area may be a progressive or interlaced method. It is possible. Also, when displaying in color, the color elements controlled by pixels are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (where W represents white). Alternatively, some models use RGB with one or more additional colors such as yellow, cyan, or magenta. The size of the display area for each dot of the color element may differ. However, the present invention is color - Not limited to display devices, it can also be applied to monochrome display devices. can.

[0281] Furthermore, as a display element included in the display device, an electroluminescent light-emitting element is used. It can be applied to light-emitting devices that utilize electroluminescence. They are distinguished by whether they are organic or inorganic compounds, and generally the former are organic E The latter is called an L element, and the latter an inorganic EL element.

[0282] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each of these is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Then, these... The recombination of electrons and holes causes the luminescent organic compound to form an excited state. And when that excited state returns to the ground state, it emits light. From this mechanism, Such light-emitting devices are called current-excited light-emitting devices.

[0283] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized type of luminescence used.

[0284] Furthermore, it is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display), and it is a paper-like material. It offers the same readability, lower power consumption compared to other display devices, and a thin and light form factor. It has the advantage of being such.

[0285] Electrophoresis display devices can take various forms, but one is a first particle with a positive charge and Multiple microcapsules containing a second particle having a negative charge are in the solvent or solute. It is a dispersed substance, and by applying an electric field to the microcapsules, the microcapsules Move the particles in the cell in opposite directions and display only the color of the particles that have gathered on one side. Furthermore, the first or second particle contains dye and moves in the absence of an electric field. It is immovable. Also, the color of the first particle and the color of the second particle are different (including colorless). )

[0286] Thus, electrophoretic devices can detect the movement of substances with high dielectric constants into high electric field regions. This display utilizes a mild dielectrophoretic effect.

[0287] When the above microcapsules are dispersed in a solvent, it is called an electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0288] Furthermore, the first and second particles in the microcapsules are made of conductive material, insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A type of material selected from trochromic materials, magnetophoretic materials, or a composite material thereof Use it.

[0289] Furthermore, a display device using the twist ball display method can also be applied as electronic paper. Yes, it is possible. The twist ball display method uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, which are electrode layers, and the first electrode layer and the second This method of displaying information involves controlling the orientation of spherical particles by creating a potential difference in the electrode layer. be.

[0290] Applying the transistors shown in Embodiments 1 to 5 to the display device shown as an example above. Therefore, a display device with various functions can be provided.

[0291] This embodiment can be implemented in appropriate combination with other embodiments.

[0292] (Embodiment 7) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. As an electronic device, for example, a television set (television, or television Receivers (also called receivers), computer monitors, digital cameras, digital video cameras Digital photo frame, mobile phone (also called mobile phone or mobile phone device), portable Examples include game consoles, personal digital assistants, audio playback devices, and large game machines such as pachinko machines. ru.

[0293] Figure 6(A) shows a semiconductor device as shown in any of Embodiments 1 to 6, with at least one component. This is a notebook-type personal computer that was implemented and manufactured using the following methods: main unit 3001, casing 3 It consists of 002, a display unit 3003, a keyboard 3004, and the like.

[0294] Figure 6(B) shows a semiconductor device as shown in any of Embodiments 1 to 6, with at least one component. This is a personal digital assistant (PDA) manufactured by implementing the above, and the main unit 3021 has a display unit 3023 Furthermore, an external interface 3025 and operation buttons 3024, etc. are provided. A stylus 3022 is included as an accessory for the device.

[0295] Furthermore, the semiconductor device shown in any of Embodiments 1 to 6 can be used as electronic paper. This is possible. Figure 6(C) shows an e-book created by implementing the electronic paper as a component. Figure 6(C) shows an example of an e-book. For example, e-book 2700 is a box. It consists of two enclosures, body 2701 and enclosure 2703. Enclosure 2701 and enclosure 2703 is integrated with the shaft portion 2711, and the shaft portion 2711 acts as an axis for opening and closing. This configuration makes it possible to perform actions similar to those of a paper book. Yes.

[0296] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed in the display unit on the right (display unit 2705 in Figure 6(C)), and the table on the left... An image can be displayed on the display unit (display unit 2707 in Figure 6(C)).

[0297] Furthermore, Figure 6(C) shows an example in which the housing 2701 is equipped with an operating section, etc. Body 2701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, etc. The page can be turned using operation key 2723. Note that it is on the same plane as the display unit of the casing. It may also be configured to include a keyboard and pointing device. External connection terminals (earphone jack, USB terminal, etc.), recording media insertion slot, etc. are located on the front or sides. It may also be configured to include these features. Furthermore, the eBook 2700 may be equipped with the functionality of an electronic dictionary. This configuration is also acceptable.

[0298] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. By wireless means, The system will be configured to allow users to purchase and download desired book data from an e-book server. It is also possible.

[0299] Figure 6(D) shows a semiconductor device as shown in any of Embodiments 1 to 6, with at least one component. This is a mobile phone that was manufactured by implementing and manufacturing, and consists of two casings, casing 2800 and casing 2801. It has been done. The enclosure 2801 contains a display panel 2802, a speaker 2803, and a micro Phone 2804, pointing device 2806, camera lens 2807, external connection It is equipped with terminal 2808, etc. Furthermore, the housing 2800 is used for charging portable information terminals. It is equipped with a solar cell 2810, an external memory slot 2811, and other features. It is built into the 2801 enclosure.

[0300] Furthermore, the display panel 2802 is equipped with a touch panel, and as shown in Figure 6(D), it displays video. The multiple operation keys 2805 are shown with dotted lines. Note that the output from the solar cell 2810 A boost circuit is also implemented to increase the voltage from the source voltage to the voltage required for each circuit.

[0301] The display panel 2802 changes its display orientation as appropriate depending on the usage mode. Since the camera lens 2807 is located on the same plane as the 2802, video calls are possible. Speaker 2803 and microphone 2804 are not limited to voice calls, but also video calls. Recording and playback are possible. Furthermore, the casings 2800 and 2801 slide apart, as shown in the diagram. As shown in 6(D), it can be transformed from an unfolded state to an overlapping state, making it suitable for carrying around. It can be made even smaller.

[0302] External connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication with personal computers, etc. By inserting a recording medium into memory slot 2811, it becomes possible to store and move larger amounts of data. ru.

[0303] Furthermore, even if it has infrared communication capabilities, television reception capabilities, etc. in addition to the above functions good.

[0304] Figure 6(E) shows a semiconductor device as shown in any of Embodiments 1 to 6, with at least one component. This is a digital video camera manufactured by implementing the following: main unit 3051, display unit (A) 3057 Eyepiece 3053, operation switch 3054, display unit (B) 3055, battery 3056 It is composed of the following:

[0305] Figure 6(F) shows a semiconductor device as shown in any of Embodiments 1 to 6, with at least one component. This shows an example of the television system 9600 that was implemented. Television system 9600 The display unit 9603 is incorporated into the housing 9601. The display unit 9603 displays the video. It is possible to display this. Also, here the stand 9605 supports the casing 9601. It shows a well-structured configuration.

[0306] The television unit 9600 is operated using the control switches on the housing 9601 and a separate remote control. This can be done using the control unit. Furthermore, the remote control unit can be accessed from the said remote control unit. The configuration may also include a display unit that shows the information to be output.

[0307] The television system 9600 will be configured to include a receiver, modem, etc. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0308] This embodiment can be freely combined with embodiments 1 to 6. [Explanation of symbols]

[0309] 400 circuit boards 401 Guard Layer 402 Gate Insulation Layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating layer 409 Insulating layer 410 transistors 411 Insulating layer 413 Channel formation region 414a Source area 414b Drain area 415a Region containing low-concentration oxygen deficiency-inducing factors 415b Region containing low-concentration oxygen deficiency-inducing factors 420 Oxide Semiconductor Layer 421 Oxygen deficiency-inducing factors 430 Oxygen deficiency-inducing factors 431a Region containing oxygen deficiency-inducing factors 431b Region containing oxygen deficiency-inducing factors 432 Oxygen deficiency-inducing factors 433 Oxide semiconductor layer 434 Oxygen deficiency-inducing factors 440 transistors 450 Oxide semiconductor layer 450a First oxide semiconductor layer 450b Second oxide semiconductor layer 454 Second oxide semiconductor layer 500 circuit boards 501 Grid Unit Layer 502 Gate Insulation Layer 503 Oxide semiconductor layer 507 Insulating layer 510 transistors 511a Region without oxygen deficiency-inducing factors 511b Region without oxygen deficiency-inducing factors 512a Source area 512b Drain region 513 Channel formation region 520 Oxide Semiconductor Layer 521 Oxygen deficiency-inducing factors 545a Second source electrode layer 545b Second drain electrode layer 555a First source electrode layer 555b First drain electrode layer 600 circuit boards 601 Grid Unit Layer 602 Gate Insulation Layer 604 Gate Insulation Layer 607 Insulating layer 609 Insulating layer 611a Region without oxygen deficiency-inducing factors 611b Region without oxygen deficiency-inducing factors 613 Channel formation region 614a Source area 614b Drain area 615a Region containing low-concentration oxygen deficiency-inducing factors 615b Region containing low-concentration oxygen deficiency-inducing factors 620 oxide semiconductor layer 625a First source electrode layer 625b First drain electrode layer 630 Oxygen deficiency-inducing factors 631a Region containing oxygen deficiency-inducing factors 631b Region containing oxygen deficiency-inducing factors 632 Oxygen deficiency-inducing factors 633 Oxide semiconductor layer 635a Second source electrode layer 635b Second drain electrode layer 636 Oxygen deficiency-inducing factors 640 transistors 650 transistors 2700 eBooks 2701 enclosure 2703 Casing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Keys 2725 Speakers 2800 cabinets 2801 enclosure 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation Keys 2806 Pointing device 2807 Camera Lens 2808 External connection terminal 2810 solar cells 2811 External memory slot 3001 Main Unit 3002 enclosure 3003 Display section 3004 Keyboard 3021 Main Unit 3022 Stylus 3023 Display section 3024 Operation Buttons 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 First substrate 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 Second substrate 4018 FPC 4018a FPC 4018b FPC 9600 Television equipment 9601 enclosure 9603 Display section 9605 Stand

Claims

1. Oxide semiconductor layer, The gate insulating layer on the oxide semiconductor layer, The gate electrode layer on the gate insulating layer, The gate electrode layer has an insulating layer, The oxide semiconductor layer has regions containing elements selected from one or more of the following: titanium, tungsten, molybdenum, aluminum, cobalt, zinc, indium, silicon, boron, hydrogen, and nitrogen. The aforementioned region overlaps with the gate insulating layer in the semiconductor device.

2. Oxide semiconductor layer, The gate insulating layer on the oxide semiconductor layer, The gate electrode layer on the gate insulating layer, The gate electrode layer has an insulating layer, The oxide semiconductor layer has regions containing elements selected from one or more of the following: titanium, tungsten, molybdenum, aluminum, cobalt, zinc, indium, silicon, boron, hydrogen, and nitrogen. A semiconductor device wherein the aforementioned element is added to the region via the gate insulating layer.

3. Oxide semiconductor layer, The gate insulating layer on the oxide semiconductor layer, The gate electrode layer on the gate insulating layer, The gate electrode layer has an insulating layer, The oxide semiconductor layer has regions containing elements selected from one or more of the following: titanium, tungsten, molybdenum, aluminum, cobalt, zinc, indium, silicon, boron, hydrogen, and nitrogen. The region is the gate insulating layer and overlaps with the insulating layer, in a semiconductor device.

4. Oxide semiconductor layer, The gate insulating layer on the oxide semiconductor layer, The gate electrode layer on the gate insulating layer, The gate electrode layer has an insulating layer, The oxide semiconductor layer has regions containing elements selected from one or more of the following: titanium, tungsten, molybdenum, aluminum, cobalt, zinc, indium, silicon, boron, hydrogen, and nitrogen. A semiconductor device wherein the aforementioned element is added to the region via the gate insulating layer.

5. In any one of claims 1 to 4, Having a conductive film on the insulating layer, A semiconductor device in which the conductive film is connected to the oxide semiconductor layer through an opening in the gate insulating layer and an opening in the insulating layer.

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