Semiconductor device and method for manufacturing a semiconductor device

Abstract

Reduces the step formation in the semiconductor layer. [Solution] The semiconductor device 10 comprises a semiconductor layer 12 having a first surface and a second surface 12B, a first insulating layer 30 formed on the second surface 12B of the semiconductor layer 12, a gate electrode 32 formed on the first insulating layer 30, a second insulating layer 34 formed on the gate electrode 32, a third insulating layer 42 covering the first insulating layer 30 and the second insulating layer 34, and a source electrode 44 formed on the third insulating layer 42, the source electrode 44 including a source contact portion 46 that penetrates the first insulating layer 30 and the third insulating layer 42 and contacts the semiconductor layer 12. The first insulating layer 30 includes a gate insulating portion 36 interposed between the gate electrode 32 and the semiconductor layer 12, and the gate insulating portion 36 includes a curved side surface 36A located between the gate electrode 32 and the semiconductor layer 12. The minimum distance between the curved side surface 36A and the semiconductor layer 12 is smaller than the minimum distance between the gate electrode 32 and the semiconductor layer 12.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a MISFET (Metal-Insulator-Semiconductor Field-Effect-Transistor) having a superjunction structure. The MISFET is n + A drain layer of type n - A type drift layer, a p-type channel region, a p-type pillar layer, and n + Type source area and p + It includes a p-type channel contact region, a gate electrode, a gate insulating film, and an interlayer insulating film. The p-type pillar layer extends from the p-type channel region to n + It extends toward the drain layer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-161712

[0004] [overview] In the etching process of the gate insulating film formed on the semiconductor layer of a MISFET having a superjunction structure, steps may be formed on the surface of the semiconductor layer. Such steps cause localized stress concentration, which can result in defects in the semiconductor layer. Defects in the semiconductor layer can affect the drain-source leakage current of the MISFET. DSS This could be a cause of an increase.

[0005] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes forming a semiconductor layer of a first conductivity type having a first surface and a second surface opposite to the first surface; forming a pillar region of a second conductivity type within the semiconductor layer; forming an insulating layer covering the second surface of the semiconductor layer; forming a metal layer on the insulating layer; selectively removing the metal layer to form a gate electrode including a first opening penetrating the metal layer; etching the insulating layer through the first opening; and forming a thermal oxide film on the gate electrode, the insulating layer, and the semiconductor layer. Etching the insulating layer includes forming a second opening having a curved sidewall in the insulating layer by isotropic etching to partially expose the semiconductor layer, wherein the exposed surface of the semiconductor layer forms a flat surface continuous with the second surface of the semiconductor layer covered by the insulating layer. Forming the thermal oxide film includes forming a gate insulating portion interposed between the gate electrode and the semiconductor layer, wherein the gate insulating portion includes a curved side surface formed by the growth of the thermal oxide film on the curved sidewall. The minimum distance between the curved side surface and the semiconductor layer is smaller than the minimum distance between the gate electrode and the semiconductor layer.

[0006] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a first insulating layer formed on the second surface of the semiconductor layer, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a third insulating layer covering the first insulating layer and the second insulating layer, and a source electrode formed on the third insulating layer. The source electrode includes a source contact portion that penetrates the first insulating layer and the third insulating layer and is in contact with the semiconductor layer. The first insulating layer includes a gate insulating portion interposed between the gate electrode and the semiconductor layer, and the gate insulating portion includes a curved side surface located between the gate electrode and the semiconductor layer. The minimum distance between the curved side surface and the semiconductor layer is smaller than the minimum distance between the gate electrode and the semiconductor layer. [Brief explanation of the drawing]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view of an exemplary semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a partially enlarged view of FIG. 1. [Figure 3] FIG. 3 is a schematic cross-sectional view showing an exemplary manufacturing process of the semiconductor device shown in FIG. 2. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a manufacturing process following FIG. 3. [Figure 5] FIG. 5 is a schematic cross-sectional view showing a manufacturing process following FIG. 4. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a manufacturing process following FIG. 5. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing process following FIG. 6. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] FIG. 11 is a schematic cross-sectional view showing an exemplary etching process of a semiconductor device according to a comparative example. [Figure 12] FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a comparative example. [Figure 13] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a modified example.

[0008] [Detailed Description] Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn to a fixed scale. Also, for ease of understanding, the hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0009] The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is merely for purposes of explanation and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0010] [Semiconductor Device Having a Super Junction Structure] FIG. 1 is a schematic cross-sectional view of a semiconductor device 10 having a super junction structure according to an embodiment of the present invention. FIG. 2 is a partially enlarged view of FIG. 1, in which a portion F2 surrounded by a dashed-dotted line in FIG. 1 is enlarged.

[0011] As shown in FIG. 1, the semiconductor device 10 includes a semiconductor layer 12 having a first surface 12A and a second surface 12B opposite to the first surface 12A. Note that the Z-axis shown in FIG. 1 extends in the Z direction orthogonal to the first surface 12A and the second surface 12B. The term "planar view" used in the present disclosure means viewing the semiconductor device 10 in the Z direction. Unless otherwise explicitly stated, "planar view" refers to viewing the semiconductor device 10 from above along the Z-axis. The semiconductor layer 12 may include a semiconductor substrate 14 and an epitaxial layer 16 formed on the semiconductor substrate 14. The semiconductor substrate 14 includes the first surface 12A of the semiconductor layer 12, and the epitaxial layer 16 may include the second surface 12B of the semiconductor layer 12.

[0012] The semiconductor substrate 14 may be an n-type semiconductor substrate containing n-type impurities. In one example, the semiconductor substrate 14 can be a silicon (Si) substrate. In another example, the semiconductor substrate 14 may be a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or any semiconductor substrate applicable to a MISFET. The n-type impurity concentration of the semiconductor substrate 14 can be, for example, 1.0×10 + cm 18 cm -3 ~5.0×10 20 cm -3 and can be set.

[0013] The epitaxial layer 16 is an n-type impurity containing n-type impurities that has been epitaxially grown on the semiconductor substrate 14. - It may be a type of layer. For example, the epitaxial layer 16 can be a Si epitaxial layer. For example, the impurity concentration of the epitaxial layer 16 is 1.0 × 10⁻⁶. 10 cm -3 ~1.0×10 16 cm -3 That's fine.

[0014] The semiconductor layer 12 may include a drain region 18, a drift region 20, a channel region 22, a pillar region 24, a source region 26, and a channel contact region 28. The drain region 18 may correspond to the semiconductor substrate 14. The drift region 20, channel region 22, pillar region 24, source region 26, and channel contact region 28 can be formed within the epitaxial layer 16.

[0015] The channel region 22 can be formed from the second surface 12B of the semiconductor layer 12 to a predetermined depth. The channel region 22 may be a region in the epitaxial layer 16 in which p-type impurities are implanted. The impurity concentration of the channel region 22 is, in one example, 1.0 × 10⁻⁶. 15 cm -3 ~1.0×10 19 cm -3 It can be done this way.

[0016] The pillar region 24 may be formed continuously with the channel region 22. The pillar region 24 may extend from the channel region 22 toward the drain region 18 (semiconductor substrate 14) within the epitaxial layer 16. Since the pillar region 24 does not reach the drain region 18, a drift region 20 may extend between the pillar region 24 and the drain region 18. The pillar region 24 may or may not have a constant width. In one example, the width of the pillar region 24 may change periodically along the Z direction as shown in Figure 1. The pillar region 24 may be a region within the epitaxial layer 16 in which p-type impurities are implanted. In one example, the impurity concentration of the pillar region 24 is 1.0 × 10⁻⁶. 15 cm -3 ~1.0×10 19 cm -3 This can be done. The impurity concentration in the pillar region 24 may be equivalent to the impurity concentration in the channel region 22.

[0017] The source region 26 can be formed within the channel region 22 from the second surface 12B of the semiconductor layer 12 to a predetermined depth. The source region 26 is formed shallower than the channel region 22. The source region 26 may be a region within the channel region 22 in which n-type impurities are implanted. The impurity concentration of the source region 26 is, in one example, 1.0 × 10⁻⁶. 18 cm -3 ~5.0×10 20 cm -3 This can be done. The impurity concentration in the source region 26 may be higher than that in the drift region 20.

[0018] The channel contact region 28 can be formed below the source contact portion 46 of the source electrode 44, which will be described later. The channel contact region 28 can be adjacent to the channel region 22 and the source region 26. The channel contact region 28 may be a region within the channel region 22 and the source region 26 in which p-type impurities have been implanted. The impurity concentration of the channel contact region 28 is, in one example, 5.0 × 10⁻⁶. 17 cm -3 ~1.0×10 19cm -3 This can be done. The impurity concentration in the channel contact region 28 may be higher than that in the channel region 22.

[0019] In this disclosure, n-type is also referred to as the first conductivity type, and p-type as the second conductivity type. Accordingly, the semiconductor layer 12 may include a drain region 18 of the first conductivity type including a first surface 12A, a drift region 20 of the first conductivity type formed on the drain region 18, a channel region 22 of the second conductivity type formed on the second surface 12B, and a pillar region 24 of the second conductivity type connected to the channel region 22 and extending toward the drain region 18.

[0020] n-type impurities may be at least one of phosphorus (P), arsenic (As), and antimony (Sb), for example. p-type impurities may be at least one of boron (B) and aluminum (Al), for example.

[0021] As shown in Figure 2, the semiconductor device 10 may further include a first insulating layer 30 formed on the second surface 12B of the semiconductor layer 12, a gate electrode 32 formed on the first insulating layer 30, and a second insulating layer 34 formed on the gate electrode 32.

[0022] The first insulating layer 30 includes a gate insulating portion 36 interposed between the gate electrode 32 and the semiconductor layer 12. In other words, the gate insulating portion 36 may be the portion of the first insulating layer 30 on which the gate electrode 32 is formed. Therefore, the bottom surface 32A of the gate electrode 32 can be in contact with the gate insulating portion 36. On the other hand, the top surface 32B and side surface 32C of the gate electrode 32 can be in contact with the second insulating layer 34.

[0023] The gate insulating portion 36 may cover a part of the surface of the source region 26, the surface of the channel region 22, and the surface of the drift region 20 of the semiconductor layer 12. The gate insulating portion 36 may include a curved side surface 36A located between the gate electrode 32 and the semiconductor layer 12. The curved side surface 36A is formed by isotropic etching in an etching process for forming the gate insulating portion 36, which will be described later with reference to Figure 6. In this embodiment, the first insulating layer 30 and the second insulating layer 34 can form a cavity 38. The cavity 38 is at least partially surrounded by the curved side surface 36A. At least a portion of the cavity 38 may be located between the gate electrode 32 and the semiconductor layer 12.

[0024] The second surface 12B of the semiconductor layer 12 may include a step 40 located below the curved side surface 36A of the gate insulating portion 36. The step 40 may be less than 25 nm in the direction perpendicular to the second surface 12B. At least a portion of the cavity 38 may be located between the gate electrode 32 and the step 40.

[0025] The semiconductor device 10 may further include a third insulating layer 42 covering the first insulating layer 30 and the second insulating layer 34, and a source electrode 44 formed on the third insulating layer 42. The source electrode 44 may include a source contact portion 46 that penetrates the first insulating layer 30 and the third insulating layer 42 and contacts the semiconductor layer 12. The source contact portion 46 can penetrate the source region 26 and contact the channel contact region 28. In one example, the source electrode 44 may be formed of AlSiCu.

[0026] The first insulating layer 30 and the second insulating layer 34 may be formed by a thermal oxide film, and the third insulating layer 42 may be formed by a CVD film. Here, the thermal oxide film may be a silicon dioxide (SiO2) film formed by thermal oxidation. The CVD film may be an SiO2 film formed by chemical vapor deposition (CVD). More specifically, the CVD film may include a USG (Undoped Silicate Glass) film, a BPSG (Boron-Doped Phospho-Silicate Glass) film, or both. Since the cavity 38 is formed by the first insulating layer 30 and the second insulating layer 34, it can be surrounded by the thermal oxide film. The gate electrode 32 may, in one example, be formed by conductive polysilicon.

[0027] Returning to Figure 1, the semiconductor device 10 may further include a drain electrode 48 formed on the first surface 12A of the semiconductor layer 12. The drain electrode 48 may be electrically connected to the drain region 18. The drain electrode 48 can be formed from at least one of Ti, Ni, Au, Ag, Cu, Al, Cu alloy, and Al alloy.

[0028] Thus, the semiconductor device 10 can include a drain electrode 48 formed on the first surface 12A of the semiconductor layer 12 and a source electrode 44 formed above the second surface 12B. Therefore, the semiconductor device 10 can be a vertical device in which the main current flows in a direction intersecting the first surface 12A and the second surface 12B of the semiconductor layer 12. In the upper portion including the second surface 12B of the semiconductor layer 12, n-type drift regions 20 and p-type pillar regions 24 are arranged alternately, as shown in Figure 1. In a semiconductor device 10 having such a superjunction structure, a depletion layer spreads from the pn junction surface between the n-type drift region 20 and the p-type pillar region 24, and a depletion layer of about the same depth as the pillar region 24 can be formed in the drift region 20. This can improve the breakdown voltage of the semiconductor device 10.

[0029] [Manufacturing method for semiconductor devices] Next, an example of a method for manufacturing a semiconductor device 10 having a superjunction structure according to this embodiment will be described.

[0030] Figures 3 to 11 are schematic cross-sectional views illustrating an exemplary manufacturing process of the semiconductor device 10. Note that Figures 3 to 11 show some of the same parts as those shown in Figure 2 of the semiconductor device 10. For ease of understanding, components similar to those in Figure 2 are denoted by the same reference numerals in Figures 3 to 11.

[0031] As shown in Figure 3, the method for manufacturing the semiconductor device 10 may include forming an n-type semiconductor layer 12 having a first surface 12A (see Figure 1) and a second surface 12B opposite to the first surface 12A, and forming a p-type pillar region 24 within the semiconductor layer 12. The pillar region 24 can be formed by implanting p-type impurities into the semiconductor layer 12 (epitaxial layer 16). More specifically, the pillar region 24 extending in the Z direction within the semiconductor layer 12 may be formed by repeatedly forming an n-type epitaxial layer in which p-type impurities are selectively implanted. In another example, the pillar region 24 may be formed by forming a trench in the epitaxial layer 16 and growing a p-type epitaxial layer within the trench.

[0032] Figure 4 is a schematic cross-sectional view showing the manufacturing process following Figure 3. As shown in Figure 4, the manufacturing method may include forming an insulating layer 50 covering the second surface 12B of the semiconductor layer 12, and forming a metal layer 52 on the insulating layer 50. In one example, the insulating layer 50 may be SiO2 formed by a thermal oxidation method. The metal layer 52 may be conductive polysilicon.

[0033] Figure 5 is a schematic cross-sectional view showing the manufacturing process following Figure 4. As shown in Figure 5, the manufacturing method may include selectively removing the metal layer 52 to form a gate electrode 32 including a first opening 54 penetrating the metal layer 52, and implanting p-type impurities into the semiconductor layer 12 through the first opening 54. The p-type impurities can be implanted into a first region 56 including the second surface 12B of the semiconductor layer 12. The first region 56 is located relatively close to the second surface 12B of the semiconductor layer 12 and is not continuous with the pillar region 24 in this process.

[0034] Figure 6 is a schematic cross-sectional view showing the manufacturing process following Figure 5. As shown in Figure 6, the manufacturing method may include etching the insulating layer 50 through the first opening 54. Etching the insulating layer 50 includes forming a second opening 60 having a curved side wall 58 in the insulating layer 50 by isotropic etching, thereby partially exposing the semiconductor layer 12. The insulating layer 50 that is not etched in this process can constitute the gate insulating portion 36 shown in Figure 2.

[0035] In isotropic etching, etching of the insulating layer 50 proceeds not only in a direction perpendicular to the surface of the insulating layer 50 (a direction perpendicular to the second surface 12B of the semiconductor layer 12), but also in a lateral direction (a direction parallel to the second surface 12B). As a result, a portion of the bottom surface 32A of the gate electrode 32 (the portion continuous with the first opening 54) is exposed, and an undercut is formed in the insulating layer 50. Therefore, the second opening 60 may be at least partially larger than the first opening 54. Because the side wall 58 is curved, the second opening 60 can have smaller dimensions the closer it is to the second surface 12B of the semiconductor layer 12 than to the gate electrode 32. The curved side wall 58 of the second opening 60 may be located between the gate electrode 32 and the semiconductor layer 12. By growing a thermal oxide film 64, which will be described later with reference to Figures 7 and 8, on the curved side wall 58 formed by isotropic etching, the curved side surface 36A of the gate insulating portion 36 shown in Figure 2 can be formed.

[0036] Since isotropic etching is employed in this process, the exposed surface 62 of the semiconductor layer 12 does not need to be etched much. Therefore, the exposed surface 62 of the semiconductor layer 12 can form a flat surface that is continuous with the second surface 12B of the semiconductor layer 12 covered by the insulating layer 50. In other words, isotropic etching does not form any steps on the second surface 12B of the semiconductor layer 12 that could cause defects in the semiconductor layer 12.

[0037] In one example, isotropic etching can be performed by wet etching. In another example, isotropic etching may be performed, for example, by dry etching using a reactive gas (chemical dry etching).

[0038] Figure 7 is a schematic cross-sectional view showing the manufacturing process following Figure 6. As shown in Figure 7, the manufacturing method may further include forming a thermal oxide film 64 on the gate electrode 32, the insulating layer 50, and the semiconductor layer 12. In this step, p-type impurities contained in the first region 56 (see Figure 6) are diffused into the semiconductor layer 12 by annealing to form a channel region 22. As a result, the channel region 22 may be formed continuously with the pillar region 24. The thermal oxide film 64 can be formed by a reaction between the exposed surfaces of the gate electrode 32, the insulating layer 50, and the semiconductor layer 12 and oxygen. As a result, the top surface 32B, the side surface 32C, and part of the bottom surface 32A of the gate electrode 32, the curved side wall 58 of the insulating layer 50, and the exposed surface 62 (see Figure 6) of the semiconductor layer 12 can be covered with the thermal oxide film 64. Due to this oxidation reaction, the semiconductor layer 12 and the gate electrode 32 may change from the shape shown in Figure 6. More specifically, a slight recess in the exposed surface 62 shown in Figure 6 may create a step 40 on the flat surface of the semiconductor layer 12 formed by the exposed surface 62 and the second surface 12B. The step 40 is formed near the curved side wall 58 and can therefore be located below the gate electrode 32. The step 40 located below the gate electrode 32 is relatively small, and in one example may be less than 25 nm in the direction perpendicular to the second surface 12B.

[0039] Figure 8 is a schematic cross-sectional view showing the manufacturing process following Figure 7. As shown in Figure 8, the manufacturing method may further include forming a source region 26. In this step, n-type impurities are injected into the semiconductor layer 12 through the first opening 54 and the second opening 60, and the injected n-type impurities are diffused into the semiconductor layer 12 by annealing to form the source region 26. This annealing process causes the thermal oxide film 64 formed in the process shown in Figure 7 to grow even thicker. In this embodiment, during the growth of this thermal oxide film 64, a cavity 38 surrounded by the thermal oxide film 64 is formed due to an undercut of the insulating layer 50. Thus, forming the thermal oxide film 64 may include forming the cavity 38 surrounded by the thermal oxide film 64.

[0040] At least a portion of the cavity 38 can be located between the gate electrode 32 and the semiconductor layer 12. This makes it possible to obtain a gate insulating portion 36 having the curved side surface 36A shown in Figure 2.

[0041] Figure 9 is a schematic cross-sectional view showing the manufacturing process following Figure 8. As shown in Figure 9, the manufacturing method may further include forming a CVD film 66 on the thermal oxide film 64. The CVD film 66 may be an SiO2 film formed by the CVD method. More specifically, the CVD film 66 may include a USG film, a BPSG film, or both.

[0042] Figure 10 is a schematic cross-sectional view showing the manufacturing process following Figure 9. As shown in Figure 10, the manufacturing method may include forming a channel contact region 28 and forming an opening 68 that penetrates the CVD film 66 and the thermal oxide film 64 and reaches the channel contact region 28. After this step, a source electrode 44 (see Figure 2) including a source contact portion 46 within the opening 68 is formed, and the semiconductor device 10 shown in Figure 2 can be obtained.

[0043] Although the manufacturing method for the semiconductor device 10 is described above as including multiple manufacturing steps performed sequentially, it should be understood that some manufacturing steps may be performed in parallel and / or in a different order. Furthermore, some manufacturing steps may be omitted, and different processes may be performed in any of the manufacturing steps compared to the example above.

[0044] [Effect] The operation of the semiconductor device 10 of this embodiment will be described below. In the semiconductor device 10 of this embodiment, etching of the insulating layer 50 covering the second surface 12B of the semiconductor layer 12 is performed in order to form the gate insulating portion 36. In etching the insulating layer 50, isotropic etching is used to form a second opening 60 having a curved side wall 58 in the insulating layer 50, partially exposing the semiconductor layer 12. At this time, the exposed surface 62 of the semiconductor layer 12 is hardly concave by isotropic etching, so a flat surface continuous with the second surface 12B of the semiconductor layer 12 covered by the insulating layer 50 can be formed.

[0045] Here, for comparison, we will refer to Figures 11 and 12 to describe an example where the etching of the insulating layer 50 is performed by anisotropic etching rather than isotropic etching. Figure 11 is a schematic cross-sectional view showing an exemplary etching process of semiconductor device 100 (see Figure 12) according to a comparative example. In Figure 11, components similar to those in semiconductor device 10 (see Figure 6 in particular) are denoted by the same reference numerals. Detailed explanations of components similar to those in semiconductor device 10 are omitted.

[0046] In the process shown in Figure 11, the insulating layer 50 is etched through the first opening 54, similar to the process shown in Figure 6. The process shown in Figure 11 differs from the process shown in Figure 6 in that a second opening 102 is formed in the insulating layer 50 by anisotropic etching.

[0047] In anisotropic etching, etching of the insulating layer 50 mainly proceeds in a direction perpendicular to the surface of the insulating layer 50 (a direction perpendicular to the second surface 12B of the semiconductor layer 12). In the example in Figure 11, anisotropic etching is performed by reactive ion etching. As shown in Figure 11, etching proceeds relatively slowly in the insulating layer 50 near the gate electrode 32, which acts as a shield against the reactive ions used in reactive ion etching. In particular, the insulating layer 50 below the bottom surface 32A of the gate electrode 32 is hardly etched, unlike in the case of Figure 6. The second opening 102 has smaller dimensions the closer it is to the second surface 12B of the semiconductor layer 12 than to the gate electrode 32. As a result, the side wall 104 of the second opening 102 is not located below the gate electrode 32, and therefore the second opening 102 is smaller than or equal to the first opening 54.

[0048] The semiconductor layer 12 exposed by the second opening 102 of the insulating layer 50 is etched from the surface by anisotropic etching, and the exposed surface 106 is recessed from the second surface 12B of the semiconductor layer 12 covered by the insulating layer 50. As a result, a step 108 is created between the second surface 12B and the exposed surface 106. In the example in Figure 11, a step 108 of approximately 45 nm is formed in the direction perpendicular to the second surface 12B.

[0049] Thus, the step 108 formed by anisotropic etching is relatively large. On the other hand, in the process shown in Figure 6, isotropic etching does not form any steps on the second surface 12B of the semiconductor layer 12 that could cause defects in the semiconductor layer 12. As a result, in the case of isotropic etching shown in Figure 6, the exposed surface 62 of the semiconductor layer 12 can form a flat surface that is continuous with the second surface 12B of the semiconductor layer 12 covered by the insulating layer 50.

[0050] Figure 12 is a schematic cross-sectional view of a semiconductor device 100 obtained after the etching process shown in Figure 11, followed by a process similar to the manufacturing process of the semiconductor device 10 shown in Figures 7-10. In Figure 12, the same reference numerals are used for components that are the same as those in the semiconductor device 10 (see Figure 2 in particular).

[0051] In the semiconductor device 100, the step 108 of the semiconductor layer 12 formed in the etching process shown in Figure 11 remains largely unchanged. However, when the second insulating layer 34 is formed by thermal oxidation, the step 108 may be even larger than after the process shown in Figure 11. In the semiconductor device 100, since the step 108 is not located below the gate electrode 32, a cavity like the cavity 38 shown in Figure 2 is not formed. Also, in the semiconductor device 100, since the step 108 is not located below the gate electrode 32, the gate insulating portion 110 does not have a side surface located between the gate electrode 32 and the semiconductor layer 12.

[0052] The relatively large step 108 in the semiconductor layer 12 causes stress concentration in its vicinity. This stress concentration leads to defects in the semiconductor layer 12, and as a result, the drain-source leakage current I in the semiconductor device 100 is higher compared to the semiconductor device 10. DSS It increases.

[0053] In contrast, in the manufacturing method of the semiconductor device 10 of this embodiment, a second opening 60 having a curved side wall 58 is formed in the insulating layer 50 by isotropic etching, partially exposing the semiconductor layer 12. As a result, the exposed surface 62 of the semiconductor layer 12 can form a flat surface continuous with the second surface 12B of the semiconductor layer 12 covered by the insulating layer 50. Due to the use of isotropic etching, the gate insulating portion 36 of the semiconductor device 10 comes to include a curved side surface 36A located between the gate electrode 32 and the semiconductor layer 12. Therefore, any step 40 that may be formed during the manufacturing process will be located below the gate electrode 32. This makes it possible to make the step 40 relatively small. Therefore, according to the semiconductor device 10 and the manufacturing method of the semiconductor device 10 of this embodiment, the step 40 formed in the semiconductor layer 12 can be reduced. Reducing the step 40 alleviates localized stress concentration in the semiconductor layer 12, and as a result, the occurrence of defects in the semiconductor layer 12 can be suppressed. Therefore, in the semiconductor device 10, the drain-source leakage current I DSS This can suppress the increase.

[0054] [effect] The semiconductor device 10 and the method for manufacturing the semiconductor device 10 according to this embodiment have the following advantages.

[0055] (1) Etching the insulating layer 50 may include forming a second opening 60 having a curved side wall 58 in the insulating layer 50 by isotropic etching, thereby partially exposing the semiconductor layer 12. The exposed surface 62 of the semiconductor layer 12 can form a flat surface that is continuous with the second surface 12B of the semiconductor layer 12 covered by the insulating layer 50.

[0056] This makes it possible to relatively reduce the step 40 that may be formed in the semiconductor layer 12 during the manufacturing process of the semiconductor device 10, thereby suppressing the occurrence of defects in the semiconductor layer 12. As a result, the drain-source leakage current I DSS This can suppress the increase.

[0057] (2) The curved side wall 58 may be located between the gate electrode 32 and the semiconductor layer 12. This allows the step 40 formed near the curved side wall 58 during the manufacturing process to be located below the gate electrode 32, making it possible to make the step 40 relatively small.

[0058] (3) The step 40 formed on the flat surface of the semiconductor layer 12 may be less than 25 nm in the direction perpendicular to the second surface 12B. This makes local stress concentration in the semiconductor layer 12 relatively small, thereby suppressing the occurrence of defects in the semiconductor layer 12 and reducing the drain-source leakage current I DSS This can suppress the increase.

[0059] (4) Forming the thermal oxide film 64 includes forming a cavity 38 surrounded by the thermal oxide film 64, at least a portion of which may be located between the gate electrode 32 and the semiconductor layer 12. The presence of the cavity 38 located between the gate electrode 32 and the semiconductor layer 12 relieves stress concentration in the semiconductor layer 12 in its vicinity, thereby suppressing the occurrence of defects in the semiconductor layer 12.

[0060] (5) Forming the thermal oxide film 64 includes forming a cavity 38 surrounded by the thermal oxide film 64, and at least a portion of the cavity 38 may be located between the gate electrode 32 and the step 40. The presence of the cavity 38 located between the gate electrode 32 and the step 40 alleviates stress concentration in the semiconductor layer 12 near the step 40 where stress tends to be high, thereby more effectively suppressing the occurrence of defects in the semiconductor layer 12.

[0061] (6) The first insulating layer 30 includes a gate insulating portion 36 interposed between the gate electrode 32 and the semiconductor layer 12, and the gate insulating portion 36 may include a curved side surface 36A located between the gate electrode 32 and the semiconductor layer 12.

[0062] This allows the step 40 formed near the curved side surface 36A during the manufacturing process to be located below the gate electrode 32, thus making the step 40 relatively small.

[0063] Furthermore, the curved side surface 36A located between the gate electrode 32 and the semiconductor layer 12 is a unique structure formed by isotropic etching, as described above. Therefore, it is recognized that the gate insulating portion 36 having the side surface 36A was subjected to isotropic etching during the manufacturing process. As described above, the step height 40 in the semiconductor device 10 is smaller than when anisotropic etching is performed. Therefore, in a semiconductor device 10 in which the gate insulating portion 36 has a side surface 36A, the step height 40 formed in the semiconductor layer 12 can be reduced. Reducing the step height 40 alleviates localized stress concentration in the semiconductor layer 12, and as a result, the occurrence of defects in the semiconductor layer 12 can be suppressed. Therefore, in the semiconductor device 10, the drain-source leakage current I DSS This can suppress the increase.

[0064] (7) The first insulating layer 30 and the second insulating layer 34 form a cavity 38 that is at least partially surrounded by the curved side surface 36A, and at least a portion of the cavity 38 can be located between the gate electrode 32 and the semiconductor layer 12. The presence of the cavity 38 located between the gate electrode 32 and the semiconductor layer 12 relieves stress concentration in the semiconductor layer 12 in its vicinity, thereby suppressing the occurrence of defects in the semiconductor layer 12.

[0065] (8) The first insulating layer 30 and the second insulating layer 34 form a cavity 38 that is at least partially surrounded by the curved side surface 36A, and at least a portion of the cavity 38 can be located between the gate electrode 32 and the step 40. The presence of the cavity 38 located between the gate electrode 32 and the step 40 alleviates stress concentration in the semiconductor layer 12 near the step 40 where stress tends to be high, thereby more effectively suppressing the occurrence of defects in the semiconductor layer 12.

[0066] [Example of changes] The above-described embodiment can be further modified and implemented as follows. The first insulating layer 30 and the second insulating layer 34 do not necessarily have to form a cavity 38 as shown in Figure 2. Figure 13 is a schematic cross-sectional view of a modified semiconductor device 200. In Figure 13, the same reference numerals are used for components that are the same as those in the semiconductor device 10 (see Figure 2 in particular). Detailed explanations of components that are the same as those in the semiconductor device 10 are omitted.

[0067] In the semiconductor device 200 shown in Figure 13, the first insulating layer 30 and the second insulating layer 34 do not form a closed cavity, so the third insulating layer 42 is embedded in the gap 202 defined by the first insulating layer 30 and the second insulating layer 34. At least a portion of the gap 202 can be located between the gate electrode 32 and the semiconductor layer 12. In this case, the curved side surface 36A of the gate insulating portion 36 can be in contact with the third insulating layer 42.

[0068] In the modified semiconductor device 200, due to the adoption of isotropic etching, the gate insulating portion 36 of the semiconductor device 10 includes a curved side surface 36A located between the gate electrode 32 and the semiconductor layer 12. Therefore, any step 40 that may be formed during the manufacturing process will be located below the gate electrode 32. This makes it possible to make the step 40 relatively small, and as a result, the drain-source leakage current I DSS This can suppress the increase.

[0069] In the above embodiment, a structure in which the conductivity types of each region within the semiconductor layer 12 are reversed may be adopted. That is, a p-type region may become an n-type region, and an n-type region may become a p-type region.

[0070] One or more of the various examples described herein can be combined to the extent that they do not conflict with the technical specifications. In this specification, “at least one of A and B” should be understood to mean “A only, or B only, or both A and B.”

[0071] As used herein, the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, the expression “the first layer is formed on the second layer” is intended to mean that in one embodiment the first layer may be in contact with and directly positioned on the second layer, while in other embodiments the first layer may be positioned above the second layer without contact. In other words, the term “on” does not preclude structures in which another layer is formed between the first and second layers.

[0072] The terms used herein to indicate direction, such as “vertical,” “horizontal,” “upward,” “downward,” “up,” “down,” “forward,” “backward,” “lateral,” “left,” “right,” “front,” and “rear,” depend on the specific orientation of the apparatus described and illustrated. Various alternative orientations can be assumed in this disclosure, and therefore these terms indicating direction should not be interpreted narrowly.

[0073] For example, the Z direction as used herein does not necessarily have to be vertical, nor does it have to perfectly coincide with the vertical. Therefore, the various structures described herein (e.g., the structure shown in Figure 1) are not limited to the "up" and "down" in the Z direction described herein being the "up" and "down" in the vertical direction. For example, the X direction may be vertical, or the Y direction may be vertical.

[0074] [Note] The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0075] (Note A1) A method for manufacturing a semiconductor device (10) having a superjunction structure, To form a semiconductor layer (12) of a first conductivity type having a first surface (12A) and a second surface (12B) opposite to the first surface (12A), To form a second conductivity type pillar region (24) within the semiconductor layer (12), To form an insulating layer (50) that covers the second surface (12B) of the semiconductor layer (12), Forming a metal layer (52) on the insulating layer (50), Selectively remove the metal layer (52) to form a gate electrode (32) including a first opening (54) penetrating the metal layer (52), Etching the insulating layer (50) through the first opening (54) Includes, Etching the insulating layer (50) involves isotropic etching to form a second opening (60) having a curved side wall (58) in the insulating layer (50), thereby partially exposing the semiconductor layer (12), and the exposed surface (62) of the semiconductor layer (12) forms a flat surface continuous with the second surface (12B) of the semiconductor layer (12) covered by the insulating layer (50). A method for manufacturing a semiconductor device (10).

[0076] (Appendix A2) The method for manufacturing a semiconductor device (10) as described in Appendix A1, wherein the curved side wall (58) is located between the gate electrode (32) and the semiconductor layer (12).

[0077] (Note A3) A method for manufacturing a semiconductor device (10) as described in Appendix A1 or A2, wherein the second aperture (60) has a smaller dimension the closer it is to the second surface (12B) of the semiconductor layer (12) than the gate electrode (32).

[0078] (Note A4) Forming a thermal oxide film (64) on the gate electrode (32), the insulating layer (50), and the semiconductor layer (12). A method for manufacturing a semiconductor device (10) as described in any one of the appendices A1 to A3, further including the above.

[0079] (Note A5) The method for manufacturing a semiconductor device (10) as described in Appendix A4, wherein forming the thermal oxide film (64) includes forming a step (40) on the flat surface (62, 12B), the step (40) being located below the gate electrode (32).

[0080] (Note A6) The method for manufacturing a semiconductor device (10) as described in Appendix A5, wherein the step (40) is less than 25 nm in the direction perpendicular to the second surface (12B).

[0081] (Note A7) A method for manufacturing a semiconductor device (10) according to any one of the appendices A4 to A6, wherein forming the thermal oxide film (64) includes forming a cavity (38) surrounded by the thermal oxide film (64), and at least a portion of the cavity (38) is located between the gate electrode (32) and the semiconductor layer (12).

[0082] (Note A8) A method for manufacturing a semiconductor device (10) according to Appendix A5 or A6, wherein forming the thermal oxide film (64) includes forming a cavity (38) surrounded by the thermal oxide film (64), and at least a portion of the cavity (38) is located between the gate electrode (32) and the step (40).

[0083] (Note A9) A method for manufacturing a semiconductor device (10) according to any one of the appendices A4 to A8, further comprising forming a CVD film (66) on the thermal oxide film (64).

[0084] (Note A10) Injecting impurities into the semiconductor layer (12) through the first opening (54) A method for manufacturing a semiconductor device (10) according to any one of the appendices A4 to A9, further comprising the impurity (12) being diffused into the semiconductor layer (12) when forming the thermal oxide film (64).

[0085] (Note B1) A semiconductor device (10) having a superjunction structure, A semiconductor layer (12) having a first surface (12A) and a second surface (12B) opposite to the first surface (12A), A first insulating layer (30) formed on the second surface (12B) of the semiconductor layer (12), A gate electrode (32) formed on the first insulating layer (30), A second insulating layer (34) formed on the gate electrode (32), A third insulating layer (42) covering the first insulating layer (30) and the second insulating layer (34), A source electrode (44) formed on the third insulating layer (42), the source electrode (44) including a source contact portion (46) that penetrates the first insulating layer (30) and the third insulating layer (42) and contacts the semiconductor layer (12), and Equipped with, The first insulating layer (30) includes a gate insulating portion (36) interposed between the gate electrode (32) and the semiconductor layer (12), and the gate insulating portion (36) includes a curved side surface (36A) located between the gate electrode (32) and the semiconductor layer (12). Semiconductor device (10).

[0086] (Note B2) The first insulating layer (30) and the second insulating layer (34) are formed by a thermal oxide film. The third insulating layer (42) is formed by a CVD film. Semiconductor device (10) as described in Appendix B1.

[0087] (Note B3) The semiconductor device (10) according to Appendix B1 or B2, wherein the second surface (12B) of the semiconductor layer (12) includes a step (40) located below the gate electrode (32).

[0088] (Note B4) The semiconductor device (10) described in Appendix B3, wherein the step (40) is less than 25 nm in the direction perpendicular to the second surface (12B).

[0089] (Note B5) The semiconductor device (10) according to any one of appendices B1 to B4, wherein the first insulating layer (30) and the second insulating layer (34) form a cavity (38) at least partially surrounded by the curved side surface (36A), and at least a portion of the cavity (38) is located between the gate electrode (32) and the semiconductor layer (12).

[0090] (Note B6) The semiconductor device (10) according to Appendix B3 or B4, wherein the first insulating layer (30) and the second insulating layer (34) form a cavity (38) at least partially surrounded by the curved side surface (36A), and at least a portion of the cavity (38) is located between the gate electrode (32) and the step (40).

[0091] (Note B7) The curved side surface (36A) is in contact with the third insulating layer (42). A semiconductor device (200) as described in any one of the appendices B1 to B4.

[0092] (Note B8) The curved side surface (36A) is formed by isotropic etching, as described in any one of the appendices B1 to B7 (10;200).

[0093] (Note B9) The semiconductor layer (12) is A drain region (18) of the first conductivity type including the first surface (12A), A first-conductivity type drift region (20) formed on the drain region (18), A second conductivity type channel region (22) formed on the second surface (12B), A second conductive pillar region (24) is connected to the channel region (22) and extends toward the drain region (18). Semiconductor devices (10;200) including any one of the appendices B1 to B8.

[0094] (Note C1) A semiconductor device (10) having a superjunction structure, A semiconductor layer (12) having a first surface (12A) and a second surface (12B) opposite to the first surface (12A), A first insulating layer (30) formed on the second surface (12B) of the semiconductor layer (12), A gate electrode (32) formed on the first insulating layer (30), A second insulating layer (34) formed on the gate electrode (32), A third insulating layer (42) covering the first insulating layer (30) and the second insulating layer (34), A source electrode (44) formed on the third insulating layer (42), the source electrode (44) including a source contact portion (46) that penetrates the first insulating layer (30) and the third insulating layer (42) and contacts the semiconductor layer (12), and Equipped with, The second surface (12B) of the semiconductor layer (12) includes a step (40) located below the gate electrode (32). Semiconductor device (10).

[0095] (Note C2) The semiconductor device (10) described in Appendix C1, wherein the step (40) is less than 25 nm in the direction perpendicular to the second surface (12B).

[0096] (Note C3) The first insulating layer (30) includes a gate insulating portion (36) interposed between the gate electrode (32) and the semiconductor layer (12), and the gate insulating portion (36) includes a curved side surface (36A) located between the gate electrode (32) and the semiconductor layer (12). Semiconductor device (10) as described in Appendix C1 or C2.

[0097] (Note C4) The semiconductor device (10) according to Appendix C3, wherein the first insulating layer (30) and the second insulating layer (34) form a cavity (38) at least partially surrounded by the curved side surface (36A), and at least a portion of the cavity (38) is located between the gate electrode (32) and the step (40).

[0098] (Note C5) The curved side surface (36A) is in contact with the third insulating layer (42). Semiconductor device (200) as described in Appendix C3 or C4.

[0099] (Appendix C6) The first insulating layer (30) and the second insulating layer (34) are formed by a thermal oxide film. The third insulating layer (42) is formed by a CVD film. A semiconductor device (10;200) as described in any one of the appendices C1 to C5.

[0100] (Note C7) The semiconductor layer (12) is A drain region (18) of the first conductivity type including the first surface (12A), A first-conductivity type drift region (20) formed on the drain region (18), A second conductivity type channel region (22) formed on the second surface (12B), A second conductive pillar region (24) is connected to the channel region (22) and extends toward the drain region (18). A semiconductor device (10;200) including any one of the appendices C1 to C6.

[0101] The above description is illustrative only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims. [Explanation of symbols]

[0102] 10, 100, 200… Semiconductor device, 12… Semiconductor layer, 12A… First surface, 12B… Second surface, 14… Semiconductor substrate, 16… Epitaxial layer, 18… Drain region, 20… Drift region, 22… Channel region, 24… Pillar region, 26… Source region, 28… Channel contact region, 30… First insulating layer, 32… Gate electrode, 34… Second insulating layer, 36… Gate insulating portion, 3 6A...side, 38...cavity, 40...step, 42...third insulating layer, 44...source electrode, 46...source contact area, 48...drain electrode, 50...insulating layer, 52...metal layer, 54...first opening, 56...first region, 58...side wall, 60...second opening, 62...exposed surface, 64...thermal oxide film, 66...CVD film, 68...opening, 102...second opening, 104...side wall, 106...exposed surface, 108...step.

Claims

1. A method for manufacturing a semiconductor device having a superjunction structure, To form a semiconductor layer of a first conductivity type having a first surface and a second surface opposite to the first surface, To form a pillar region of the second conductivity type within the semiconductor layer, To form an insulating layer covering the second surface of the semiconductor layer, Forming a metal layer on the insulating layer, Selectively remove the metal layer to form a gate electrode including a first opening that penetrates the metal layer. Etching the insulating layer through the first opening, Forming a thermal oxide film on the gate electrode, the insulating layer, and the semiconductor layer. Includes, Etching the insulating layer involves isotropic etching to form a second opening having a curved sidewall in the insulating layer, thereby partially exposing the semiconductor layer, wherein the exposed surface of the semiconductor layer forms a flat surface continuous with the second surface of the semiconductor layer covered by the insulating layer. Forming the thermal oxide film includes forming a gate insulating portion interposed between the gate electrode and the semiconductor layer, wherein the gate insulating portion includes a curved side surface formed by the growth of the thermal oxide film on the curved side wall. The minimum distance between the curved side surface and the semiconductor layer is smaller than the minimum distance between the gate electrode and the semiconductor layer. A method for manufacturing a semiconductor device.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the curved side wall is located between the gate electrode and the semiconductor layer.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the second opening has a smaller dimension than the gate electrode as it approaches the second surface of the semiconductor layer.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein forming the thermal oxide film includes forming a step on the flat surface, the step being located below the gate electrode.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the step is less than 25 nm in a direction perpendicular to the second surface.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein forming the thermal oxide film includes forming a cavity surrounded by the thermal oxide film, and at least a portion of the cavity is located between the gate electrode and the semiconductor layer.

7. The method for manufacturing a semiconductor device according to claim 4 or 5, wherein forming the thermal oxide film includes forming a cavity surrounded by the thermal oxide film, and at least a portion of the cavity is located between the gate electrode and the step.

8. Impurities of the first conductivity type are injected into the semiconductor layer through the first and second openings to form a source region of the first conductivity type. The method for manufacturing a semiconductor device according to claim 6 or 7, further comprising the above, wherein the cavity is formed to overlap the source region in a plan view.

9. A semiconductor device having a superjunction structure, A semiconductor layer having a first surface and a second surface opposite to the first surface, A first insulating layer formed on the second surface of the semiconductor layer, A gate electrode formed on the first insulating layer, A second insulating layer formed on the gate electrode, A third insulating layer covering the first insulating layer and the second insulating layer, A source electrode formed on the third insulating layer, the source electrode including a source contact portion that penetrates the first insulating layer and the third insulating layer and contacts the semiconductor layer. Equipped with, The first insulating layer includes a gate insulating portion interposed between the gate electrode and the semiconductor layer, and the gate insulating portion includes a curved side surface located between the gate electrode and the semiconductor layer. The minimum distance between the curved side surface and the semiconductor layer is smaller than the minimum distance between the gate electrode and the semiconductor layer. Semiconductor equipment.

10. The first insulating layer and the second insulating layer are formed by a thermal oxide film. The third insulating layer is formed by a CVD film. The semiconductor device according to claim 9.

11. The semiconductor device according to claim 9 or 10, wherein the second surface of the semiconductor layer includes a step located below the gate electrode.

12. The semiconductor device according to claim 11, wherein the step is less than 25 nm in a direction perpendicular to the second surface.

13. The semiconductor device according to any one of claims 9 to 12, wherein the first insulating layer and the second insulating layer form a cavity at least partially surrounded by the curved side surface, and at least a portion of the cavity is located between the gate electrode and the semiconductor layer.

14. The semiconductor device according to claim 11 or 12, wherein the first insulating layer and the second insulating layer form a cavity at least partially surrounded by the curved side surface, and at least a portion of the cavity is located between the gate electrode and the step.

15. The aforementioned semiconductor layer is A drain region of the first conductivity type including the first surface, A first conductivity type drift region formed on the drain region, A second conductivity type channel region formed on the second surface, A second conductivity type pillar region connected to the channel region and extending toward the drain region and A semiconductor device according to any one of claims 9 to 14, including the semiconductor device described in any one of claims 9 to 14.

16. The aforementioned semiconductor layer is A first conductivity type source region that includes a portion of the second surface and is electrically connected to the source electrode. The semiconductor device according to claim 13 or 14, comprising, wherein the cavity overlaps with the source region in a plan view.

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