Semiconductor equipment

Abstract

To provide a semiconductor device that can improve recovery failure tolerance. [Solution] A depletion region 16 of a first conductivity type is formed in the upper surface portion of the body layer 13, in the portion located below the gate wiring 21, where the applied voltage between the lower electrode 28 and the upper electrode 26 is 0V. The depletion region 16 is formed below at least a portion of the end of the gate wiring 21, and the upper surface of the body layer 13 is exposed from the depletion region at least a portion of the portion inside the end of the gate wiring 21.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] A semiconductor device including a MOSFET element or the like has a configuration in which, for example, a body layer is laminated on the upper surface of a drift layer, a drain electrode is formed on the lower surface side of the drift layer, and gate wiring and a source electrode are formed on the upper surface side of the body layer. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0003] In such a semiconductor device, a displacement current flows through the PN junction capacitance between the drift layer and the body layer during the recovery operation. At this time, the potential of the body layer rises due to the path resistance of the body layer, and a potential difference occurs between the gate wiring and the body layer. When this potential difference becomes large, a high electric field is applied to the gate insulating film formed between the body layer and the gate wiring, and breakdown is likely to occur.

[0004] The semiconductor device described in Patent Document 1 includes a MOSFET element having a configuration in which a p-type body layer is laminated on the upper surface of an n-type drift layer, and a p + , + -type region is formed on the upper surface side surface layer portion of the body layer so as to contact the gate insulating film.

[0005] p [[ID=​​​​​​​​​​​​​​​

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the semiconductor device described in Patent Document 1, in the lower part of the p-type region and the n-type region, the p-type region is thinner than other parts, so the path resistance of the displacement current in the p-type region becomes larger than other parts. Therefore, when the p-type region and the n-type region are formed in the entire surface layer portion of the body layer under the gate wiring, the portion with a large path resistance becomes wider, so the temperature locally rises during the recovery operation, and there is a risk of device breakdown.

[0008] In view of the above points, an object of the present disclosure is to provide a semiconductor device capable of improving the recovery breakdown tolerance.

Means for Solving the Problems

[0009] ​​​​​​​​To achieve the above objective, according to one aspect of this disclosure, the semiconductor device comprises a drift layer (11) of a first conductivity type, a body layer (13) of a second conductivity type laminated on the upper surface of the drift layer, a bottom electrode (28) formed on the lower side of the drift layer, a gate wiring (21) formed on the upper side of the body layer and connected to a gate electrode (20), a gate insulating film (19) formed between the upper surface of the body layer and the gate wiring, and a top electrode (26) formed on the upper side of the body layer, wherein a depletion region (16) of a first conductivity type is formed in the upper surface portion of the body layer located below the gate wiring, and the depletion region is formed below at least a portion of the end of the gate wiring, and the upper surface of the body layer is exposed from the depletion region below at least a portion of the portion inside the end of the gate wiring.

[0010] The depletion region is less affected by the potential rise caused by displacement current flowing through the body layer. Therefore, forming a depletion region below the gate wiring reduces the electric field applied to the gate insulating film. Near the ends of the gate wiring, a higher electric field is more likely to be applied to the gate insulating film compared to the area inside the ends, making it more susceptible to failure. Therefore, forming a depletion region below at least a portion of the ends of the gate wiring can suppress the failure of the gate insulating film. Furthermore, by configuring the upper surface of the body layer to be exposed from the depletion region below at least a portion of the area inside the ends of the gate wiring, the increase in path resistance in the lower part of the inner portion can be suppressed, thereby suppressing element failure due to temperature rise. These measures can improve the recovery failure withstand capability.

[0011] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0012] [Figure 1] This is a cross-sectional view of a semiconductor device according to the first embodiment. [Figure 2] This is an enlarged view of the vicinity of the depletion region in Figure 1. [Figure 3] This is a top view of the body layer. [Figure 4A] This is a cross-sectional view showing the manufacturing process of semiconductor devices. [Figure 4B] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 4A. [Figure 4C] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 4B. [Figure 4D] Figure 4C is a cross-sectional view showing the manufacturing process of a semiconductor device. [Figure 5] This is a cross-sectional view of the comparative example. [Figure 6] This is a cross-sectional view showing the path resistance in the first embodiment. [Figure 7] This is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 8] This is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 9] This is a top view of the body layer in the fourth embodiment. [Figure 10] This is a top view of the body layer in the fourth embodiment. [Figure 11] This is a top view of the body layer in another embodiment. [Figure 12] This is a top view of the body layer in another embodiment. [Modes for carrying out the invention]

[0013] The embodiments of this disclosure will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0014] (First Embodiment) A first embodiment will be described. The semiconductor device 1 of this embodiment, shown in Figure 1, includes a MOSFET element. Of the semiconductor device 1, the region that operates as a MOSFET element is designated as the active region 2, and the other regions are designated as the inactive region 3. In this embodiment, the case in which the MOSFET element of the semiconductor device 1 is an n-channel element with n-type as the first conductivity type and p-type as the second conductivity type will be described.

[0015] The semiconductor device 1 includes a substrate 10. The substrate 10 is made of n-type SiC (silicon carbide). An n-type drift layer 11 is formed on the upper surface of the substrate 10.

[0016] The direction parallel to the upper surface of the body layer 13, as described later, is defined as the x-direction. The direction perpendicular to the upper surface of the body layer 13, i.e., the thickness direction of the body layer 13, is defined as the y-direction. The direction parallel to the upper surface of the body layer 13 and perpendicular to the x-direction is defined as the z-direction.

[0017] The drift layer 11 is configured to function as an electric field relaxation layer. Specifically, multiple linear p-type column regions 12 extending in the z direction are formed on the upper surface of the drift layer 11, and the surface of the drift layer 11 has an SJ (Super Junction) structure in which n-type regions and p-type column regions 12 are arranged alternately in the x direction.

[0018] A body layer 13 doped with p-type impurities is laminated on the upper surface of the drift layer 11. The upper surface of the body layer 13 has an n-type region 14, p + A type region 15 and a depletion region 16 are formed.

[0019] n-type region 14 is formed in active region 2, and depletion region 16 is formed in inactive region 3. + A portion of the type region 15 is formed in the active region 2, and the other portion is formed in the inactive region 3. + Of the type region 15, the portion formed in the active region 2 is p + The type region 15a is defined as the part formed in the inactive region 3, and the part formed in the inactive region 3 is p+ Let this be type region 15b.

[0020] In the active region 2, a trench 17 is formed that penetrates the body layer 13 and the n-type region 14 and leads into the interior of the drift layer 11. The n-type region 14 is located on both sides of the trench 17 in the x-direction.

[0021] p + The p-type region 15 is a region with a higher p-type impurity concentration than the p-type column region 12 and the body layer 13. + The n-type region 15a is formed so as to be in contact with the n-type region 14 from the opposite side of the trench 17. That is, p + The type region 15a consists of a portion that is in contact with the n-type region 14 located on one side in the x-direction relative to the trench 17 from one side in the x-direction, and a portion that is in contact with the n-type region 14 located on the other side in the x-direction relative to the trench 17 from the other side in the x-direction.

[0022] p + The type region 15b is a contact portion that connects the body layer 13 to the source electrode 26, which will be described later, and is located between the active region 2 and the depletion region 16. The depletion region 16 is located below the end of the first gate wiring 21, which will be described later. The depletion region 16 is defined as a region with a lower n-type impurity concentration than the substrate 10, the drift layer 11, and the n-type region 14. The depletion region 16 is formed to become depleted when the applied voltage between the drain electrode 28 and the source electrode 26, which will be described later, is 0V.

[0023] A field insulating film 18 made of SiO2 (silicon oxide) is laminated on the upper surface of the body layer 13 included in the inactive region 3. The upper surface of the depletion region 16 is covered by the field insulating film 18. A gate insulating film 19 made of SiO2 is laminated on the upper surface of the field insulating film 18 and on the upper surface of the body layer 13 exposed from the field insulating film 18. The gate insulating film 19 is also formed inside the trench 17, and the walls and bottom of the trench 17 are covered by the gate insulating film 19.

[0024] A gate electrode 20 is formed inside the trench 17 by filling it with Poly-Si (polycrystalline silicon). The gate electrode 20 is insulated from the drift layer 11, body layer 13, and n-type region 14 by a gate insulating film 19. A first gate wiring 21 made of Poly-Si is formed on the upper surface of the gate insulating film 19. The first gate wiring 21 is a lead wire for connecting the gate electrode 20 to a second gate wiring 27, which will be described later, and is connected to the gate electrode 20 in a part not shown. An interlayer insulating film 22 made of SiO2 is formed on the upper surfaces of the gate insulating film 19, the gate electrode 20, and the first gate wiring 21.

[0025] In the active region 2, the gate insulating film 19 and the interlayer insulating film 22 are penetrated, and the n-type region 14 and p + A trench 23 is formed that exposes the upper surface of the portion in contact with the mold region 15a.

[0026] In the inactive region 3, p penetrates the field insulating film 18, the gate insulating film 19, and the interlayer insulating film 22. + A trench 24 is formed that exposes the upper surface of the mold region 15b. In the inactive region 3, a trench 25 is formed that penetrates the interlayer insulating film 22 and exposes the upper surface of the first gate wiring 21.

[0027] An Al-Si (aluminum silicon) layer is formed on the upper surface of the interlayer insulating film 22, and this Al-Si layer constitutes the source electrode 26 and the second gate wiring 27. The source electrode 26 corresponds to the upper surface electrode. A recess is formed between the source electrode 26 and the second gate wiring 27, exposing the upper surface of the interlayer insulating film 22, and the source electrode 26 and the second gate wiring 27 are electrically insulated. In addition to the upper surface of the interlayer insulating film 22, the source electrode 26 is also formed inside the trenches 23 and 24, in n-type regions 14, p + It is connected to type regions 15a and 15b.

[0028] The second gate wiring 27 is formed not only on the upper surface of the interlayer insulating film 22 but also inside the trench 25 and is connected to the first gate wiring 21. The gate electrode 20 is connected to a pad (not shown) via the first gate wiring 21 and the second gate wiring 27. A drain electrode 28 made of Al-Si is laminated on the lower surface of the substrate 10. The drain electrode 28 corresponds to the bottom electrode.

[0029] Details of the arrangement of the depletion region 16 will now be described. The depletion region 16 is formed at least on the lower part of the end of the first gate wiring 21. Furthermore, the depletion region 16 is not formed at least on the lower part of the portion inside the end of the first gate wiring 21, and the upper surface of the body layer 13 is exposed from the depletion region 16 at least on the lower part of the portion inside the end of the first gate wiring 21.

[0030] In this embodiment, the depletion region 16 is formed at the positions shown in Figures 2 and 3. Region Re1 in Figure 3 shows the portion of the body layer 13 facing the first gate wiring 21. Note that in Figure 2, only a portion of the first gate wiring 21 is shown, while in Figure 3, the portion of the body layer 13 facing the portion of the first gate wiring 21 shown in Figure 2 is shown as region Re1.

[0031] Specifically, the first gate wiring 21 includes a rectangular portion with the z-direction as the longitudinal direction and the x-direction as the short direction, and a portion that connects this rectangular portion to the gate electrode 20. In Figure 2, only this rectangular portion of the first gate wiring 21 is shown, while in Figure 3, the portion opposite this rectangular portion is shown as region Re1.

[0032] In the x-direction, of the ends of the first gate wiring 21, p is relative to the center of the first gate wiring 21. + The end opposite to the mold region 15b is designated as the first end 21a, and the center of the first gate wiring 21 is p +The end portion on the same side as the type region 15b is defined as the second end portion 21b. As shown in FIG. 3, the depletion region 16 is a linear region extending in the z direction along the first end portion 21a and the second end portion 21b.

[0033] The dimensions of the depletion region 16 will be described. As shown in FIG. 2, in the x direction, the depletion region 16 protrudes outside the first gate wiring 21 from the end portion of the first gate wiring 21. Let the width in the x direction of this protruding portion be X1. Also, a part of the depletion region 16 overlaps the first gate wiring 21 in the x direction. Let the width in the x direction of this overlapping portion be X2. Let the width in the x direction of the first gate wiring 21 be X3.

[0034] As will be described later, the depletion region 16 suppresses the breakdown of the field insulating film 18 and the gate insulating film 19. In order to obtain this effect, it is desirable that 0 < X1 < 5 μm and 0 < X < X3. Note that the conditions for these X1 and X2 are not essential. For example, X1 = 0 may be possible, or X1 ≥ 5 μm may be possible, or X2 = 0 may be possible. Also, the dimensions of the depletion region 16 under the first end portion 21a and the depletion region 16 under the second end portion 21b may be different.

[0035] Also, let the width in the y direction of the depletion region 16 be Y1, and let the width in the y direction of the body layer 13 be Y2, and 0 < Y1 < Y2 is defined.

[0036] The manufacturing method of the semiconductor device 1 will be described using FIGS. 4A to 4D. Note that in FIGS. 4A to 4D, the illustration of the active region 2 and the substrate 10 is omitted. In the process shown in FIG. 4A, an n-type substrate 10 made of SiC is prepared, and an epitaxial drift layer 11 made of SiC is grown on the upper surface of the substrate 10. Then, a p-type column region 12 is formed by ion implantation into the drift layer 11. Further, a body layer 13 is formed by ion implantation.

[0037] In the process shown in FIG. 4B, an n-type region 14, p +It forms an n-type region 15 and a depletion region 16. + The formation of the type region 15 and the depletion region 16 can be carried out in any order. When forming the depletion region 16, the donor density N, which will be described later, D The film deposition conditions and ion implantation conditions are set so that equation 4 is satisfied. As a result, the depletion region 16 is depleted when the applied voltage between the drain electrode 28 and the source electrode 26 is 0V. n-type region 14, p + After forming the mold region 15 and the depletion region 16, a trench 17 is formed by etching.

[0038] In the process shown in Figure 4C, in the inactive region 3, the body layer 13, p + A field insulating film 18 is formed on the upper surfaces of the type region 15b and the depletion region 16 by thermal oxidation. Then, the upper surface of the body layer 13 exposed from the field insulating film 18 and the upper surface of the n-type region 14 and p + A gate insulating film 19 is formed by thermal oxidation on the upper surface of the mold region 15a, the walls and bottom surface of the trench 17, and the upper surface of the field insulating film 18. Subsequently, a gate electrode 20 is formed inside the trench 17 by CVD (Chemical Vapor Deposition), and a first gate wiring 21 is formed on the upper surface of the gate insulating film 19.

[0039] In the process shown in Figure 4D, an interlayer insulating film 22 is formed on the upper surfaces of the gate insulating film 19, gate electrode 20, and first gate wiring 21 by thermal oxidation. Then, trenches 23, 24, and 25 are formed by etching. After the process shown in Figure 4D, a source electrode 26 and a second gate wiring 27 are formed on the upper side of the substrate 10 by sputtering, and a drain electrode 28 is formed on the lower side of the substrate 10, thereby forming the semiconductor device 1 shown in Figure 1.

[0040] The conditions under which the depletion region 16 becomes depleted are explained. In the process shown in Figure 4B, depletion progresses from the body layer 13 toward the center of the portion that becomes the depletion region 16. The width of the depleted region in the direction toward the center of the depletion region 16 from the body layer 13 is W. depl、nLet's assume. When forming a horizontally long depletion region 16, that is, when X1 + X2 > Y1, then W depl、n ≧Y1, the entire depletion region 16 will be depleted. Also, when forming a vertically long depletion region 16, that is, when X1 + X2 < Y1, then W depl、n ≧(X1 + X2) / 2, the entire depletion region 16 will be depleted.

[0041] The width W depl、n is expressed by Equation 1. ε SiC is the dielectric constant of SiC, ψ bi is the built-in potential of the depletion region 16, q is the elementary charge, N A is the acceptor density of the body layer 13, and N D is the donor density of the depletion region 16.

[0042]

Equation

[0043]

Equation

[0044] <​​​​​​​​​​​​​​​​​​​​The operation of semiconductor device 1 will now be described. In semiconductor device 1, when a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 20, an inversion layer is formed in the body layer 13 near the trench 17, and a drain-source current flows according to the voltage between the drain electrode 28 and the source electrode 26. When the gate voltage is less than the threshold voltage, no inversion layer is formed, and no drain-source current flows.

[0046] During the recovery operation when semiconductor device 1 is turned off, a displacement current flows to the body layer 13 through the PN junction capacitance between the drift layer 11 and the body layer 13. The displacement current flows between the body layer 13 and p + The wire is drawn through the mold region 15b to the source electrode 26. At this time, the potential of the body layer 13 rises due to the path resistance of the body layer 13, and a potential difference is created between the first gate wiring 21 and the body layer 13.

[0047] Specifically, if ΔV is the potential difference between the first gate wiring 21 and the body layer 13, I is the current flowing through the body layer 13, and Rs is the path resistance of the body layer 13, then ΔV = I·Rs. If Id is the displacement current and Irr is the recovery current, then I = Id + Irr. When Irr = 0, then I = Id. If C is the capacitance of the PN junction between the drift layer 11 and the body layer 13, and dV / dt is the time derivative of the voltage between the drain electrode 28 and the source electrode 26, then Id = C·(dV / dt).

[0048] When the potential difference ΔV becomes large, a high electric field is applied to the field insulating film 18 and the gate insulating film 19, making them prone to breakdown. To suppress this, for example, as shown in Figure 5, at the lower part of the first gate wiring 21, n is applied to the surface layer of the body layer 13. + A type region 30 is formed, n + p + It is conceivable that type region 31 will be formed. + Type region 31 is n + The body layer 13 is separated by the type region 30. With this configuration, p +By suppressing the intrusion of displacement current into the mold region 31, it is possible to suppress the application of a high electric field to the field insulating film 18 and the gate insulating film 19.

[0049] However, n + Type region 30 and p + In the lower part of the mold region 31, the body layer 13 becomes thinner compared to other parts, and in the current path indicated by arrow A1, the resistance R1 of the body layer 13 below the gate wiring 21 is greater than the resistance R2 of the body layer 13 in other parts. Therefore, as shown in Figure 5, the entire region below the first gate wiring 21 in the surface layer of the body layer 13 is n + Type region 30 and p + When the mold region 31 is formed, the area with high path resistance becomes larger, which may cause the element to break down due to heat generation.

[0050] In this embodiment, a depletion region 16 is formed at the lower end of the first gate wiring 21. Since the depletion region 16 is depleted when the applied voltage between the drain electrode 28 and the source electrode 26 is 0V, it is less affected by the potential rise of the body layer 13, and the electric field applied to the field insulating film 18 and the gate insulating film 19 is reduced near the depletion region 16.

[0051] Near the end of the first gate wiring 21, a higher electric field is more likely to be applied to the field insulating film 18 and the gate insulating film 19 compared to the area inside the end of the first gate wiring 21, making them more susceptible to damage. Therefore, by forming a depletion region 16 below the end of the first gate wiring 21, damage to the field insulating film 18 and the gate insulating film 19 can be efficiently suppressed.

[0052] Furthermore, in the lower part of the portion inside the end of the first gate wiring 21, the depletion region 16 is not formed, and the upper surface of the body layer 13 is exposed from the depletion region 16 and in contact with the field insulating film 18. In other words, the body layer 13 in the portion inside the end of region Re1 has the same thickness as the body layer 13 in the portion away from region Re1 and the depletion region 16 in the x direction.

[0053] As shown in Figure 6, the resistance R3 of the body layer 13 in the lower part of the depletion region 16 is greater than the resistance R4 of the body layer 13 in the region located outside the first gate wiring 21 in the x-direction. However, in this embodiment, the depletion region 16 is formed in the lower part of the end of the first gate wiring 21, and a portion of the lower part of the portion inside the end of the first gate wiring 21 is provided in which the depletion region 16 is not formed. As a result, in this portion, the resistance R5 of the body layer 13 becomes as low as the resistance R4. Therefore, the increase in path resistance can be suppressed, and element failure due to temperature rise can be suppressed.

[0054] As described above, in this embodiment, a depletion region 16 is formed below the first gate wiring 21, which becomes depleted when the applied voltage between the drain electrode 28 and the source electrode 26 is 0V. The depletion region 16 is formed below at least a portion of the end of the first gate wiring 21, and the upper surface of the body layer 13 is exposed from the depletion region 16 at least a portion of the portion inside the end of the first gate wiring 21. This suppresses the destruction of the field insulating film 18 and the gate insulating film 19 due to the application of an electric field, suppresses element destruction due to temperature rise, and improves the recovery breakdown withstand capability of the semiconductor device 1.

[0055] Furthermore, in the configuration shown in Figure 5, p + The side and bottom surfaces of the mold region 31 are n + Because it needs to be covered by the mold region 30, the dimensional constraints in the x, y, and z directions become strict, which may reduce the freedom of layout. In contrast, in this embodiment, the depletion region 16 is n - Since it is a type domain, n + Type region 30 and p + Compared to using a laminated structure of mold region 31, there are fewer dimensional constraints and greater freedom in layout.

[0056] (Second Embodiment) A second embodiment will now be described. This embodiment is similar to the first embodiment in that the arrangement of the depletion region 16 is changed, and other aspects are the same as the first embodiment. Therefore, only the parts that differ from the first embodiment will be described.

[0057] As shown in Figure 7, the depletion region 16 in this embodiment is not formed below the second end portion 21b, but only below the first end portion 21a. In the body layer 13, the p in contact with the source electrode 26 + Because the potential tends to rise in the region far from type region 15b, p + In the lower part of the first end 21a, which is far from the mold region 15b, a particularly high electric field is likely to be applied to the field insulating film 18 and the gate insulating film 19. In contrast, by forming a depletion region 16 only in the lower part of the first end 21a, it is possible to efficiently suppress the breakdown of the field insulating film 18 and the gate insulating film 19 while reducing the path resistance in the lower part of the second end 21b, thereby further suppressing device breakdown due to temperature rise.

[0058] This embodiment, with the same configuration and operation as the first embodiment, can obtain the same effects as the first embodiment.

[0059] Furthermore, according to the above embodiment, the following effects can be obtained.

[0060] (1) The depletion region 16 is formed only in the lower part of the first end 21a of the first end 21a and the second end 21b. This makes it possible to suppress the breakdown of the field insulating film 18 and the gate insulating film 19 while reducing the path resistance in the lower part of the second end 21b, thereby further suppressing device breakdown due to temperature rise.

[0061] (Third embodiment) A third embodiment will now be described. This embodiment is similar to the first embodiment in that the arrangement of the depletion region 16 is changed, and everything else is the same as the first embodiment. Therefore, only the parts that differ from the first embodiment will be described.

[0062] As shown in Figure 8, the depletion region 16 in this embodiment is not formed below the first end 21a, but only below the second end 21b. Depending on the layout of the parts of the semiconductor device 1, the displacement current may concentrate, causing p to contact the source electrode 26. + The field insulating film 18 and gate insulating film 19 are more susceptible to damage in the lower part of the second end 21b, which is close to the mold region 15b. In such cases, by forming a depletion region 16 only in the lower part of the second end 21b, it is possible to suppress the damage of the field insulating film 18 and gate insulating film 19 while reducing the path resistance in the lower part of the first end 21a, thereby further suppressing device failure due to temperature rise.

[0063] This embodiment, with the same configuration and operation as the first embodiment, can obtain the same effects as the first embodiment.

[0064] Furthermore, according to the above embodiment, the following effects can be obtained.

[0065] (1) The depletion region 16 is formed only in the lower part of the second end 21b of the first end 21a and the second end 21b. This makes it possible to suppress the breakdown of the field insulating film 18 and the gate insulating film 19 while reducing the path resistance in the lower part of the first end 21a, thereby further suppressing device breakdown due to temperature rise.

[0066] (Fourth embodiment) A fourth embodiment will now be described. This embodiment is similar to the first embodiment in that the shape of the depletion region 16 is changed, and other aspects are the same as the first embodiment. Therefore, only the parts that differ from the first embodiment will be described.

[0067] In this embodiment, the depletion region 16 formed along the first end 21a and the second end 21b is divided into multiple parts. Specifically, as shown in Figure 9, the depletion region 16 is formed with a separation between the portion formed at the corner of region Re1 and the linear portion extending in the z direction along the end of region Re1.

[0068] In the current path indicated by arrow A2, the body layer 13 is thicker and the path resistance of the body layer 13 is smaller compared to the path passing through the lower part of the depletion region 16, thus further suppressing element failure due to temperature rise.

[0069] In Figure 9, the depletion region 16 is divided between a portion formed at the corner of region Re1 and a straight portion, but the straight portion may be divided into multiple parts. For example, as shown in Figure 10, the straight portion of the depletion region 16 may be divided into two in the center. In the configuration shown in Figure 10, the current path indicated by arrow A3 has a smaller path resistance in the body layer 13 compared to the path passing through the lower part of the depletion region 16, thus further suppressing element failure due to temperature rise.

[0070] Furthermore, at the lower part of the corner of the first gate wiring 21, the field insulating film 18 and gate insulating film 19 are more likely to be destroyed due to a potential increase in the body layer 13 compared to other parts. Therefore, a depletion region 16 may be formed only at the corner of region Re1, and in the straight portion at the end of region Re1, the upper surface of the body layer 13 may be exposed from the depletion region 16 and in contact with the field insulating film 18. This further suppresses element destruction due to temperature rise.

[0071] When designing the semiconductor device 1, the position and width of the depletion region 16 should be adjusted by considering the magnitude of the electric field applied to the field insulating film 18 and the gate insulating film 19, and the amount of temperature rise in the body layer 13.

[0072] This embodiment, with the same configuration and operation as the first embodiment, can obtain the same effects as the first embodiment.

[0073] Furthermore, according to the above embodiment, the following effects can be obtained.

[0074] (1) The depletion region 16 is formed along the end of the first gate wiring 21 and is divided into multiple sections. This further suppresses element failure due to temperature rise.

[0075] (Other embodiments) Furthermore, this disclosure is not limited to the embodiments described above and can be modified as appropriate. Also, the embodiments described above are not unrelated to each other and can be combined as appropriate, except in cases where combination is clearly impossible. Furthermore, it goes without saying that the elements constituting the embodiments are not necessarily essential, except when explicitly stated to be particularly essential or when they are clearly considered essential in principle. Also, when numerical values ​​such as the number, numerical values, quantities, or ranges of the components of an embodiment are mentioned, the embodiments are not limited to those specific numbers, except when explicitly stated to be particularly essential or when they are clearly limited to a specific number in principle. Furthermore, when the shapes, positional relationships, etc., of the components are mentioned in the embodiments, the embodiments are not limited to those shapes, positional relationships, etc., except when explicitly stated or when they are clearly limited to a specific shape, positional relationship, etc.

[0076] For example, as shown in Figure 11, the fourth embodiment may be combined with the second embodiment. In the configuration shown in Figure 11, the path resistance of the body layer 13 is reduced in the current path indicated by arrow A4, and the temperature rise can be further suppressed compared to the second embodiment. Also, as shown in Figure 12, the fourth embodiment may be combined with the third embodiment. In the configuration shown in Figure 12, the path resistance of the body layer 13 is reduced in the current path indicated by arrow A5, and the temperature rise can be further suppressed compared to the third embodiment.

[0077] Furthermore, a depletion region 16 may be formed in the lower part of a portion of the portion inside the end of the first gate wiring 21. Alternatively, a depletion region 16 may be formed in the lower part of the entire end of the first gate wiring 21. For example, in addition to the lower parts of the first end 21a and the second end 21b, a depletion region 16 may be formed in a rectangular frame shape along the lower parts of both ends of the first gate wiring 21 in the z direction. Also, the entire depletion region 16 does not have to be depleted. For example, there may be an undepleted area in the center of the depletion region 16.

[0078] Furthermore, although the above embodiments described the case in which the semiconductor device 1 has a MOSFET element, the semiconductor device 1 may also have a JFET (Junction Field Effect Transistor) element or an IGBT (Insulated Gate Bipolar Transistor) element. Also, an SJ structure may not be formed in the drift layer 11.

[0079] Furthermore, in the above embodiments, n-type was used as the first conductivity type and p-type as the second conductivity type. However, the present disclosure may also be applied to a p-channel element in which p-type is the first conductivity type and n-type is the second conductivity type.

[0080] (Perspective of this disclosure) [First point of view] A semiconductor device, A first conductive drift layer (11), A second conductive body layer (13) is laminated on the upper surface of the drift layer, The lower electrode (28) formed on the lower side of the drift layer, A gate wiring (21) formed on the upper surface side of the body layer and connected to the gate electrode (20), A gate insulating film (19) formed between the upper surface of the body layer and the gate wiring, The body layer comprises an upper electrode (26) formed on the upper surface side, Of the upper surface portion of the body layer, the portion located below the gate wiring has a depletion region (16) of the first conductivity type that is depleted when the applied voltage between the lower electrode and the upper electrode is 0V. The depletion region is formed at the lower part of at least a portion of the end of the gate wiring, The semiconductor device wherein the body layer has an upper surface that is exposed from the depletion region at least below a portion of the part of the body layer that is inside the end of the gate wiring. [Second perspective] In a direction parallel to the upper surface of the body layer, Of the depletion regions, with the width of the portion protruding outside the gate wiring from the end of the gate wiring being X1, The semiconductor device according to the first aspect, where 0 < X1 < 5 μm. [Third aspect] In the direction parallel to the upper surface of the body layer, Of the depletion regions, with the width of the portion overlapping the gate wiring being X2, With the width of the gate wiring being X3, The semiconductor device according to the first or second aspect, where 0 < X2 < X3. [Fourth aspect] With the thickness of the depletion region being Y1, With the thickness of the body layer being Y2, The semiconductor device according to any one of the first to third aspects, where 0 < Y1 < Y2. [Fifth aspect] With the acceptor density of the body layer being N A And, With the donor density of the depletion region being N D And, With the dielectric constant of SiC being ε SiC And, With the built-in potential of the depletion region being ψ bi And, With the elementary charge being q, In the direction from the body layer toward the center of the depletion region, with the width of the depleted region being W depl、n And, With the width W required for the entire depletion region to be depleted being W depl、n And, depl、n1 And, The semiconductor device according to any one of the first to fourth aspects, satisfying Equation 4. [Sixth aspect] The upper electrode is in contact with a contact portion (15b) formed in the surface layer portion of the body layer inside a trench (24) penetrating the gate insulating film, In the direction parallel to the upper surface of the body layer, Of the two ends of the gate wiring, the end on the side of the gate wiring opposite to the contact portion relative to the center of the gate wiring is designated as the first end (21a), and the end on the same side of the gate wiring relative to the center of the gate wiring as the contact portion is designated as the second end (21b). The semiconductor device according to any one of the first to fifth views, wherein the depletion region is formed only on the lower part of the first end of the first end and the second end. [Seventh perspective] The upper electrode is in contact with a contact portion (15b) formed on the surface of the body layer inside a trench (24) that penetrates the gate insulating film. In a direction parallel to the upper surface of the body layer, Of the two ends of the gate wiring, the end on the side of the gate wiring opposite to the contact portion relative to the center of the gate wiring is designated as the first end (21a), and the end on the same side of the gate wiring relative to the center of the gate wiring as the contact portion is designated as the second end (21b). The semiconductor device according to any one of the first to fifth views, wherein the depletion region is formed only on the lower part of the second end of the first end and the second end. [Perspective 8] The semiconductor device according to any one of the first to seventh views, wherein the depletion region is formed along the end of the gate wiring and is divided into a plurality of parts. [Perspective 9] The first conductivity type is n-type, The semiconductor device according to any one of the first to eighth views, wherein the second conductivity type is p-type. [Perspective 10] The first conductivity type is p-type, The semiconductor device according to any one of the first to eighth views, wherein the second conductivity type is n-type. [Explanation of Symbols]

[0081] 11 Drift Layer 13 Body Layers 16 Depletion region 19 Gate insulating film 20 gates 21. First Gate Wiring 26 Source electrodes 28 Drain electrode

Claims

1. A semiconductor device, A first conductive drift layer (11), A second conductive body layer (13) is laminated on the upper surface of the drift layer, The lower electrode (28) formed on the lower side of the drift layer, A gate wiring (21) is formed on the upper surface side of the body layer and connected to the gate electrode (20), A gate insulating film (19) formed between the upper surface of the body layer and the gate wiring, The body layer comprises an upper electrode (26) formed on the upper surface side, In the upper surface portion of the body layer, the portion located below the gate wiring is formed in a depletion region (16) of the first conductivity type that becomes depleted when the applied voltage between the lower electrode and the upper electrode is 0V. The depletion region is formed at the lower part of at least a portion of the end of the gate wiring, The semiconductor device wherein the body layer has an upper surface that is exposed from the depletion region at least below a portion of the part of the body layer that is inside the end of the gate wiring.

2. In a direction parallel to the upper surface of the body layer, Let X1 be the width of the portion of the depletion region that protrudes from the end of the gate wiring to the outside of the gate wiring. The semiconductor device according to claim 1, wherein 0 < X1 < 5 μm.

3. In a direction parallel to the upper surface of the body layer, Let X2 be the width of the portion of the depletion region that overlaps with the gate wiring. Let X3 be the width of the gate wiring. The semiconductor device according to claim 1, wherein 0 < X2 < X3.

4. Let Y1 be the thickness of the depletion region. Let Y2 be the thickness of the body layer. The semiconductor device according to claim 1, wherein 0 < Y1 < Y2.

5. The acceptor density of the body layer is N Ａ year, The donor density in the depletion region is N Ｄ year, The dielectric constant of SiC is ε ＳｉＣ year, The built-in potential of the depletion region is ψ ｂｉ year, Let the elementary charge be q. The width of the depleted region in the direction from the body layer toward the center of the depleted region is W. ｄｅｐｌ、ｎ year, The width W required for the entire depletion region to become depleted ｄｅｐｌ、ｎ W ｄｅｐｌ、ｎ１ as, A semiconductor device according to claim 1 that satisfies formula 4. [Math 4]

6. The upper electrode is in contact with a contact portion (15b) formed on the surface of the body layer inside a trench (24) that penetrates the gate insulating film. In a direction parallel to the upper surface of the body layer, Of the two ends of the gate wiring, the end on the side of the gate wiring opposite to the contact portion relative to the center of the gate wiring is designated as the first end (21a), and the end on the same side of the gate wiring as the contact portion relative to the center of the gate wiring is designated as the second end (21b). The semiconductor device according to claim 1, wherein the depletion region is formed only in the lower part of the first end of the first end and the second end.

7. The upper electrode is in contact with a contact portion (15b) formed on the surface of the body layer inside a trench (24) that penetrates the gate insulating film. In a direction parallel to the upper surface of the body layer, Of the two ends of the gate wiring, the end on the side of the gate wiring opposite to the contact portion relative to the center of the gate wiring is designated as the first end (21a), and the end on the same side of the gate wiring as the contact portion relative to the center of the gate wiring is designated as the second end (21b). The semiconductor device according to claim 1, wherein the depletion region is formed only in the lower part of the second end of the first end and the second end.

8. The semiconductor device according to claim 1, wherein the depletion region is formed along the end of the gate wiring and is divided into a plurality of parts.

9. The first conductivity type is n-type, The semiconductor device according to claim 1, wherein the second conductivity type is p-type.

10. The first conductivity type is p-type, The semiconductor device according to claim 1, wherein the second conductivity type is n-type.

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