Bonded wafer and method for manufacturing the same

Abstract

This invention provides a high-quality bonded wafer in which an extremely low-resistance n-type silicon wafer is bonded to a high-resistance, low-oxygen n-type silicon layer that functions as a device layer. [Solution] The bonded wafers 100, 200, and 300 of the present invention have a silicon wafer 10 on which the dopant is phosphorus and has a resistivity of 0.5 mΩ·cm to 1.2 mΩ·cm, and a silicon amorphous layer 50 on which the dopant is phosphorus and has a resistivity of 0.01 Ω·cm to 10 Ω·cm and 5 × 10 17 atoms / cm 3 The silicon amorphous layer 50 is void-free and consists of silicon layers 22, 32, and 46 having the following oxygen concentrations bonded together.

Description

[Technical Field]

[0001] The present invention relates to a bonded wafer comprising an extremely low-resistance n-type silicon wafer and a high-resistance, low-oxygen n-type silicon layer that functions as a device layer, and a method for manufacturing the same. [Background technology]

[0002] For example, epitaxial silicon wafers for power MOS transistors require extremely low resistivity of the silicon wafer on which the silicon epitaxial layer is formed. Therefore, epitaxial silicon wafers are provided in which a high-resistivity, low-oxygen n-type silicon epitaxial layer is formed on the surface of an n-type silicon wafer that has been highly doped with phosphorus (P) to achieve a resistivity of 1.2 mΩ·cm or less.

[0003] In recent years, there has been a demand for n-type silicon wafers with extremely low resistivity, specifically 0.9 mΩ·cm or less. However, when silicon wafers have extremely low resistivity, epitaxial growth can lead to stacking faults (SF) in the silicon epitaxial layer.

[0004] Patent Document 1 describes that by subjecting an extremely low-resistance n-type silicon wafer to high-temperature heat treatment (argon annealing) before forming the silicon epitaxial layer, the generation of fission chain (SF) in the silicon epitaxial layer formed thereafter can be suppressed.

[0005] Furthermore, Patent Document 2 describes that SF generation in the silicon epitaxial layer is caused by composite dislocation loop defects present in the extremely low-resistance n-type silicon wafer, and that by including a predetermined concentration of carbon in the extremely low-resistance n-type silicon wafer, the composite dislocation loop defects can be reduced, and consequently, the generation of SF in the silicon epitaxial layer can be suppressed.

[0006] On the other hand, Patent Document 3 describes a method for manufacturing a bonded wafer by vacuum room-temperature bonding. Specifically, it describes a method for manufacturing an epitaxial wafer characterized by comprising: an epitaxial layer formation step of forming an epitaxial layer on the surface of an active layer wafer; a bonding step of applying an activation treatment to the surface of the epitaxial layer and the surface of the support substrate wafer in a vacuum and room temperature environment to form amorphous layers on both surfaces, and then bonding the active layer wafer and the support substrate wafer via the amorphous layers on both surfaces; and a substrate removal step of removing the active layer wafer to expose the epitaxial layer. In normal epitaxial growth, the support substrate wafer is exposed to a high-temperature environment during epitaxial growth, causing oxygen in the support substrate wafer to diffuse into the epitaxial layer. However, with the above method, the support substrate wafer is not exposed to a high-temperature environment, so oxygen in the support substrate wafer does not diffuse into the epitaxial layer. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2014-11293 [Patent Document 2] Japanese Patent Publication No. 2023-70066 [Patent Document 3] Japanese Patent Publication No. 2017-152570 [Overview of the project] [Problems that the invention aims to solve]

[0008] The technologies described in Patent Documents 1 and 2 are effective in suppressing the generation of fission chains (SFs) in the silicon epitaxial layer when forming a silicon epitaxial layer on an ultra-low resistance n-type silicon wafer, but they cannot completely eliminate the generation of SFs. Since the silicon epitaxial layer is a device layer on which semiconductor devices such as power MOS transistors are formed, it is desirable to reduce the generation of SFs as much as possible.

[0009] Therefore, the inventor considered bonding an n-type silicon layer with specifications corresponding to a silicon epitaxial layer to an ultra-low-resistance n-type silicon wafer by a vacuum normal-temperature bonding method, rather than forming a silicon epitaxial layer on the ultra-low-resistance n-type silicon wafer. If this can be realized, it is clear that the bonded silicon layer does not have SF generated by epitaxial growth. However, as described above, since there are a large number of composite dislocation loop defects in the ultra-low-resistance n-type silicon wafer, naturally, composite dislocation loop defects are also exposed on the surface of the silicon wafer. Therefore, it is generally considered difficult to bond a silicon layer to an ultra-low-resistance n-type silicon wafer void-free using the vacuum normal-temperature bonding method, and applying the vacuum normal-temperature bonding method as described in Patent Document 3 to an ultra-low-resistance n-type silicon wafer has not been considered so far.

[0010] In fact, according to the research of the inventor, simply applying the vacuum normal-temperature bonding method to an ultra-low-resistance n-type silicon wafer forms voids (bonded parts such as voids) on the bonding surface between the silicon wafer and the silicon layer, and the silicon layer cannot be bonded void-free.

[0011] In view of the above problems, an object of the present invention is to provide a high-quality bonded wafer in which an ultra-low-resistance n-type silicon wafer and a high-resistance and low-oxygen n-type silicon layer functioning as a device layer are bonded together, and a suitable manufacturing method therefor.

Means for Solving the Problems

[0012] To solve the above problems, the present inventors conducted intensive research and obtained the following findings. That is, by optimizing the bonding conditions of the vacuum room temperature bonding method, it was found that an n-type silicon layer can be bonded void-free to an extremely low-resistance n-type silicon wafer having dislocation loop defects. Specifically, in the activation treatment step of vacuum room temperature bonding, it was important that the thickness of the amorphous layer formed on the surface layer portion of the extremely low-resistance n-type silicon wafer be 5 nm or more. By forming an amorphous layer with a thickness of a predetermined value or more, it is considered that the surface layer portion (amorphous layer) of the n-type silicon wafer is in a state where no composite dislocation loop defects exist. As a result, the n-type silicon layer can be bonded to the extremely low-resistance n-type silicon wafer without voids on the bonding surface.

[0013] Based on the above findings, the gist configuration of the present invention completed is as follows. [1] A silicon layer having a dopant of phosphorus, a resistivity of 0.01 Ω·cm or more and 10 Ω·cm or less, and an oxygen concentration of 5×10 17 atoms / cm 3 is bonded via a silicon amorphous layer to the surface of a silicon wafer having a dopant of phosphorus and a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, and the silicon amorphous layer is void-free, a bonded wafer.

[0014] [2] The bonded wafer according to [1] above, wherein the silicon wafer has composite dislocation loop defects.

[0015] [3] The bonded wafer according to [1] or [2] above, wherein the silicon layer is free of stacking defects.

[0016] [4] The bonded wafer according to any one of [1] to [3] above, wherein the silicon layer is obtained from an FZ silicon wafer.

[0017] [5] The bonded wafer according to any one of the above [1] to [3], wherein the silicon layer is obtained from a dislocation cluster-free and COP-free CZ silicon wafer.

[0018] [6] The bonded wafer according to any one of the above [1] to [3], wherein the silicon layer is obtained from the silicon epitaxial layer of an epitaxial silicon wafer.

[0019] [7] A step of preparing a silicon wafer having a dopant of phosphorus and a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, The dopant is phosphorus, with a resistivity of 0.01 Ω·cm to 10 Ω·cm and 5 × 10 17 atoms / cm 3 The process of preparing an FZ silicon wafer having the following oxygen concentrations, An activation treatment step in which the surface of the silicon wafer and the surface of the FZ silicon wafer are irradiated with ionized neutral elements under vacuum and room temperature to form a first amorphous layer with a thickness of 5 nm or more on the surface of the silicon wafer and a second amorphous layer on the surface of the FZ silicon wafer, The process continues by bringing the first amorphous layer and the second amorphous layer into contact under vacuum and room temperature, thereby bonding the silicon wafer and the FZ silicon wafer via a silicon amorphous layer formed by the integration of the first amorphous layer and the second amorphous layer. Subsequently, the FZ silicon wafer is thinned to form a silicon layer, A method for manufacturing a bonded wafer, comprising having and obtaining the bonded wafer described in any one of the above items [1] to [3].

[0020] [8] A step of preparing a silicon wafer having a dopant of phosphorus and a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, The dopant is phosphorus, with a resistivity of 0.01 Ω·cm to 10 Ω·cm and 5 × 10 17 atoms / cm 3A process for preparing a dislocation cluster-free and COP-free CZ silicon wafer having the following oxygen concentrations, An activation treatment step in which the surface of the silicon wafer and the surface of the CZ silicon wafer are irradiated with ionized neutral elements under vacuum and room temperature to form a first amorphous layer with a thickness of 5 nm or more on the surface of the silicon wafer and a second amorphous layer on the surface of the CZ silicon wafer, The process continues by bringing the first amorphous layer and the second amorphous layer into contact under vacuum and room temperature, thereby bonding the silicon wafer and the CZ silicon wafer via a silicon amorphous layer formed by the integration of the first amorphous layer and the second amorphous layer. Subsequently, the CZ silicon wafer is thinned to form a silicon layer, A method for manufacturing a bonded wafer, comprising having and obtaining the bonded wafer described in any one of the above items [1] to [3].

[0021] [9] A step of preparing a silicon wafer having a dopant of phosphorus and a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, On the surface of the second silicon wafer, the dopant is phosphorus, and the resistivity is between 0.01 Ω·cm and 10 Ω·cm, and 5 × 10 17 atoms / cm 3 A step to prepare an epitaxial silicon wafer on which a silicon epitaxial layer having the following oxygen concentrations is formed, An activation treatment step in which ionized neutral elements are irradiated onto the surface of the silicon wafer and the surface of the silicon epitaxial layer under vacuum and room temperature to form a first amorphous layer with a thickness of 5 nm or more on the surface of the silicon wafer and a second amorphous layer on the surface of the silicon epitaxial layer, The process continues by bringing the first amorphous layer and the second amorphous layer into contact under vacuum and room temperature, thereby bonding the silicon wafer and the epitaxial silicon wafer via a silicon amorphous layer formed by the integration of the first amorphous layer and the second amorphous layer. Subsequently, the second silicon wafer is removed, and optionally the silicon epitaxial layer is further reduced in thickness to form a silicon layer. A method for manufacturing a bonded wafer, comprising having and obtaining the bonded wafer described in any one of the above items [1] to [3]. [Effects of the Invention]

[0022] According to the present invention, it is possible to provide a high-quality bonded wafer comprising an extremely low-resistance n-type silicon wafer and a high-resistance, low-oxygen n-type silicon layer that functions as a device layer, and a suitable method for manufacturing the same. [Brief explanation of the drawing]

[0023] [Figure 1] This is a schematic cross-sectional view of bonded wafers 100, 200, and 300 according to one embodiment of the present invention. [Figure 2] Figures (A) to (F) are schematic cross-sectional views illustrating a method for manufacturing a bonded wafer 100 according to a first embodiment of the present invention. [Figure 3] Figures (A) to (F) are schematic cross-sectional views illustrating a method for manufacturing a bonded wafer 200 according to a second embodiment of the present invention. [Figure 4] Figures (A) to (F) are schematic cross-sectional views illustrating a method for manufacturing a bonded wafer 300 according to a third embodiment of the present invention. [Figure 5] This is a schematic cross-sectional view of a vacuum room-temperature bonding apparatus 60 used in each embodiment of the present invention. [Figure 6] This figure shows the observation points for cross-sectional TEM when evaluating the presence or absence of voids in a silicon amorphous layer. [Modes for carrying out the invention]

[0024] [Method for manufacturing bonded wafers] (First Embodiment) Referring to FIGS. 2(A) to (F), a method for manufacturing the bonded wafer 100 according to the first embodiment of the present invention will be described. First, as shown in FIG. 2(A), a silicon wafer 10 having a dopant of phosphorus and a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less is prepared. Further, as shown in FIG. 2(C), an FZ silicon wafer 20 having a dopant of phosphorus, a resistivity of 0.01 Ω·cm or more and 10 Ω·cm or less, and an oxygen concentration of 5×10 17 atoms / cm 3 or less is prepared.

[0025] Next, as shown in FIGS. 2(A), (B), (C), and (D), the surface 10A of the silicon wafer 10 and the surface 20A of the FZ silicon wafer 20 are irradiated with ionized neutral elements at room temperature under vacuum, so that the surface layer portion of the silicon wafer 10 is made into a first amorphous layer 50A, and the surface layer portion of the FZ silicon wafer 20 is made into a second amorphous layer 50B (activation treatment step). Here, it is important that the thickness of the first amorphous layer 50A is 5 nm or more, which will be described in detail later.

[0026] As shown in FIGS. 2(B), (D), and (E), subsequently, at room temperature under vacuum, the first amorphous layer 50A and the second amorphous layer 50B are brought into contact with each other, and the silicon wafer 进行10 and the FZ silicon wafer 20 are bonded through a silicon amorphous layer 50 formed by integrating the first amorphous layer 50A and the second amorphous layer 50B.

[0027] Thereafter, as shown in FIGS. 2(E) and (F), the FZ silicon wafer 20 is thinned to form a silicon layer 22. Thus, as shown in FIGS. 1 and 2(F), a bonded wafer 100 in which the silicon layer 22 is bonded to the surface of the silicon wafer 10 through the silicon amorphous layer 50 is obtained. The silicon layer 22 is obtained from the FZ silicon wafer 20 and functions as a device layer on which semiconductor devices such as power MOS transistors are formed.

[0028] (Second Embodiment) A method for manufacturing a bonded wafer 200 according to a second embodiment of the present invention will be described with reference to Figures 3(A) to (F). First, as shown in Figure 3(A), a silicon wafer 10 is prepared in which the dopant is phosphorus and the resistivity is between 0.5 mΩ·cm and 1.2 mΩ·cm. Also, as shown in Figure 3(C), a silicon wafer 10 is prepared in which the dopant is phosphorus and the resistivity is between 0.01 Ω·cm and 10 Ω·cm and 5 × 10 17 atoms / cm 3 Prepare a dislocation cluster-free and COP-free CZ silicon wafer 30 having the following oxygen concentrations.

[0029] Next, as shown in Figures 3(A), (B), (C), and (D), the surface 10A of the silicon wafer 10 and the surface 30A of the CZ silicon wafer 30 are irradiated with ionized neutral elements under vacuum and room temperature to create a first amorphous layer 50A on the surface of the silicon wafer 10 and a second amorphous layer 50B on the surface of the CZ silicon wafer 30 (activation treatment step). Here, it is important that the thickness of the first amorphous layer 50A be 5 nm or more, but more details will be described later.

[0030] As shown in Figures 3(B), (D), and (E), the first amorphous layer 50A and the second amorphous layer 50B are brought into contact under vacuum and room temperature conditions, thereby bonding the silicon wafer 10 and the CZ silicon wafer 30 via a silicon amorphous layer 50 formed by the integration of the first amorphous layer 50A and the second amorphous layer 50B.

[0031] Subsequently, as shown in Figures 3(E) and 3(F), the CZ silicon wafer 30 is thinned to form a silicon layer 32. In this way, as shown in Figures 1 and 3(F), a bonded wafer 200 is obtained in which the silicon layer 32 is bonded to the surface of the silicon wafer 10 via a silicon amorphous layer 50. The silicon layer 32 is obtained from a dislocation cluster-free and COP-free CZ silicon wafer 30 and functions as a device layer on which semiconductor devices such as power MOS transistors are formed.

[0032] (Third embodiment) A method for manufacturing a bonded wafer 300 according to a third embodiment of the present invention will be described with reference to Figures 4(A) to (F). First, as shown in Figure 4(A), a silicon wafer 10 is prepared in which the dopant is phosphorus and the resistivity is between 0.5 mΩ·cm and 1.2 mΩ·cm. Also, as shown in Figure 4(C), on the surface of the second silicon wafer 42, a dopant is prepared in which the resistivity is between 0.01 Ω·cm and 10 Ω·cm and 5 × 10 17 atoms / cm 3 Prepare an epitaxial silicon wafer 40 on which a silicon epitaxial layer 44 having the following oxygen concentrations is formed.

[0033] Next, as shown in Figures 4(A), (B), (C), and (D), the surface 10A of the silicon wafer 10 and the surface 44A of the silicon epitaxial layer 44 are irradiated with ionized neutral elements under vacuum and room temperature to create the first amorphous layer 50A on the surface of the silicon wafer 10 and the second amorphous layer 50B on the surface of the silicon epitaxial layer 44 (activation treatment step). Here, it is important that the thickness of the first amorphous layer 50A be 5 nm or more, but more details will be described later.

[0034] As shown in Figures 4(B), (D), and (E), the first amorphous layer 50A and the second amorphous layer 50B are brought into contact under vacuum and room temperature conditions, thereby bonding the silicon wafer 10 and the epitaxial silicon wafer 40 via a silicon amorphous layer 50 formed by the integration of the first amorphous layer 50A and the second amorphous layer 50B.

[0035] Subsequently, as shown in Figures 4(E) and 4(F), the second silicon wafer 42 is removed, and optionally the silicon epitaxial layer 44 is further reduced in thickness to form a silicon layer 46. In this way, as shown in Figures 1 and 4(F), a bonded wafer 300 is obtained in which the silicon layer 46 is bonded to the surface of the silicon wafer 10 via a silicon amorphous layer 50. The silicon layer 46 is obtained from the silicon epitaxial layer 44 of the epitaxial silicon wafer 40 and functions as a device layer on which semiconductor devices such as power MOS transistors are formed.

[0036] [Silicon wafer 10] The silicon wafer 10 is an extremely low-resistivity n-type single-crystal silicon wafer with a phosphorus dopant and a resistivity of 0.5 mΩ·cm to 1.2 mΩ·cm. This is because, when the bonded wafers 100, 200, and 300 of this embodiment are applied to the fabrication of power MOS transistors, the resistivity of the silicon wafer 10 must be extremely low. From this viewpoint, the resistivity of the silicon wafer 10 is set to 1.2 mΩ·cm or less. In particular, the resistivity of the silicon wafer 10 is preferably 1.0 mΩ·cm or less, and more preferably 0.9 mΩ·cm or less. In this case, the generation of SF during epitaxial growth is particularly likely to be a problem, making it easier to demonstrate the effects of the present invention. The dopant concentration of the silicon wafer 10 is appropriately set to achieve the above resistivity.

[0037] In this specification, "resistivity of the silicon wafer" is the value measured on the surface of the silicon wafer 10 using the four-probe method. For bonded wafers 100, 200, and 300, the resistivity of the silicon wafer 10 is the value measured on the back surface of the silicon wafer 10 (the surface on which the silicon layer is not bonded) using the four-probe method.

[0038] Such an extremely low-resistance, n-type silicon wafer 10 has composite dislocation loop defects inside, and these composite dislocation loop defects are also exposed on its surface. Furthermore, composite dislocation loop defects are also present inside the silicon wafer 10 in bonded wafers 100, 200, and 300.

[0039] The presence or absence of composite dislocation loop defects can be evaluated by cleaving the silicon wafer 10 in the thickness direction and observing the cleaved surface with a transmission electron microscope (TEM). Dislocation loop defects are defects in which disordered parts of the crystal arrangement are linked together in a loop shape, and composite dislocation loop defects are large defects exceeding 60 nm in size, where multiple dislocation loop defects overlap.

[0040] The diameter of the silicon wafer 10 is not particularly limited and may be 300 mm or less, or 200 mm or less. The thickness of the silicon wafer 10 is not particularly limited and may be, for example, 200 μm or more and 800 μm or less.

[0041] [Silicon layers 22, 32, 46] The silicon layers 22, 32, and 46 bonded to the silicon wafer 10 function as device layers on which semiconductor devices such as power MOS transistors are formed, and therefore have specifications equivalent to the silicon epitaxial layer in a conventional epitaxial silicon wafer for power MOS transistors. In this embodiment, the silicon layers 22, 32, and 46 have phosphorus as a dopant, a resistivity of 0.01 Ω·cm to 10 Ω·cm and 5 × 10⁻¹⁰ 17 atoms / cm 3 The n-type silicon layer has the following oxygen concentration. By setting the resistivity to between 0.01 Ω·cm and 10 Ω·cm, the generation of parasitic resistance in power MOS transistors can be suppressed. The dopant concentrations of silicon layers 22, 32, and 46 are appropriately set to achieve the above resistivity. In addition, the oxygen concentration is set to 5 × 10 17 atoms / cm 3By doing the following, the formation of oxygen precipitates within the silicon layer can be reliably prevented, and the generation of leakage current caused by oxygen precipitates can be prevented during device fabrication.

[0042] In this specification, "resistivity of the silicon layer" refers to the value measured on the surface of silicon layers 22, 32, and 46 using the four-probe method. The same applies to the resistivity of the various wafers or silicon epitaxial layers that form the silicon layer. Furthermore, in this specification, "oxygen concentration of the silicon layer" refers to the value measured according to the method compliant with ASTM F121-1979. The same applies to the oxygen concentration of the various wafers or silicon epitaxial layers that form the silicon layer.

[0043] The thickness of the silicon layers 22, 32, and 46 can be appropriately determined according to the type and structure of the semiconductor device formed thereon, and is preferably 1 μm to 100 μm.

[0044] Examples of substrates to be bonded to the silicon wafer 10, which can obtain a silicon layer with the specifications described above, include the FZ silicon wafer 20 shown in the first embodiment, the CZ silicon wafer 30 shown in the second embodiment, and the epitaxial silicon wafer 40 shown in the third embodiment. These will be described below.

[0045] [FZ Silicon Wafer 20] The FZ silicon wafer 20 used in the first embodiment becomes the silicon layer 22 in the bonded wafer 100, and is therefore a high-resistivity, low-oxygen n-type single-crystal silicon wafer having the same dopant species, resistivity, and oxygen concentration as the silicon layer 22. In this respect, the FZ silicon wafer is a wafer obtained by slicing a single-crystal silicon ingot grown by the Floating Zone (FZ) method with a wire saw or the like, and since there is no oxygen supply source in its manufacturing process, the oxygen concentration throughout the entire thickness direction is 3 × 10⁻¹⁰. 16 atoms / cm 3The wafer will be below the detection limit specified below. Therefore, in this invention, the FZ silicon wafer can be suitably used as a substrate to be bonded to the silicon wafer 10. The diameter of the FZ silicon wafer 20 is the same as the diameter of the silicon wafer 10. The thickness of the FZ silicon wafer 20 is not particularly limited and may be, for example, 200 μm or more and 800 μm or less.

[0046] [CZ Silicon Wafer 30] The CZ silicon wafer 30 used in the second embodiment becomes the silicon layer 32 in the bonded wafer 200, and is therefore a high-resistivity, low-oxygen n-type single-crystal silicon wafer having the same dopant species, resistivity, and oxygen concentration as the silicon layer 32. A CZ silicon wafer is a wafer obtained by slicing a single-crystal silicon ingot grown by the Czochralski (CZ) method with a wire saw or the like, and generally has an oxygen concentration of 1 × 10⁻⁶. 17 atoms / cm 3 The above 18 x 10 17 atoms / cm 3 The following applies. In this invention, for example, the oxygen concentration throughout the thickness direction is 5 × 10, which is produced by using the MCZ (Magnetic field applied Czochralski) method. 17 atoms / cm 3 The following CZ silicon wafers can be suitably used as substrates to be bonded to the silicon wafer 10. The diameter of the CZ silicon wafer 30 is equal to the diameter of the silicon wafer 10. The thickness of the CZ silicon wafer 30 is not particularly limited and may be, for example, 200 μm or more and 800 μm or less.

[0047] The CZ silicon wafer 30 is assumed to be dislocation cluster-free and COP-free. In the production of single-crystal silicon ingots by the CZ method, the defect distribution formed within the single crystal differs depending on the thermal history experienced by the single-crystal ingot during growth. It is known that crystalline regions are formed within the single-crystal ingot, such as regions where dislocation clusters originating from interstitial silicon occur, regions where vacancy-induced vacancy aggregation defects (COP: Crystal Originated Particles) occur, and defect-free regions where dislocation clusters and COPs do not exist. In this embodiment, a silicon wafer that does not contain dislocation clusters and vacancy aggregation defects (COP: Crystal Originated Particles) is used as the CZ silicon wafer 30. This makes it possible to obtain a silicon layer 32 that does not contain dislocation clusters and COPs, and to suppress the generation of dark current in the photodiode formation region (space charge region).

[0048] In this specification, "COP-free" means that no COPs are detected by the observation and evaluation described below. Specifically, first, a silicon wafer cut from a single-crystal silicon ingot grown by the CZ method is subjected to SC-1 cleaning (i.e., cleaning with a mixture of ammonia water, hydrogen peroxide water, and ultrapure water in a 1:1:15 ratio). After cleaning, the surface of the silicon wafer is observed and evaluated using a KLA-Tencor Surfscan SP-2 surface defect inspection device to identify light point defects (LPDs) that are presumed to be surface pits. The observation mode is set to oblique mode (oblique incidence mode), and the estimation of surface pits is based on the detection size ratio of the wide / narrow channel. The LPDs thus identified are evaluated for whether or not they are COPs using an atomic force microscope (AFM). A silicon wafer in which no COPs are observed based on this observation and evaluation is defined as a "COP-free silicon wafer".

[0049] Dislocation clusters are large defects (dislocation loops) of about 10 μm in size that form as aggregates of excess interstitial silicon. By applying etching treatments such as Seco etching or by decorating with Cu to make them visible, the presence or absence of dislocation clusters can be easily confirmed at a visual level.

[0050] [Epitaxial silicon wafer 40] The epitaxial silicon wafer 40 used in the third embodiment is formed by forming a silicon epitaxial layer 44 on the surface of a second silicon wafer 42. Since the silicon epitaxial layer 44 becomes the silicon layer 46 in the bonded wafer 400, it is a high-resistivity, low-oxygen n-type single-crystal silicon layer having the same dopant species, resistivity, and oxygen concentration as the silicon layer 46. In this regard, since there is no oxygen supply source in the epitaxial growth process, the oxygen concentration throughout the thickness direction is 3 × 10⁻¹⁰. 16 atoms / cm 3 The epitaxial layer 44 is below the detection limit. Therefore, in the present invention, the epitaxial silicon wafer 40 can be suitably used as a substrate to which the silicon wafer 10 is bonded. The diameter of the epitaxial silicon wafer 40 is the same as the diameter of the silicon wafer 10. The thickness of the epitaxial silicon wafer 40 is not particularly limited and may be, for example, 200 μm or more and 800 μm or less. Of these, the thickness of the silicon epitaxial layer 44 only needs to be equal to or greater than the thickness of the final silicon layer 46, and may be, for example, 1 μm or more and 100 μm or less.

[0051] Since the second silicon wafer 42 is removed after bonding, its specifications (dopant species, resistivity, and oxygen concentration) are not particularly limited. However, to reduce the influence of oxygen diffusion and dopant diffusion from the second silicon wafer 42 to the silicon epitaxial layer 44, it is preferable that its specifications be close to those of the silicon epitaxial layer 44. For this reason, the dopant is preferably phosphorus, and the resistivity is preferably 0.01 Ω·cm to 10 Ω·cm. The oxygen concentration is 10 × 10 17atoms / cm 3 The following is preferable: 5 × 10 17 atoms / cm 3 The following is more preferable:

[0052] [Bonding process using vacuum room temperature bonding method] The vacuum room-temperature bonding method will be described in detail below, using the first embodiment as an example, but the same applies to the second and third embodiments.

[0053] First, as shown in Figures 2(A), (B), (C), and (D), the surface 10A of silicon wafer 10 and the surface 20A of FZ silicon wafer 20 are irradiated with ionized neutral elements under vacuum and room temperature to create a first amorphous layer 50A on the surface of silicon wafer 10 and a second amorphous layer 50B on the surface of FZ silicon wafer 20 (activation treatment process). At this time, dangling bonds (bonding hands) inherent to silicon appear on the surfaces of the first amorphous layer 50A and the second amorphous layer 50B. Since these dangling bonds are energetically unstable, when the surfaces of the first amorphous layer 50A and the second amorphous layer 50B are brought into contact under vacuum and room temperature, a bonding force instantly acts between the wafers to eliminate the dangling bonds on the surfaces of each layer, and the two wafers are firmly bonded together without the need for heat treatment or other procedures.

[0054] In vacuum room-temperature bonding, activation treatment can be performed by sputtering the surface of each wafer (bonding surface) by ionizing neutral elements accelerated by an ion beam device, or by performing plasma etching, which involves accelerating neutral elements ionized in a plasma atmosphere onto the surface of each wafer for etching.

[0055] Figure 5 shows an example of a vacuum room-temperature bonding apparatus that activates the bonding surfaces of silicon wafer 10 and FZ silicon wafer 20 (or CZ silicon wafer 30 or epitaxial silicon wafer 40) by plasma etching, and then bonds the two wafers together. This vacuum room-temperature bonding apparatus 60 includes a plasma chamber 61, a gas inlet 62, a vacuum pump 63, a pulse voltage application device 64, and wafer fixing stands 65A and 65B.

[0056] First, silicon wafers 10 and FZ silicon wafers 20 (or CZ silicon wafers 30 or epitaxial silicon wafers 40) are placed and fixed on wafer fixing stands 65A and 65B, respectively, in the plasma chamber 61. Next, the pressure inside the plasma chamber 61 is reduced by a vacuum pump 63, and then the source gas is introduced into the plasma chamber 61 from the gas inlet 62. Subsequently, a pulsed negative voltage is applied to the wafer fixing stands 65A and 65B (and each wafer fixed thereto) by a pulse voltage application device 64. This generates plasma from the source gas and accelerates the ions of the source gas contained in the generated plasma toward both wafers 10 and 20 for irradiation.

[0057] Here, it is important that the activation process is carried out so that the thickness of the first amorphous layer 50A formed on the surface of the silicon wafer 10 is 5 nm or more. By forming the first amorphous layer 50A with a predetermined thickness or more in this way, although composite dislocation loop defects exist inside the silicon wafer 10, composite dislocation loop defects are absent from the first amorphous layer 50A on its surface. As a result, it becomes possible to bond the silicon wafer 10 and the FZ silicon wafer 20 (or CZ silicon wafer 30 or epitaxial silicon wafer 40) without the presence of voids at the bonding surface. On the other hand, if the thickness of the first amorphous layer 50A is excessive, the flatness of the surface of the first amorphous layer 50A that forms the bonding surface deteriorates, and bonding defects may occur. Therefore, it is preferable that the thickness of the first amorphous layer 50A is 20 nm or less.

[0058] The thickness of the second amorphous layer 50B formed on the surface of the FZ silicon wafer 20, CZ silicon wafer 30, or silicon epitaxial layer 44 is not particularly limited and can be, for example, 2 nm or more, as in the conventional method. On the other hand, if the thickness of the second amorphous layer 50B is excessive, the flatness of the surface of the second amorphous layer 50B which forms the bonding surface will deteriorate, and bonding defects may occur. Therefore, it is preferable that the thickness of the second amorphous layer 50B be 20 nm or less. In this embodiment, since the thickness of the first amorphous layer 50A needs to be relatively thick, from the viewpoint of process cost, it is preferable that the thickness of the second amorphous layer 50B be smaller than the thickness of the first amorphous layer 50A.

[0059] The thicknesses of the first amorphous layer 50A and the second amorphous layer 50B can be controlled by adjusting the pulse voltage used to accelerate the ions.

[0060] The silicon amorphous layer 50 in bonded wafers 100, 200, and 300 is formed by integrating a first amorphous layer 50A and a second amorphous layer 50B, and its thickness may be between 7 nm and 40 nm.

[0061] The neutral element to be irradiated is preferably at least one selected from the group consisting of argon (Ar), neon (Ne), xenon (Xe), hydrogen (H), helium (He), and silicon (Si).

[0062] The pressure (vacuum) inside the plasma chamber 61 is 1 × 10⁻⁶ -5 It is preferable to keep the Pa level below Pa. This suppresses the reattachment of sputtered elements to the wafer surface, allowing the activation treatment to be performed without reducing the dangling bond formation rate.

[0063] The pulse voltage applied to the silicon wafer 10 is important for controlling the thickness of the first amorphous layer 50A formed on the surface of the silicon wafer 10. It is preferable to set the pulse voltage applied to the silicon wafer 10 so that the acceleration energy of the irradiated element on the wafer surface is between 2.5 keV and 10 keV. If the acceleration energy is less than 2.5 keV, it is difficult to make the thickness of the first amorphous layer 50A 5 nm or more. If the acceleration energy exceeds 10 keV, the acceleration voltage is excessive, ions are implanted into the wafer, and the amorphous layer is not formed on the surface of the wafer.

[0064] The pulse voltage applied to the FZ silicon wafer 20, CZ silicon wafer 30, or epitaxial silicon wafer 40 is important for controlling the thickness of the second amorphous layer 50B formed on the surface of these wafers. It is preferable to set the pulse voltage applied to each wafer so that the acceleration energy of the irradiated element on the wafer surface is between 1.0 keV and 10 keV. If the acceleration energy is less than 1.0 keV, it is difficult to achieve a thickness of 2 nm or more for the second amorphous layer 50B. Furthermore, if the acceleration energy exceeds 10 keV, the acceleration voltage is excessive, causing ions to be implanted into the wafer, preventing the formation of an amorphous layer on the surface.

[0065] The pulse voltage frequency determines the number of times each wafer is irradiated with ions. The pulse voltage frequency is preferably between 10 Hz and 10 kHz. Setting the pulse voltage frequency above 10 Hz absorbs variations in ion irradiation, stabilizing the ion irradiation amount. Furthermore, setting the pulse voltage frequency below 10 kHz stabilizes plasma formation by glow discharge.

[0066] The pulse width of the pulse voltage determines the time that ions are irradiated onto each wafer. Preferably, the pulse width is between 1 μs and 10 ms. A pulse width of 1 μs or more allows for stable ion irradiation of each wafer. Furthermore, a pulse width of 10 ms or less ensures stable plasma formation by glow discharge.

[0067] In the above process, the wafers are not heated, so their temperature remains at room temperature (typically between 30°C and 90°C).

[0068] [Silicon layer formation process] In the first embodiment, the FZ silicon wafer 20 is thinned to form a silicon layer 22. In the second embodiment, the CZ silicon wafer 30 is thinned to form a silicon layer 32. In the third embodiment, the second silicon wafer 42 is removed, and optionally the silicon epitaxial layer 44 is further thinned to form a silicon layer 46. Specifically, each wafer 20, 30, 42 and optionally the silicon epitaxial layer 44 are thinned by grinding and polishing from the surface opposite to the bonding surface. Known or arbitrary grinding and polishing methods can be suitably used for this grinding and polishing, and specifically, surface grinding and mirror polishing methods can be used.

[0069] [Bonded wafers] The bonded wafers 100, 200, and 300 manufactured in this manner according to one embodiment of the present invention are formed by bonding a silicon wafer 10 having a dopant of phosphorus and a resistivity of 0.5 mΩ·cm to 1.2 mΩ·cm to the surface of a silicon amorphous layer 50, with the dopant of phosphorus and a resistivity of 0.01 Ω·cm to 10 Ω·cm and 5 × 10 17 atoms / cm 3 The silicon amorphous layer 50 is characterized by being void-free, and is composed of silicon layers 22, 32, and 46 having the following oxygen concentrations bonded together.

[0070] In this specification, "void-free silicon amorphous layer" means that when a bonded wafer is cleaved in the thickness direction and the silicon amorphous layer portions of the cleaved cross-sections at the nine locations shown in Figure 6 are observed with a transmission electron microscope (TEM), no cavities larger than 120 nm are detected. The nine locations shown in Figure 6 are the center point of the wafer surface (point 3), and the points 5 mm inward from the outer edge of the wafer on two mutually orthogonal diameters passing through the center point (points 1, 5, 6, 9) and the midpoint between the outer edge of the wafer and the center point (points 2, 4, 7, 8).

[0071] The silicon amorphous layer 50 in bonded wafers 100, 200, and 300 can be visualized by cleaving each wafer in the thickness direction and observing the cleaved cross-section with a transmission electron microscope (TEM).

[0072] The silicon layers 22, 32, and 46 were not formed by epitaxial growth on the silicon wafer 10, but rather originate from the wafer bonded to the silicon wafer 10. Therefore, the silicon layers 22, 32, and 46 are stacking fault (SF) free.

[0073] In this specification, "a silicon layer is stacking fault-free" means that no stacking faults (SFs) are detected by the following method. Specifically, the surface of the silicon layer is measured using a surface defect inspection device (Surfscan SP-2, manufactured by KLA-Tencor). More precisely, measurements are taken in Normal mode (DCN mode) to detect LPDs (Large-Planted Disorders) of 90 nm size or larger observed on the surface of the silicon layer (excluding the annular region within 3 mm radially from the outermost edge). The detected LPD areas of 90 nm size or larger are observed and evaluated using an atomic force microscope (AFM) to determine whether or not the LPDs are stacking faults.

[0074] The diameters of the bonded wafers 100, 200, and 300 are not particularly limited and may be 300 mm or less, or 200 mm or less. The thickness of the bonded wafers 100, 200, and 300 is not particularly limited and may be, for example, 200 μm or more and 900 μm or less.

[0075] As described above, the present invention provides a high-quality bonded wafer in which an extremely low-resistance n-type silicon wafer and a high-resistance, low-oxygen n-type silicon layer are bonded together. [Examples]

[0076] (Preparation of extremely low-resistance n-type silicon wafers) A silicon wafer with a diameter of 200 mm, a thickness of 725 μm, a phosphorus dopant, and a resistivity of 0.9 mΩ·cm (as shown in Table 1) was prepared by cutting from a single-crystal silicon ingot grown by the CZ method, and this was used in samples No. 1 to 7. When the presence or absence of composite dislocation loop defects was evaluated using the method described above, composite dislocation loop defects were found to be present in this silicon wafer.

[0077] (Preparation of the wafer that will become the silicon layer) FZ silicon wafers were prepared by cutting from single-crystal silicon ingots grown using the FZ method. These wafers had a diameter of 200 mm, a thickness of 725 μm, a phosphorus dopant, and a resistivity of 0.3 Ω·cm as shown in Table 1. These wafers were used in samples No. 1 to 5.

[0078] A CZ silicon wafer with a diameter of 200 mm, a thickness of 725 μm, phosphorus as the dopant, and a resistivity of 0.3 Ω·cm (as shown in Table 1) was prepared by cutting a single-crystal silicon ingot grown using the CZ method with an applied magnetic field, and this was used in No. 6.

[0079] An epitaxial silicon wafer was obtained by cutting a CZ silicon wafer with a diameter of 200 mm, a thickness of 725 μm, a phosphorus dopant, and a resistivity of 0.3 Ω·cm as shown in Table 1, from a single-crystal silicon ingot grown by the CZ method. On this wafer, a silicon epitaxial layer with a thickness of 8 μm, a phosphorus dopant, and a resistivity of 0.3 Ω·cm as shown in Table 1 was formed to obtain an epitaxial silicon wafer, which was used in No. 7.

[0080] Table 1 shows the oxygen concentration, COP, and presence or absence of dislocation clusters for all of the FZ silicon wafers used in No. 1-5, the CZ silicon wafer used in No. 6, and the epitaxial silicon wafer used in No. 7.

[0081] (Fabrication of bonded wafers) In Nos. 1-5, an ultra-low resistance n-type silicon wafer and an FZ silicon wafer were bonded using a vacuum room-temperature bonding method. In No. 6, an ultra-low resistance n-type silicon wafer and a CZ silicon wafer were bonded using a vacuum room-temperature bonding method. In No. 7, an ultra-low resistance n-type silicon wafer and an epitaxial silicon wafer were bonded using a vacuum room-temperature bonding method. The specific conditions are shown below.

[0082] 25℃, 1×10 -5 Plasma was generated by flowing Ar in a Pa vacuum chamber, and Ar ions were irradiated onto the surfaces of two wafers to activate each wafer surface. At this time, the pulse voltage applied to each wafer was set so that the acceleration energy was the value shown in Table 1. The frequency was 140 Hz and the pulse width was 55 μs. This activation treatment formed an amorphous layer of the thickness shown in Table 1 on the surface of each wafer. Subsequently, the two wafers were bonded together by bringing the two activated surfaces into contact under vacuum and room temperature, using the activated surfaces as the bonding surface.

[0083] Subsequently, in Nos. 1-5, the FZ silicon wafers were ground and polished to obtain a silicon layer with a thickness of 4 μm, as shown in Table 1. In No. 6, the CZ silicon wafer was ground and polished to obtain a silicon layer with a thickness of 4 μm, as shown in Table 1. In No. 7, the CZ silicon wafer that served as the support substrate for the silicon epitaxial layer was removed by grinding, and the 8 μm thick silicon epitaxial layer was further reduced in thickness by grinding and polishing to obtain a silicon layer with a thickness of 4 μm, as shown in Table 1. In this way, bonded wafers were obtained in Nos. 1-7.

[0084] (Measurement of the thickness of the amorphous layer) The thickness of the amorphous layer after bonding was measured using the method described above, and the results are shown in Table 1.

[0085] (Evaluation of the presence or absence of voids) The presence or absence of voids in the bonded wafers was evaluated using the method described above, and the results are shown in Table 1.

[0086] (Evaluation of the presence or absence of stacking faults) The presence or absence of stacking faults in the silicon layer of the bonded wafer was evaluated using the method described above, and the results are shown in Table 1.

[0087] (result) As is clear from Table 1, in the example of the present invention, it was possible to bond an extremely low-resistance n-type silicon wafer and a high-resistance, low-oxygen n-type silicon layer without voids. In contrast, in the comparative example, the thickness of the amorphous layer formed on the extremely low-resistance n-type silicon wafer was insufficient, resulting in the formation of voids after bonding.

[0088] [Table 1] [Industrial applicability]

[0089] The bonded wafer of the present invention can be suitably used for fabricating semiconductor devices such as power MOS transistors on a silicon layer.

[0090] Low / medium voltage power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), used as power devices in portable devices, have a constant electrical resistance between the drain and source when operated (turned on) (this is called "on-resistance"). Reducing the on-resistance of low / medium voltage power MOSFETs can reduce the power consumption of portable devices. Against this backdrop, device manufacturers are requesting silicon wafers with high concentrations of n-type dopants, such as arsenic (As), phosphorus (P), and antimony (Sb), to reduce the on-resistance of low / medium voltage power MOSFETs.

[0091] The bonded wafer of the present invention, despite using a silicon wafer with a high concentration of n-type dopant, has no stacking faults in the silicon layer on which the device is formed, and the silicon layer and silicon wafer are firmly bonded together, resulting in improved product quality and contributing to the promotion of economic growth (Development Goal: SDGs8) for the entire semiconductor industry. [Explanation of Symbols]

[0092] 100 bonded wafers 200 bonded wafers 300 bonded wafers 10. Silicon wafers (ultra-low resistance n-type silicon wafers) 10A Surface of silicon wafer 20 FZ silicon wafers Surface of 20A FZ silicon wafer 22. Silicon layer (high-resistance, low-oxygen n-type silicon layer) 30 CZ silicon wafer Surface of 30A CZ silicon wafer 32. Silicon layer (high-resistance, low-oxygen n-type silicon layer) 40 Epitaxial silicon wafers 42 Second silicon wafer 44 Silicone epitaxial layer 44A Surface of the silicon epitaxial layer 46. ​​Silicon layer (high-resistance, low-oxygen n-type silicon layer) 50A First Amorphous Layer 50B Second Amorphous Layer 50 Amorphous silicon layer 60 Vacuum room temperature bonding equipment 61 Plasma Chamber 62 Gas inlet 63 Vacuum pump 64. Pulse voltage application device 65A Wafer Mounting Stand 65B Wafer Mounting Stand

Claims

1. On the surface of a silicon wafer having a dopant of phosphorus and a resistivity of 0.5 mΩ·cm to 1.2 mΩ·cm, a silicon amorphous layer is added, with the dopant of phosphorus having a resistivity of 0.01 Ω·cm to 10 Ω·cm and 5 × 10 １７ atoms / cm ３ It is made up of silicon layers having the following oxygen concentrations bonded together, A bonded wafer in which the silicon amorphous layer is void-free.

2. The bonded wafer according to claim 1, wherein a composite dislocation loop defect exists in the silicon wafer.

3. The bonded wafer according to claim 1, wherein the silicon layer is free of stacking faults.

4. The bonded wafer according to any one of claims 1 to 3, wherein the silicon layer is obtained from an FZ silicon wafer.

5. The bonded wafer according to any one of claims 1 to 3, wherein the silicon layer is obtained from a dislocation cluster-free and COP-free CZ silicon wafer.

6. The bonded wafer according to any one of claims 1 to 3, wherein the silicon layer is obtained from the silicon epitaxial layer of an epitaxial silicon wafer.

7. A step of preparing a silicon wafer in which the dopant is phosphorus and which has a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, The dopant is phosphorus, with a resistivity of 0.01 Ω·cm to 10 Ω·cm and 5 × 10 １７ atoms / cm ３ The process of preparing an FZ silicon wafer having the following oxygen concentrations, An activation treatment step in which the surface of the silicon wafer and the surface of the FZ silicon wafer are irradiated with ionized neutral elements under vacuum and room temperature to form a first amorphous layer with a thickness of 5 nm or more on the surface of the silicon wafer and a second amorphous layer on the surface of the FZ silicon wafer, The process continues by bringing the first amorphous layer and the second amorphous layer into contact under vacuum and room temperature, thereby bonding the silicon wafer and the FZ silicon wafer via a silicon amorphous layer formed by the integration of the first amorphous layer and the second amorphous layer. Subsequently, the FZ silicon wafer is thinned to form a silicon layer, A method for manufacturing a bonded wafer, comprising having a bonded wafer according to any one of claims 1 to 3.

8. A step of preparing a silicon wafer in which the dopant is phosphorus and which has a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, The dopant is phosphorus, with a resistivity of 0.01 Ω·cm to 10 Ω·cm and 5 × 10 １７ atoms / cm ３ A process for preparing a dislocation cluster-free and COP-free CZ silicon wafer having the following oxygen concentrations, An activation treatment step in which the surface of the silicon wafer and the surface of the CZ silicon wafer are irradiated with ionized neutral elements under vacuum and room temperature to form a first amorphous layer with a thickness of 5 nm or more on the surface of the silicon wafer and a second amorphous layer on the surface of the CZ silicon wafer, The process continues by bringing the first amorphous layer and the second amorphous layer into contact under vacuum and room temperature, thereby bonding the silicon wafer and the CZ silicon wafer via a silicon amorphous layer formed by the integration of the first amorphous layer and the second amorphous layer. Subsequently, the CZ silicon wafer is thinned to form a silicon layer, A method for manufacturing a bonded wafer, comprising having a bonded wafer according to any one of claims 1 to 3.

9. A step of preparing a silicon wafer in which the dopant is phosphorus and which has a resistivity of 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, On the surface of the second silicon wafer, the dopant is phosphorus, and the resistivity is between 0.01 Ω·cm and 10 Ω·cm, and 5 × 10 １７ atoms / cm ３ A step to prepare an epitaxial silicon wafer on which a silicon epitaxial layer having the following oxygen concentrations is formed, An activation treatment step in which the surface of the silicon wafer and the surface of the silicon epitaxial layer are irradiated with ionized neutral elements under vacuum and room temperature to form a first amorphous layer with a thickness of 5 nm or more on the surface of the silicon wafer and a second amorphous layer on the surface of the silicon epitaxial layer, The process continues by bringing the first amorphous layer and the second amorphous layer into contact under vacuum and room temperature, thereby bonding the silicon wafer and the epitaxial silicon wafer via a silicon amorphous layer formed by the integration of the first amorphous layer and the second amorphous layer. Subsequently, the second silicon wafer is removed, and optionally the silicon epitaxial layer is further reduced in thickness to form a silicon layer. A method for manufacturing a bonded wafer, comprising having a bonded wafer according to any one of claims 1 to 3.

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