Method for fabricating a metal oxide layer, and transistor

Abstract

This invention provides a method for producing metal oxide layers with high carrier mobility. [Solution] The method comprises a first to fifth step, wherein in the first step, a first amorphous film is formed; in the second step, a first crystalline film is formed from the first amorphous film by a first heat treatment; in the third step, a part of the first crystalline film is removed by wet etching to form a seed crystal layer; in the fourth step, a second amorphous film is formed on the seed crystal layer; and in the fifth step, a second crystalline film is formed from the second amorphous film by a second heat treatment. The first amorphous film, the first crystalline film, the seed crystal layer, the second amorphous film, and the second crystalline film each contain indium and oxygen, the first crystalline film has randomly oriented crystal grains, the seed crystal layer has a first crystal orientation with respect to the surface on which it is formed, and the second crystalline film consists of crystal grains having the first crystal orientation.

Description

Technical Field

[0001] One aspect of the present invention relates to a metal oxide layer, a transistor, a semiconductor device, a display device, a memory device, and an electronic device. One aspect of the present invention relates to a method for manufacturing a metal oxide layer, a method for manufacturing a transistor, and a method for manufacturing a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As the technical field of one aspect of the present invention, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device having them, a driving method thereof, or a manufacturing method thereof can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip provided with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. In addition, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may be semiconductor devices themselves and may each have a semiconductor device.

Background Art

[0004] In recent years, high-definition display devices have been demanded. As devices that require high-definition display devices, for example, devices for virtual reality (VR: Virtual Reality), augmented reality (AR: Augmented Reality), substitutional reality (SR: Substitutional Reality), and mixed reality (MR: Mixed Reality) have been actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also called light-emitting devices). Examples of light-emitting elements include organic EL (Electro-Luminescence) elements and light-emitting diodes (LEDs). Patent Document 1 discloses a high-definition display device using an organic EL element.

[0006] Technology related to transistors using semiconductor thin films is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors (OS, also called metal oxides) are attracting attention as other materials.

[0007] Indium oxide (Indium Oxide, InO) is an oxide semiconductor that can be applied to transistors. X Examples include indium gallium zinc oxide (also written as In-Ga-Zn oxide or IGZO), which is also written as IGZO. Non-Patent Documents 1 and 2 disclose thin-film transistors using indium oxide. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] International Publication No. 2016 / 038508 [Non-patent literature]

[0009] [Non-Patent Document 1] Dhananjay & Chu, CW Realization of In2O3 thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 1-4 (2007). [Non-Patent Document 2] Y. Magari et al., “High-mobility hydrogenated polycrystalline In2O3(In2O3:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022) [Non-Patent Document 3] Takashi Koida, "High-Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet<URL:https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> [Overview of the project] [Problems that the invention aims to solve]

[0010] One aspect of the present invention aims to provide a metal oxide layer with high carrier mobility. Alternatively, one aspect of the present invention aims to provide a metal oxide layer consisting of crystal grains with aligned crystal orientations. Alternatively, one aspect of the present invention aims to provide a novel metal oxide layer. Alternatively, one aspect of the present invention aims to provide a transistor, semiconductor device, display device, or memory device to which a metal oxide layer is applied. Alternatively, one aspect of the present invention aims to provide a transistor with high field-effect mobility. Alternatively, one aspect of the present invention aims to provide a transistor with high on-current. Alternatively, one aspect of the present invention aims to provide a semiconductor device, display device, or memory device with high operating speed.

[0011] Alternatively, one aspect of the present invention aims to provide a method for producing a metal oxide layer with high carrier mobility. Alternatively, one aspect of the present invention aims to provide a method for producing a metal oxide layer consisting of crystal grains with aligned crystal orientations. Alternatively, one aspect of the present invention aims to provide a novel method for producing a metal oxide layer. Alternatively, one aspect of the present invention aims to provide a method for producing a transistor or semiconductor device to which a metal oxide layer is applied. Alternatively, one aspect of the present invention aims to provide a method for producing a transistor with high field-effect mobility. Alternatively, one aspect of the present invention aims to provide a method for producing a transistor with high on-current.

[0012] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0013] One aspect of the present invention is a method for producing a metal oxide layer comprising first to fifth steps, wherein in the first step, a first amorphous film is formed; in the second step, a first crystalline film is formed from the first amorphous film by a first heat treatment; in the third step, a part of the first crystalline film is removed by wet etching to form a seed crystal layer; in the fourth step, a second amorphous film is formed on the seed crystal layer; and in the fifth step, a second crystalline film is formed from the second amorphous film by a second heat treatment, wherein the first amorphous film, the first crystalline film, the seed crystal layer, the second amorphous film, and the second crystalline film each contain indium and oxygen, the first crystalline film has randomly oriented crystal grains, the seed crystal layer has a first crystal orientation with respect to the surface to be formed, and the second crystalline film has crystal grains having the first crystal orientation.

[0014] Furthermore, in the above, the first amorphous film and the second amorphous film are each deposited by sputtering in an atmosphere containing oxygen and hydrogen at a substrate temperature of 25°C to 140°C, the first heat treatment and the second heat treatment are each carried out in an atmosphere containing nitrogen or oxygen, or both, at a temperature of 150°C to 650°C, and wet etching is preferably carried out using one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid.

[0015] Furthermore, in the above, the first crystal orientation is, <111> The second crystallized film is formed relative to the upper surface of the seed crystal layer. <111> It is preferable that the crystal orientation is such that it has the following characteristics.

[0016] Furthermore, one aspect of the present invention is a transistor having a metal oxide layer formed using the above-described method for producing a metal oxide layer, an insulating layer, and a conductive layer, wherein the metal oxide layer has a region that overlaps with the conductive layer via the insulating layer, the metal oxide layer functions as a channel formation region of the transistor, the insulating layer functions as a gate insulating layer of the transistor, and the conductive layer functions as a gate electrode of the transistor. [Effects of the Invention]

[0017] According to one aspect of the present invention, a metal oxide layer with high carrier mobility can be provided. Alternatively, according to one aspect of the present invention, a metal oxide layer consisting of crystal grains with aligned crystal orientations can be provided. Alternatively, according to one aspect of the present invention, a novel metal oxide layer can be provided. Alternatively, according to one aspect of the present invention, a transistor, semiconductor device, display device, or memory device to which a metal oxide layer is applied can be provided. Alternatively, according to one aspect of the present invention, a transistor with high field-effect mobility can be provided. Alternatively, according to one aspect of the present invention, a transistor with high on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device, display device, or memory device with high operating speed can be provided.

[0018] Alternatively, according to one aspect of the present invention, a method for producing a metal oxide layer with high carrier mobility can be provided. Alternatively, according to one aspect of the present invention, a method for producing a metal oxide layer consisting of crystal grains with aligned crystal orientations can be provided. Alternatively, according to one aspect of the present invention, a method for producing a novel metal oxide layer can be provided. Alternatively, according to one aspect of the present invention, a method for producing a transistor or semiconductor device to which a metal oxide layer is applied can be provided. Alternatively, according to one aspect of the present invention, a method for producing a transistor with high field-effect mobility can be provided. Alternatively, according to one aspect of the present invention, a method for producing a transistor with high on-current can be provided.

[0019] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims. [Brief explanation of the drawing]

[0020] [Figure 1] Figures 1(A) to 1(C) are perspective views illustrating the method for fabricating the indium oxide layer. [Figure 2] Figures 2(A1) and 2(B1) are perspective views illustrating the method for fabricating the indium oxide layer. Figures 2(A2) and 2(B2) are cross-sectional views illustrating the method for fabricating the indium oxide layer. [Figure 3] Figure 3 is a flowchart illustrating the method for fabricating the indium oxide layer. [Figure 4] Figures 4(A) and 4(B) illustrate the carrier concentration dependence of hole mobility. Figure 4(C) is a cross-sectional view illustrating an indium oxide film. [Figure 5] Figures 5(A) through 5(C) illustrate the crystal structure of indium oxide. [Figure 6] Figure 6(A) is a plan view showing an example of a transistor. Figures 6(B) and 6(C) are cross-sectional views showing an example of a transistor. [Figure 7]Figure 7(A) is a plan view showing an example of a transistor. Figure 7(B) is a cross-sectional view showing an example of a transistor. [Figure 8] Figure 8(A) is a cross-sectional view showing an example of a transistor. Figure 8(B) is a perspective view showing an example of a transistor. [Figure 9] Figure 9(A) is a plan view showing an example of a transistor. Figures 9(B) and 9(C) are cross-sectional views showing an example of a transistor. [Figure 10] Figures 10(A) through 10(C) are perspective views showing an example of a transistor. [Figure 11] Figures 11(A) to 11(C) are cross-sectional views showing an example of a transistor fabrication method. [Figure 12] Figures 12(A) to 12(C) are cross-sectional views showing an example of a transistor fabrication method. [Figure 13] Figures 13(A) to 13(C) are cross-sectional views showing an example of a transistor fabrication method. [Figure 14] Figures 14(A) to 14(C) are cross-sectional views showing an example of a transistor fabrication method. [Figure 15] Figure 15 is a block diagram of the display device. [Figure 16] Figures 16(A) to 16(C) are circuit diagrams showing examples of pixel circuit configurations. [Figure 17] Figures 17(A) to 17(C) are circuit diagrams showing examples of pixel circuit configurations. [Figure 18] Figure 18 is a block diagram illustrating an example of a semiconductor device configuration. [Figure 19] Figures 19(A) to 19(E) illustrate examples of memory cell circuit configurations. [Figure 20] Figures 20(A) to 20(C) illustrate examples of memory cell circuit configurations. [Figure 21] Figures 21(A) and 21(B) show examples of electronic components. [Figure 22]Figures 22(A) through 22(C) show examples of large-scale computers. Figure 22(D) shows an example of space equipment. Figure 22(E) shows an example of a storage system applicable to data centers. [Figure 23] Figures 23(A) through 23(F) show examples of electronic devices. [Figure 24] Figures 24(A) to 24(G) show examples of electronic devices. [Figure 25] Figures 25(A) through 25(F) show examples of electronic devices. [Figure 26] Figures 26(A) to 26(D) are surface SEM images of the indium oxide layer according to the example. [Figure 27] Figure 27(A) is a surface SEM image of the indium oxide layer according to the example. Figure 27(B) is the EBSD measurement result of the indium oxide layer according to the example. [Modes for carrying out the invention]

[0021] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0022] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0023] The positions, sizes, and extents of each component shown in the drawings may not represent their actual positions, sizes, and extents for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the drawings.

[0024] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of components and do not limit the number of components or the order of components (e.g., process order or stacking order). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0025] In this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, an identifying numeral such as "_1", "[n]", or "[m,n]" may be added to the reference numeral. Furthermore, when describing a common matter for multiple elements with identifying numerals, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0026] The words "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0027] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and Thin Film Transistors (TFTs).

[0028] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, etc., depending on the situation.

[0029] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0030] For example, assuming a circuit containing A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0031] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0032] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0033] In this specification, unless otherwise specified, on-current refers to the drain current (also written as Id) when the transistor is in the ON state (also called the conducting state). Unless otherwise specified, the ON state refers to the state in an n-channel transistor where the voltage between the gate and source (also written as Vg or Vgs) is equal to or greater than the threshold voltage (also written as Vth), and in a p-channel transistor where it is less than or equal to the threshold voltage.

[0034] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0035] In this specification, "parallel" means that two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means that two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means that two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means that two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0036] In this specification, the top surface shape of a component refers to the contour shape of the component in a plan view (also called a top view). A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0037] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlaps between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in this case too, it may be said that "matching or roughly matching top shapes." Furthermore, when the top shapes match or roughly match, it may also be said that "the edges match or roughly match," or "the edges are aligned or roughly aligned."

[0038] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0039] In drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X-axis, and unless explicitly stated, forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are directions that intersect each other. For example, the X, Y, and Z directions are directions that are orthogonal to each other.

[0040] In this specification, space groups representing the symmetry of crystal structures are denoted using international notation (or Hermann-Mauguin notation) Short notation. In addition, space group numbers from the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be included. Furthermore, Miller indices are used to indicate crystal planes and crystal directions. While crystallography uses a bar above the number to indicate space groups, crystal planes, and crystal directions, due to formatting constraints in this specification, a minus sign (-) may be placed before the number instead. Individual orientations indicating directions within a crystal are represented by [ ], collective orientations indicating all equivalent directions are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}. Note that even with the same space group number, the notation of the space group may differ depending on the choice of crystal axes.

[0041] In this specification, a grain boundary refers to, for example, the boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, boundaries between adjacent crystal grains with the same crystal orientation are not included in grain boundaries. For example, even if a boundary is observed between two crystal grains in a transmission electron microscope (TEM) image, if the crystal orientations of the two crystal grains are the same or approximately the same, the boundary may not be called a grain boundary. Also, in electron backscatter diffraction (EBSD or EBSP), if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same crystal grain.

[0042] In this specification and other texts, the cubic crystal structure is sometimes referred to as cubic crystal or cubic structure. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0043] In this specification, "crystallized film" refers to a crystalline film formed by crystallizing an amorphous film.

[0044] In this specification, a "seed crystal layer" has at least one crystal grain (seed crystal, or seed crystal grain). If multiple crystal grains are present, they are collectively referred to as the "seed crystal layer." These multiple crystal grains may be separated from each other. Therefore, the "seed crystal layer" can also be referred to as a "group of seed crystals" or a "group of seed crystal grains."

[0045] (Embodiment 1) One aspect of the present invention is a method for producing a metal oxide layer consisting of crystal grains with aligned crystal orientations.

[0046] The metal oxide layer is a crystalline indium oxide layer containing indium (In) and oxygen (O). The crystal grains constituting the indium oxide layer are relative to the surface on which it is formed. <111> It has a sense of direction.

[0047] In one embodiment of the present invention, a method for manufacturing the material is first to form an amorphous indium oxide film (a first amorphous film).

[0048] Next, the first amorphous film is subjected to the first heat treatment to crystallize the first amorphous film, thereby forming the first crystalline film. The first crystalline film is a polycrystalline film consisting of randomly oriented crystal grains.

[0049] Next, the first crystallized film is wet-etched with an acid-containing etchant to remove a portion of the first crystallized film, thereby forming a seed crystal layer. The seed crystal layer is formed from randomly oriented crystal grains that constitute the first crystallized film, with respect to the surface to be formed. <111> This is a layer in which multiple crystal grains with specific orientations remain.

[0050] Next, an amorphous indium oxide film (a second amorphous film) is deposited on the seed crystal layer.

[0051] Next, a second heat treatment is performed to crystallize the second amorphous film, thereby forming a second crystalline film. The second crystalline film is formed with respect to the upper surface of the seed crystal layer, where the second amorphous film is... <111> This is a film that has undergone crystal growth in a specific orientation. The second crystallized film has a crystal structure that reflects the crystal structure of the seed crystal layer.

[0052] The second crystallized film is formed relative to the surface to be formed. <111> This is a crystallized film composed of crystal grains aligned in orientation. Therefore, the second crystallized film is expected to have higher carrier mobility than the first crystallized film, which is composed of randomly oriented crystal grains.

[0053] The second crystallized film can be applied, for example, to a semiconductor layer having a channel formation region of a transistor. By applying the second crystallized film to the semiconductor layer of a transistor, it is expected that a transistor with higher field-effect mobility and a larger on-current can be realized compared to when the first crystallized film is applied to the same semiconductor layer.

[0054] In the following, a method for producing an indium oxide layer, which is a metal oxide layer according to one aspect of the present invention, the characteristics of indium oxide, the crystal structure of indium oxide, etc., will be explained with reference to the drawings.

[0055] <Method for preparing an indium oxide layer> Below, a method for producing a crystalline indium oxide layer, which is a metal oxide layer according to one embodiment of the present invention, will be described with reference to Figures 1(A) to 3. Figures 1(A), 1(B), 1(C), 2(A1), and 2(B1) are perspective views of the laminate at each step of the production method. Figure 2(A2) is a cross-sectional view of the laminate at the step corresponding to Figure 2(A1). Figure 2(B2) is a cross-sectional view of the laminate at the step corresponding to Figure 2(B1). Figure 3 is a flowchart showing the sequence of steps in the production method.

[0056] First, in step S1 shown in Figure 3, a first amorphous film 108a1 is deposited on the substrate 101 (Figure 1(A)).

[0057] It is preferable that the substrate 101 has sufficient heat resistance to withstand subsequent heat treatment. It is also preferable that the substrate 101 is made of a material that does not affect the crystallinity of the film formed on the substrate. For example, when an amorphous film is formed on the substrate 101 and the film is crystallized by subsequent heat treatment, it is preferable that the crystal structure of the substrate 101 does not affect the crystallization. For example, it is not preferable to use a crystalline film made of the same material as the amorphous film formed on the substrate 101 as the substrate 101.

[0058] For example, a quartz substrate can be used as the substrate 101. Although the substrate 101 is shown as a single-layer structure in Figure 1(A), etc., it can also be a laminated structure of two or more layers. For example, a glass substrate on which an inorganic insulating film such as silicon oxide or silicon nitride has been deposited can also be used as the substrate 101. Furthermore, the substrate 101 can also be configured to have semiconductor elements on it.

[0059] The first amorphous film 108a1 is an amorphous indium oxide film. The first amorphous film 108a1 can be deposited, for example, by a sputtering method using a target containing indium and oxygen.

[0060] When using sputtering to deposit the first amorphous film 108a1, a noble gas (typically argon) or oxygen as a single gas, or a mixture of a noble gas and oxygen, can be used as the sputtering gas. The proportion of the noble gas (typically argon) in the total sputtering gas is, for example, 50% to 100%, preferably 70% to 100%, and more preferably 90% to 100%. By increasing the proportion of the noble gas (typically argon) in the total sputtering gas, a first amorphous film 108a1 with low crystallinity can be deposited.

[0061] Furthermore, the sputtering gas can also contain hydrogen (H2). By introducing hydrogen when depositing the first amorphous film 108a1 using the sputtering method, it is possible to deposit a first amorphous film 108a1 with low crystallinity. In addition, it is possible to suppress the generation of crystal nuclei or promote the annihilation of crystal nuclei during the deposition of the first amorphous film 108a1.

[0062] The substrate temperature during the deposition of the first amorphous film 108a1 is preferably between room temperature (25°C) and 140°C, more preferably between room temperature and 100°C, and even more preferably at room temperature. For example, setting the substrate temperature to room temperature is preferable as it increases productivity. Furthermore, by setting the substrate temperature to room temperature or by depositing the first amorphous film 108a1 without heating the substrate, the crystallinity can be reduced.

[0063] Furthermore, the first amorphous film 108a1 can also be deposited using atomic layer deposition (ALD). For the deposition of the first amorphous film 108a1, a first precursor and a first oxidizing agent can be used. The first precursor preferably contains indium. In this case, an indium oxide film is deposited as the first amorphous film 108a1. That is, an oxide film containing a single element other than oxygen is deposited. When the first precursor contains indium, thermal ALD can be used as the ALD method.

[0064] Indium-containing precursors that can be used include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, dimethyl(2-propanolato)indium, and the like.

[0065] Furthermore, inorganic precursors that do not contain hydrocarbons can also be used as indium precursors. Examples of indium-containing inorganic precursors include halogenated indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film deposition by the ALD method can be performed while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0066] The deposition of the first amorphous film 108a1 is preferably carried out using a precursor with a low impurity concentration, i.e., a high purity precursor. The precursor preferably has a purity of 3N (99.9%) or higher, more preferably 4N (99.99%) or higher, even more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher. By using a high purity precursor, the impurities in the first amorphous film 108a1 can be reduced.

[0067] Furthermore, it is preferable to use a precursor that has been purified by two or more distillations (also called rectification or precision distillation) as the first precursor. Using such a precursor makes it easier to form a metal oxide film with fewer impurities, which is preferable. Performing distillation multiple times is preferable because it can further suppress the retention of impurities in the precursor that originate from the starting materials used in the manufacture of the precursor. However, the present invention is not limited to the above, and a precursor purified by a single distillation, i.e., simple distillation, can also be used. Using simple distillation can reduce manufacturing costs, which is preferable.

[0068] Furthermore, ozone (O3), oxygen (O2), water (H2O), hydrogen peroxide (H2O2), etc., can be used as the first oxidizing agent. Preferably, the first oxidizing agent contains at least one of ozone and oxygen. The first oxidizing agent may also contain at least one of water and hydrogen peroxide. This makes it possible to form a first amorphous film 108a1 with low crystallinity.

[0069] Unless otherwise specified in this specification, when ozone, oxygen, or water are used as oxidizing agents, these shall include not only gaseous or molecular states, but also plasma states, radical states, or ionic states.

[0070] The pulse time for introducing the first oxidizing agent is preferably 0.1 seconds to 30 seconds, more preferably 0.3 seconds to 15 seconds, and even more preferably 0.3 seconds to 10 seconds. By shortening the pulse time for introducing the first oxidizing agent and reducing the amount of the first oxidizing agent introduced, more hydrogen contained in the first precursor remains in the film. By leaving more hydrogen in the film, the formation of crystal nuclei is suppressed, and some of the crystal nuclei in the film are eliminated, resulting in a smaller number of crystal nuclei in the film.

[0071] Here, the substrate heating temperature when introducing the first precursor into the reaction chamber is preferably set to a temperature corresponding to the decomposition temperature of the first precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, for example, the substrate heating temperature can be set to room temperature (25°C) or higher and 350°C or lower, preferably room temperature or higher and 200°C or lower, and more preferably room temperature or higher and 150°C or lower. By lowering the substrate heating temperature, a first amorphous film 108a1 with low crystallinity can be formed.

[0072] Next, in step S2 shown in Figure 3, the first heat treatment is performed to crystallize the first amorphous film 108a1, thereby forming the first crystalline film 108p1 (Figure 1(B)).

[0073] The first crystallized film 108p1 is a polycrystalline indium oxide film formed by crystal growth of the first amorphous film 108a1 through the first heat treatment. Figure 1(B) schematically shows how the first crystallized film 108p1 is composed of randomly oriented crystal grains of various sizes by applying different hatching patterns to each crystal grain.

[0074] The heat treatment temperature is preferably 150°C to 650°C, more preferably 150°C to 550°C, more preferably 150°C to 450°C, more preferably 150°C to 350°C, more preferably 150°C to 300°C, and more preferably 150°C to 250°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a very low content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the first crystallized film 108p1 as much as possible. In addition, performing the heat treatment in an oxygen-containing atmosphere may enhance the effect of reducing defects in the first crystallized film 108p1. For the heat treatment, for example, an oven or a rapid thermal annealing (RTA) device can be used. Using an RTA device can shorten the heat treatment time.

[0075] Next, in step S3 shown in Figure 3, wet etching is performed on the first crystallized film 108p1. This wet etching removes a portion of the first crystallized film 108p1 and forms a seed crystal layer 108s (Figure 1(C)). As explained in <Crystal Structure of Indium Oxide>, the randomly oriented crystal grains of the first crystallized film 108p1 may have different etching rates for wet etching depending on their crystal orientation relative to the surface to be formed (in this case, the upper surface of the substrate 101). For example, relative to the surface to be formed <111> Crystal grains oriented in a particular direction are relative to the surface on which they are formed. <001> The etching rate for wet etching may be slower than that for crystal grains oriented in a specific direction. Therefore, for example, the first crystallized film 108p1 may have a slower etching rate relative to the surface to be formed. <111> Crystal grains oriented in a specific direction, <001> When crystal grains oriented in a particular direction are present, wet etching is performed <001> The crystal grains that are oriented in a particular direction are removed first. <111> It is possible to leave crystal grains oriented in a specific direction on the substrate 101. Figure 1(C) schematically shows how, among the randomly oriented crystal grains of the first crystallized film 108p1 shown in Figure 1(B), only crystal grains with a specific crystal orientation remain after the wet etching. That is, the seed crystal layer 108s has a specific crystal orientation (for example, <111> This is an indium oxide layer composed of multiple crystal grains having a specific orientation.

[0076] The etchant used for wet etching preferably contains an acid. For example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used. By performing wet etching on the first crystallized film 108p1, which is a polycrystalline indium oxide film, using the above-mentioned acid-containing etchant, it is possible to utilize the difference in etching rates due to the crystal orientation or crystallinity of the crystal grains in the first crystallized film 108p1 to leave crystal grains with a slower etching orientation as a seed crystal layer 108s.

[0077] Furthermore, since the seed crystal layer 108s acts as a seed crystal for the crystallized film (second crystallized film 108p2) to be formed in a later step, it is preferable that it is composed of multiple crystal grains aligned to a specific crystal orientation with respect to the surface to be formed (in this case, the upper surface of the substrate 101). For example, if the concentration of the etchant used for wet etching is too low, the temperature is too low, or the processing time is too short, multiple crystal grains with different crystal orientations will remain after wet etching. Conversely, if the concentration of the etchant used for wet etching is too high, the temperature is too high, or the processing time is too long, all the crystal grains of the first crystallized film 108p1 will disappear after wet etching. Therefore, it is preferable that the concentration of the etchant used for wet etching, the temperature, and the processing time are set to conditions such that among the randomly oriented crystal grains of the first crystallized film 108p1, the crystal grain having the crystal orientation that exhibits the slowest etching rate with respect to the etchant remains.

[0078] Next, in step S4 shown in Figure 3, a second amorphous film 108a2 is formed on the seed crystal layer 108s and the substrate 101 (Figures 2(A1) and 2(A2)).

[0079] For the deposition of the second amorphous film 108a2, refer to the description relating to the deposition of the first amorphous film 108a1.

[0080] Note that while Figure 2(A2), etc., shows an example where the upper surface of the film deposited on the seed crystal layer 108s (here, the second amorphous film 108a2) is flat or approximately flat, this is not always the case. Depending on the size of the seed crystal layer 108s (height relative to the substrate surface) or the thickness of the film deposited on the seed crystal layer 108s, the upper surface of the film deposited on the seed crystal layer 108s may have an uneven shape.

[0081] Next, in step S5 shown in Figure 3, a second heat treatment is performed to crystallize the second amorphous film 108a2, thereby forming a second crystalline film 108p2 (Figures 2(B1) and 2(B2)).

[0082] The second crystallized film 108p2 is a polycrystalline indium oxide film formed by crystal growth of the second amorphous film 108a2 by the second heat treatment. The second crystallized film 108p2 is formed with respect to the surface to be formed (in this case, the upper surface of the substrate 101) with a specific crystal orientation (for example, <111> With respect to the upper surface of the seed crystal layer 108s having a crystal orientation (in this case, <111> It is a film that has undergone crystal growth in a specific direction.

[0083] When the second amorphous film 108a2 crystallizes, the region in contact with the seed crystal layer 108s crystallizes first, and then the crystallization progresses laterally toward the region not in contact with the seed crystal layer 108s. Figure 2(B2) schematically shows the progression of crystal growth with arrows. Furthermore, when the crystal grains that have grown starting from the multiple seed crystals in the seed crystal layer 108s formed on the substrate 101 grow to the surface of the second amorphous film 108a2, adjacent crystal grains collide with each other, stopping crystal growth and completing the formation of the second crystallized film 108p2. The collision site between adjacent crystal grains (crystal grain boundary) becomes the crystal grain boundary. Figure 2(B1) schematically shows how the second crystallized film 108p2 is composed of multiple crystal grains that reflect the crystal orientation of the seed crystal layer 108s, by applying the same hatching pattern to both the seed crystal layer 108s and the crystal grains of the second crystallized film 108p2.

[0084] In Figure 2(B1), the second crystallized film 108p2 is shown as a polycrystalline film with grain boundaries, but it may also be a single-crystal film. In this case, since the second crystallized film 108p2 does not have grain boundaries, the carriers flowing through the second crystallized film 108p2 are not affected by carrier scattering at the grain boundaries. Therefore, a higher carrier mobility can be achieved than when the second crystallized film 108p2 is a polycrystalline film.

[0085] The crystallinity of the second crystallized film 108p2 can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0086] When the second crystallized film 108p2 is a polycrystalline film, it is preferable that the grain size of the crystal grains contained in the second crystallized film 108p2 is large. By using a polycrystalline film with large grain size, the number of grain boundaries in the second crystallized film 108p2 can be reduced. Therefore, the second crystallized film 108p2, which is made of a polycrystalline film with large grain size, can reduce the influence of carrier scattering from grain boundaries and achieve high carrier mobility.

[0087] When a polycrystalline indium oxide film is used as the second crystallized film 108p2, the grain size of the crystal grains contained in the indium oxide film is preferably, for example, 0.1 μm or larger, more preferably 0.2 μm or larger, more preferably 0.3 μm or larger, more preferably 0.4 μm or larger, more preferably 0.5 μm or larger, more preferably 0.6 μm or larger, and more preferably 0.7 μm or larger. Since a larger grain size is preferred, no particular upper limit is set for the grain size. Note that the grain size of the crystal grains is not limited to the range described above.

[0088] The grain size of the crystal grains contained in the second crystallized film 108p2 can be analyzed, for example, by optical microscopy, scanning electron microscopy (SEM), TEM, scanning transmission electron microscopy (STEM), or EBSD. Alternatively, a combination of these methods can be used for analysis. For example, the average grain size of multiple crystal grains can be used as the grain size. Furthermore, the grain size of a crystal grain can be defined, for example, as the diameter of a circle with the same area as the crystal grain. This diameter is sometimes called the equivalent diameter of a circle.

[0089] Furthermore, if the thickness of the second crystallized film 108p2 is thin, it may not be possible to evaluate the crystallinity and grain size.

[0090] For the temperature, atmosphere, and equipment applicable to the second heat treatment, refer to the description relating to the temperature, atmosphere, and equipment applicable to the first heat treatment.

[0091] If the temperature of the second heat treatment is too high, crystal nuclei not originating from the seed crystal layer 108s (for example, crystal grains having a different crystal orientation from the seed crystal layer 108s; hereinafter also referred to as native nuclei) may be generated in the second amorphous film 108a2, and crystal growth using these native nuclei as seed crystals may be induced. Conversely, if the temperature of the second heat treatment is too low, the rate of crystal growth of crystal grains originating from the seed crystal layer 108s will be slow, which may result in low productivity of the laminate. Therefore, it is preferable that the temperature, treatment time, etc., of the second heat treatment be set to conditions that do not generate native nuclei and that satisfy the acceptable range of productivity of the laminate. The second heat treatment can be performed under the same conditions as the first heat treatment, or under different conditions.

[0092] <Characteristics of Indium Oxide> In the following, the properties and characteristics of a crystalline indium oxide layer, which is a metal oxide layer according to one embodiment of the present invention, will be described.

[0093] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0094] Indium oxide is a semiconductor material with properties entirely different from oxide semiconductors such as IGZO and zinc oxide. Due to its properties and characteristics, indium oxide is a preferred semiconductor material for use in semiconductor layers having channel formation regions in transistors, for example. For instance, applying indium oxide to such a semiconductor layer can be expected to achieve superior transistor characteristics (e.g., high field-effect mobility, large on-current) compared to using other oxide semiconductor materials such as IGZO or zinc oxide.

[0095] This section describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO. Figure 4(A) shows the carrier concentration dependence of silicon (Si) and indium oxide (InO X Figure 4(B) is a schematic diagram of the carrier concentration dependence of hole mobility for IGZO.

[0096] First, as indicated by the arrows in Figure 4(B), IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 4(A), indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 3). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 4(B) are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 4(A).

[0097] In Figure 4(A), the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is such that the carrier concentration value is 1 × 10⁻⁶. 15 cm -3 This range includes, for example, 1 × 10 14 cm-3 Above, 1×10 18 cm -3 The following range. By sufficiently reducing the carrier concentration, it can be expected that the value of the hole mobility can be increased to about 270 cm 2 / (V·s).

[0098] In indium oxide, the region where the carrier concentration is in the range R1 can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, copper, etc. By substituting these elements for indium, the carrier concentration can be lowered. Also, examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, antimony, etc. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0099] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and it can be said that it is a suitable carrier concentration range for, for example, the source region and drain region of a transistor, or a resistor, or a transparent conductive film. The range R2 is a range including a carrier concentration value of 1×10 20 cm -3 and, for example, 1×10 19 cm -3 or more and 1×10 22 cm -3 or less. By sufficiently increasing the carrier concentration, it can be expected that the resistivity can be reduced to 1×10<00000…​​​​​​​ In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be considered an oxide in which valence electron control is possible. Note that in IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with the IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 4(A) within the indium oxide film, a so-called nin junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0102] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0103] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors with high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0104] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0105] The crystallinity of indium oxide can be analyzed, for example, by XRD, TEM, or ED. Alternatively, a combination of these methods may be used for analysis.

[0106] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0107] The channel formation region refers to the region within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0108] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0109] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0110] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². 2 / (V·s) or more, preferably 100cm 2 (V·s) or more, more preferably 150cm 2 / (V·s) or more, more preferably 200cm 2 / (V·s) or more, more preferably 250cm 2 It can be set to (V·s) or more.

[0111] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 4(C), indium oxide films (InO X Oxygen (O) diffusing into the indium oxide film is released as oxygen molecules (O2) after passing through the film. It may also be released as water molecules (H2O) by reacting with hydrogen contained in the film. Furthermore, if oxygen vacancies (Vo) exist in the film, diffusing oxygen atoms fill those vacancies. Because oxygen diffuses easily through the indium oxide film, it can be said that it is easier to fill oxygen vacancies compared to the IGZO film.

[0112] Thus, because indium oxide films are more prone to reducing oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0113] Furthermore, as shown in Figure 4(C), the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules (H2). Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0114] A transistor using an indium oxide film is a storage-type transistor that uses electrons as the majority carrier. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0115] Table 1 shows the effective masses of single-crystal indium oxide (here, In2O3) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-response) can be realized. In addition, because of the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. -15 A) Less than or equal to, or 1aA(1 × 10 -18 A) is less than or equal to 1aA(1 × 10) under room temperature (25°C) conditions. -18 A) Less than or equal to 1zA(1×10) -21 A) The following is possible. Furthermore, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize transistors with higher field-effect mobility and lower off-current than silicon transistors (hereinafter referred to as Si transistors).

[0116] [Table 1]

[0117] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This can improve the crystallinity of the indium oxide film. A substrate (for example, a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0118] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] between the crystals of the seed layer and the crystals of the formed film (in this case, the indium oxide film) is calculated as Δa = ((L1 - L2) / L2) × 100. Here, L1 is the length of the unit cell vector or lattice constant of the crystals of the formed film, and L2 is the length of the unit cell vector or lattice constant of the crystals of the seed layer.

[0119] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably 0. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0120] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) can crystallize into a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0121] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For instance, by setting the crystal orientation of the surface of the seed layer to

[0001] and the crystal orientation of the underside of the indium oxide film to

[0111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures, YbFe2O4-type structures, Yb2Fe3O7-type structures, and modified forms thereof. An example of a crystal having a YbFe2O4-type or Yb2Fe3O7-type structure is IGZO.

[0122] <Crystal structure of indium oxide> The following describes the crystal structure of a crystalline indium oxide layer, which is a metal oxide layer according to one embodiment of the present invention. Note that this description focuses on single-crystal indium oxide (In2O3).

[0123] Figure 5(A) is a diagram illustrating the crystal structure of single-crystal indium oxide (In2O3), viewed from the a-axis direction. Single-crystal indium oxide has a cubic bixbite-type crystal structure. In Figure 5(A), indium atoms and oxygen atoms are shown at sizes corresponding to their atomic radii. As shown in Figure 5(A), when a bixbite-type indium oxide crystal is viewed from a direction perpendicular to the c-axis (in this case, the a-axis direction), it has a structure in which layers of indium (In) and oxygen (O) are alternately stacked in the c-axis direction.

[0124] Figure 5(B) shows the crystal structure of indium oxide shown in Figure 5(A), viewed from a direction perpendicular to the (111) plane (the plane corresponding to the hexagon in Figure 5(B)). Figure 5(C) shows the crystal structure of indium oxide shown in Figure 5(A), viewed from a direction perpendicular to the (001) plane (the plane corresponding to the square shown in Figure 5(C)).

[0125] As mentioned above, single-crystal indium oxide (In2O3) has a cubic crystal structure. This is the same crystal structure as single-crystal silicon (Si). In silicon, it is known that the atomic density is higher on the (111) plane than on the (001) plane, and in indium oxide, as shown in Figures 5(B) and 5(C), the interatomic distance appears different depending on the crystal plane being observed. In other words, indium oxide has different atomic densities depending on the crystal plane.

[0126] In the case of single-crystal indium oxide (In2O3), the In-In distances in the (111) plane (arrows shown in Figure 5(B)) are said to be 0.334 nm and 0.385 nm, and the In-In distance in the (001) plane (arrows shown in Figure 5(C)) is said to be 0.384 nm. Therefore, it can be said that indium oxide has a crystal structure in which the atomic density in the (111) plane is higher than that in the (001) plane.

[0127] The differences in atomic density across the crystal planes of indium oxide, as described above, are thought to be reflected in the differences in electron density across each crystal plane. That is, crystal planes with lower atomic density may have lower electron density, while crystal planes with higher atomic density may have higher electron density. Therefore, in indium oxide, the electron density of the (111) plane may be higher than that of the (001) plane.

[0128] Furthermore, the difference in electron density across each crystal plane is thought to be reflected in the difference in the strength of the ionic bonds between atoms across each crystal plane. This may be one of the reasons why, as mentioned above in the <Method for Fabricating the Indium Oxide Layer>, when wet etching is performed on a polycrystalline indium oxide film (first crystallized film 108p1), the etching rate differs depending on the crystal orientation of the randomly oriented crystal grains. In other words, in the case of the indium oxide layer, the ionic bonds between atoms on the (111) plane are stronger than the ionic bonds between atoms on the (001) plane. Therefore, when wet etching is performed on a polycrystalline film containing a mixture of crystal grains with (111) planes parallel to the substrate surface and crystal grains with (001) planes parallel to the substrate surface, it is presumed that the crystal grains with (001) planes parallel to the substrate surface will be removed first.

[0129] The following describes a specific example of a transistor configuration to which a crystalline indium oxide layer, which is a metal oxide layer according to one aspect of the present invention, can be applied. The metal oxide layer according to one aspect of the present invention can be applied to the semiconductor layer (mainly the channel formation region) of a transistor.

[0130] <Transistor Configuration Example 1> Figure 6(A) shows a plan view (also called a top view) of transistor 100. Figure 6(B) shows a cross-sectional view along the dashed line A1-A2 shown in Figure 6(A). Figure 6(C) shows a cross-sectional view along the dashed line B1-B2 shown in Figure 6(A). Note that in Figure 6(A), some components of transistor 100 (such as the insulating layer) are omitted. In subsequent drawings, as in Figure 6(A), some components may also be omitted in the plan view of the transistor.

[0131] The transistor 100 is provided on an insulating layer 110 provided on a substrate 102.

[0132] The transistor 100 includes a conductive layer 104, a conductive layer 112a, a conductive layer 112b, an insulating layer 106, and a semiconductor layer 108. In the transistor 100, the conductive layer 104 functions as a gate electrode. A portion of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as either a source electrode or a drain electrode. The conductive layer 112b functions as either a source electrode or a drain electrode. Each layer constituting the transistor 100 can be a single-layer structure or a multilayer structure.

[0133] A semiconductor layer 108 is provided in contact with the upper surface of the insulating layer 110. An insulating layer 106 is provided on the semiconductor layer 108. A portion of the insulating layer 106 (the region overlapping with the conductive layer 104) functions as the gate insulating layer of the transistor 100. The insulating layer 106 has openings 147a and 147b in the region overlapping with the semiconductor layer 108. Openings 147a and 147b are provided so as to sandwich the region of the insulating layer 106 that functions as the gate insulating layer of the transistor 100.

[0134] A conductive layer 104, a conductive layer 112a, and a conductive layer 112b are provided on the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. The conductive layer 112a is provided so as to cover a part of the opening 147a, and the conductive layer 112b is provided so as to cover a part of the opening 147b. The conductive layer 112a has a region that contacts the upper surface of the semiconductor layer 108 within the opening 147a, and the conductive layer 112b has a region that contacts the upper surface of the semiconductor layer 108 within the opening 147b. The semiconductor layer 108 is electrically connected to the conductive layer 112a and the conductive layer 112b, respectively. The same material can be used for the conductive layer 104, the conductive layer 112a, and the conductive layer 112b. Furthermore, the conductive layer 104, the conductive layer 112a, and the conductive layer 112b can each be formed in the same process. For example, by forming films that will become conductive layer 104, conductive layer 112a, and conductive layer 112b, and then processing the films, conductive layer 104, conductive layer 112a, and conductive layer 112b can be formed, respectively.

[0135] The portion of the semiconductor layer 108 that overlaps with the conductive layer 104 functions as the channel formation region of the transistor 100. The semiconductor layer 108 has a pair of regions 108L that sandwich the channel formation region, and a pair of regions 108D outside of that.

[0136] The region of semiconductor layer 108 in contact with conductive layer 112a functions as either the source region or the drain region of transistor 100, and the region of semiconductor layer 108 in contact with conductive layer 112b functions as the other source region or drain region of transistor 100. The source region and drain region are regions with lower electrical resistance compared to the channel formation region. The source region and drain region can also be described as regions with higher carrier concentration and higher oxygen vacancy density compared to the channel formation region.

[0137] Regions 108L and 108D each contain impurity elements. These impurity elements may include one or more of the following: hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of the following impurity elements: boron, phosphorus, aluminum, magnesium, and silicon.

[0138] Using conductive layers 104, 112a, and 112b as masks, impurity elements are supplied (also called added or implanted) to the semiconductor layer 108. As a result, region 108D is formed in the semiconductor layer 108 in a region that does not overlap with conductive layers 104, 112a, 112b, or the insulating layer 106, and region 108L is formed in a region that does not overlap with conductive layers 104, 112a, or 112b, but overlaps with the insulating layer 106.

[0139] Of the semiconductor layer 108, the region in contact with the conductive layer 112a and the region 108D adjacent to that region function as either a source region or a drain region. Of the semiconductor layer 108, the region in contact with the conductive layer 112b and the region 108D adjacent to that region function as either a source region or a drain region.

[0140] Transistor 100 is a planar transistor in which conductive layers 112a and 112b are arranged on the same plane. It is also a so-called top-gate transistor, having a gate electrode above the semiconductor layer 108. For example, by supplying impurity elements to the semiconductor layer 108 using the conductive layer 104, which functions as the gate electrode, as a mask, a region 108D that functions as the source region and drain region can be formed in a self-aligned manner. Transistor 100 can be called a TGSA (Top Gate Self-Aligned) type transistor.

[0141] The channel length of transistor 100 can be controlled by the length of the conductive layer 104. Therefore, the channel length of transistor 100 is greater than or equal to the minimum dimensions of the exposure apparatus used to fabricate the transistor. By increasing the channel length, a transistor with high saturation can be made.

[0142] In this specification, the term "high saturation" may be used to describe a transistor's drain current (Id)-drain voltage (Vd) characteristics where the change in current in the saturation region is small.

[0143] It is preferable to use a metal oxide exhibiting semiconductor properties for the semiconductor layer 108 (mainly the channel formation region). Transistors using metal oxides (hereinafter referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have remarkably low off-currents and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, the power consumption of semiconductor devices can be reduced by applying OS transistors. When a metal oxide is used for the semiconductor layer, the semiconductor layer can be called an oxide semiconductor layer or a metal oxide layer.

[0144] It is particularly preferable to use the aforementioned indium oxide for the semiconductor layer 108. By using indium oxide for the semiconductor layer 108, a high-performance transistor that achieves both a large on-current and a small off-current can be realized. Furthermore, impurities can be included in the metal oxide as dopants.

[0145] The metal oxide used in the semiconductor layer 108 is preferably either a polycrystalline semiconductor or a single-crystal semiconductor. Using a polycrystalline or single-crystal semiconductor allows for the realization of a transistor with higher field-effect mobility and larger on-current compared to using an amorphous semiconductor. It is also preferable because it can suppress the degradation of transistor characteristics.

[0146] The band gap of the metal oxide used in the semiconductor layer 108 is preferably 2.0 eV or higher, and more preferably 2.5 eV or higher.

[0147] For evaluating the band gap of metal oxides, optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS, or ESCA: Electron Spectrometry for Chemical Analysis), or X-ray absorption fine structure (XAFS) can be used. Furthermore, multiple methods can be combined for analysis. The electron affinity or energy at the bottom of the conduction band can be determined from the ionization potential (the difference between the vacuum level and the energy at the top of the valence band) and the band gap. For evaluating the ionization potential, for example, ultraviolet photoelectron spectroscopy (UPS) can be used.

[0148] As described in <Method for Fabricating the Indium Oxide Layer>, the semiconductor layer 108 is formed when a second amorphous film 108a2, deposited on the seed crystal layer 108s, undergoes a second heat treatment to grow crystals in a crystal orientation that reflects the crystal structure of the seed crystal layer 108s. Furthermore, the semiconductor layer 108 is composed of crystal grains that have grown laterally starting from the seed crystal layer 108s. Therefore, for example, the presence of the seed crystal layer 108s can potentially be confirmed by observing the vicinity of the center of the crystal grain in a plan view using TEM observation or the like.

[0149] As the insulating layer 110, either an inorganic insulating layer or an organic insulating layer, or both, can be used. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. Preferably, the insulating layer 110 has one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0150] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0151] The insulating layer 110 has a region that is in contact with the semiconductor layer 108. In the semiconductor layer 108, a portion of the region in contact with the insulating layer 110 can function as a channel formation region. Therefore, when a metal oxide is used for the semiconductor layer 108, it is preferable that the insulating layer 110 contains oxygen. This improves the interface characteristics between the semiconductor layer 108 and the insulating layer 110. Furthermore, it is even more preferable to use a film that releases oxygen when heated for the insulating layer 110. The heat applied during the manufacturing process of the transistor 100 causes the insulating layer 110 to release oxygen, thereby supplying oxygen to the semiconductor layer 108. By supplying oxygen from the insulating layer 110 to the semiconductor layer 108, particularly to the channel formation region, oxygen deficiency (V) can be reduced. O ) is repaired, and oxygen deficiency (V OThis can reduce the noise. Therefore, a transistor 100 can be made that exhibits good electrical characteristics and is highly reliable. One or more of the above-mentioned oxides and oxiditrides can be suitably used for the insulating layer 110. Specifically, the insulating layer 110 preferably has silicon and oxygen, and one or both of silicon oxide and silicon oxiditride can be suitably used.

[0152] For example, oxygen can be supplied to the insulating layer 110 by heat treatment in an oxygen-containing atmosphere or by plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110 by forming an oxide film on its upper surface in an oxygen-containing atmosphere using a sputtering method. The oxide film can then be removed. The method for supplying oxygen to the insulating layer 110 will be explained in <Example of Transistor Fabrication Method>.

[0153] In the insulating layer 110, it is preferable that substances (e.g., atoms, molecules, and ions) diffuse easily. It is also preferable that the diffusion coefficient of substances in the insulating layer 110 is large. In particular, it is preferable that oxygen diffuses easily in the insulating layer 110. That is, it is preferable that the diffusion coefficient of oxygen in the insulating layer 110 is large. The oxygen contained in the insulating layer 110 diffuses through the insulating layer 110 and is supplied to the semiconductor layer 108 through the interface between the insulating layer 110 and the semiconductor layer 108. By making the insulating layer 110 such that oxygen diffuses easily, the oxygen contained in the insulating layer can be efficiently supplied to the semiconductor layer 108 (especially the channel formation region).

[0154] Although Figure 6(B), etc., shows the insulating layer 110 as a single-layer structure, this is not limited to this, and it can also be a laminated structure of two or more layers. For example, if the insulating layer 110 is a two-layer laminated structure consisting of a first insulating layer and a second insulating layer provided on the first insulating layer, it is preferable to use an insulating material that contains oxygen and releases oxygen when heated in at least the second insulating layer (i.e., the insulating layer on the side in contact with the semiconductor layer 108). This allows the oxygen contained in the second insulating layer to be supplied to the semiconductor layer 108 (mainly the channel formation region).

[0155] On the other hand, it is preferable to use an insulating material that is not easily permeable to substances for the first insulating layer. That is, it is preferable that the first insulating layer functions as a barrier film. This makes it possible to suppress the diffusion of impurities into the insulating layer 110 from the layer below the insulating layer 110 (the substrate 102 side) and the diffusion of such impurities into the semiconductor layer 108. In addition, it is possible to suppress the diffusion of oxygen contained in the second insulating layer to the substrate 102 side, which would reduce the amount of oxygen supplied to the semiconductor layer 108.

[0156] In this specification, the term "barrier film" refers to a film that possesses barrier properties. Barrier properties refer to one or both of the following functions: the function of suppressing the diffusion of a target substance (also known as low permeability), and the function of capturing or fixing the substance (also known as gettering). For example, an insulating layer that possesses barrier properties can be called a barrier insulating layer.

[0157] Next, the channel length and channel width of transistor 100 will be explained using Figures 6(A) to 6(C). Here, the portion of semiconductor layer 108 that overlaps with conductive layer 104 will be described as the channel formation region.

[0158] The channel length of transistor 100 is the length of the region where the semiconductor layer 108 and the conductive layer 104 overlap between a pair of regions 108D. In Figures 6(A) and 6(B), the channel length L100 of transistor 100 is indicated by a dashed double arrow. The channel length L100 of transistor 100 is determined by the length of the conductive layer 104 (length in the direction parallel to the dashed line A1-A2) and is greater than or equal to the minimum dimensions of the exposure apparatus used to manufacture the transistor. For example, the channel length L100 can be 1.5 μm or more. By increasing the channel length, a transistor with high saturation can be made.

[0159] The channel width of transistor 100 is the width of the overlapping region of semiconductor layer 108 and conductive layer 104 in a direction perpendicular to the channel length direction (parallel to the dashed line B1-B2) in a plan view. In Figures 6(A) and 6(C), the channel width W100 of transistor 100 is indicated by a double-headed arrow on the dashed line.

[0160] As shown in Figures 6(A) and 6(C), it is preferable that the conductive layer 104 protrudes outward from the edge of the semiconductor layer 108 in the channel width direction of the transistor 100. In this case, as shown in Figure 6(C), the entire channel width direction of the semiconductor layer 108 is covered by the conductive layer 104 via the insulating layer 106. With this configuration, the semiconductor layer 108 can be electrically surrounded by the electric field from the conductive layer 104.

[0161] In semiconductor layer 108, region 108D is a region with lower electrical resistance compared to the channel formation region. Region 108D can also be described as a region with a higher carrier concentration, higher oxygen vacancy density, and higher impurity concentration compared to the channel formation region.

[0162] Region 108L is a region with electrical resistance similar to or lower than that of the channel-forming region. Region 108L can also be described as a region with carrier concentration similar to or higher than that of the channel-forming region, oxygen deficiency density similar to or higher than that of the channel-forming region, and impurity concentration similar to or higher than that of the channel-forming region. Furthermore, region 108L is a region with electrical resistance similar to or higher than that of region 108D. Region 108L can also be described as a region with carrier concentration similar to or lower than that of region 108D, oxygen deficiency density similar to or lower than that of the channel-forming region, and impurity concentration similar to or lower than that of the channel-forming region.

[0163] Region 108L functions as a buffer region to mitigate the drain electric field. Since region 108L does not overlap with the conductive layer 104, it is a region where almost no channel is formed even when a gate voltage is applied to the conductive layer 104. It is preferable that the carrier concentration in region 108L is higher than that of the channel formation region. This allows region 108L to function as an LDD (Lightly Doped Drain) region. By providing region 108L, which functions as an LDD region, between the channel formation region and region 108D, a transistor 100 with a high drain breakdown voltage can be realized.

[0164] Preferably, the carrier concentration in the semiconductor layer 108 has a distribution such that it is lowest in the channel formation region, and increases in the order of region 108L and region 108D. By providing region 108L between the channel formation region and region 108D, the carrier concentration in the channel formation region can be kept extremely low, even if impurities such as hydrogen diffuse from region 108D during the manufacturing process.

[0165] Furthermore, the carrier concentration in region 108L is not uniform, and there may be a gradient where the carrier concentration decreases from region 108D towards the channel formation region. For example, the hydrogen concentration or oxygen deficiency (V) in region 108L O The concentration of either or both of the following can be configured to have a gradient such that the concentration decreases from the region 108D side to the channel formation region side.

[0166] It is preferable that a portion of the conductive layer 112a and conductive layer 112b are located inside the openings 147a and 147b, respectively, as shown in Figure 6(B), etc. In other words, it is preferable that a portion of the conductive layer 112a has a region in contact with the semiconductor layer 108 inside the opening 147a, and a portion of the conductive layer 112b has a region in contact with the semiconductor layer 108 inside the opening 147b. This allows the region of the semiconductor layer 108 in contact with the conductive layer 112a to be adjacent to one of the pair of regions 108D, and similarly, the region of the semiconductor layer 108 in contact with the conductive layer 112b to be adjacent to the other of the pair of regions 108D. The region of the semiconductor layer 108 in contact with the conductive layer 112a, and one of the pair of regions 108D, function as either the source region or the drain region of the transistor 100. The region of the semiconductor layer 108 that is in contact with the conductive layer 112b, and the other of the pair of regions 108D, function as the source region or the other drain region of the transistor 100.

[0167] The top shapes of openings 147a and 147b are not particularly limited. While Figure 6(A) and others show openings 147a and 147b having rounded corners, the present invention is not limited to this configuration. The top shapes of openings 147a and 147b can be, for example, circular, elliptical, triangular, quadrilateral (including rectangles, rhombuses, and squares), pentagonal, or polygons with rounded corners. The polygons can be concave polygons (polygons with at least one interior angle exceeding 180 degrees) or convex polygons (polygons with all interior angles 180 degrees or less). In this specification, "circular" is not limited to a perfect circle.

[0168] Here, a configuration is shown in which conductive layers 112a and 112b are formed in the same process as conductive layer 104, but the present invention is not limited to this. Conductive layers 112a and 112b can be formed in a different process than conductive layer 104. For example, a conductive layer 104 is formed on an insulating layer 106, and impurity elements are supplied to the semiconductor layer 108 using the conductive layer 104 as a mask to form a source region and a drain region. Next, openings reaching the source region and openings reaching the drain region are formed in the insulating layer 106, and conductive layers 112a and 112b can be formed to cover these openings.

[0169] While Figure 6(B) and other figures show an example where the thickness of the semiconductor layer 108 is uniform regardless of location, the present invention is not limited to this. The semiconductor layer 108 can be configured to have different thicknesses in the region that overlaps with the insulating layer 106 and in the region that does not overlap. For example, when forming the openings 147a and 147b, a portion of the semiconductor layer 108 is removed, which may result in the thickness of the region of the semiconductor layer 108 that does not overlap with the insulating layer 106 being thinner than the thickness of the overlapping region. Alternatively, the semiconductor layer 108 can be configured to have different thicknesses in the region that overlaps with the insulating layer 106, the conductive layer 112a, and the conductive layer 112b, and in the region that does not overlap with any of these. For example, when forming conductive layers 112a and 112b, a portion of the semiconductor layer 108 may be removed, resulting in the thickness of the region of the semiconductor layer 108 that does not overlap with the insulating layer 106, conductive layer 112a, or conductive layer 112b being thinner than the thickness of the region that overlaps with any of these. Alternatively, the semiconductor layer 108 can be configured to have different thicknesses in the region that overlaps with the insulating layer 106, the region that overlaps with any of the insulating layer 106, conductive layer 112a, or conductive layer 112b, and the region that does not overlap with any of these.

[0170] The metal oxide used in semiconductor layer 108 has oxygen vacancies (V) in the channel formation region. O A defect in which hydrogen has entered (hereinafter referred to as V O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. In this way, V OTo obtain a metal oxide with sufficiently reduced H content, impurities such as water and hydrogen must be removed from the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment), and oxygen must be supplied to the metal oxide to create an oxygen deficiency (V). O It is important to repair ). O By using metal oxides with sufficiently reduced impurities such as H in the channel formation region of a transistor, stable electrical characteristics can be provided. Furthermore, by supplying oxygen to the metal oxide, oxygen deficiencies (V) can be reduced. O The process of repairing ) is sometimes referred to as oxygenation treatment.

[0171] The metal oxide used in semiconductor layer 108 has a carrier concentration of 1 × 10 in the channel formation region. 18 cm -3 The following is preferable: 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3 It is even more preferable that it be less than . There is no limit to the lower limit of the carrier concentration in the channel formation region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0172] OS transistors exhibit minimal fluctuations in electrical properties due to radiation exposure, meaning they have high radiation resistance, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors are suitable for use in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors are suitable for use in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, protons, and neutrons).

[0173] The following describes materials that can be used for each component of the transistor 100, other than the semiconductor layer 108 and insulating layer 110 mentioned above.

[0174] [Conductive layer 112a, conductive layer 112b, conductive layer 104] The conductive layers 112a, 112b, and 104 can each be a single-layer or multi-layer structure. Materials that can be used for the conductive layers 112a, 112b, and 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys comprising one or more of the aforementioned metals. Conductive materials with low electrical resistivity, each containing one or more of copper, silver, gold, and aluminum, can be suitably used for the conductive layers 112a, 112b, and 104. Copper or aluminum are particularly preferred due to their excellent mass-productivity.

[0175] Conductive layers 112a, 112b, and 104 can each be made of a conductive metal oxide (oxide conductor). Examples of oxide conductors (OC) include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called silicon-containing ITO or ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide. Oxide conductors containing indium are particularly preferred due to their high conductivity.

[0176] Oxygen vacancies (V) in metal oxides with semiconductor properties O ) forms the oxygen deficiency (V O When hydrogen is added to a metal oxide, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0177] The conductive layers 112a, 112b, and 104 can each have a laminated structure consisting of a conductive film containing the aforementioned oxide conductor and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0178] A Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be applied to conductive layers 112a, 112b, and 104, respectively. Using a Cu-X alloy film allows for processing by wet etching, thus reducing manufacturing costs.

[0179] The conductive layers 112a, 112b, and 104 can be made of the same material, or some or all of them can be made of different materials.

[0180] The conductive layer 112a and the conductive layer 112b each have a region that is in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, if easily oxidized metals (e.g., aluminum) are used for both the conductive layer 112a and the conductive layer 112b, insulating oxides (e.g., aluminum oxide) may form between the conductive layer 112a and the semiconductor layer 108, and between the conductive layer 112b and the semiconductor layer 108, potentially hindering conductivity. Therefore, it is preferable to use conductive materials that are resistant to oxidation, conductive materials that maintain low electrical resistance even when oxidized, or oxide conductive materials for the conductive layer 112a and the conductive layer 112b, respectively.

[0181] For conductive layers 112a and 112b, it is preferable to use materials such as titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel, respectively. These are preferred because they are conductive materials that are resistant to oxidation, or materials that maintain low electrical resistance even when oxidized.

[0182] The conductive layer 112a and the conductive layer 112b can each be made from the aforementioned oxide conductors. Specifically, metal oxides such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, silicon-containing In-Sn oxide, and gallium-doped zinc oxide can be used.

[0183] A nitride conductor can be used for the conductive layer 112a and the conductive layer 112b, respectively. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0184] The conductive layer 112a, conductive layer 112b, and conductive layer 104 can each have a laminated structure. When conductive layer 112a and conductive layer 112b each have a laminated structure, it is preferable to use an oxidation-resistant conductive material for at least the layer of conductive layer 112a and conductive layer 112b that is in contact with the semiconductor layer 108.

[0185] [Insulating layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made from materials that can be used for the insulating layer 110.

[0186] The insulating layer 106 has regions that are in contact with each of the semiconductor layer 108, conductive layer 112a, conductive layer 112b, conductive layer 104, and insulating layer 110. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least one of the aforementioned oxides and oxiditrides is used for the film constituting the insulating layer 106 that is in contact with the semiconductor layer 108. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxiditride, or aluminum oxide can be suitably used for the insulating layer 106.

[0187] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxidized nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxidized nitrides having silicon and hafnium, and nitrides having silicon and hafnium. In addition, a material that can exhibit ferroelectricity can be used as the gate insulating layer. Examples of materials that can exhibit ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO X Examples of metal oxides include (where X is a real number greater than 0). Also, as a material that may possess ferroelectric properties, examples include materials obtained by adding element J1 (where element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. For example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be 1:1 or close to it. Furthermore, as a material that may possess ferroelectric properties, examples include materials obtained by adding element J2 (where element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. For example, the ratio of the number of zirconium atoms to the number of element J2 atoms can be 1:1 or close to it. Also, as a material that may possess ferroelectric properties, examples include lead titanate (PbTiO2). X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, can be used.

[0188] In Figure 6(B), etc., the insulating layer 106 is shown as a single-layer structure, but the present invention is not limited to this. The insulating layer 106 can be a laminated structure.

[0189] [Circuit board 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or organic resin substrates can be used as the substrate 102. Furthermore, the substrate 102 can be configured to have semiconductor elements on it. The shape of the semiconductor substrate and the insulating substrate can be circular or rectangular.

[0190] A flexible substrate can be used as the substrate 102, and transistors 100, etc., can be formed directly on the flexible substrate. Alternatively, for example, a release layer can be provided between the substrate 102 and the transistors 100, etc. By providing a release layer, after partially or completely completing the semiconductor device on it, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0191] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, and does not concern itself with elasticity or the ability to restore to its original shape.

[0192] For example, flexible electronic devices can deform in response to external forces. Flexible electronic devices can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Similarly, flexible display devices (also called flexible display devices, flexible display devices, flexible displays, etc.) can deform in response to external forces. Flexible display devices can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Furthermore, flexible substrates (also called flexible substrates, flexible substrates, etc.) can deform in response to external forces. Flexible substrates can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Note that "deforms in response to external forces" above means that it can be deformed by an average adult's hand without requiring excessive force. Note that flexibility can be quantified as the deformation of an object in response to an external force using testing machines capable of measuring stress-strain (tensile testing machines, compression testing machines, etc.).

[0193] Furthermore, in this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may also have parts that are not flexible (also called rigid parts).

[0194] Furthermore, in this specification, a highly flexible object is defined as the object that deforms more when two objects are deformed with the same external force. Also, when a first part and a second part of an object are deformed with the same external force, the part that deforms more is considered to be the highly flexible part.

[0195] The following describes an example of a transistor configuration different from the aforementioned transistor 100, to which the metal oxide layer according to one aspect of the present invention can be applied. Note that in the following, parts that overlap with the aforementioned transistor 100 may be omitted from the explanation. Furthermore, in the drawings shown below, parts having the same function as the aforementioned transistor 100 may have the same hatching pattern and may not be denoted by reference numerals.

[0196] <Example of transistor configuration 2> Figure 7(A) shows a plan view of transistor 100A. Figure 7(B) shows a cross-sectional view along the dashed line A1-A2 shown in Figure 7(A). Figure 8(A) shows a cross-sectional view along the dashed line B1-B2 shown in Figure 7(A). Figure 8(B) shows a perspective view of a portion of transistor 100A that has been cut out. Note that in Figure 7(A), some components of transistor 100A (such as the insulating layer) are omitted.

[0197] Transistor 100A differs from the planar transistor 100 described in <Transistor Configuration Example 1> in that it is a vertical transistor in which the source electrode and drain electrode are arranged at different heights. Furthermore, it differs from the insulating layer 110 in contact with the channel formation region of transistor 100 in that the insulating layer 110 in contact with the channel formation region of transistor 100A has a multilayer structure.

[0198] The transistor 100A is provided on a substrate 102. The transistor 100A has a conductive layer 104, an insulating layer 106, a conductive layer 112a, a conductive layer 112b, and a semiconductor layer 108. The conductive layer 104 functions as a gate electrode. A part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as either a source electrode or a drain electrode. The conductive layer 112b functions as either a source electrode or a drain electrode. Of the semiconductor layer 108, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region. In addition, of the semiconductor layer 108, the region between the source region and the drain region functions as a channel forming region. That is, of the semiconductor layer 108, the entire region between the source region and the drain region that overlaps with the gate electrode via the gate insulating layer can function as a channel forming region.

[0199] The detailed configuration of transistor 100A will be explained.

[0200] A conductive layer 112a is provided on the substrate 102. An insulating layer 110a is provided on the conductive layer 112a and on the substrate 102. An insulating layer 110b is provided on the insulating layer 110a. An insulating layer 110c is provided on the insulating layer 110b. A conductive layer 112b is provided on the insulating layer 110c. Note that insulating layers 110a, 110b, and 110 are sometimes collectively referred to as insulating layer 110.

[0201] The conductive layer 112a, the insulating layer 110, and the conductive layer 112b have overlapping regions. In these regions, the insulating layer 110 is provided so as to be sandwiched between the conductive layer 112a and the conductive layer 112b.

[0202] The insulating layer 110 and the conductive layer 112b have openings 143 that reach the conductive layer 112a. The openings 143 are provided to have regions that overlap with the conductive layer 112a and the conductive layer 112b, respectively.

[0203] A semiconductor layer 108 is provided in contact with the upper surface of the conductive layer 112a, the side surface of the insulating layer 110, the side surface of the conductive layer 112b, and the upper surface of the conductive layer 112b within the opening 143. The semiconductor layer 108 is provided such that, in a plan view, it has a region that overlaps with the opening 143.

[0204] Here, it is preferable that the insulating layer 110b is an insulating layer containing oxygen. Furthermore, it is preferable that it is an insulating layer that releases oxygen upon heating. That is, it is preferable to apply an insulating material to the insulating layer 110 that can be used for the insulating layer 110 described in <Transistor Configuration Example 1>. This allows, for example, when a metal oxide is used for the semiconductor layer 108, the oxygen contained in the insulating layer 110b to be supplied to the metal oxide. This allows oxygen deficiencies in the metal oxide to be repaired, thereby improving the electrical characteristics and reliability of the transistor 100A.

[0205] On the other hand, it is preferable that insulating layers 110a and 110c are insulating layers that have barrier properties against gases such as oxygen and hydrogen. This makes it possible to suppress the release of oxygen contained in insulating layer 110b to the outside through insulating layer 110a or insulating layer 110c.

[0206] Materials with a higher nitrogen content than insulating layer 110b can be used for insulating layers 110a and 110c. Increasing the nitrogen content of the insulating layers can improve the barrier properties against oxygen and hydrogen.

[0207] Furthermore, insulating layers 110a and 110c may have regions where the hydrogen concentration in the film is lower than that of insulating layer 110b.

[0208] The film density of insulating layer 110a and insulating layer 110c is preferably higher than the film density of insulating layer 110b. By increasing the film density of the insulating layer, the barrier properties against oxygen and hydrogen can be improved.

[0209] For example, when silicon oxide or silicon oxide nitride is used for the insulating layer 110b, silicon nitride or silicon oxide nitride can be used for the insulating layer 110a and insulating layer 110c, respectively. Furthermore, hafnium oxide or aluminum oxide can be suitably used as the insulating layer 110a and insulating layer 110c.

[0210] Furthermore, the insulating layer 110a and insulating layer 110c can be constructed by laminating two or more materials selected from silicon nitride, silicon oxide nitride, hafnium oxide, and aluminum oxide, respectively.

[0211] An insulating layer 106 is provided on the semiconductor layer 108. The insulating layer 106 has a region that is in contact with the upper surface of the semiconductor layer 108.

[0212] A conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 has a region that is in contact with the upper surface of the insulating layer 106.

[0213] The semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are each provided so as to have a region that overlaps with the opening 143.

[0214] As shown in Figure 7(B), etc., one surface of the semiconductor layer 108 inside the opening 143 has a region that faces the conductive layer 104 via the insulating layer 106. The other surface of the semiconductor layer 108 inside the opening 143 has a region that contacts the upper surface of the conductive layer 112a, a region that contacts the side surface of the insulating layer 110, and a region that contacts the side surface of the conductive layer 112b. On the outside of the opening 143, the other surface of the semiconductor layer 108 has a region that contacts the upper surface of the conductive layer 112b.

[0215] In transistor 100A, the source electrode and drain electrode are positioned at different heights relative to the surface of the substrate 102, and the drain current flows perpendicular to, or approximately perpendicular to, the surface of the substrate 102. In transistor 100A, it can also be said that the drain current flows in the vertical direction, or approximately vertical direction. Therefore, transistor 100A can be called a vertical transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).

[0216] Because transistor 100A allows the source and drain electrodes to be mounted on top of each other, it is possible to miniaturize the transistor compared to a planar transistor and significantly reduce the area occupied by the transistor on the substrate.

[0217] The top surface shape of the opening 143 can be, for example, circular or elliptical. The top surface shape of the opening 143 can also be a polygon such as a triangle, quadrilateral (including rectangle, rhombus, and square), or pentagon, or a polygon with rounded corners. As shown in Figure 7(A), the top surface shape of the opening 143 is preferably circular. By making the top surface shape of the opening 143 circular, the processing accuracy when forming the opening 143 can be improved, and a fine-sized opening 143 can be formed. In this specification, the term "circular" is not limited to a perfect circle.

[0218] The channel length and channel width of transistor 100A will be described.

[0219] In the semiconductor layer 108, the region in contact with the conductive layer 112a functions as either a source region or a drain region, the region in contact with the conductive layer 112b functions as either a source region or a drain region, and the region between the source region and the drain region functions as a channel-forming region.

[0220] The channel length of a transistor is the distance between the source region and the drain region. In Figures 7(B) and 8(A), the channel length L100A of transistor 100A is shown by a dashed double arrow. In Figures 7(B) and 8(A), the distance along the semiconductor layer 108 between the upper surface of conductive layer 112a and the upper surface of conductive layer 112b is shown as the channel length L100A of transistor 100A.

[0221] In some cases, the channel length L100A of transistor 100A may be defined as the sum of the thicknesses of insulating layer 110a, insulating layer 110b, and insulating layer 110c in the region sandwiched between the upper surface of conductive layer 112a and the lower surface of conductive layer 112b (in Figures 7(B) and 8(A), the thickness T110 is indicated by a dashed double arrow). Alternatively, the channel length L100A of transistor 100A may be defined as the sum of the thickness T110 and the thickness of conductive layer 112b.

[0222] Here, the channel length L100A of transistor 100A is determined by the respective thicknesses of the insulating layers 110a, 110b, 110c, and 112b, or by the angle θ110 between the surface of the semiconductor layer 108 within the opening 143 (here, the respective sides of the insulating layers 110a, 110b, 110c, and 112b) and the surface of the insulating layer 110a (here, the top surface of the conductive layer 112a), and is not affected by the performance of the exposure apparatus used to fabricate the transistor. Therefore, the channel length L100A can be set to a value smaller than the limiting resolution of the exposure apparatus, making it possible to realize transistors of a very small size.

[0223] The channel length L100A can be, for example, 5 nm to less than 3 μm, 7 nm to 2.5 μm, 10 nm to 2 μm, 10 nm to 1.5 μm, 10 nm to 1.2 μm, 10 nm to 1 μm, 10 nm to 500 nm, 10 nm to 300 nm, 10 nm to 200 nm, 10 nm to 100 nm, 10 nm to 50 nm, 10 nm to 30 nm, or 10 nm to 20 nm. For example, the channel length L100 can also be 100 nm to 1 μm.

[0224] The thickness T110 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0225] The angle θ110 can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less. A smaller angle θ110 is preferable because it can improve the coverage of the layers (semiconductor layer 108, etc.) formed along the side walls of the opening 143 (here, the sides of the insulating layer 110a, insulating layer 110b, insulating layer 110c, and conductive layer 112b). On the other hand, a value of angle θ110 closer to 90 degrees is preferable because it can reduce the area occupied by the transistor on the substrate surface.

[0226] By shortening the channel length L100A, the on-current of transistor 100A can be increased. For example, by using transistor 100A in semiconductor devices such as display devices and memory devices, it is possible to create circuits that can operate at high speeds. Furthermore, it becomes possible to reduce the circuit's footprint. Therefore, by applying transistor 100A to semiconductor devices such as display devices and memory devices, miniaturization of such semiconductor devices can be achieved.

[0227] For example, by applying transistor 100A to a display device, the bezel of the display device can be narrowed. Also, for example, when applying transistor 100A to a large display device or a high-definition display device, even if the number of wires increases, the signal delay in each wire can be reduced, and display unevenness can be suppressed.

[0228] The channel width of transistor 100A is the length of the source region or the drain region in a plan view (Figure 7(A)). In other words, the channel width of transistor 100A is the length of the region where semiconductor layer 108 and conductive layer 112a are in contact, or the length of the region where semiconductor layer 108 and conductive layer 112b are in contact, in a plan view. Alternatively, the channel width of transistor 100A may be an intermediate value between the length of the region where semiconductor layer 108 and conductive layer 112a are in contact and the length of the region where semiconductor layer 108 and conductive layer 112b are in contact, in a plan view.

[0229] Here, the channel width of transistor 100A is described as the perimeter length of the region where the semiconductor layer 108 and the conductive layer 112b are in contact, in a plan view. In Figures 7(A), 7(B), and 8(A), the channel width W100 of transistor 100A is shown by a solid double arrow. The channel width W100 can also be described as the perimeter length of the opening 143 in a plan view.

[0230] The channel width W100 is determined by the top surface shape of the aperture 143, etc. In Figures 7(A), 7(B), and 8(A), the width D143 of the aperture 143 is indicated by a double-headed arrow. The width D143 refers to the shortest side of the smallest rectangle that circumscribes the aperture 143 in a plan view. When the aperture 143 is formed using photolithography, the width D143 of the aperture 143 will be greater than or equal to the limiting resolution of the exposure device. For example, the width D143 is between 0.20 μm and less than 5.0 μm. If the top surface shape of the aperture 143 is circular, the width D143 corresponds to the diameter of the aperture 143, and the channel width W100 can be calculated as "D143 × π".

[0231] Regarding transistor 100A, in addition to the explanation above, you can refer to the explanation regarding transistor 100 in <Transistor Configuration Example 1>.

[0232] <Transistor Configuration Example 3> Figure 9(A) shows a plan view of transistor 100B. Figure 9(B) shows a cross-sectional view along the dashed line A1-A2 shown in Figure 9(A). Figure 9(C) shows a cross-sectional view along the dashed line B1-B2 shown in Figure 9(A). Note that some components of transistor 100B (such as the insulating layer) are omitted in Figure 9(A).

[0233] Transistor 100B is a vertical transistor, similar to transistor 100A. However, while transistor 100A has a semiconductor layer 108 along the openings 143 formed in the insulating layer 110 and the conductive layer 112b, transistor 100B differs in that the semiconductor layer 108 is provided along the sides of the island-shaped insulating layer 110 and conductive layer 112b.

[0234] Transistor 100B is provided on an insulating layer 109 provided on substrate 102.

[0235] Transistor 100B has a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode, and a part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode or a drain electrode, and the conductive layer 112b functions as the other of the source electrode or the drain electrode. In the semiconductor layer 108, a region overlapping the gate electrode through the gate insulating layer between the source electrode and the drain electrode functions as a channel formation region. Also, in the semiconductor layer 108, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0236] Perspective views of a structure including the transistor 100B are shown in FIGS. 10(A) to 10(C). FIG. 10(A) is a perspective view of the structure. Note that some insulating layers (insulating layer 110 and insulating layer 106) are made transparent, and only the outlines are shown by dashed lines. FIG. 10(B) is a perspective view obtained by omitting the conductive layer 104 and the insulating layer 106 from the perspective view shown in FIG. 10(A). FIG. 10(C) is a perspective view obtained by omitting the semiconductor layer 108 and the conductive layer 112b from the perspective view shown in FIG. 10(B). Note that in the perspective view shown in FIG. 10(C), the outline of the insulating layer 110 is shown by a solid line.

[0237] The conductive layer 112a is provided on the insulating layer 109. The insulating layer 110 is provided on the conductive layer 112a and on the insulating layer 109 so as to have a region overlapping the conductive layer 112a. The conductive layer 112b is provided on the insulating layer 110. The conductive layer 112a has a region in contact with the insulating layer 109. The insulating layer 110 is in contact with each of the conductive layer 112a and the conductive layer 112b and has a region sandwiched therebetween. The conductive layer 112a has a region overlapping the conductive layer 112b through the insulating layer 110.

[0238] As shown in FIG. 9(B), the conductive layer 112a has a region where the insulating layer 110 is provided and a region where the insulating layer 110 is not provided. Also, the side surface of the insulating layer 110 is located in a region overlapping the conductive layer 112a.

[0239] The semiconductor layer 108 is provided on the conductive layer 112a, on the conductive layer 112b, and on the insulating layer 110. The semiconductor layer 108 has regions that contact the upper surface and the side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the upper surface of the conductive layer 112a. The semiconductor layer 108 is connected to the conductive layer 112a and is connected to the conductive layer 112b. The semiconductor layer 108 has a shape along the shapes of the upper surface and the side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the upper surface of the conductive layer 112a. The semiconductor layer 108 is provided across a region where the insulating layer 110 is provided on the conductive layer 112a and a region where the insulating layer 110 is not provided on the conductive layer 112a.

[0240] The semiconductor layer 108 has a first region that contacts the conductive layer 112a, a second region that contacts the side surface of the insulating layer 110, and a third region that contacts the conductive layer 112b. The first region contacts the second region, and the second region contacts the third region. It can also be said that the first region is continuous with the second region and the second region is continuous with the third region. The first region functions as one of the source region or the drain region, and the third region functions as the other of the source region or the drain region. The channel formation region is located in the second region.

[0241] Also, as shown in FIG. 9(C), the insulating layer 110 has a side surface that does not contact the semiconductor layer 108. This side surface contacts the insulating layer 106. That is, it can be said that the insulating layer 110 has a side surface that contacts the semiconductor layer 108 and the insulating layer 106 in a cross section along the dashed line A1 - A2, and has a side surface that contacts the insulating layer 106 in a cross section along the dashed line B1 - B2.

[0242] The insulating layer 106 that functions as the gate insulating layer of the transistor 100B is provided so as to cover the semiconductor layer 108. The insulating layer 106 has regions that contact the upper surface and the side surface of the semiconductor layer 108 and the side surface of the insulating layer 110. Also, the insulating layer 106 has regions that contact the upper surface and the side surface of the conductive layer 112a, the upper surface and the side surface of the conductive layer 112b, and the upper surface of the insulating layer 109.

[0243] The conductive layer 104, which functions as the gate electrode of transistor 100B, is provided on the insulating layer 106 and has a region in contact with the upper surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. Furthermore, the conductive layer 104 has a region that faces the side surface of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108. The conductive layer 104 is provided such that at least the region in contact with the side surface of the insulating layer 110 is covered by the semiconductor layer 108. This allows the region to function as the channel formation region of transistor 100B.

[0244] It is preferable that the conductive layer 104 covers the entire semiconductor layer 108. As shown in Figure 9(A), it is preferable that the conductive layer 104 encompasses the semiconductor layer 108 in a plan view. By covering the semiconductor layer 108 with the conductive layer 104, damage to the semiconductor layer 108 when a layer is formed on the transistor 100B can be suppressed. This makes it possible to realize a transistor 100B that exhibits good electrical characteristics and is highly reliable. It is also possible to have a configuration in which the semiconductor layer 108 has regions that are not covered by the conductive layer 104.

[0245] A step is formed between the region on the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are provided and the region where the insulating layer 110 and the conductive layer 112b are not provided, and the semiconductor layer 108, insulating layer 106, and conductive layer 104 can be provided along this step.

[0246] As mentioned above, transistor 100B, like transistor 100A, is a vertical transistor. Therefore, transistor 100B can achieve the same effect as transistor 100A.

[0247] The insulating layer 109 is provided between the transistor 100B, the insulating layer 110, and the substrate 102. The insulating layer 109 has regions that are in contact with the conductive layer 112a, the insulating layer 110, and the insulating layer 106. The insulating layer 109 can be made from the same materials as those used for the insulating layer 110.

[0248] The insulating layer 109 preferably has barrier properties. It is preferable to use a material for the insulating layer 109 that does not easily allow impurities (e.g., water and hydrogen) contained in the substrate 102 to diffuse. This makes it possible to suppress the diffusion of impurities from the substrate 102 to the transistor 100B.

[0249] The insulating layer 109, which functions as a barrier film, can be made from, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, an aluminum nitride, a silicon nitride, and a silicon nitride oxide. Specifically, the insulating layer 109 can preferably be made from, for example, one or more aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0250] The insulating layer 109 preferably contains impurities (e.g., water and hydrogen) that lower the electrical resistance of the semiconductor layer 108, and is made of a material that releases these impurities through heat treatment or the like. The impurities released from the insulating layer 109 diffuse into the region of the conductive layer 112a that is in contact with the insulating layer 109. Furthermore, the impurities diffused into the conductive layer 112a diffuse into the region of the semiconductor layer 108 that is in contact with the conductive layer 112a, so that region contains impurities, and the electrical resistance of that region can be lowered. In other words, the electrical resistance of either the source region or the drain region can be lowered. Therefore, a transistor with a large on-current can be made, and a semiconductor device that operates at high speed can be made.

[0251] In one aspect of the present invention, since a metal oxide layer is used for the semiconductor layer 108, it is more preferable that the impurities released by the insulating layer 109 contain hydrogen. The hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 108 via the conductive layer 112a, causing the region of the semiconductor layer 108 in contact with the conductive layer 112a to contain hydrogen, thereby increasing the carrier concentration in that region. In other words, the electrical resistance of either the source region or the drain region can be lowered. The insulating layer 109 preferably contains, for example, silicon and hydrogen. Typically, silicon nitride containing hydrogen can be suitably used for the insulating layer 109.

[0252] It is more preferable to use a material for the insulating layer 109 that releases impurities that lower the electrical resistance of the conductive layer 112a. This makes it possible to lower the electrical resistance of the conductive layer 112a.

[0253] The thickness of the insulating layer 109 is preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, more preferably 20 nm to 100 nm, and more preferably 20 nm to 50 nm.

[0254] If the thickness of the insulating layer 109 is too high and the amount of impurities released from the insulating layer 109 becomes too large, the amount of impurities that diffuse into the semiconductor layer 108 will increase, resulting in oxygen vacancies (V) generated by these impurities. O ) and V O The amount of H is repaired by oxygen supplied from the insulating layer 110b, which is the oxygen deficiency (V O ) and V O The amount of H may exceed the amount of other substances. On the other hand, if the thickness of the insulating layer 109 is thin, the amount of impurities that diffuse into the conductive layer 112a and the semiconductor layer 108 will decrease, which may increase the electrical resistance of the conductive layer 112a and the electrical resistance of either the source region or the drain region. By setting the thickness of the insulating layer 109 within the aforementioned range, oxygen vacancies (V) in the channel formation region can be reduced. O ) and V OThis can suppress the increase in H and lower the electrical resistance of the conductive layer 112a, as well as the electrical resistance of either the source region or the drain region. Note that the thickness of the insulating layer 109 is not limited to the aforementioned range.

[0255] The insulating layer 110a has regions that are in contact with the upper surface of the insulating layer 109 and the upper and side surfaces of the conductive layer 112a. This suppresses the diffusion of impurities contained in the insulating layer 109 and the conductive layer 112a into the channel formation region of the semiconductor layer 108 via the insulating layer 110b.

[0256] The insulating layer 109 preferably has a region with a higher hydrogen content than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109.

[0257] Furthermore, impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a and either the source region or the drain region of the semiconductor layer 108. However, at least the region of the semiconductor layer 108 in contact with the insulating layer 110b receives oxygen from the insulating layer 110b, thus preventing oxygen deficiency (V) in the channel formation region. O ) and V O This allows for a reduction in H. This suppresses the shift in the threshold voltage, enabling the realization of a transistor that achieves both a small cutoff current (drain current when the gate voltage is 0V) and a large on-current. Therefore, it becomes possible to realize a semiconductor device that achieves both low power consumption and high performance.

[0258] It is preferable that the insulating layer 109 has a region with a higher hydrogen content than the insulating layer 110a. For example, secondary ion mass spectrometry (SIMS) can be used to analyze the hydrogen content of the insulating layer 110 and the like.

[0259] By varying the film formation conditions of the insulating layer 109 and the insulating layer 110a respectively, the amount of hydrogen released can be adjusted. Specifically, for the insulating layer 109 and the insulating layer 110a, any one or more of the film formation power (film formation power density) at the time of formation, the film formation pressure, the film formation gas species, the film formation gas flow rate ratio, the film formation temperature, and the distance between the substrate and the electrode can be made different from each other. For example, by making the film formation power density of the insulating layer 109 smaller than the film formation power density of the insulating layer 110a, the hydrogen content in the insulating layer 109 can be made higher than the hydrogen content in the insulating layer 110a. Thereby, the amount of hydrogen released from itself can be increased by the heat applied to the insulating layer 109.

[0260] The film formation gas used for forming the insulating layer 109 preferably has a higher hydrogen content than the film formation gas used for forming the insulating layer 110a. Specifically, when forming a silicon nitride film or a silicon oxynitride film on each of the insulating layer 109 and the insulating layer 110a using the plasma enhanced chemical vapor deposition (PECVD: also referred to as Plasma Enhanced Chemical Vapor Deposition or plasma CVD) method, the ratio of the flow rate of ammonia gas to the total film formation gas used for forming the insulating layer 109 (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the film formation gas used for forming the insulating layer 110a. By forming the insulating layer 109 under the condition of a high ammonia flow rate ratio, the hydrogen content in the insulating layer 109 can be increased. Also, the amount of hydrogen released from itself can be increased by the heat applied to the insulating layer 109.

[0261] It is more preferable that the film density of the insulating layer 110a is higher than that of the insulating layer 109. This suppresses the diffusion of hydrogen contained in the insulating layer 109 into the channel formation region of the semiconductor layer 108 via the insulating layers 110a and 110b. For evaluation of film density, for example, Rutherford backscattering (RBS) or X-ray reflectivity (XRR) can be used. Differences in film density can sometimes be evaluated using cross-sectional TEM images. In TEM observation, a high film density results in a darker transmission electron (TE) image, while a low film density results in a lighter transmission electron (TE) image. Therefore, in the transmission electron (TE) image, the insulating layer 110a may appear darker compared to the insulating layer 109. Even when the same material is applied to the insulating layer 109 and the insulating layer 110a, the film densities are different, so the boundary between them may be observed as a difference in contrast in the cross-sectional TEM image.

[0262] Although the insulating layer 110 is shown here as a three-layer laminated structure, the present invention is not limited to this. Preferably, the insulating layer 110 has at least an insulating layer 110b. It is also possible to have a configuration that does not have one or both of the insulating layers 110a and 110c. Furthermore, the insulating layer 110 can have a laminated structure of four or more layers.

[0263] The upper surface shape of the conductive layer 112b is preferably the same as or approximately the same as the upper surface shape of the insulating layer 110. Figure 9(A), etc., shows a configuration in which the upper surface shape of the conductive layer 112b is the same as the upper surface shape of the insulating layer 110. The conductive layer 112b and the insulating layer 110 can be formed using the same mask layer. For example, an insulating film that will become the insulating layer 110 and a conductive film that will become the conductive layer 112b on the insulating film are formed, and a mask layer (e.g., a resist mask) is formed on the conductive film. Then, by processing the conductive film and the insulating film using the mask layer as a mask, a conductive layer 112b and an insulating layer 110 with the same or approximately the same upper surface shape can be formed. By processing the insulating film that will become the insulating layer 110 and the conductive film that will become the conductive layer 112b in the same process, manufacturing costs can be reduced. In Figure 9(A), etc., the top surfaces of the conductive layer 112b and the insulating layer 110 are shown as rectangles, but the top surfaces of the conductive layer 112b and the insulating layer 110 are not particularly limited.

[0264] Regarding transistor 100B, in addition to the explanation above, you can refer to the explanation regarding transistor 100 in <Transistor Configuration Example 1> and the explanation regarding transistor 100A in <Transistor Configuration Example 2>.

[0265] <Example of transistor fabrication method> In the following section, an example of a method for manufacturing a transistor according to one embodiment of the present invention will be described using Figures 11(A) to 14(C). Note that explanations of the materials and formation methods of each element constituting the transistor may be omitted if they are the same as those described in <Transistor Configuration Example 1>, etc.

[0266] Thin films (insulating films, semiconductor films, conductive films, etc.) that make up transistors can be formed using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), ALD, and other methods. CVD methods include PECVD and thermal CVD. One type of thermal CVD is metal-organic chemical vapor deposition (MOCVD).

[0267] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute transistors can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, or knife coating.

[0268] When processing the thin films that constitute transistors, photolithography or similar methods can be used. Alternatively, thin films can be processed using nanoimprint lithography, sandblasting, or lift-off methods. Furthermore, island-like thin films can be directly formed using a deposition method that utilizes a shielding mask such as a metal mask.

[0269] There are two main methods of photolithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0270] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0271] For etching thin films, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0272] In the following, an example of a method for fabricating the transistor 100 shown in Figures 6(A) to 6(C) will be explained using Figures 11(A) to 14(C). Each figure shows a cross-sectional view between the dashed line A1 and A2 shown in Figure 6(B).

[0273] First, an insulating layer 110 is formed on the substrate 102. Sputtering or PECVD methods can be suitably used to form the insulating layer 110.

[0274] When the PECVD method is used to form the insulating layer 110, the substrate temperature during formation is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. By setting the substrate temperature during the formation of the insulating layer 110 within the above range, the release of impurities (e.g., water and hydrogen) from itself can be reduced, and the diffusion of impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor 100 that exhibits good electrical characteristics and is highly reliable can be realized. Furthermore, when the sputtering method is used to form the insulating layer 110, the substrate temperature during formation can also be set to room temperature.

[0275] Furthermore, since the insulating layer 110 is formed before the semiconductor layer 108, there is no need to worry about oxygen being released from the semiconductor layer 108 due to the heat applied during the formation of the insulating layer 110.

[0276] After forming the insulating layer 110, oxygen can be supplied to the insulating layer 110. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. For plasma treatment, a device that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that convert gas into plasma using high-frequency power include PECVD devices, plasma etching devices, and plasma ashing devices. Plasma treatment is preferably performed in an atmosphere containing oxygen. For example, plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N2O), nitrogen dioxide (NO2), carbon monoxide, and carbon dioxide.

[0277] Furthermore, the plasma treatment can be performed without exposing the surface of the insulating layer 110 to the atmosphere. For example, when a PECVD apparatus is used to form the insulating layer 110, it is preferable to perform the plasma treatment in the same PECVD apparatus. This can increase productivity. Specifically, after forming the insulating layer 110 in the PECVD apparatus, the N2O plasma treatment can be performed continuously in the same apparatus.

[0278] Next, it is preferable to perform a treatment to supply oxygen to the insulating layer 110. For example, oxygen can be supplied to the insulating layer 110 by forming an oxygen-containing film on the insulating layer 110. Alternatively, oxygen can be supplied to the insulating layer 110 by performing a heat treatment after forming an oxygen-containing film. For example, oxygen can be effectively supplied to the insulating layer 110 by forming aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), silicon-containing indium tin oxide (ITSO), or a metal oxide material applicable to the semiconductor layer 108 on the insulating layer 110.

[0279] When heat treatment is performed after forming an oxygen-containing film on the insulating layer 110, the temperature of the heat treatment is preferably, for example, 150°C or higher but below the strain point of the substrate, 200°C or higher but 450°C or lower, 230°C or higher but 400°C or lower, 250°C or higher but 350°C or lower, or 250°C or higher but 300°C or lower. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can be used as the atmosphere containing nitrogen or oxygen. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating layer 110 as much as possible. An oven, RTA device, etc. can be used for the heat treatment. By using an RTA device, the heat treatment time can be shortened.

[0280] After the oxygen supply treatment described above, it is preferable to remove the oxygen-containing film formed on the insulating layer 110.

[0281] The process of supplying oxygen to the insulating layer 110 is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atom ions, or oxygen molecular ions can be supplied to the insulating layer 110 by ion doping, ion implantation, or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating layer 110, and then oxygen can be supplied to the insulating layer 110 through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0282] It is preferable that a large amount of oxygen is released from the insulating layer 110 to the channel formation region of the transistor 100. By supplying oxygen to the insulating layer 110, the amount of oxygen contained in the insulating layer 110 increases, and the amount of oxygen supplied from the insulating layer 110 to the semiconductor layer 108 can be increased. As a result, even transistors 100 with short channel lengths can exhibit good electrical characteristics.

[0283] Next, a first amorphous film 108a1 is deposited on the insulating layer 110 (Figure 11(A)). This deposition corresponds to step S1 in the flowchart shown in Figure 3. As mentioned above, the first amorphous film 108a1 is an amorphous indium oxide film. For details on the deposition method, etc., please refer to the description in Figure 1(A).

[0284] Next, a first heat treatment is performed to crystallize the first amorphous film 108a1, thereby forming the first crystalline film 108p1 (Figure 11(B)). This heat treatment corresponds to step S2 in the flowchart shown in Figure 3. As mentioned above, the first crystalline film 108p1 is a polycrystalline indium oxide film consisting of randomly oriented crystal grains of various particle sizes. Details regarding the temperature, atmosphere, etc., of this heat treatment can be found in the description in Figure 1(B).

[0285] In this example of the manufacturing method, a first amorphous film 108a1 is formed on the insulating layer 110 (Figure 11(A)), and then a first heat treatment is performed to form a first crystalline film 108p1 from the first amorphous film 108a1 (Figure 11(B)). However, this is not the only method. For example, a crystalline film (corresponding to the first crystalline film 108p1) can also be formed on the insulating layer 110 using sputtering or ALD. In this case, the first heat treatment is unnecessary, thus reducing the number of steps.

[0286] Furthermore, when depositing a crystalline film using the sputtering method or the ALD method, a highly crystalline film can be deposited by performing the deposition at a substrate temperature higher than that used for depositing the first amorphous film 108a1 described above. Also, for example, when using the sputtering method, a highly crystalline film can be deposited by reducing the hydrogen (H2) content in the sputtering gas or by using a sputtering gas that does not contain hydrogen. Also, for example, when using the ALD method, a highly crystalline film can be deposited by using a first oxidizing agent that does not contain water (H2O), hydrogen peroxide (H2O2), etc.

[0287] Next, a portion of the first crystallized film 108p1 is removed to form a crystallized layer 108p1e (Figure 11(C)). For example, a wet etching method can be suitably used to form the crystallized layer 108p1e (first wet etching). It is preferable to form the crystallized layer 108p1e in an island-like manner in a region that overlaps with the channel formation region of the transistor 100. This allows for the selective formation of the seed crystal layer 108s, which will be formed later, in a region that overlaps with the channel formation region.

[0288] Furthermore, the formation of the crystallized layer 108p1e can be omitted. This reduces the number of steps involved in the fabrication of the transistor 100.

[0289] Next, wet etching (second wet etching) is performed on the crystallized layer 108p1e. This wet etching corresponds to step S3 in the flowchart shown in Figure 3. This wet etching removes a portion of the crystallized layer 108p1e, specifically, crystal grains other than those with the slowest etching rate against the etchant, and forms a seed crystal layer 108s (Figure 12(A)). That is, the seed crystal layer 108s is a layer composed of crystal grains with the slowest etching rate against the etchant (which can also be said to be the crystal orientation with the highest etching resistance to the etchant) among the various crystal orientations of the crystallized layer 108p1e. Details of the etchant and other materials that can be used for this wet etching can be found in the description in Figure 1(C).

[0290] Next, a second amorphous film 108a2 is deposited on the seed crystal layer 108s and the insulating layer 110 (Figure 12(B)). This deposition corresponds to step S4 in the flowchart shown in Figure 3. As mentioned above, the second amorphous film 108a2 is an amorphous indium oxide film. For details on the deposition method, etc., please refer to the descriptions in Figures 2(A1) and 2(A2).

[0291] Next, a second heat treatment is performed to crystallize the second amorphous film 108a2, thereby forming a second crystalline film 108p2 (Figure 12(C)). This heat treatment corresponds to step S5 in the flowchart shown in Figure 3. As described above, the second crystalline film 108p2 is an indium oxide film in which the second amorphous film 108a2 has crystallized on the upper surface of the seed crystal layer 108s in a crystal orientation that reflects the crystal structure of the seed crystal layer 108s. In Figure 12(C), the progression of crystal growth is schematically shown with arrows. The crystal grains constituting the second crystalline film 108p2 have the same crystal orientation as the seed crystal layer 108s. For details on the temperature, atmosphere, etc. of this heat treatment, please refer to the descriptions in Figures 2(B1) and 2(B2).

[0292] Next, a portion of the second crystallized film 108p2 is removed to form a semiconductor layer 108 (Figure 13(A)). For example, a wet etching method can be suitably used to form the semiconductor layer 108 (third wet etching). The semiconductor layer 108 is formed in an island-like manner in the region that overlaps with the channel formation region of the transistor 100.

[0293] It is preferable to perform a heat treatment after forming the second crystallized film 108p2, or after processing the second crystallized film 108p2 into a semiconductor layer 108, and then forming an oxygen-containing film on the aforementioned insulating layer 110. This heat treatment can remove hydrogen and water contained in the second crystallized film 108p2 or the semiconductor layer 108, or adsorbed on the surface. Furthermore, this heat treatment may improve the film quality of the second crystallized film 108p2 or the semiconductor layer 108 (for example, reducing defects or improving crystallinity).

[0294] This heat treatment also allows oxygen to be supplied from the insulating layer 110 to the second crystallized film 108p2 or the semiconductor layer 108. This reduces the oxygen deficiency (V) in the channel formation region of the transistor 100. OThis can reduce the amount of heat applied. In this case, it is more preferable to perform a heat treatment before processing the second crystallized film 108p2 into the semiconductor layer 108. However, the heat treatment is not limited to this, and oxygen may also be supplied to the channel formation region of the transistor 100 in steps where heat is applied after the formation of the second crystallized film 108p2 (for example, the step of forming the insulating layer 106).

[0295] Note that this heat treatment can be omitted if it is not necessary. Alternatively, the heat treatment can be omitted here and combined with a heat treatment performed in a later step. Furthermore, a high-temperature treatment in a later step (for example, a film deposition process) may also serve as this heat treatment.

[0296] Next, an insulating film 106f is formed to cover the semiconductor layer 108 and the insulating layer 110, which will become the insulating layer 106 (Figure 13(B)). For example, the PECVD method or the ALD method can be suitably used to form the insulating film 106f.

[0297] Since a metal oxide is used in the semiconductor layer 108, it is preferable that the insulating layer 106 functions as a barrier film that suppresses the diffusion of oxygen. Because the insulating layer 106 has the function of suppressing oxygen diffusion, the diffusion of oxygen contained in the semiconductor layer 108 to the area above the insulating layer 106 is suppressed, and oxygen vacancies (V) are formed in the semiconductor layer 108. O This can suppress the increase in ). As a result, a transistor 100 that exhibits good electrical characteristics and is highly reliable can be realized.

[0298] By increasing the temperature during the formation of the insulating film 106f, an insulating layer 106 with fewer defects can be formed. However, if the temperature during the formation of the insulating film 106f is high, oxygen will be detached from the semiconductor layer 108, resulting in oxygen vacancies (V) in the semiconductor layer 108. O ) and V OIn some cases, the amount of H may increase. The substrate temperature during the formation of the insulating film 106f is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, and more preferably 300°C to 400°C. By setting the substrate temperature during the formation of the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced, and the detachment of oxygen from the semiconductor layer 108 can be suppressed. Therefore, a transistor 100 that exhibits good electrical characteristics and is highly reliable can be realized.

[0299] Before forming the insulating film 106f, the surface of the semiconductor layer 108 can be subjected to plasma treatment. This plasma treatment can reduce impurities (e.g., water) adsorbed on the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, enabling the realization of a highly reliable transistor 100. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the formation of the insulating film 106f. The plasma treatment can be performed in an atmosphere such as oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, it is preferable that the plasma treatment and the formation of the insulating film 106f are performed continuously without exposure to the atmosphere.

[0300] Next, the insulating film 106f is processed to form an insulating layer 106 (Figure 13(C)). The insulating layer 106 is provided with openings 147a and 147b that reach the semiconductor layer 108. Dry etching can be suitably used to form the insulating layer 106.

[0301] Next, conductive films 104f, which will form conductive layers 104, 112a, and 112b, are formed on the insulating layer 106 (Figure 14(A)). For forming the conductive films 104f, sputtering, thermal CVD (including MOCVD), or ALD can be suitably used.

[0302] Next, the conductive film 104f is processed to form conductive layers 104, 112a, and 112b (Figure 14(B)). Conductive layer 104 is formed to have a region that overlaps with the semiconductor layer 108 and the insulating layer 106. Conductive layer 112a is formed to have a region that overlaps with the opening 147a. Conductive layer 112b is formed to have a region that overlaps with the opening 147b.

[0303] Next, impurities are supplied (also called added or implanted) to the semiconductor layer 108 using conductive layers 104, 112a, and 112b as masks. As a result, region 108D is formed in the semiconductor layer 108 in a region that does not overlap with conductive layers 104, 112a, 112b, and 106, and region 108L is formed in the region that does not overlap with conductive layers 104, 112a, and 112b, but overlaps with the insulating layer 106 (Figure 14(C)). At this time, it is preferable to determine the conditions for supplying impurities by considering the material and thickness of the conductive layer 104 that acts as a mask, so that as few impurities as possible are supplied to the region of the semiconductor layer 108 that overlaps with the conductive layer 104. As a result, a channel-forming region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 108 that overlaps with the conductive layer 104.

[0304] Plasma ion doping or ion implantation can be suitably used to supply impurities. These methods allow for highly precise control of the concentration profile in the depth direction by adjusting the ion acceleration voltage and dose amount. Using plasma ion doping can increase productivity. Furthermore, using ion implantation with mass separation can improve the purity of the supplied impurities.

[0305] In supplying impurities, it is preferable to adjust the supply conditions so that the impurity concentration is highest on the surface of the semiconductor layer 108, or in the area close to the surface.

[0306] For supplying impurities, the raw materials can include, for example, gases containing the aforementioned impurity elements. When supplying boron, typically one or more B2H6 gas or BF3 gas can be used. Similarly, when supplying phosphorus, typically PH3 gas can be used. Furthermore, these raw material gases can be diluted with noble gases.

[0307] For example, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used as raw materials for supplying impurities. The raw materials are not limited to gases; solids or liquids can also be heated and vaporized for use.

[0308] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 108.

[0309] For example, when supplying boron by ion implantation or plasma ion doping, the acceleration voltage can be in the range of, for example, 5kV to 100kV, preferably 7kV to 70kV, and more preferably 10kV to 50kV. The dose can also be, for example, 1 × 10⁻⁶ 13 ions / cm 2 The above 1 x 10 17 ions / cm 2 The following is preferably 1 × 10 14 ions / cm 2 The above 5 x 10 16 ions / cm 2 More preferably 1 × 10 15 ions / cm 2 The above 3 x 10 16 ions / cm 2 The following range is possible.

[0310] When supplying phosphorus by ion implantation or plasma ion doping, the acceleration voltage can be in the range of, for example, 10kV to 100kV, preferably 30kV to 90kV, and more preferably 40kV to 80kV. The dose can also be, for example, 1 × 10⁻⁶ 13 ions / cm 2 The above 1 x 10 17 ions / cm 2 The following is preferably 1 × 10 14 ions / cm 2 The above 5 x 10 16 ions / cm 2 More preferably 1 × 10 15 ions / cm 2 The above 3 x 10 16 ions / cm 2 The following range is possible.

[0311] The method of supplying impurities is not limited to this; for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc., can be used.

[0312] For example, by performing plasma processing in an atmosphere containing a hydrogen-containing gas using a plasma CVD apparatus, hydrogen can be supplied as an impurity to the semiconductor layer 108 in a region that does not overlap with the conductive layer 104.

[0313] By following the above steps, a transistor 100 according to one aspect of the present invention can be manufactured.

[0314] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0315] (Embodiment 2) A transistor to which the metal oxide layer according to one aspect of the present invention can be applied (transistor 100, transistor 100A, transistor 100B, etc.) can be applied, for example, to a display device. In this embodiment, a circuit and the like applicable to a display device according to one aspect of the present invention will be described.

[0316] Figure 15 is a block diagram illustrating the display device 200. The display device 200 includes a display unit 435, a first drive circuit unit 431, and a second drive circuit unit 432.

[0317] The display unit 435 has a plurality of pixels 230 arranged in a matrix of m rows (where m is an integer of 1 or more) and n columns (where n is an integer of 1 or more).

[0318] In Figure 15, the pixel 230 in the 1st row and nth column is shown as pixel 230[1,n], the pixel 230 in the mth row and 1st column is shown as pixel 230[m,1], and the pixel 230 in the mth row and nth column is shown as pixel 230[m,n]. In addition, any pixel 230 included in the display unit 435 may be shown as pixel 230[r,s]. r is an integer between 1 and m, and s is an integer between 1 and n.

[0319] The circuit included in the first drive circuit section 431 functions, for example, as a scan line drive circuit (also called a gate driver). The circuit included in the second drive circuit section 432 functions, for example, as a signal line drive circuit (also called a source driver). It is also possible to provide some circuit in a position facing the first drive circuit section 431 across the display section 435. Similarly, it is possible to provide some circuit in a position facing the second drive circuit section 432 across the display section 435. The circuits included in the first drive circuit section 431 and the second drive circuit section 432 are collectively referred to as the peripheral drive circuit 433.

[0320] The peripheral drive circuit 433 can utilize various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit. A transistor 100 according to one aspect of the present invention can be used in the peripheral drive circuit 433. Furthermore, the transistors in the peripheral drive circuit and the transistors included in the pixel 230 can be formed using the same process.

[0321] Furthermore, the display device 200 has m wires 436, each arranged in roughly parallel directions and whose potential is controlled by a circuit included in the first drive circuit section 431, and n wires 437, each arranged in roughly parallel directions and whose potential is controlled by a circuit included in the second drive circuit section 432.

[0322] Note that Figure 15 shows an example where wiring 436 and wiring 437 are connected to pixel 230. However, wiring 436 and wiring 437 are just examples, and the wiring connected to pixel 230 is not limited to wiring 436 and wiring 437.

[0323] <Example of pixel circuit configuration> Figures 16(A) to 17(C) show examples of the configuration of the pixel 230. The pixel 230 has a pixel circuit 51 (pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, pixel circuit 51D, pixel circuit 51E, or pixel circuit 51F) and a light-emitting element 61.

[0324] The light-emitting element described in this embodiment refers to a self-emissive display element such as an organic EL element. The light-emitting element connected to the pixel circuit can be a self-emissive element such as an LED, microLED, QLED (Quantum-dot LED), or semiconductor laser.

[0325] The pixel circuit 51A shown in Figure 16(A) is a 2Tr1C type pixel circuit having transistors 52A and 52B, and a capacitor 53.

[0326] One of the sources or drains of transistor 52A is connected to wiring SL, and the gate of transistor 52A is connected to wiring GL. The other source or drain of transistor 52A is connected to the gate of transistor 52B and one terminal of capacitor 53. One of the sources or drains of transistor 52B is connected to wiring ANO. The other source or drain of transistor 52B is connected to the other terminal of capacitor 53 and the anode of light-emitting element 61. The cathode of light-emitting element 61 is connected to wiring VCOM. The region where the other source or drain of transistor 52A, the gate of transistor 52B, and one terminal of capacitor 53 are connected functions as node ND.

[0327] Wiring GL corresponds to wiring 436, and wiring SL corresponds to wiring 437. Wiring VCOM is a wire that provides a potential to supply current to the light-emitting element 61. Transistor 52A has the function of controlling the conduction state (a state in which current can flow) or non-conduction state between wiring SL and the gate of transistor 52B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO and VSS is supplied to wiring VCOM. Transistor 52A can also be called a selection transistor because it functions as a switch to control the selection and deselection of pixel 230.

[0328] By turning transistor 52A ON, an image signal is supplied from wiring SL to node ND. Subsequently, by turning transistor 52A OFF, the image signal is held in node ND. To reliably hold the image signal supplied to node ND, it is preferable to use a transistor with a low off-current for transistor 52A. For example, it is preferable to use an OS transistor as transistor 52A.

[0329] Transistor 52B has the function of controlling the amount of current flowing to the light-emitting element 61. Transistor 52B can also be called a drive transistor. Capacitor 53 has the function of maintaining the gate potential of transistor 52B. The intensity of the light emitted by the light-emitting element 61 is controlled according to the image signal supplied to the gate (node ​​ND) of transistor 52B.

[0330] For example, some or all of the transistors in the pixel circuit 51A can be the transistors 100, 100A, 100B, etc., shown in Embodiment 1.

[0331] The pixel circuit 51B shown in Figure 16(B) is a 3Tr1C type pixel circuit having transistors 52A, 52B, 52C, and capacitor 53. The pixel circuit 51B shown in Figure 16(B) has a configuration in which transistor 52C is added to the pixel circuit 51A shown in Figure 16(A), and the wiring connected to the gate of transistor 52A and the wiring connected to the gate of transistor 52C are each independently configured.

[0332] Furthermore, the gate of transistor 52A is connected to wiring GL1, and the gate of transistor 52C is connected to wiring GL2. By providing separate wiring for the gates of transistor 52A and transistor 52C, different potentials can be applied to the gates of the two transistors, allowing them to operate independently.

[0333] One of the sources or drains of transistor 52C is connected to the other of the sources or drains of transistor 52B. The other of the sources or drains of transistor 52C is connected to wiring V0. For example, wiring V0 is supplied with a reference potential.

[0334] Transistor 52C has the function of controlling the conduction or non-conduction state between the source or drain of transistor 52B and the wiring V0 based on the potential of the wiring GL2. When an n-channel transistor is used for transistor 52B, the reference potential of the wiring V0 provided via transistor 52C can suppress variations in the gate-source voltage of transistor 52B.

[0335] Furthermore, the wiring V0 can be used to obtain current values ​​that can be used to set pixel parameters. More specifically, wiring V0 can function as a monitor line for outputting the current flowing through transistor 52B or the current flowing through light-emitting element 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the outside.

[0336] For example, some or all of the transistors in the pixel circuit 51B can be the transistors 100, 100A, 100B, etc., shown in Embodiment 1.

[0337] The pixel circuit 51C shown in Figure 16(C) has a configuration in which the wiring connected to the gate of transistor 52A and the wiring connected to the gate of transistor 52C in the pixel circuit 51B shown in Figure 16(B) are common (wiring GL). Because the pixel circuit 51C has this configuration, the number of wires can be reduced compared to the pixel circuit 51B, and therefore the number of power supplies connected to each wire can be reduced. Accordingly, a display device having the pixel circuit 51C can reduce the number of manufacturing processes and miniaturize the display device compared to a display device having the pixel circuit 51B.

[0338] For example, some or all of the transistors in the pixel circuit 51C can be the transistors 100, 100A, 100B, etc., shown in Embodiment 1.

[0339] The pixel circuit 51D shown in Figure 17(A) has a configuration in which transistor 52D is added to the pixel circuit 51B shown in Figure 16(B). The pixel circuit 51D shown in Figure 17(A) is a 4Tr1C type pixel circuit having transistors 52A, 52B, 52C, 52D, and capacitor 53.

[0340] One of the sources or drains of transistor 52D is connected to node ND, and the other source or drain is connected to wiring V0.

[0341] Wirings GL1, GL2, and GL3 are connected to the pixel circuit 51D. Wiring GL1 is connected to the gate of transistor 52A, wiring GL2 is connected to the gate of transistor 52C, and wiring GL3 is connected to the gate of transistor 52D.

[0342] In this embodiment, wiring GL1, wiring GL2, and wiring GL3 are sometimes collectively referred to as wiring GL. Therefore, wiring GL is not limited to one wire, as in pixel circuits 51A and 51C, but may consist of multiple wires, as in pixel circuits 51B and 51D.

[0343] By simultaneously making transistors 52C and 52D conduct, the source and gate of transistor 52B become at the same potential, making transistor 52B non-conducting. This allows the current flowing to the light-emitting element 61 to be forcibly interrupted. Such a pixel circuit is suitable for display methods that alternate between display periods and off periods.

[0344] The pixel circuit 51E shown in Figure 17(B) is an example of adding a capacitor 53A to the pixel circuit 51D shown in Figure 17(A). The capacitor 53A functions as a retaining capacitor. The pixel circuit 51D shown in Figure 17(A) is a 4Tr1C type pixel circuit. The pixel circuit 51E shown in Figure 17(B) is a 4Tr2C type pixel circuit.

[0345] The pixel circuit 51F shown in Figure 17(C) is a 6Tr1C type pixel circuit having transistors 52A, 52B, 52C, 52D, 52E, 52F, and capacitor 53.

[0346] Either the source or drain of transistor 52A is connected to wire SL, and the gate of transistor 52A is connected to wire GL2. Either the source or drain of transistor 52D is connected to wire ANO, and the gate of transistor 52D is connected to wire GL1. The other source or drain of transistor 52D is connected to either the source or drain of transistor 52B. The other source or drain of transistor 52B is connected to the other source or drain of transistor 52A, and to either the source or drain of transistor 52F. The gate of transistor 52F is connected to wire GL3.

[0347] One source or drain of transistor 52E is connected to the other source or drain of transistor 52D, and one source or drain of transistor 52B. The other source or drain of transistor 52E is connected to the gate of transistor 52B and one terminal of capacitor 53. The other terminal of capacitor 53 is connected to the other source or drain of transistor 52F, the anode of light-emitting element 61, and one source or drain of transistor 52C. The gates of transistor 52E and transistor 52C are connected to wiring GL4. The other source or drain of transistor 52C is connected to wiring V0. The region to which the other source or drain of transistor 52E, the gate of transistor 52B, and one terminal of capacitor 53 are connected functions as node ND.

[0348] For example, some or all of the transistors in pixel circuits 51D, 51E, and 51F can be replaced with transistors 100, 100A, 100B, etc., as shown in Embodiment 1.

[0349] For example, by using a TGSA type transistor such as transistor 100 as the driving transistor for the pixel circuit of a display device having a light-emitting element, the high saturation of the TGSA type transistor can stabilize the luminescence brightness of the light-emitting element.

[0350] Furthermore, by using vertical transistors such as transistor 100A and transistor 100B as drive transistors in the pixel circuit of a display device having a light-emitting element, the luminescence brightness of the light-emitting element can be increased due to the large on-current of the vertical transistor.

[0351] Furthermore, by using vertical transistors such as transistor 100A and transistor 100B in the pixel circuit of the display device, the occupied area of ​​the pixel circuit can be reduced. Therefore, the resolution of the display device can be increased. For example, a display device can be realized with a resolution of 1000ppi or more and 10000ppi or less, preferably 2000ppi or more and 9000ppi or less, more preferably 3000ppi or more and 8000ppi or less, even more preferably 4000ppi or more and 8000ppi or less, even more preferably 5000ppi or more and 8000ppi or less, and even more preferably 6000ppi or more and 8000ppi or less.

[0352] Furthermore, by reducing the area occupied by the pixel circuit, the number of pixels in the display device can be increased (higher resolution). For example, it becomes possible to realize display devices with extremely high resolutions such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K2K (3840 x 2160 pixels), or 8K4K (7680 x 4320 pixels).

[0353] Furthermore, by using vertical transistors such as transistor 100A and transistor 100B in the peripheral drive circuits (scan line drive circuits, signal line drive circuits, etc.) of the display device, it is possible to realize a display device with a narrow bezel and high-speed operation.

[0354] Furthermore, by using OS transistors such as transistor 100, transistor 100A, and transistor 100B in the pixel circuit and peripheral drive circuit of a display device, the low off-current of the OS transistors can be used to reduce the power consumption of the display device.

[0355] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0356] (Embodiment 3) A transistor to which a metal oxide layer according to one aspect of the present invention can be applied (transistor 100, transistor 100A, transistor 100B, etc.) can be applied to various semiconductor devices in addition to display devices. In this embodiment, a semiconductor device 900 to which a transistor according to one aspect of the present invention can be applied will be described. The semiconductor device 900 can function as a memory device.

[0357] Figure 18 shows a block diagram illustrating an example configuration of a semiconductor device 900. The semiconductor device 900 shown in Figure 18 includes a drive circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Figure 18 shows an example in which the memory array 920 has multiple memory cells 950 arranged in a matrix.

[0358] A transistor according to one aspect of the present invention (transistor 100, transistor 100A, transistor 100B, etc.) as exemplified in Embodiment 1 can be applied to the memory cell 950. By using such a transistor to which a metal oxide layer according to one aspect of the present invention can be applied, the operating speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. In addition, the capacity per unit area of ​​the memory device can be increased.

[0359] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0360] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0361] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 can also be generated by the control circuit 912.

[0362] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 so that this operating mode is executed.

[0363] The voltage generation circuit 928 has the function of generating a negative voltage. The WAKE signal has the function of controlling the input of the CLK signal to the voltage generation circuit 928. For example, when a high-level signal is given as the WAKE signal, the CLK signal is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0364] The peripheral circuit 911 is a circuit for writing and reading data to / from the memory cell 950. The peripheral circuit 911 includes a row decoder 941 (Row Decoder), a column decoder 942 (Column Decoder), a row driver 923 (Row Driver), a column driver 924 (Column Driver), an input circuit 925 (Input Cir.), an output circuit 926 (Output Cir.), and a sense amplifier 927 (Sense Amplifier).

[0365] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for designating the row to be accessed, and the column decoder 942 is a circuit for designating the column to be accessed. The row driver 923 has the function of selecting the row designated by the row decoder 941. The column driver 924 has functions such as writing data to the memory cell 950, reading data from the memory cell 950, and holding the read data.

[0366] The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read by the column driver 924 from the memory cell 950 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. Also, the output circuit 926 has the function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

[0367] The PSW 931 has the function of controlling the supply of V to the peripheral circuit 915. DD The PSW 932 has the function of controlling the supply of V to the row driver 923. Here, the high power supply voltage of the semiconductor device 900 is V HM and the low power supply voltage is GND (ground potential). Also, V DD is, and the low power supply voltage is GND (ground potential). Also, V HMThis is a high power supply voltage used to raise the word line to a high level, V DD It is higher than that. The on / off state of PSW931 is controlled by signal PON1, and the on / off state of PSW932 is controlled by signal PON2. In Figure 18, in peripheral circuit 915, V DD The number of power domains supplied is set to 1, but it can be multiple. In this case, a power switch should be provided for each power domain.

[0368] Using Figures 19(A) to 20(C), other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0369] [NOSRAM] Figure 19(A) shows an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 951 has a transistor M1, a transistor M2, and a capacitance element C. Transistor M1 functions as a data writing transistor. Transistor M2 functions as a data reading transistor. Capacitor element C functions as a data retention capacitance. In this specification and elsewhere, a memory device having a gain cell type memory cell using an OS transistor for transistor M1 is called NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory).

[0370] The first terminal of transistor M1 (either source or drain) is connected to the first terminal (one electrode) of capacitive element C, the second terminal of transistor M1 (the other source or drain) is connected to wiring WBL, and the gate of transistor M1 is connected to wiring WWL. The second terminal (the other electrode) of capacitive element C is connected to wiring CAL. The first terminal of transistor M2 (either source or drain) is connected to wiring RBL, the second terminal of transistor M2 (the other source or drain) is connected to wiring VSL, and the gate of transistor M2 is connected to the first terminal of capacitive element C.

[0371] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WWL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element C. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0372] Data writing is performed by applying a high-level potential to the wiring WWL, making transistor M1 conductive, and connecting the wiring WBL to the first terminal of the capacitive element C. Specifically, when transistor M1 is conductive, a potential corresponding to the data to be recorded is applied to the wiring WBL, and this potential is written to the first terminal of the capacitive element C and the gate of transistor M2. Subsequently, a low-level potential is applied to the wiring WWL, making transistor M1 non-conductive, thereby maintaining the potential of the first terminal of the capacitive element C and the potential of the gate of transistor M2.

[0373] Data is read by applying a predetermined potential to the wiring VSL. The current flowing between the source and drain of transistor M2, and the potential of the first terminal of transistor M2, are determined by the potential of the gate and the potential of the second terminal of transistor M2. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M2, the potential held at the first terminal of capacitive element C (or the gate of transistor M2) can be read. In other words, the data written to this memory cell can be read from the potential held at the first terminal of capacitive element C (or the gate of transistor M2).

[0374] Furthermore, for example, the wiring WBL and wiring RBL can be combined into a single wiring BIL. An example of such a memory cell circuit configuration is shown in Figure 19(B). Memory cell 952 is configured such that the wiring WBL and wiring RBL of memory cell 951 are combined into a single wiring BIL, and the second terminal of transistor M1 and the first terminal of transistor M2 are connected to this wiring BIL. In other words, memory cell 952 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0375] Figure 19(C) shows a memory cell 953, which is an example where the capacitive element C and wiring CAL in memory cell 951 are omitted. Similarly, Figure 19(D) shows a memory cell 954, which is an example where the capacitive element C and wiring CAL in memory cell 952 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0376] In the memory cells 951 to 954 shown in Figures 19(A) to 19(D), transistor 100, transistor 100A, transistor 100B, etc., shown in Embodiment 1 can be applied to one or both of transistors M1 and M2.

[0377] Because the OS transistor has the characteristic of having an extremely low off-current, the written data can be retained by transistor M1 for a long time, reducing the frequency of memory cell refreshes, or even eliminating the need for memory cell refresh operations altogether. Therefore, the power consumption of the storage device can be reduced. In addition, because the leakage current is very low, multi-level data or analog data can be retained in each of the memory cells 951, 952, 953, and 954.

[0378] Furthermore, as described in Embodiment 1, transistors 100, 100A, 100B, etc., to which the metal oxide layer according to one embodiment of the present invention can be applied have high field-effect mobility and large on-current. Therefore, it is possible to realize a storage device with high operating speed (data writing speed and data reading speed).

[0379] Memory cells 951, 952, 953, and 954, which use OS transistors as transistors M1 and M2, are all embodiments of NOSRAM.

[0380] Furthermore, a Si transistor can also be used as transistor M2. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0381] Furthermore, when an OS transistor is used as transistor M2, the memory cell can be constructed as a unipolar circuit.

[0382] Figure 19(E) also shows a gain cell type memory cell 955 with three transistors and one capacitance element. The memory cell 955 has transistors M1 to M3 and a capacitance element C. Transistor M3 functions as a data readout transistor. In other words, while memory cells 951 to 954 have a configuration with only one data readout transistor (transistor M2), memory cell 955 differs in that it has two data readout transistors (transistors M2 and M3).

[0383] The first terminal of transistor M1 is connected to the first terminal of capacitive element C, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WWL. The second terminal of capacitive element C is connected to the first terminal of transistor M2 and to wiring GNDL. The second terminal of transistor M2 is connected to the first terminal of transistor M3 (either source or drain), and the gate of transistor M2 is connected to the first terminal of capacitive element C. The second terminal of transistor M3 (the other source or drain) is connected to wiring BIL, and the gate of transistor M3 is connected to wiring RWL.

[0384] Wiring BIL functions as a bit line, wiring WWL functions as a write word line, and wiring RWL functions as a read word line. Wiring GNDL is a wire that provides a low level potential.

[0385] Data is written by applying a high-level potential to the wiring WWL, making transistor M1 conductive, and connecting the wiring BIL to the first terminal of the capacitive element C. Specifically, when transistor M1 is conductive, a potential corresponding to the data to be recorded is applied to the wiring BIL, and this potential is written to the first terminal of the capacitive element C and the gate of transistor M2. Subsequently, a low-level potential is applied to the wiring WWL, making transistor M1 non-conductive, thereby maintaining the potential of the first terminal of the capacitive element C and the potential of the gate of transistor M2.

[0386] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M3 becomes conductive, and the wiring BIL and the second terminal of transistor M2 become connected. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M2, but the potential of the second terminal of transistor M2 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element C (or the gate of transistor M2). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element C (or the gate of transistor M2) can be read. In other words, the data written to this memory cell can be read from the potential held at the first terminal of the capacitive element C (or the gate of transistor M2).

[0387] In the memory cell 955 shown in Figure 19(E), transistor 100, transistor 100A, transistor 100B, etc., shown in Embodiment 1 can be applied to one or both of transistors M1 and M2.

[0388] Furthermore, it is preferable to apply an OS transistor to transistor M3 as well. For example, an OS transistor made of the same material as transistor M1 can be used for transistor M3. Alternatively, an OS transistor made of the same material as transistor M2 can be used. Alternatively, an OS transistor made of a different material from both transistor M1 and transistor M2 can be used.

[0389] In particular, it is preferable to use an OS transistor made of the same material as transistor M1 for transistor M3. This allows transistor M3 to be a normally-off transistor. Therefore, it is possible to prevent transistor M3 from turning on in memory cells that are not targeted for data reading (i.e., memory cells to which a high-level potential is not applied to the wiring RWL), thereby suppressing malfunctions such as accidental data reading.

[0390] Furthermore, Si transistors can also be used as transistors M2 and M3. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer. Therefore, it may be possible to improve the read speed of the memory device compared to using OS transistors for both transistors M2 and M3. It is also possible to use an OS transistor for one of transistors M2 and M3 and a Si transistor for the other.

[0391] Furthermore, when OS transistors are used as transistors M2 and M3, the memory cell can be configured as a unipolar circuit.

[0392] [DOSRAM] Figure 20(A) shows an example of the circuit configuration of a memory cell in a DRAM (Dynamic Random Access Memory). In this specification, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 960 has a transistor M4 and a capacitive element C.

[0393] Furthermore, transistor M4 can also be configured to have a front gate (sometimes simply called a gate) and a back gate. In this configuration, the back gate can be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate can be connected.

[0394] The first terminal of transistor M4 (either source or drain) is connected to the first terminal (one electrode) of capacitive element C, the second terminal of transistor M4 (the other source or drain) is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WWL. The second terminal (the other electrode) of capacitive element C is connected to wiring CAL.

[0395] Wiring BIL functions as a bit line, and wiring WWL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element C. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0396] Data writing and reading are performed by applying a high-level potential to the wiring WWL, making transistor M4 conductive, and connecting the wiring BIL to the first terminal of the capacitive element C.

[0397] Furthermore, the memory cell that can be used in memory cell 950 is not limited to memory cell 960, and the circuit configuration can be changed. For example, the memory cell 961 can be configured as shown in Figure 20(B). Memory cell 961 is an example in which there is no capacitive element C and wiring CAL. The first terminal of transistor M4 is electrically floating.

[0398] In the memory cell 961, the potential written via transistor M4 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0399] Furthermore, it is preferable to use an OS transistor (transistor 100, transistor 100A, transistor 100B, etc.) as transistor M4, as described in Embodiment 1. By using such a transistor, the operating speed of the memory device can be improved. In addition, the occupied area of ​​the memory cell can be reduced. OS transistors also have the characteristic of having an extremely small off-current. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be made very small. In other words, since the written data can be held by transistor M4 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 960 and 961.

[0400] In the memory cell 960 and memory cell 961 shown in Figures 20(A) and 20(B), the transistor M4 can be replaced with the transistor 100, transistor 100A, transistor 100B, etc., shown in Embodiment 1.

[0401] [OS-SRAM] Figure 20(C) shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification, SRAM using an OS transistor is referred to as OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 962 shown in Figure 20(C) is a memory cell of a backup-capable SRAM.

[0402] The memory cell 962 includes transistors M5 to M8, transistors MS1 to MS4, and capacitive elements C1 and C2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0403] The first terminal of transistor M5 (either source or drain) is connected to wiring BIL, and the second terminal of transistor M5 (the other source or drain) is connected to the first terminal of transistor MS1 (either source or drain), the first terminal of transistor MS3 (either source or drain), the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M8 (either source or drain). The gate of transistor M5 is connected to wiring WWL. The first terminal of transistor M6 (either source or drain) is connected to wiring BILB, and the second terminal of transistor M6 (the other source or drain) is connected to the first terminal of transistor MS2 (either source or drain), the first terminal of transistor MS4 (either source or drain), the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M7 (either source or drain). The gate of transistor M6 is connected to wiring WWL.

[0404] The second terminal of transistor MS1 (the other side of the source or drain) is connected to wiring VDL. The second terminal of transistor MS2 (the other side of the source or drain) is connected to wiring VDL. The second terminal of transistor MS3 (the other side of the source or drain) is connected to wiring GNDL. The second terminal of transistor MS4 (the other side of the source or drain) is connected to wiring GNDL.

[0405] The second terminal of transistor M7 (the other of the source or drain) is connected to the first terminal (one electrode) of capacitive element C1, and the gate of transistor M7 is connected to wiring BRL. The second terminal of transistor M8 (the other of the source or drain) is connected to the first terminal (one electrode) of capacitive element C2, and the gate of transistor M8 is connected to wiring BRL.

[0406] The second terminal (the other electrode) of capacitive element C1 is connected to the wiring GNDL, and the second terminal (the other electrode) of capacitive element C2 is connected to the wiring GNDL.

[0407] Wiring BIL and BILB function as bit lines, wiring WWL functions as a word line, and wiring BRL controls the conduction and non-conduction states of transistors M7 and M8.

[0408] Wiring VDL is a wire that provides a high potential, and wiring GNDL is a wire that provides a low potential.

[0409] Data is written by applying a high-level potential to wiring WWL and wiring BRL. Specifically, when transistor M8 is conducting, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the second terminal side of transistor M8.

[0410] Incidentally, since the memory cell 962 is configured as an inverter loop by transistors MS1 to MS4, an inverted signal of the data signal corresponding to the potential is input to the second terminal of transistor M6. Because transistor M6 is conducting, the potential applied to wiring BIL, i.e., the inverted signal of the signal input to wiring BIL, is output to wiring BILB. Also, because transistors M7 and M8 are conducting, the potential of the second terminal of transistor M5 and the potential of the second terminal of transistor M6 are held at the first terminal of capacitive element C2 and the first terminal of capacitive element C1, respectively. Subsequently, by applying a low-level potential to wiring WWL and wiring BRL, and making transistors M5 to M8 non-conducting, the potentials of the first terminal of capacitive element C1 and the first terminal of capacitive element C2 are held.

[0411] Data is read by first precharging wiring BIL and wiring BILB to a predetermined potential, then applying a high-level potential to wiring WWL and wiring BRL. This refreshes the potential of the first terminal of capacitive element C1 via the inverter loop of memory cell 962 and outputs it to wiring BILB. Similarly, the potential of the first terminal of capacitive element C2 is also refreshed via the inverter loop of memory cell 962 and outputs it to wiring BIL. Since wiring BIL and wiring BILB fluctuate from their precharged potentials to the potentials of the first terminals of capacitive element C2 and C1, respectively, the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0412] Furthermore, it is preferable to use OS transistors as transistors M5 to M8. This allows the written data to be retained for a long time by transistors M5 to M8, thereby reducing the frequency of memory cell refreshes. Alternatively, it may be possible to eliminate the need for memory cell refresh operations altogether. In addition, by using the OS transistors described in Embodiment 1 (transistor 100, transistor 100A, transistor 100B, etc.) as transistors M5 to M8, the operating speed of the storage device can be improved. Furthermore, the occupied area of ​​the memory cell can be reduced.

[0413] Furthermore, Si transistors can also be used as transistors MS1 through MS4.

[0414] In the memory cell 962 shown in Figure 20(C), transistors M5 to M8, as well as transistors MS3 and MS4, some or all of the transistors can be replaced with transistors 100, 100A, 100B, etc., as shown in Embodiment 1.

[0415] Thus, by applying a transistor according to one aspect of the present invention to the memory cell 962, an extremely high-performance memory cell 962 can be realized that combines excellent retention characteristics with a fast operating speed.

[0416] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0417] (Embodiment 4) In this embodiment, an example of an application of a semiconductor device according to one aspect of the present invention will be explained using Figures 21(A) to 25(F).

[0418] A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, large computers, space equipment, data centers (also referred to as DCs), and various electronic devices. By using a semiconductor device according to one aspect of the present invention, it is possible to achieve lower power consumption and higher performance in electronic components, large computers, space equipment, data centers, and various electronic devices.

[0419] Furthermore, a display device having a semiconductor device according to one aspect of the present invention can be used in the display units of various electronic devices. A display device having a semiconductor device according to one aspect of the present invention can be easily made higher resolution and higher definition.

[0420] Examples of electronic devices include television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0421] In particular, a display device according to one aspect of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0422] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (detail) of the display device according to one aspect of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more. By using a display device having one or both of these high resolutions and high detail, it is possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display device according to one embodiment of the present invention. For example, the display device can support various aspect ratios such as 1:1 (square), 4:3, 16:9, or 16:10.

[0423] The electronic device of this embodiment may have sensors (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0424] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, or text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0425] [Electronic components] Figure 21(A) shows a perspective view of a circuit board (mounted board 1989) on which electronic component 1980 is mounted. The electronic component 1980 shown in Figure 21(A) has a semiconductor device 1981 within a mold 1984. Some details have been omitted in Figure 21(A) to show the inside of the electronic component 1980. The electronic component 1980 has a land 1985 on the outside of the mold 1984. The land 1985 is connected to an electrode pad 1986, and the electrode pad 1986 is connected to the semiconductor device 1981 via a wire 1987. The electronic component 1980 is mounted, for example, on a printed circuit board 1988. Multiple such electronic components are combined and connected on the printed circuit board 1988 to complete the mounted board 1989.

[0426] Furthermore, the semiconductor device 1981 has a drive circuit layer 1982 and a memory layer 1983. The memory layer 1983 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 1982 and the memory layer 1983 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 1982 and the memory layer 1983, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0427] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-electrodes such as TSV, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0428] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 1983 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 1983, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0429] The semiconductor device 1981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0430] Next, a perspective view of electronic component 1990 is shown in Figure 21(B). Electronic component 1990 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 1990 has an interposer 1991 on a package substrate 1992 (printed circuit board), and a semiconductor device 1994 and multiple semiconductor devices 1981 are provided on the interposer 1991.

[0431] Electronic component 1990 shows an example of using semiconductor device 1981 as high-bandwidth memory (HBM). Furthermore, semiconductor device 1994 can be used in integrated circuits such as central processing units (CPUs), graphics processing units (GPUs), or field-programmable gate arrays (FPGAs).

[0432] For the package substrate 1992, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used. For the interposer 1991, for example, a silicon interposer or a resin interposer can be used.

[0433] The interposer 1991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 1991 also has the function of connecting integrated circuits provided on the interposer 1991 to electrodes provided on the package substrate 1992. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 1991, and these through electrodes may be used to connect the integrated circuits and the package substrate 1992. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0434] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0435] Furthermore, in SiP, MCM, etc., which use silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit placed on the silicon interposer and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0436] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when trying to reduce the size of electronic component 1990, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0437] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 1990. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 1991. For example, in the electronic component 1990 shown in this embodiment, it is preferable to align the heights of the semiconductor device 1981 and the semiconductor device 1994.

[0438] To mount the electronic component 1990 onto another substrate, electrodes 1993 may be provided at the bottom of the package substrate 1992. Figure 21(B) shows an example in which the electrodes 1993 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 1992, BGA (Ball Grid Array) mounting can be realized. Alternatively, the electrodes 1993 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 1992, PGA (Pin Grid Array) mounting can be realized.

[0439] Electronic component 1990 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0440] [Large computer] Next, a perspective view of the large-scale computer 5600 is shown in Figure 22(A). The large-scale computer 5600 shown in Figure 22(A) has multiple rack-mount type computers 5620 housed in rack 5610. The large-scale computer 5600 may also be referred to as a supercomputer.

[0441] Computer 5620 can have the configuration shown in the perspective view in Figure 22(B), for example. In Figure 22(B), computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0442] The PC card 5621 shown in Figure 22(C) is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 22(C) shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, you can refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below for details on these semiconductor devices.

[0443] The connector 5629 has a shape that allows it to be inserted into slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0444] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0445] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0446] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5627 include FPGAs, GPUs, and CPUs. For example, electronic component 1990 can be used as the semiconductor device 5627.

[0447] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be connected by soldering these terminals to the wiring on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5628 include memory devices. For example, electronic component 1990 can be used as the semiconductor device 5628.

[0448] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0449] [Space equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment.

[0450] One embodiment of the present invention includes an OS transistor. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical properties due to radiation exposure. In other words, they have high resistance to radiation, making them highly reliable and suitable for use in environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used as transistors constituting semiconductor devices installed in space shuttles, artificial satellites, or space probes. Examples of radiation include X-rays and neutrons. Outer space generally refers to altitudes of 100 km or higher, but the outer space described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0451] Figure 22(D) shows satellite 6800 as an example of space equipment. Satellite 6800 consists of a body 6801, solar panels 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 22(D), planet 6804 is shown as an example in outer space.

[0452] Furthermore, although not shown in Figure 22(D), a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0453] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutrons, protons, heavy ions, and mesons.

[0454] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel does not receive sunlight, or if the amount of sunlight hitting the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to install a secondary battery 6805 on the satellite 6800. Note that solar panels are sometimes called solar cell modules.

[0455] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0456] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 6807.

[0457] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected off objects on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0458] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes.

[0459] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0460] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as ensuring data immutability. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, or securing cooling equipment required for data storage, which necessitates the construction of larger buildings.

[0461] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. Therefore, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. This, in turn, contributes to space savings in the data center.

[0462] Furthermore, since the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0463] Figure 22(E) shows a storage system applicable to a data center. The storage system 7010 shown in Figure 22(E) has multiple servers 7001sb as hosts 7001 (shown as Host Computer) and multiple storage devices 7003md as storage 7003 (shown as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (SAN) and a storage control circuit 7002 (shown as Storage Controller).

[0464] Host 7001 corresponds to a computer that accesses data stored in storage 7003. The hosts 7001 may be connected to each other via a network.

[0465] While Storage 7003 shortens data access speed, i.e., the time required for data storage and retrieval, by using flash memory, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. To address the problem of the long access speed of Storage 7003, storage systems typically include cache memory within the storage to shorten the time required for data storage and retrieval.

[0466] The aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

[0467] By using OS transistors as the transistors for storing the aforementioned cache memory data, and configuring them to maintain a potential corresponding to the data, the refresh frequency can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking the memory cell arrays.

[0468] [Electronic equipment] Figures 23(A) to 23(F) illustrate an example of a wearable device that can be worn on the head. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, or a function to display MR content. By having an electronic device that has the function to display at least one of the following content types, such as AR, VR, SR, or MR, it is possible to enhance the user's sense of immersion.

[0469] The electronic device 800 shown in Figure 23(A) includes a pair of display panels 810, a pair of housings 811, a communication unit (not shown), a pair of mounting units 813, a control unit 814, an imaging unit (not shown), a pair of optical members 816, a frame 817, and a pair of nose pads 818.

[0470] A display device according to one aspect of the present invention can be applied to the display panel 810. Therefore, an electronic device capable of displaying extremely high resolution can be created. Furthermore, a semiconductor device according to one aspect of the present invention can be applied to the control unit 814. This makes it possible to reduce the power consumption of the electronic device.

[0471] The electronic device 800 can project an image displayed on the display panel 810 onto the display area 819 of the optical element 816. Because the optical element 816 is translucent, the user can see the image displayed on the display area superimposed on the transmitted image visible through the optical element 816. Therefore, the electronic device 800 is an electronic device capable of AR display.

[0472] The electronic device 800 may be equipped with a camera capable of capturing images of the area in front of it as an imaging unit. Furthermore, by equipping the electronic device 800 with an acceleration sensor such as a gyro sensor, it can detect the orientation of the user's head and display an image corresponding to that orientation in the display area 819.

[0473] The communications unit has a wireless communication device, which can supply video signals and the like. Alternatively, instead of the wireless communication device, or in addition to the wireless communication device, it may be equipped with a connector to which a cable supplying video signals and power voltage can be connected.

[0474] Furthermore, the electronic device 800 is equipped with a battery that can be charged wirelessly, wired, or both.

[0475] The housing 811 may be equipped with a touch sensor module. The touch sensor module has the function of detecting when the outer surface of the housing 811 is touched. The touch sensor module can detect the user's tap or slide operations and perform various processes. For example, a tap operation can be used to pause or resume the video, and a slide operation can be used to fast forward or rewind. Furthermore, by providing a touch sensor module in each of the two housings 811, the range of operations can be expanded.

[0476] The electronic device 830A shown in Figure 23(B) and the electronic device 830B shown in Figure 23(C) each include a pair of display units 840, a housing 841, a communication unit 842, a pair of mounting units 843, a control unit 844, a pair of imaging units 845, and a pair of lenses 846.

[0477] A display device according to one aspect of the present invention can be applied to the display unit 840. Therefore, an electronic device capable of displaying extremely high resolution can be created. This allows the user to experience a high level of immersion. Furthermore, a semiconductor device according to one aspect of the present invention can be applied to the control unit 844. This reduces the power consumption of the electronic device.

[0478] The display unit 840 is located inside the housing 841 in a position where it can be viewed through the lens 846. Furthermore, by displaying different images on a pair of display units 840, a three-dimensional display using parallax can also be performed.

[0479] Electronic devices 830A and 830B can each be described as electronic devices for VR. A user wearing either electronic device 830A or electronic device 830B can view the image displayed on the display unit 840 through the lens 846.

[0480] It is preferable that electronic devices 830A and 830B each have a mechanism that allows adjustment of the left and right positions of the lens 846 and the display unit 840 so that they are in the optimal position according to the user's eye position. It is also preferable that they have a mechanism that adjusts the focus by changing the distance between the lens 846 and the display unit 840.

[0481] The attachment portion 843 allows the user to attach the electronic device 830A or 830B to their head. While the attachment portion 843 is exemplified in Figure 23(B) and other figures as resembling the temples (or arms) of eyeglasses, it is not limited to this shape. The attachment portion 843 only needs to be wearable by the user; for example, it may be helmet-shaped or band-shaped.

[0482] The imaging unit 845 has the function of acquiring external information. The data acquired by the imaging unit 845 can be output to the display unit 840. An image sensor can be used in the imaging unit 845. In addition, multiple cameras may be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

[0483] Although an example with an imaging unit 845 is shown here, any distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 845 is one form of a detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0484] The electronic device 830A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 840, housing 841, and mounting unit 843. This allows users to enjoy video and audio simply by wearing the electronic device 830A, without needing separate audio equipment such as headphones, earphones, or speakers.

[0485] Electronic devices 830A and 830B may each have input terminals. Cables can be connected to the input terminals to supply video signals from video output devices, etc., and power for charging batteries provided in the electronic devices.

[0486] An electronic device according to one aspect of the present invention may have a function for wireless communication with an earphone 820. The earphone 820 has a communication unit (not shown) and has a wireless communication function. The earphone 820 can receive information (e.g., voice data) from the electronic device through its wireless communication function. For example, the electronic device 800 shown in Figure 23(A) has a function for transmitting information to the earphone 820 through its wireless communication function.

[0487] Furthermore, the electronic device may have an earphone section. The electronic device 830B shown in Figure 23(C) has an earphone section 847. For example, the earphone section 847 and the control unit 844 can be connected to each other by wire. Part of the wiring connecting the earphone section 847 and the control unit 844 may be located inside the housing 841 or the mounting section 843. Also, the earphone section 847 and the mounting section 843 may have magnets. This allows the earphone section 847 to be fixed to the mounting section 843 by magnetic force, which is preferable as it facilitates storage.

[0488] Furthermore, the electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have an audio input terminal and / or an audio input mechanism. For example, a sound-collecting device such as a microphone can be used as the audio input mechanism. By having an audio input mechanism, the electronic device may be given the function of a so-called headset.

[0489] Figures 23(D) and 23(E) show perspective views of a goggle-type electronic device 860A for VR. Figures 23(D) and 23(E) show an example in which a pair of curved display devices 870 (display device 870_R and display device 870_L) are located within a housing 875. The electronic device 860A also includes a motion detection unit 871, a gaze detection unit 872, a calculation unit 873, a communication unit 874, lenses 876, operation buttons 877, a wearable device 878, a sensor 879, a dial 880, and the like.

[0490] Having two display devices 870 allows the user to view one display device per eye. This enables the display of high-resolution images, even when performing 3D displays using parallax. Furthermore, the display device 870 is curved in an arc shape with the user's eye as the approximate center. This ensures that the distance from the user's eye to the display surface of the display device 870 remains constant, allowing the user to see more natural images. In addition, even if the display device 870 exhibits so-called viewing angle dependence, where the brightness or chromaticity of the light changes depending on the viewing angle, the configuration allows the user's eye to be positioned in the direction of the normal to the display surface of the display device 870. Therefore, the effect can be practically ignored, especially in the horizontal direction, resulting in the display of more realistic images.

[0491] As shown in Figure 23(E), the lens 876 is positioned between the display device 870 and the user's eye. Figure 23(E) shows an example where a dial 880 is used to change the position of the lens for diopter adjustment. Note that if the electronic device 860A has an autofocus function, the dial 880 for diopter adjustment is not required.

[0492] Figure 23(F) shows a goggle-type electronic device 860B having a single display device 870. This configuration allows for a reduction in the number of components.

[0493] The display device 870 can display two images side by side in two regions, one for the right eye and one for the left eye. This allows for the display of stereoscopic images using binocular parallax. The display device 870 may display two different images using parallax, or it may display two identical images side by side without using parallax.

[0494] Alternatively, a single image visible to both eyes may be displayed across the entire surface of the display device 870. This makes it possible to display a panoramic image across both edges of the field of view, thereby enhancing the sense of realism.

[0495] A display device according to one aspect of the present invention can be applied to the display device 870. Because the display device according to one aspect of the present invention has extremely high resolution, even when magnified using the lens 876, the user cannot see the pixels, and a more realistic image can be displayed.

[0496] The electronic device 6500 shown in Figure 24(A) is a portable information terminal that can be used as a smartphone.

[0497] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.

[0498] The electronic device 6520 shown in Figure 24(B) is a portable information terminal that can be used as a tablet device.

[0499] The electronic device 6520 includes a housing 6501, a display unit 6502, buttons 6504, a speaker 6505, a microphone 6506, a camera 6507, a control device 6509, and connection terminals 6519.

[0500] In each of the electronic devices 6500 and 6520, the display unit 6502 is equipped with a touch panel function. The control device 6509 has one or more selected from, for example, a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be used for either or both of the display unit 6502 and the control device 6509.

[0501] Figure 24(C) is a schematic cross-sectional view of the housing 6501 of the electronic device 6500 or electronic device 6520, including the end on the microphone 6506 side.

[0502] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0503] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0504] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and the FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on the printed circuit board 6517.

[0505] A display device according to one embodiment of the present invention can be applied to the display panel 6511. As a result, an extremely lightweight electronic device can be realized. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back of the pixel section, an electronic device with a narrow bezel can be realized.

[0506] Figure 24(D) shows an example of a television system. The television system 7100 has a display unit 7000 incorporated into a housing 7101. Here, the housing 7101 is shown supported by a stand 7103.

[0507] A display device according to one embodiment of the present invention can be applied to the display unit 7000.

[0508] The television device 7100 shown in Figure 24(D) can be operated using the operation switches on the housing 7101 and a separate remote control unit 7111. Alternatively, the display unit 7000 may be equipped with a touch sensor, and the television device 7100 can be operated by touching the display unit 7000 with a finger or the like. The remote control unit 7111 may have a display unit that displays information output from the remote control unit 7111. Channels and volume can be controlled and the image displayed on the display unit 7000 can be controlled using the operation keys or touch panel on the remote control unit 7111.

[0509] The television system 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0510] Figure 24(E) shows an example of a notebook computer. The notebook computer 7200 includes a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7215, and the like. A display unit 7000 is incorporated into the casing 7211. The control device 7215 has one or more components selected from, for example, a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be used for either or both of the display unit 7000 and the control device 7215.

[0511] Figures 24(F) and 24(G) show examples of digital signage.

[0512] The digital signage 7300 shown in Figure 24(F) includes a housing 7301, a display unit 7000, a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0513] Figure 24(G) shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7000 that is provided along the curved surface of the column 7401.

[0514] In Figures 24(F) and 24(G), a display device according to one embodiment of the present invention can be applied to the display unit 7000.

[0515] The larger the display area 7000, the more information can be provided at once. Furthermore, a larger display area 7000 is more eye-catching, which can, for example, enhance the effectiveness of advertising.

[0516] Applying a touch panel to the display unit 7000 is preferable because it not only allows images or videos to be displayed on the display unit 7000, but also enables intuitive operation by the user. Furthermore, when used for purposes such as providing route information or traffic information, intuitive operation can enhance usability.

[0517] Furthermore, as shown in Figures 24(F) and 24(G), it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 or information terminal 7411 such as a smartphone owned by the user. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or information terminal 7411. In addition, the display on the display unit 7000 can be switched by operating the information terminal 7311 or information terminal 7411.

[0518] Furthermore, the digital signage 7300 or digital signage 7400 can be used to run games using the screen of the information terminal 7311 or information terminal 7411 as the control device (controller). This allows an unspecified number of users to participate in and enjoy the game simultaneously.

[0519] Furthermore, a semiconductor device and display device according to one aspect of the present invention can be applied to the area around the driver's seat of a mobile vehicle.

[0520] Figure 25(A) is a diagram showing the area around the windshield inside the car's interior. Figure 25(A) shows display panels 9001a, 9001b, and 9001c mounted on the dashboard, as well as display panel 9001d mounted on the pillar.

[0521] Display panels 9001a to 9001c can provide various information by displaying navigation information, speedometer, tachometer, mileage, fuel gauge, gear status, or air conditioning settings. Furthermore, the display items and layout shown on the display panels can be changed as needed to suit the user's preferences, enhancing the design. Display panels 9001a to 9001c can also be used as lighting devices.

[0522] The display panel 9001d can compensate for the blind spots (views obstructed by the pillars) by displaying images from imaging devices installed on the vehicle body. In other words, by displaying images from imaging devices installed on the outside of the vehicle, blind spots can be compensated for, thereby enhancing safety. Furthermore, by displaying images that compensate for unseen areas, safety checks can be performed more naturally and without discomfort. The display panel 9001d can also be used as a lighting device.

[0523] Figure 25(B) is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can be used, for example, as a smartwatch (registered trademark). The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless communication headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. Charging may be performed by wireless power supply.

[0524] The portable information terminal 9200 shown in Figure 25(B) comprises a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, sensors 9007 (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0525] Figure 25(C) is a perspective view showing a foldable personal information terminal 9201. The personal information terminal 9201 includes a housing 9000a, a housing 9000b, a display unit 9001, and operation buttons 9056.

[0526] The housing 9000a and housing 9000b are connected by a hinge 9055, which allows them to be folded in half.

[0527] The display unit 9001 of the portable information terminal 9201 is supported by two housings (housing 9000a and housing 9000b) connected by a hinge 9055.

[0528] Figures 25(D) to 25(F) are perspective views showing a foldable personal information terminal 9202. Figure 25(D) shows the personal information terminal 9202 in an unfolded state, Figure 25(F) shows it in a folded state, and Figure 25(E) shows a state in between, transitioning from one of Figures 25(D) or 25(F) to the other. Thus, the personal information terminal 9202 can be folded into three sections.

[0529] The display unit 9001 of the portable information terminal 9202 is supported by three housings 9000 connected by a hinge 9055.

[0530] In Figures 25(C) to 25(F), a display device according to one embodiment of the present invention can be applied to the display unit 9001. For example, the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.

[0531] The personal digital assistant (PDA) 9201 and PDA 9202 offer excellent portability when folded and superior readability due to their seamless, wide display area when unfolded.

[0532] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from electronic components, large computers, space equipment, data centers, and electronic devices, power consumption can be reduced. Therefore, as energy demand is expected to increase due to the increased performance or integration of semiconductor devices, using a semiconductor device according to one aspect of the present invention makes it possible to reduce emissions of greenhouse gases, such as carbon dioxide (CO2). In addition, because a semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0533] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate. [Examples]

[0534] In this example, among the manufacturing methods of crystalline indium oxide, which is a metal oxide layer of one aspect of the present invention (Figs. 1(A) to 2(B2)), the processes according to Figs. 1(A) to 1(C) (that is, from the formation of the first crystallization film 108p1 to the first wet etching of the film) were carried out, and the surface of the sample after the process was observed.

[0535] <Fabrication of Samples> In this example, four samples (Samples A to D) with conditional first wet etching were fabricated.

[0536] First, a 50-nm-thick first amorphous film 108a1 was formed on a quartz substrate prepared as the substrate 101 by sputtering (corresponding to Fig. 1(A)). The film formation was carried out using an In2O3 target in an atmosphere containing 1% O2 gas and 5% H2 gas at room temperature of the substrate. The first amorphous film 108a1 is an amorphous indium oxide film.

[0537] Subsequently, the first heat treatment was carried out to form the first crystallization film 108p1 (corresponding to Fig. 1(B)). The heat treatment was carried out at 350 °C for 1 hour in a dry air atmosphere using an oven device. The first crystallization film 108p1 is a polycrystalline indium oxide film.

[0538] Up to this point, it is common for Samples A to D. [[ID=I9]]

[0539] Subsequently, the first wet etching was carried out on the first crystallization film 108p1 (corresponding to Fig. 1(C)). The wet etching was carried out at a liquid temperature of 60 °C using an etchant containing oxalic acid. Also, the processing time of the wet etching (immersion time of the etchant) was 30 minutes for Sample A, 1 hour for Sample B, 2 hours for Sample C, and 3 hours for Sample D, respectively.

[0540] Thus, Samples A to D were fabricated.

[0541] <SEM Observation> For each of Samples A to D prepared above, SEM observation of the sample surface was performed.

[0542] Figures 26(A) to 26(D) show the surface SEM images of Samples A to D. Figure 26(A) is the surface SEM image of Sample A, Figure 26(B) is the surface SEM image of Sample B, Figure 26(C) is the surface SEM image of Sample C, and Figure 26(D) is the surface SEM image of Sample D. Each SEM image is the observation result at a magnification of 25,000 times.

[0543] As shown in Figures 26(A) to 26(D), it was confirmed that as the wet etching treatment time became longer, the remaining crystal grains tended to decrease and shrink. Among the randomly oriented crystal grains of the first crystallization film 108p1, it is suggested that the etching progresses earlier for the crystal orientations with a higher etching rate. When the treatment time is 2 hours (Figure 26(C)), it can be confirmed that crystal grains with a size of several hundred nm are slightly scattered, but when the treatment time reaches 3 hours (Figure 26(D)), it was found that almost all crystal grains are etched.

[0544] <EBSD Measurement> Among Samples A to D, EBSD measurement was performed on Sample C (Figure 26(C)) in which it was confirmed by the above SEM observation that some crystal grains remained.

[0545] Figure 27(A) shows the surface SEM image of Sample C, and Figure 27(B) shows the EBSD measurement result of Sample C. In the SEM image shown in Figure 27(A), the area surrounded by the square frame is the measurement area of the EBSD measurement result shown in Figure 27(B). Also, the five crystal grains surrounded by circles in the SEM image shown in Figure 27(A) correspond to the areas surrounded by circles in the EBSD measurement result shown in Figure 27(B).

[0546] As a result of the EBSD measurement, it was confirmed that the crystal grains remaining in Sample C have a crystal orientation near <111>. There is a possibility that the crystal grains correspond to the seed crystal layer 108s shown in Figure 1(C).

[0547] In this embodiment, wet etching is performed on a polycrystalline indium oxide film having randomly oriented crystal grains with an etchant containing an acid (in this case, oxalic acid), thereby creating a specific crystal orientation on the surface to be formed (in this case, <111> We confirmed that it is possible to retain crystal grains with a specific orientation.

[0548] Subsequently, by performing the processes shown in Figures 2(A1) to 2(B2) (i.e., the deposition of the second amorphous film 108a2 and the second heat treatment), the above crystal grains are used as seed crystals to form the second amorphous film 108a2 with a specific crystal orientation relative to the upper surface of the above crystal grains (here, <111> The possibility of growing crystals in a specific orientation was demonstrated. [Explanation of Symbols]

[0549] 51: Pixel circuit, 51A: Pixel circuit, 51B: Pixel circuit, 51C: Pixel circuit, 51D: Pixel circuit, 51E: Pixel circuit, 51F: Pixel circuit, 52A: Transistor, 52B: Transistor, 52C: Transistor, 52D: Transistor, 52E: Transistor, 52F: Transistor, 53: Capacitor, 53A: Capacitor, 61: Light-emitting element, 100: Transistor, 100A: Transistor, 100B: Transistor, 101: Substrate, 102: Substrate, 104: Conductive layer, 104f: Conductive film, 106: Insulating layer, 106f: Insulating film, 108: Semiconductor layer, 108a1: No. 1: Amorphous film, 108a2: Second amorphous film, 108p1: First crystallized film, 108p1e: Crystallized layer, 108p2: Second crystallized film, 108s: Seed crystal layer, 108D: Region, 108L: Region, 109: Insulating layer, 110: Insulating layer, 110a: Insulating layer, 110b: Insulating layer, 110c: Insulating layer, 112a: Conductive layer, 112b: Conductive layer, 143: Aperture, 147a: Aperture, 147b: Aperture, 200: Display device, 230: Pixel, 431: First drive circuit section, 432: Second drive circuit section, 433: Peripheral drive circuit, 435: Display section, 436: Wiring, 437: Wiring, 8 00: Electronic device, 810: Display panel, 811: Housing, 813: Mounting part, 814: Control unit, 816: Optical component, 817: Frame, 818: Nose pad, 819: Display area, 820: Earphone, 830A: Electronic device, 830B: Electronic device, 840: Display unit, 841: Housing, 842: Communication unit, 843: Mounting part, 844: Control unit, 845: Imaging unit, 846: Lens, 847: Earphone unit, 860A: Electronic device, 860B: Electronic device, 870: Display device, 870_L: Display device, 870_R: Display device, 871: Motion detection unit, 872: Eye-gaze detection unit, 873: Calculation unit, 874: Communication unit, 875: Housing, 876: Lens, 877: Operation buttons, 878: Mounting device, 879: Sensor, 880: Dial, 900: Semiconductor device, 910: Drive circuit, 911: Peripheral circuit, 912: Control circuit, 915: Peripheral circuit, 920: Memory array, 923: Row driver, 924: Column driver, 925: Input circuit, 926: Output circuit, 927: Sense amplifier, 928: Voltage generation circuit, 931: PSW, 932: PSW, 941: Row decoder, 942: Column decoder, 950: Memory cell, 951: Memory cell, 952: Memory cell953: Memory cell, 954: Memory cell, 955: Memory cell, 960: Memory cell, 961: Memory cell, 962: Memory cell, 1980: Electronic component, 1981: Semiconductor device, 1982: Driving circuit layer, 1983: Memory layer, 1984: Mold, 1985: Land, 1986: Electrode pad, 1987: Wire, 1988: Printed circuit board, 1989: Mounted circuit board, 1990: Electronic component, 1991: Interposer, 1992: Package substrate, 1993: Electrode, 1994: Semiconductor device, 5600: Large computer, 5610: Rack, 5620: Computer, 562 1: PC card, 5622: board, 5623: connector, 5624: connector, 5625: connector, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connector, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: enclosure, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control unit, 6510: protective component, 6511: display panel, 6512: optical component, 6513: touch sensor panel 6515:FPC, 6516:IC, 6517:Printed circuit board, 6518:Battery, 6519:Connection terminal, 6520:Electronic equipment, 6800:Artificial satellite, 6801:Aircraft body, 6802:Solar panel, 6803:Antenna, 6804:Planet, 6805:Rechargeable battery, 6807:Control device, 7000:Display unit, 7001:Host, 7001sb:Server, 7002:Storage control circuit, 7003:Storage, 7003md:Memory device, 7004:Storage area network, 7010:Storage system, 7100:Television equipment, 7101 : enclosure, 7103: stand, 7111: remote control, 7200: notebook computer, 7211: enclosure, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7215: control unit, 7300: digital signage, 7301: enclosure, 7303: speaker, 7311: information terminal, 7400: digital signage, 7401: column, 7411: information terminal, 9000: enclosure, 9000a: enclosure, 9000b: enclosure, 9001: display unit, 9001a: display panel, 9001b: display panel, 9001c: display panel,9001d: Display panel, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9055: Hinge, 9056: Operation buttons, 9200: Personal digital assistant, 9201: Personal digital assistant, 9202: Personal digital assistant

Claims

1. The process comprises a first to a fifth step, In the first step described above, a first amorphous film is formed, In the second step described above, a first crystalline film is formed from the first amorphous film by the first heat treatment, In the third step described above, a portion of the first crystallized film is removed by wet etching to form a seed crystal layer. In the fourth step described above, a second amorphous film is formed on the seed crystal layer. In the fifth step described above, a second crystalline film is formed from the second amorphous film by a second heat treatment. The first amorphous film, the first crystallized film, the seed crystal layer, the second amorphous film, and the second crystallized film each contain indium and oxygen. The first crystallized film has randomly oriented crystal grains, The seed crystal layer has a first crystal orientation with respect to the surface to be formed, The second crystallized film consists of crystal grains having the first crystal orientation. A method for fabricating a metal oxide layer.

2. In claim 1, The first amorphous film and the second amorphous film are each deposited by sputtering in an atmosphere containing oxygen and hydrogen at a substrate temperature of 25°C to 140°C. The first and second heat treatments are carried out in an atmosphere containing nitrogen, oxygen, or both, at a temperature of 150°C to 650°C. The aforementioned wet etching is carried out using one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid. A method for fabricating a metal oxide layer.

3. In claim 1 or claim 2, The first crystal orientation is <111>, The second crystallized film has a crystal orientation of <111> with respect to the upper surface of the seed crystal layer. A method for fabricating a metal oxide layer.

4. A transistor having a metal oxide layer formed using the method for producing a metal oxide layer described in claim 1 or claim 2, an insulating layer, and a conductive layer, The metal oxide layer has a region that overlaps with the conductive layer via the insulating layer, The metal oxide layer has the function of a channel formation region of the transistor. The insulating layer has the function of being the gate insulating layer of the transistor. The conductive layer has the function of a gate electrode of the transistor. Transistor.

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