Semiconductor equipment

Abstract

To provide semiconductor devices that are easy to miniaturize. To provide semiconductor devices that enable high integration. [Solution] The semiconductor device comprises first to third conductive layers, a semiconductor layer, and first to third insulating layers. The first insulating layer covers the first conductive layer and has a slit that reaches the first conductive layer. The semiconductor layer has a portion located on the first insulating layer, a portion along the side surface of the first insulating layer, and a portion in contact with the first conductive layer. The second insulating layer covers the semiconductor layer, and the second conductive layer covers the second insulating layer. The third insulating layer overlaps the slit and is located on the second conductive layer. The third conductive layer is in contact with the upper surface of the semiconductor layer in the portion that overlaps with the first insulating layer, and is in contact with the upper surface of the third insulating layer in the portion that overlaps with the slit. The slit, the second conductive layer, and the third insulating layer extend in a first direction. The third conductive layer extends in a second direction intersecting the first direction.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device. One aspect of the present invention relates to a transistor. One aspect of the present invention relates to a memory device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. A semiconductor device refers to any device that can function by utilizing semiconductor properties. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs (Central Processing Units), memory, or other LSIs are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0004] CPUs, memory, or other LSI semiconductor circuits (IC chips) are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0005] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in integrated circuits and electronic devices such as image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0006] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that takes advantage of this low leakage current characteristic. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time.

[0007] Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been a growing demand for even higher density integrated circuits. There is also a need to improve the productivity of semiconductor devices, including integrated circuits. For example, Patent Document 3 discloses a technology for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple superimposed memory cells. Patent Document 4 also discloses a vertical transistor in which the side surface of the oxide semiconductor is covered by a gate electrode via a gate insulator. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Patent Document 2] Japanese Patent Publication No. 2011-151383 [Patent Document 3] International Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Publication No. 2013-211537 [Non-patent literature]

[0009] [Non-Patent Document 1] Takashi Koida, "High-Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet<URL:https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

Summary of the Invention

Problems to be Solved by the Invention

[0010] One aspect of the present invention is to provide a semiconductor device that is easy to miniaturize. Or, one aspect of the present invention is to provide a semiconductor device capable of high integration. Or, one aspect of the present invention is to provide a semiconductor device with reduced wiring load. Or, one aspect of the present invention is to provide a highly reliable semiconductor device. Or, one aspect of the present invention is to provide a semiconductor device that exhibits good electrical characteristics. Or, one aspect of the present invention is to provide a semiconductor device with high operating speed.

[0011] One aspect of the present invention is to provide a semiconductor device, a storage device, or an electronic device having a novel configuration. One aspect of the present invention is to reduce at least one of the problems of the prior art.

[0012] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems can be extracted from the description of the specification, drawings, claims, etc.

Means for Solving the Problems

[0013] One aspect of the present invention is a semiconductor device having a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer covers the first conductive layer and has a slit that reaches the first conductive layer. The semiconductor layer has a portion located on the first insulating layer, a portion inside the slit that runs along the side surface of the first insulating layer, and a portion that is in contact with the first conductive layer. The second insulating layer covers the semiconductor layer inside the slit. The second conductive layer covers the second insulating layer inside the slit. The third insulating layer overlaps the slit and is located on the second conductive layer. The third conductive layer is in contact with the upper surface of the semiconductor layer in the portion that overlaps with the first insulating layer, and is in contact with the upper surface of the third insulating layer in the portion that overlaps with the slit. The slit, the second conductive layer, and the third insulating layer extend in a first direction. The third conductive layer extends in a second direction intersecting the first direction.

[0014] Furthermore, in the above, it is preferable that the angle between the side surface inside the slit of the first insulating layer and the upper surface of the first conductive layer that is in contact with the first insulating layer is 60 degrees or more and less than 90 degrees.

[0015] Furthermore, in the above, it is preferable that the semiconductor layer contains a metal oxide.

[0016] Furthermore, in the above, it is preferable that the semiconductor layer contains an oxide containing indium.

[0017] Furthermore, in the above, it is preferable that the first conductive layer has a recess that overlaps with the slit. In this case, it is preferable that the bottom portions of the semiconductor layer, the second insulating layer, and the second conductive layer are provided along the recess.

[0018] Furthermore, in the above, it is preferable that the semiconductor layer contains a first metal oxide and the first conductive layer contains a second metal oxide. In this case, it is preferable that the first metal oxide and the second metal oxide each contain indium.

[0019] Furthermore, it is preferable that a fourth conductive layer is further provided between the upper surface of the first insulating layer and the semiconductor layer. In this case, it is preferable that the fourth conductive layer is in contact with the semiconductor layer.

[0020] Furthermore, it is preferable that the above further includes a fourth conductive layer and a fourth insulating layer located below the first conductive layer. In this case, it is preferable that the fourth insulating layer has a portion located between the first conductive layer and the fourth conductive layer.

[0021] Furthermore, in the above, it is preferable that the fourth conductive layer has a recess. In this case, it is preferable that the fourth insulating layer has a portion provided along the recess. Moreover, it is preferable that the first conductive layer has a portion located within the recess via the fourth insulating layer. [Effects of the Invention]

[0022] According to one aspect of the present invention, a semiconductor device that is easily miniaturized can be provided. Alternatively, a semiconductor device that can be highly integrated can be provided. Alternatively, a semiconductor device with reduced wiring load can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device exhibiting good electrical characteristics can be provided. Alternatively, a semiconductor device with high operating speed can be provided.

[0023] According to one aspect of the present invention, a semiconductor device, a memory device, or an electronic device having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be mitigated.

[0024] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0025] [Figure 1] Figures 1(A) and 1(B) show examples of storage device configurations. [Figure 2] Figure 2 shows an example of a storage device configuration. [Figure 3] Figure 3 shows an example of a storage device configuration. [Figure 4] Figure 4 shows an example of a storage device configuration. [Figure 5] Figure 5 shows an example of a storage device configuration. [Figure 6] Figures 6(A) and 6(B) show examples of storage device configurations. [Figure 7] Figures 7(A) and 7(B) show examples of storage device configurations. [Figure 8] Figure 8 shows an example of a storage device configuration. [Figure 9] Figure 9 shows an example of a storage device configuration. [Figure 10] Figure 10 shows an example of a storage device configuration. [Figure 11] Figure 11 shows an example of a storage device configuration. [Figure 12] Figures 12(A) to 12(D) illustrate examples of methods for manufacturing memory devices. [Figure 13] Figures 13(A) and 13(B) illustrate examples of methods for manufacturing memory devices. [Figure 14] Figures 14(A) and 14(B) illustrate examples of methods for manufacturing a memory device. [Figure 15] Figures 15(A) and 15(B) illustrate examples of methods for manufacturing memory devices. [Figure 16] Figures 16(A) and 16(B) illustrate examples of methods for manufacturing memory devices. [Figure 17] Figures 17(A) and 17(B) illustrate examples of methods for manufacturing memory devices. [Figure 18] Figures 18(A) and 18(B) illustrate the carrier concentration dependence of hall mobility. Figure 18(C) is a cross-sectional view illustrating an indium oxide film. [Figure 19] Figure 19 is a block diagram illustrating an example of a semiconductor device configuration. [Figure 20]Figures 20(A) to 20(H) illustrate examples of memory cell circuit configurations. [Figure 21] Figures 21(A) and 21(B) are perspective views illustrating an example of a semiconductor device configuration. [Figure 22] Figure 22 is a block diagram illustrating the CPU. [Figure 23] Figures 23(A) and 23(B) are perspective views of a semiconductor device. [Figure 24] Figures 24(A) and 24(B) are perspective views of a semiconductor device. [Figure 25] Figures 25(A) and 25(B) show examples of electronic component configurations. [Figure 26] Figures 26(A) to 26(C) show examples of the configuration of a large-scale computer. [Figure 27] Figure 27(A) shows an example of a space equipment configuration. Figure 27(B) shows an example of a storage system configuration. [Modes for carrying out the invention]

[0026] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0027] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0028] In the figures described herein, the size of each component, the thickness of the layers, or the area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to those figures.

[0029] Furthermore, ordinal numbers such as "the first," "the second," etc., used in this specification are added to avoid confusion of constituent elements and do not imply any numerical limitation.

[0030] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and Thin Film Transistors (TFTs).

[0031] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0032] Furthermore, in this specification, "electrically connected" includes cases where a connection is made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0033] In this specification, cases where two nodes are connected via an insulator, such as the dielectric of a capacitive element, the gate insulating film of a transistor, or an interlayer insulating film, are not included in the definition of "electrical connection."

[0034] In this specification, "approximately matching top surface shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, it may also be said that the "top surface shapes are approximately matching."

[0035] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0036] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, the surface to be formed may be described as "down" and the laminate side as "up."

[0037] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source region and the drain region by the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the ON state. The channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and channel width direction may not be uniquely determined.

[0038] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0039] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, it is higher than Vth).

[0040] (Embodiment 1) This embodiment describes an example of the configuration of a semiconductor device according to one aspect of the present invention, and an example of a method for manufacturing the same. The semiconductor device illustrated below can be applied to a storage device.

[0041] A semiconductor device according to one aspect of the present invention has a plurality of memory cells. Each memory cell has one transistor and one memory element. Various elements capable of holding stored information can be used as the memory element, such as capacitive elements, resistive switching elements, ferroelectric elements, charge trap elements, and floating gate elements.

[0042] In a memory cell, the source electrode and drain electrode are located at different heights, and current flows through the semiconductor layer in the height direction. That is, the channel length direction has a component in the height direction (vertical direction), so one aspect of the present invention can be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, or vertical channel type transistor.

[0043] More specifically, a first insulating layer, which functions as a spacer, is provided above the lower electrode (first conductive layer), which is one of the source electrode and drain electrode. The first insulating layer is provided with a slit that extends in a first direction and reaches the lower electrode. The semiconductor layer has a portion that is in contact with the lower electrode, a portion that is located on the first insulating layer, and a portion that is inside the slit and along the side surface of the first insulating layer. A gate insulating layer (second insulating layer) is provided inside the slit, covering the semiconductor layer. A gate electrode (second electrode) is also located inside the slit, covering the gate insulating layer. Preferably, the gate electrode is provided so as to fill a part of the slit. A third insulating layer is provided inside the slit, located on the gate electrode. There is also a conductive layer (third conductive layer) that functions as wiring, and this third conductive layer is in contact with the upper surface of the semiconductor layer on the first insulating layer and in contact with the upper surface of the third insulating layer in the region overlapping with the slit. A portion of the third conductive layer functions as the other of the source electrode and drain electrode, and extends in the second direction. Here, it is preferable that the slit and the third conductive layer extend in directions that intersect each other. That is, the gate electrode and the third insulating layer located inside the slit extend in a direction that intersects with the third conductive layer. In this case, the third conductive layer can function as a bit line, and the gate electrode can function as a word line.

[0044] This configuration allows the bit lines to be connected directly to the upper surface of the semiconductor layer. Therefore, compared to connecting the bit lines and the semiconductor layer using contact holes and connection plugs provided in the interlayer insulating layer, high integration becomes easier. Specifically, since there is no need for margins to account for the misalignment between the contact holes and the semiconductor layer, integration becomes possible. In addition, since a third insulating layer is provided at the intersection of the bit lines and word lines, parasitic capacitance between them can be reduced.

[0045] The capacitive elements of a memory cell can be located below the transistor. By stacking the transistor and the capacitive elements, the memory cells can be arranged at a high density. The capacitive elements can be of the so-called MIM (Metal-Insulator-Metal) type, having a dielectric between a pair of electrodes. In this case, it is preferable that the lower electrode of the transistor also serves as the upper electrode of the capacitive element. Furthermore, by using a ferroelectric material for the dielectric of the capacitive element, a ferroelectric capacitor can be created. This makes it possible to realize a non-volatile memory device.

[0046] The capacitive element can be a parallel plate type using a pair of flat electrodes, but it is preferable to use a capacitive element having a three-dimensional structure, such as a trench type or pillar type. For example, the lower electrode of the capacitive element is positioned along the inside of an opening provided in a fourth insulating layer located below the first insulating layer. This allows for a lower electrode having a recess on its upper surface. Furthermore, the upper electrode is configured to cover the recess of the lower electrode via a dielectric. This makes it possible to create a capacitive element with a small footprint and large capacitance.

[0047] It is preferable to use a metal oxide (oxide semiconductor) that exhibits semiconductor properties for the semiconductor layer. For example, silicon, a typical semiconductor material, requires doping with impurities that function as donors or acceptors in order to form the source and drain regions. However, in a vertical transistor according to one aspect of the present invention, it can be difficult to dope the semiconductor layer with impurities with high precision due to the difference in height between the source and drain and the vertical position of the channel formation region relative to the substrate surface. On the other hand, oxide semiconductors can achieve good connection with the source and drain electrodes without such impurity doping, making it possible to manufacture transistors with a three-dimensional structure, as in one aspect of the present invention, with a high yield.

[0048] Here, the lower electrode of the transistor preferably has a laminated structure in which a first conductive film and a second conductive film are laminated thereon. In this case, the second conductive film is in contact with the semiconductor layer. Furthermore, it is preferable that the second conductive film contains a conductive metal oxide (oxide conductor). Using a metal oxide in the conductive film that is in contact with the semiconductor layer containing the metal oxide is preferable because it can reduce the contact resistance and thus reduce the load on the wiring. In particular, it is preferable that the second conductive film contains the same metal element as the metal element contained in the semiconductor layer, as this can further reduce the contact resistance. Specifically, it is preferable that the semiconductor layer and the first conductive film contain one or more of In, Sn, Zn, Ga, and Ti, and it is particularly preferable that they contain In. In addition, a low-resistance metal material can be used for the first conductive film. This makes it possible to reduce both the contact resistance and the wiring resistance, thereby further reducing the load on the wiring.

[0049] Below, we will explain more specific examples with reference to the diagrams.

[0050] [Example Configuration] Figure 1(A) shows a schematic top view of the semiconductor device 50. Figure 2 shows a perspective view of the semiconductor device 50. Figures 3, 4, and 5 show schematic cross-sectional views at the cutting lines AB, CD, and EF in Figure 1(A), respectively. Note that some components (such as the insulating layer) are omitted in Figures 1(A) and 2. Arrows indicating the X, Y, and Z directions are shown in each figure.

[0051] The semiconductor device 50 has a configuration in which a plurality of memory cells 15 are arranged in the X and Y directions. The semiconductor device 50 has a conductive layer 26 that functions as a bit line extending in the X direction and a conductive layer 23 that functions as a word line extending in the Y direction. As shown in Figure 2, the memory cell 15 has a transistor 10 and a capacitive element 30 below it.

[0052] Figure 1(B) shows a circuit diagram corresponding to the semiconductor device 50. Figure 1(B) shows multiple wirings BL that function as bit lines, multiple wirings WL that are perpendicular to each bit line and function as word lines, and wiring CL. In Figure 1(B), an example is shown where wiring CL is parallel to wiring BL, but it can also be parallel to wiring WL, or arranged in a grid. Alternatively, wiring CL may be a flat conductive film.

[0053] The memory cell 15 consists of one transistor 10 and one capacitive element 30. The gate of the transistor 10 is connected to wiring WL, one of its source and drain is connected to wiring BL, and the other is connected to one electrode of the capacitive element 30. The other electrode of the capacitive element 30 is connected to wiring CL.

[0054] Wiring BL functions as wiring for writing and reading data. Wiring WL functions as wiring for controlling the on or off state (conductive or non-conductive state) of transistor 10, which functions as a switch. Wiring CL functions as a constant potential line connected to the capacitive element 30.

[0055] As shown in Figure 2, the transistor 10 and the capacitive element 30 are provided on an insulating layer 11 provided on a substrate (not shown). The insulating layer 11 functions as an underlayment insulating layer.

[0056] The transistor 10 includes a semiconductor layer 21, an insulating layer 22 that functions as a gate insulating layer, a conductive layer 23 that functions as a gate electrode, a conductive layer 24 that functions as one of the source electrode and drain electrode, and a conductive layer 26 that functions as the other of the source electrode and drain electrode. Here, an example is shown in which the conductive layer 24 has a conductive film 24a and a conductive film 24b located thereon.

[0057] The capacitive element 30 is provided on a conductive layer 55 that functions as wiring CL. The capacitive element 30 has a conductive layer 51 that functions as a lower electrode, a conductive layer 24 that functions as an upper electrode, and an insulating layer 52 that is placed between them and functions as a dielectric. In this way, it is preferable that the conductive layer 24 serves as both the lower electrode of the transistor 10 and the upper electrode of the capacitive element 30. This simplifies the manufacturing process and reduces manufacturing costs. As shown in Figure 2, etc., when the conductive layer 24 has a laminated structure of conductive film 24a and conductive film 24b, the conductive film 24a located at the bottom can be configured to function as the upper electrode of the capacitive element 30. In this case, the conductive film 24b located at the top can also be said to function as a connecting electrode for connecting the conductive film 24a and the semiconductor layer 21.

[0058] A conductive layer 55 is provided on the insulating layer 11. Here, an example is shown where the conductive layer 55 has a two-dimensional flat plate shape, but it can also be a wiring that extends in the X direction, Y direction, or other directions. Alternatively, it can be a grid shape that combines two or more parts that extend in different directions.

[0059] An insulating layer that functions as a protective insulating layer may be provided between the insulating layer 11 and the conductive layer 55. Alternatively, the insulating layer 11 may function as a protective insulating layer. The insulating layer has the function of preventing impurities such as hydrogen from diffusing into the semiconductor layer 21 from the insulating layer 11 or from below the insulating layer 11. For example, films that are less susceptible to hydrogen diffusion (have hydrogen barrier properties) than silicon oxide films, such as silicon nitride films, silicon oxide films, aluminum oxide films, magnesium oxide films, hafnium oxide films, and gallium oxide films, can be used. In particular, it is preferable to use silicon nitride films or silicon oxide films.

[0060] In this specification, the term "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and the term "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0061] An insulating layer 46 is provided on the conductive layer 55. The insulating layer 46 functions as an interlayer insulating layer. The insulating layer 46 has a plurality of openings 40 that reach the conductive layer 55, and one capacitive element 30 is provided for each opening 40. The conductive layer 51 has a portion provided along the side surface of the opening 40 of the insulating layer 46 and a portion in contact with the upper surface of the conductive layer 55. In other words, the conductive layer 51 has a cylindrical (also called cup-shaped) shape with a bottom and has a recess. The insulating layer 52 has a portion provided along the recess of the conductive layer 51, a portion in contact with the upper surface of the conductive layer 51 and a portion in contact with the upper surface of the insulating layer 46. The conductive layer 24 is provided so as to fill the recess of the conductive layer 51 via the insulating layer 52. The conductive layer 24 also has a portion provided on the insulating layer 46 via the insulating layer 52. The conductive layer 51 is provided individually for each memory cell 15 and is connected by the conductive layer 55. On the other hand, the conductive layer 24 is provided individually for each memory cell 15.

[0062] The side surface of the insulating layer 46 within the opening 40 is preferably perpendicular or approximately perpendicular to the substrate surface or the surface to be formed. By having the diameter of the opening 40 remain approximately the same from top to bottom without decreasing, the capacitance of the capacitive element 30 can be increased.

[0063] In this specification, two surfaces are perpendicular if their interior angle is between 80 degrees and 100 degrees. Two surfaces are approximately perpendicular if their interior angle is between 60 degrees and 120 degrees (including perpendicular). Two surfaces are parallel if their interior angle is between -10 degrees and 10 degrees. Two surfaces are approximately parallel if their interior angle is between -30 degrees and 30 degrees (including parallel).

[0064] Here, an example is shown where the contour of the conductive layer 51 in plan view (the contour of the opening 40) is circular, but it is not limited to this. Therefore, the horizontal cross-sectional shape of the conductive layer 51 is not limited to annular shape, but can be ring-shaped. For example, the shape of the contour of the conductive layer 51 in plan view and the horizontal cross-sectional shape are not limited to circular, but can be elliptical, a quadrilateral with rounded corners, etc. Also, it can be a regular polygon such as an equilateral triangle, square, or regular pentagon, or a polygon other than a regular polygon. Furthermore, if it is a concave polygon, such as a star polygon, where at least one interior angle exceeds 180 degrees, the capacity can be increased. Other shapes that can be used include polygons with rounded corners, closed curves that combine straight and curved lines, etc.

[0065] The capacitive element 30 illustrated in Figure 2, etc., is a so-called cylindrical or trench-type capacitive element. The configuration of the capacitive element 30 is not limited to this; for example, a pillar-type capacitive element may also be used.

[0066] Figure 2 shows an example where the bottom of the conductive layer 51 is rounded (has a concave surface). Furthermore, the bottoms of the insulating layer 52 provided along the conductive layer 51 and the conductive layer 24 provided along the insulating layer 52 also have a rounded shape (convex surface). In this way, by configuring the conductive layer 51, which forms the surface on which the insulating layer 52 is formed, to have no corners, it is possible to prevent the insulating layer 52 from becoming locally thin. Furthermore, because the bottom of the conductive layer 51 does not have corners, it is possible to prevent localized concentration of electric fields. As a result, the leakage current of the capacitive element can be suppressed, and thus reliability can be improved.

[0067] Furthermore, a rounded recess is provided on the upper surface of the conductive layer 55, and the bottom of the conductive layer 51 is positioned to engage with this recess. This configuration increases the contact area between the conductive layer 55 and the conductive layer 51, thereby reducing the contact resistance between them. The recess in the conductive layer 55 can be formed by etching a portion of the upper part of the conductive layer 55 when forming an opening in the insulating layer 46.

[0068] It is preferable to use a conductive material with lower resistance than conductive film 24b for conductive film 24a. In particular, it is preferable to include a metallic material. It is preferable to use a conductive metal oxide (oxide conductor) for conductive film 24b.

[0069] Using a conductive metal oxide in the conductive film 24b that contacts the semiconductor layer 21 containing a metal oxide is preferable because it reduces the contact resistance and thus the load on the wiring. In particular, it is preferable that the conductive film 24b contains the same metal element as the metal element contained in the semiconductor layer 21, as this further reduces the contact resistance. Specifically, it is preferable that both the semiconductor layer 21 and the conductive film 24b contain the same one or more elements selected from In, Sn, Zn, Ga, and Ti. Furthermore, by using a metal material with lower resistance than the conductive film 24b for the conductive film 24a, it is possible to reduce both the contact resistance and the wiring resistance, thereby further reducing the load on the wiring.

[0070] An insulating layer 41 is provided above the conductive layer 24 and the insulating layer 52. The insulating layer 41 has a strip-shaped slit 20 extending in the Y direction. As shown in Figures 3 to 5, the slit 20 reaches the conductive layer 24 (more specifically, the conductive film 24b). In areas where the conductive layer 24 is not provided, the insulating layer 41a is located at the bottom of the slit 20.

[0071] The side surface of the insulating layer 41 in the slit 20 is preferably inclined with respect to the substrate surface or the surface to be formed. In particular, it is preferable that the width of the slit 20 narrows from the top to the bottom. For example, the angle θ between the side surface of the insulating layer 41 in the slit 20 and the upper surface of the conductive layer 24 that is in contact with the insulating layer 41 is 60 degrees or more and less than 90 degrees, preferably 70 degrees or more and less than 90 degrees, more preferably 75 degrees or more and less than 90 degrees, and even more preferably 80 degrees or more and less than 90 degrees.

[0072] In the process of forming the slit 20 in the insulating layer 41, if the slit 20 is processed approximately vertically, it is necessary to pre-make the width of the slit 20 smaller than the width of the conductive layer 24 to account for positional misalignment during processing. On the other hand, by processing the slit 20 so that its width decreases towards the bottom, the width of the upper part of the slit 20 and the width of the conductive layer 24 can be made to be approximately the same size. As a result, it becomes unnecessary to consider the positional misalignment mentioned above, the width of the conductive layer 24 can be processed with the minimum processing dimensions, making it possible to bring adjacent memory cells 15 closer together and facilitating high integration.

[0073] The semiconductor layer 21, the insulating layer 22, and the conductive layer 23 each have portions located within the slit 20. The semiconductor layer 21 is provided along the upper surface of the insulating layer 41 and along the side surface of the insulating layer 41 within the slit 20. The insulating layer 22 is provided within the slit 20, covering the upper surface of the semiconductor layer 21. The conductive layer 23 is provided, covering the upper surface of the insulating layer 22.

[0074] The conductive layer 23 is provided so as to be embedded in the slit 20. At this time, the upper surface of the conductive layer 23 is positioned lower than the upper surface of the insulating layer 41. Furthermore, inside the slit 20, an insulating layer 43 and an insulating layer 44 are provided on the conductive layer 23. The insulating layer 43 is provided along the surfaces of the insulating layer 22 and the conductive layer 23, and the insulating layer 44 is provided so as to fill the recess on the upper surface of the insulating layer 43.

[0075] Since the semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the slit 20 of the insulating layer 41, the thickness of this portion may be reduced depending on the deposition method. For example, in deposition methods such as sputtering or plasma CVD (Chemical Vapor Deposition), films deposited on surfaces inclined or perpendicular to the substrate surface tend to be thinner compared to films deposited on surfaces parallel to the substrate surface. On the other hand, deposition methods such as atomic layer deposition (ALD) or thermal CVD can deposit films of uniform thickness regardless of the angle of the surface to be deposited.

[0076] Here, within the slit 20, the uppermost surfaces of the insulating layers 22, 43, and 44 are flattened. Furthermore, it is preferable that the height of each of these flattened upper surfaces roughly coincides with the upper surface of the portion of the semiconductor layer 21 located on the insulating layer 41. The conductive layer 26 is provided in contact with the upper surface of the semiconductor layer 21 in the region overlapping with the insulating layer 41, and in contact with the upper surfaces of the insulating layers 22, 43, and 44 in the region overlapping with the slit 20. As shown in Figure 3, the conductive layer 23 and the conductive layer 26 are insulated from the insulating layer 44 and the insulating layer 43.

[0077] The insulating layer 43 functions as a protective insulating layer that prevents impurities such as water and hydrogen contained in the insulating layer 44 from diffusing into the semiconductor layer 21 via the conductive layer 23, insulating layer 22, etc. The insulating layer 43 can be made of a material that can be used as a protective insulating layer as described above. On the other hand, the insulating layer 44 functions as an interlayer insulating layer, and it is preferable to use a material with a low dielectric constant such as silicon oxide.

[0078] The slit 20 and the conductive layer 26 are provided to extend in intersecting directions. Here, an example is shown in which the slit 20 extends in the Y direction and the conductive layer 26 extends in the X direction. The conductive layer 23, insulating layer 22, insulating layer 43, and insulating layer 44 provided inside the slit 20 are also provided to extend in the Y direction.

[0079] Within the slit 20, insulating layers 43 and 44 are provided between the conductive layer 23 and the conductive layer 26 at their intersection. This reduces the parasitic capacitance between the conductive layer 23 and the conductive layer 26.

[0080] Furthermore, an insulating layer 47 is provided covering the conductive layer 26. The insulating layer 47 functions as a protective insulating layer that prevents the diffusion of impurities such as water and hydrogen from the outside. The insulating layer 47 can be made of the same material as the insulating layer 43. Note that the insulating layer 47 may be omitted if it is not needed.

[0081] In transistor 10, since the source electrode and drain electrode are located at different heights, the current flowing through the semiconductor flows in the height direction. That is, the channel length direction can be said to have a component in the height direction (vertical direction), and therefore, a transistor according to one aspect of the present invention can also be called a VFET, vertical transistor, vertical channel transistor, etc. In transistor 10, two or more of the source electrode, semiconductor, and drain electrode can be stacked, so the occupied area can be significantly reduced compared to a so-called planar type transistor (which can also be called a lateral transistor, LFET (Lateral FET), etc.) in which the semiconductor is arranged on a plane.

[0082] Furthermore, the channel length of transistor 10 can be precisely controlled by the thickness of the insulating layer 41, which functions as a spacer, thus significantly reducing the variation in channel length compared to planar transistors. Moreover, by thinning the insulating layer 41, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and with channel lengths of 5 nm or more, 7 nm or more, or 10 nm or more can be fabricated. Therefore, transistors with extremely small channel lengths, which were not possible with mass-production exposure equipment, can be realized. Additionally, transistors with channel lengths of less than 10 nm can be realized without using the extremely expensive exposure equipment used in state-of-the-art LSI technology.

[0083] Various semiconductor materials can be used for the semiconductor layer 21, but it is particularly preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor with both high on-current and extremely low off-current can be realized at low cost. Unless otherwise specified, the following describes an example configuration in which an oxide semiconductor is used for the semiconductor layer 21.

[0084] In Figure 2, etc., an example is shown where the upper surface of the region of the conductive film 24b that overlaps with the slit 20 has a rounded recess (concave surface). As a result, within the slit 20, the bottoms of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are arranged along the concave surface of the conductive film 24b, and each has a rounded convex portion (convex surface). This makes it possible to realize a configuration in which the electric field is less likely to concentrate, similar to the conductive layer 51 of the capacitive element 30. Therefore, it is possible to realize a transistor with low leakage current and high reliability.

[0085] Here, we show an example in which the insulating layer 41 has a laminated structure in which insulating layer 41a, insulating layer 41b, and insulating layer 41c are stacked in this order from the insulating layer 52 side.

[0086] The semiconductor layer 21 is provided in contact with the inner wall of the slit 20 of the insulating layer 41. It is preferable to use an oxide insulating film for the insulating layer 41b. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. It is also preferable to have a structure in which the insulating layer 41b is sandwiched between insulating layers 41a and 41c, which have barrier properties against oxygen. This makes it possible to confine the oxygen contained in the insulating layer 41b to the region surrounded by insulating layers 41a, 41c, and the semiconductor layer 21. Furthermore, it is possible to prevent the oxygen in the insulating layer 41b from being desorbed and reduced during the process. This makes it possible to supply oxygen to the semiconductor layer 21 more efficiently.

[0087] The portion of the semiconductor layer 21 that is in contact with the insulating layer 41b is a region with reduced oxygen vacancies and can be called an i-type region. On the other hand, it is preferable that the portion that is not in contact with the insulating layer 41b be an n-type region containing many carriers. In other words, the portion of the semiconductor layer 21 that is in contact with the insulating layer 41b can be called the channel-forming region, and the region outside of that can be called the low-resistance region (also called the source region or drain region).

[0088] Since the insulating layer 41b is in contact with the semiconductor layer 21, it is preferable to use a film that contains as little hydrogen as possible. Hydrogen carriers can be generated when oxygen vacancies in the semiconductor layer 21 combine with hydrogen, which may affect, for example, the threshold voltage of the transistor 10. Therefore, an insulating film other than an oxide insulating film that does not easily allow hydrogen to diffuse may be used for the insulating layer 41b. For example, a single layer of an insulating film that has barrier properties against hydrogen and oxygen can be used as the insulating layer 41.

[0089] The insulating layer 41b can be used as an interlayer insulating film. For example, it is preferable to form it using a film deposition method such as sputtering or plasma CVD. In particular, using a sputtering method that does not use hydrogen as the deposition gas makes it possible to create a film with an extremely low hydrogen content. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0090] Since the insulating layer 41b is in contact with the channel formation region of the semiconductor layer 21, it is preferable to use an oxide insulating film. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. As the insulating layer 41b, it is preferable to use, for example, silicon oxide or silicon oxynitride.

[0091] Furthermore, since the insulating layer 41b functions as an interlayer insulating layer, it is preferable to use a film deposition method that allows for film deposition at a higher rate compared to other insulating layers. For example, an insulating film formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) by plasma CVD may be used as the insulating layer 41b. This can improve productivity.

[0092] It is preferable to use films that do not easily allow hydrogen to diffuse for insulating layers 41a and 41c. By sandwiching insulating layer 41b above and below with insulating layers 41a and 41c that do not easily allow hydrogen to diffuse, it is possible to prevent hydrogen from entering the insulating layer 41b that is in contact with the semiconductor layer 21 from the outside.

[0093] For insulating layer 41a and insulating layer 41c, one or more of the following can be used, for example: silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, and hafnium aluminate. In particular, silicon nitride and silicon oxide nitride are suitable for use as insulating layer 41a and insulating layer 41c because they release little impurities (e.g., water and hydrogen) from themselves and are less permeable to oxygen and hydrogen.

[0094] [Example 1] The following describes an example with a configuration that differs in some respects from the above example. Parts that overlap with the above should be referred to, and explanations will be omitted. Note that in the following drawings, the parts below the insulating layer 41a and conductive film 24a may be omitted.

[0095] Figure 6(A) shows an example where the side surface of the insulating layer 41 in the slit 20 is approximately perpendicular to the surface to be formed. In this case, it is preferable to make the width of the conductive layer 24 larger than the width of the slit 20. This prevents the problem of the slit 20 being formed outside the conductive layer 24 even if misalignment occurs.

[0096] As shown in Figure 6(A), if the width of the slit 20 is approximately uniform from top to bottom, the channel length of the transistor 10 matches the thickness of the insulating layer 41b, which not only simplifies the design but also makes variations in channel length extremely small.

[0097] Furthermore, as shown in Figure 6(B), within the slit 20, the side surface of the insulating layer 41b may be approximately perpendicular to the surface to be formed, while the side surface of the insulating layer 41a may be inclined with respect to the direction perpendicular to the surface to be formed. By giving the slit 20 such a shape, the channel length (i.e., the length of the portion in contact with the insulating layer 41b) can be made to match the thickness of the insulating layer 41b, as in Figure 6(A), and the width of the conductive layer 24 and the width of the upper end of the slit 20 can be made to match, as in the above configuration example. For example, by using different materials for the insulating layer 41b and the insulating layer 41a, it becomes easy to form a slit 20 with different inclination angles on the sides of the insulating layer 41b and the insulating layer 41a.

[0098] The configuration shown in Figure 7(A) is an example in which a conductive layer 25 is provided between the upper surface of the insulating layer 41c and the semiconductor layer 21.

[0099] The semiconductor layer 21 is in contact with the upper surface and the side surface on the slit 20 side of the conductive layer 25. The conductive layer 25 functions as auxiliary wiring to support the conductivity of the semiconductor layer 21. By providing the conductive layer 25, the on-current of the transistor can be increased.

[0100] Similar to the conductive layer 24, it is preferable that the conductive layer 25 uses a conductive metal oxide in at least the portion in contact with the semiconductor layer 21. Specifically, it is preferable that both the semiconductor layer 21 and the conductive layer 25 contain the same one or more elements selected from In, Sn, Zn, Ga, and Ti. Alternatively, the conductive layer 25 can be made into a laminated structure, with the conductive metal oxide used in the upper layer in contact with the semiconductor layer 21 and a low-resistance metal material used in the lower layer.

[0101] Figure 7(B) shows an example where the conductive layer 25 is applied to the configuration shown in Figure 6.

[0102] The configuration shown in Figure 8 differs from the configuration exemplified in Figure 7(A) mainly in the shape of the semiconductor layer 21.

[0103] In Figure 8, the semiconductor layer 21 is located only in the region overlapping with the slit 20 and is not provided between the conductive layer 25 and the conductive layer 26. In the region overlapping with the slit 20, the semiconductor layer 21 is in contact with the side surface of the conductive layer 25. Also, the conductive layer 26 is in contact with the upper surface of the conductive layer 25 in the region overlapping with the insulating layer 41. Furthermore, the flattened upper end of the semiconductor layer 21 is in contact with the conductive layer 26. Therefore, the conductive layer 26 and the semiconductor layer 21 are electrically connected.

[0104] For example, if the semiconductor layer 21 is extremely thin, it may be difficult to expose the upper surface of the semiconductor layer 21 by the planarization process. In such cases, it is preferable to provide a conductive layer 25 and perform the planarization process until the upper surface of the conductive layer 25 is exposed, rather than using a structure without a conductive layer 25 as shown in Figure 3, thereby obtaining the configuration shown in Figure 8.

[0105] [Differentiation 2] The configuration shown in Figure 9 differs from the above mainly in that two transistors (transistors 10a) are provided in a single slit 20.

[0106] The semiconductor layer 21, insulating layer 22, conductive layer 23, and conductive layer 24 are divided into two parts within the slit 20 along the direction of extension of the slit 20 (Y direction). The semiconductor layer 21 and insulating layer 22 are provided along one of the pair of sides of the insulating layer 41 within the slit 20.

[0107] A capacitive element 30 is provided in each of the separated conductive layers 24. This allows a configuration in which two memory cells 15 share one slit 20. In this case, two openings 40 are provided for each slit 20. The openings 40 are positioned offset in the X direction from the center of the slit 20.

[0108] Furthermore, an insulating layer 48 is provided along the conductive layer 23, the insulating layer 22, the semiconductor layer 21, the sides of the conductive layer 24, and the upper surface of the insulating layer 52. A recess is formed on the upper surface of the insulating layer 48, and an insulating layer 44 is provided on the insulating layer 48 so as to fill the recess. Preferably, the insulating layer 48 functions as a barrier film against impurities, similar to the insulating layer 43. This prevents impurities such as hydrogen contained in the insulating layer 44 from diffusing into the semiconductor layer 21.

[0109] [Difference 3] In this case, it is preferable that the semiconductor device 50 is provided by stacking a layer on which the memory cell 15 is provided and a layer on which the functional circuit is provided. The functional circuit may include, for example, a drive circuit for driving the memory cell 15, as well as an arithmetic circuit, a power supply circuit, etc. The drive circuit may include one or more of the following: a row decoder, a column decoder, a row driver, a column driver, an input circuit, an output circuit, a sense amplifier, etc. This makes it possible to reduce the footprint of the semiconductor chip including the semiconductor device 50, and also makes it possible to shorten the wiring length compared to when the functional circuit and the memory cell 15 are arranged side by side, thereby enabling high-speed operation and low power consumption.

[0110] Figure 10 shows an example in which a layer 80 on which the memory cell 15 is provided is placed, and a transistor 90 constituting a functional circuit is placed below it. In this example, one of the source electrode and drain electrode of the transistor 90 is connected to a conductive layer 26 that functions as a bit line.

[0111] Transistor 90 is a transistor in which a channel is formed in a part of a substrate 91, which is a single-crystal semiconductor substrate. Typically, single-crystal silicon can be used for the substrate 91. Alternatively, the substrate 91 can be a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. In addition, a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, may be used for the substrate 91.

[0112] The transistor 90 is provided on the substrate 91 and includes a conductive layer 94 that functions as a gate, an insulating layer 93 that functions as a gate insulating layer, a semiconductor region 92 that is part of the substrate 91, and low-resistance regions 95a and 95b that function as a source region or drain region. The transistor 90 can be either a p-channel or n-channel type. An element isolation layer 98 is provided on the substrate 91 between two adjacent transistors 90.

[0113] The transistor 90 has a convex (fin-shaped) semiconductor region 92 in which the channel is formed. Although not shown in Figure 10, in the Y direction, the sides and top surface of the semiconductor region 92 are covered by a conductive layer 94 via an insulating layer 93. Such a transistor 90 is also called a FIN-type transistor.

[0114] An insulating layer 96 is provided covering the transistor 90, an insulating layer 86 is provided on the insulating layer 96, and an insulating layer 87 is provided on the insulating layer 86. A conductive layer 81 is provided so as to be embedded in the insulating layer 87. An insulating layer 88 is provided covering the conductive layer 81 and the insulating layer 87, an insulating layer 45 is provided on the insulating layer 88, and an insulating layer 11 is provided on the insulating layer 45. A plug 82 is provided inside the openings in the insulating layer 96 and the insulating layer 86, and the conductive layer 81 and the low-resistance region 95b are connected by the plug 82. A conductive layer 84 is provided on the insulating layer 45, and the conductive layer 84 and the conductive layer 81 are connected by a plug 83 provided inside the openings in the insulating layer 45 and the insulating layer 88. The conductive layer 84 and the conductive layer 26 are connected via plugs 85 provided inside the openings in each insulating layer between them. As a result, the conductive layer 26 is connected to either the source or drain of the transistor 90.

[0115] In this example, a conductive layer 81 is provided as a wiring layer. However, the layer on which the transistor 90 is provided and the layer on which the memory cell 15 is provided can be configured in which interlayer insulating layers and wiring layers are alternately stacked (also called a multilayer wiring layer).

[0116] Figure 11 shows an example in which layers 80 having memory cells 15 are stacked. In Figure 11, an example is shown in which three layers 80 (layers 80[1] to [3] from the substrate 91 side) are stacked, but there may be two layers or four or more layers.

[0117] Plug 85 connects conductive layer 84 to the conductive layer 26 of layer 80[1]. Plug 89 connects the conductive layers 26 of the two layers 80 to each other. As a result, a total of three conductive layers 26 of layers 80[1] to [3] are connected to either the source or the drain of the transistor 90.

[0118] Here, a configuration is shown in which layer 80 is directly laminated on the substrate 91 on which the transistor 90 is provided, but this is not the only configuration. For example, the substrate 91 on which the transistor 90 is provided and the substrate on which the memory cell 15 is provided may be bonded together. For example, two substrates can be bonded together by direct bonding (hybrid bonding) using direct bonding technology such as Cu-Cu junctions. Alternatively, a method may be used in which electrodes provided in each layer are connected by forming through electrodes after bonding two or more layers together with insulating films. In particular, using a method that utilizes direct bonding or through electrodes is preferable because it is possible to make the pitch of the connecting electrodes extremely narrow, making it possible to arrange a large number of connecting electrodes at high density and thus increasing the amount of data transmitted between layers.

[0119] When joining two layers, any of the following methods may be used: CoC (Chip on Chip), CoW (Chip on Wafer), or WoW (Wafer on Wafer). WoW bonding offers excellent productivity because it bonds wafers together, but it can lead to a decrease in yield because it bonds all chips, including both good and defective chips. On the other hand, CoW bonding, which bonds chips to wafers, and CoC bonding, which bonds chips together, are less productive than WoW bonding, but they significantly improve yield because they bond only good chips together. Furthermore, while CoC bonding is less productive than the other two, it offers superior versatility because it can bond two layers even if their sizes differ significantly.

[0120] Furthermore, a wiring layer such as an interposer may be provided between the two layers. This eliminates the need to align the positions of the bonding electrodes in two adjacent layers, thereby increasing the design flexibility of each layer and enabling the realization of a higher-performance semiconductor device.

[0121] [About the components] <substrate> As substrates for forming transistors, for example, insulating substrates, semiconductor substrates, or conductive substrates can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates having metal nitrides or metal oxides can also be used. Furthermore, there are substrates in which a conductive layer or semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or insulating layer is provided on a conductive substrate. Alternatively, substrates on which elements are provided may be used. Elements that can be placed on a circuit board include capacitive elements, resistive elements, switching elements (including transistors), light-emitting elements, and memory elements.

[0122] <Semiconductor layer> The semiconductor layer 21 preferably has a metal oxide (oxide semiconductor).

[0123] It is preferable to use indium oxide as the semiconductor layer 21.

[0124] Furthermore, indium oxide may contain metallic elements that can form positive ions (also called cations). For example, indium oxide doped with metal oxides such as Ge, W, Ga, Sb, Bi, Sn, and Ti can be used. Doping an indium oxide film with such oxides can reduce oxygen deficiencies, indium deficiencies, or both in the indium oxide, thereby improving reliability.

[0125] Examples of metal oxides that can be used in the semiconductor layer 21 include Ga oxide and Zn oxide. The metal oxide preferably contains at least In or Zn. Furthermore, the metal oxide preferably has two or three elements selected from In, element M, and Zn. Element M is a metal or metalloid element with a high bond energy with oxygen, for example, a metal or metalloid element with a higher bond energy with oxygen than indium. Specific examples of element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. A metal oxide containing In, M, and Zn may hereafter be referred to as In-M-Zn oxide. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the term "metallic elements" used in this specification may include metalloid elements.

[0126] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of M. For example, possible atomic ratios of metal elements in such an In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, or compositions near these. Note that compositions near these include a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in a metal oxide, the on-current or field-effect mobility of a transistor can be increased.

[0127] Furthermore, the atomic ratio of In in an In-M-Zn oxide may be less than the atomic ratio of M. For example, possible atomic ratios of metal elements in such an In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or compositions close to these. Increasing the atomic ratio of M in the metal oxide can suppress the formation of oxygen vacancies.

[0128] The semiconductor layer 21 can be, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-W oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, or In-Ga-Al-Zn oxide. Ga-Zn oxide may also be used. Using a material containing Zn is preferable because it makes it easier to achieve high crystallinity.

[0129] Furthermore, the metal oxide may contain, in place of indium, or in addition to indium, one or more metal elements with high periodic numbers in the periodic table. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, including metal elements with high periodic numbers can sometimes increase the field-effect mobility of the transistor. Examples of metal elements with high periodic numbers include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specifically, examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0130] Furthermore, metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can sometimes increase the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0131] The formation of metal oxides can preferably use a sputtering method or an atomic layer deposition (ALD) method. In particular, it is preferable to form a metal oxide by the ALD method, which has excellent coating properties. When forming a metal oxide by the sputtering method, the composition of the metal oxide after film formation may be different from the composition of the target. In particular, for zinc, the content rate in the metal oxide after film formation may decrease to about 50% compared to the target.

[0132] In this specification and the like, the content rate of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are A X , A Y , A Z respectively, the content rate of metal element X can be expressed as A X / (A X +A Y +A Z ). Also, when the ratio of the number of atoms (atomic ratio) of metal element X, metal element Y, and metal element Z in the metal oxide is B X :B Y :B Z , the content rate of metal element X can be expressed as B X / (B X +B Y +B Z ).

[0133] For example, in the case of a metal oxide containing In, by increasing the content rate of In, a transistor with a large on-current can be realized.

[0134] By using a metal oxide that does not contain Ga, or has a low Ga content, in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. In other words, a transistor with small fluctuations in the threshold voltage in PBTS (Positive Bias Temperature Stress) testing can be obtained. Furthermore, when using a metal oxide containing Ga, it is preferable to have a lower Ga content than an In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0135] On the other hand, increasing the Ga content can result in a transistor that is highly reliable against light. In other words, it is possible to create a transistor with a smaller threshold voltage fluctuation in NBTIS (Negative Bias Temperature Illumination Stress) testing. Specifically, metal oxides in which the atomic ratio of Ga is greater than or equal to the atomic ratio of In have a larger band gap, which reduces the threshold voltage fluctuation in the transistor's NBTIS testing.

[0136] Furthermore, increasing the zinc content results in a highly crystalline metal oxide, which suppresses the diffusion of impurities within the metal oxide. Consequently, fluctuations in the transistor's electrical characteristics are suppressed, improving reliability.

[0137] The semiconductor layer 21 may be a laminated structure having two or more metal oxide layers. The two or more metal oxide layers of the semiconductor layer 21 may have the same or approximately the same composition. By using a laminated structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs. Alternatively, a laminated structure may be formed by stacking two or more oxide semiconductor layers with different compositions. Furthermore, by using the ALD method, it is possible to form metal oxide layers with continuously different compositions in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the formation of interface states between two layers with different compositions, thereby improving electrical properties and reliability. In addition, a metal oxide layer with a laminated structure may be formed using both the sputtering method and the ALD method.

[0138] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (high conductivity) than the first layer for the second layer, i.e., the side closer to the gate electrode. This makes it possible to create a transistor that is normally off and has a large on-current. Therefore, it is possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than the second layer may be used for the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and making it possible to create a transistor with a large on-current.

[0139] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material with higher mobility for the second layer than for the first and third layers. This makes it possible to realize a transistor with high on-current and high reliability.

[0140] The differences in mobility and conductivity mentioned above can be attributed, for example, to the indium content. In addition, whether or not other elements that contribute to improved conductivity are present, or the content of those elements, also affect mobility and conductivity. Examples of high-mobility materials include materials with atomic ratios of metal elements such as In:Ga:Zn=4:2:3, In:Zn=1:1, In:Zn=2:1, In:Zn=4:1, In:Sn:Zn=40:X:10 (where X is between 0.1 and 5, typically X=1), or near these compositions. On the other hand, materials with lower mobility or conductivity compared to the above materials include materials with atomic ratios of metal elements such as In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:4, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, or near these compositions.

[0141] The semiconductor layer 21 preferably uses a crystalline metal oxide layer. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline structure, or a nanocrystalline (nc) structure can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0142] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the lower the defect level density in the semiconductor layer 21 can be. On the other hand, by using a metal oxide layer with low crystallinity, it is possible to realize a transistor that can carry a large current.

[0143] In particular, it is preferable to use indium oxide for the semiconductor layer 21. Especially preferable is the use of a single-crystal indium oxide film. While it is preferable to use a crystalline film for the semiconductor layer 21, and particularly preferable to use single-crystal indium oxide, polycrystalline or microcrystalline indium oxide can also be used. Using single-crystal indium oxide suppresses carrier scattering at grain boundaries, enabling the realization of a transistor with high field-effect mobility. Furthermore, it enables the realization of a highly reliable transistor. When using polycrystalline indium oxide, it is preferable that no grain boundaries are observed, at least in the channel-forming region (the region superimposed with the conductive layer 23). This allows polycrystalline indium oxide to achieve the same effects as single-crystal indium oxide.

[0144] The thickness of the semiconductor layer 21 is more preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 3 nm to 20 nm, and even more preferably 3 nm to 10 nm. By setting the thickness of the semiconductor layer 21 within the above range, the crystallinity of the semiconductor layer 21 can be improved.

[0145] Among highly crystalline oxide semiconductors, indium oxide is a film in which hydrogen and / or oxygen can move more easily compared to, for example, an IGZO (In-Ga-Zn-O based oxide) film. Therefore, indium oxide can be said to be a film in which hydrogen and / or oxygen can be supplied and expelled more easily compared to, for example, an IGZO film. As a result, excess oxygen or excess hydrogen that can become carriers or fixed charges is less likely to accumulate in the semiconductor layer 21, making it possible to create a transistor with good electrical characteristics and reliability.

[0146] It is preferable that the semiconductor layer 21 has a reduced concentration of elements that decrease crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less.

[0147] Furthermore, when indium oxide is used in the semiconductor layer 21, gallium that is unintentionally introduced has a tendency to bond with excess oxygen atoms, which can lead to a large fluctuation in the threshold voltage in the PBTS (Positive Bias Temperature Stress) test. For this reason, when indium oxide is used in the semiconductor layer 21, the gallium concentration in the semiconductor layer 21 is preferably 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less.

[0148] Transistors using oxide semiconductors (hereinafter referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors exhibit remarkably low source-drain leakage current (hereinafter also called off-current) in the off state, allowing them to retain charge stored in a capacitor connected in series with the transistor for extended periods. Additionally, the application of OS transistors can reduce the power consumption of semiconductor devices.

[0149] One aspect of the present invention is a semiconductor device that can be applied to, for example, a processor, a memory device, or various ICs. A transistor according to one aspect of the present invention has the characteristics of being able to conduct a large current and having an extremely low off-current, making it possible to simultaneously achieve high-speed operation of the circuit and low power consumption.

[0150] One embodiment of the present invention, a semiconductor device, can also be applied to a display device, for example. To increase the luminescence brightness of a light-emitting device included in the pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to silicon transistors (hereinafter referred to as Si transistors), OS transistors have a higher breakdown voltage between the source and drain, so a high voltage can be applied between the source and drain of an OS transistor. Therefore, by using an OS transistor as the drive transistor included in the pixel circuit, the amount of current flowing through the light-emitting device can be increased, and the luminescence brightness of the light-emitting device can be increased.

[0151] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by applying an OS transistor to the drive transistor in a pixel circuit, the amount of current flowing to the light-emitting device can be precisely controlled. This allows for a higher number of grayscale levels in the pixel circuit. Furthermore, even if there are fluctuations or variations in the electrical characteristics (e.g., resistance) of the light-emitting device, a stable current can be maintained.

[0152] As described above, by using OS transistors in the drive transistors included in the pixel circuit, it is possible to achieve "suppression of black level floating," "increase in luminous brightness," "multi-gradation," and "suppression of the effects of manufacturing variations in light-emitting devices."

[0153] OS transistors exhibit less fluctuation in electrical properties due to radiation exposure than Si transistors, meaning they have higher radiation resistance and can therefore be suitably used in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, protons, and neutrons).

[0154] The semiconductor material that can be used in the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of elemental materials or compound semiconductors can be used. Examples of semiconductors made of elemental materials include silicon (including single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) or germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, or oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0155] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. Such layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0156] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides applicable as semiconductor layers in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0157] The crystallinity of the semiconductor material used in the semiconductor layer 21 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (polycrystalline semiconductor, microcrystalline semiconductor, or semiconductor having a crystalline region in part) may be used. Using a crystalline semiconductor is preferable because it can suppress the degradation of transistor characteristics.

[0158] <Gate Insulation Layer> The insulating layer 22 functions as the gate insulating layer of the transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxide nitride, aluminum oxide, aluminum oxide nitride, hafnium oxide, hafnium oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, and Ga-Zn oxide can be used. In addition, nitride insulating films such as silicon nitride, silicon oxide nitride, aluminum nitride, and aluminum oxide nitride can also be used as the insulating layer 22. Furthermore, the insulating layer 22 may have a laminated structure, for example, a laminated structure having one or more oxide insulating films and one or more nitride insulating films.

[0159] Furthermore, the insulating layer 22 is preferably made of a laminated insulating material consisting of a material with a high dielectric constant (high-k), and it is preferable to use a laminated structure of a high-k material and a material with a higher dielectric strength than the high-k material. For example, as the insulating layer 22, an insulating film (also called ZAZ) laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. Alternatively, for example, an insulating film (also called ZAZA) laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Alternatively, for example, an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By using a laminated insulating material with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic discharge breakdown of the capacitive element can be suppressed.

[0160] Furthermore, a ferroelectric material may be used as the insulating layer 22. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO. X Examples of metal oxides include (where X is a real number greater than 0).

[0161] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having the function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and an insulating film having barrier properties against hydrogen as the film located on the conductive layer 23 side which functions as the gate electrode. This suppresses the diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0162] It is preferable to use a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as an insulating film that captures or fixes hydrogen. Furthermore, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film as an insulating film that has barrier properties against hydrogen.

[0163] Alternatively, an insulating film that releases oxygen upon heating may be used in the film in contact with the semiconductor layer 21, and an insulating film that has a barrier property against hydrogen may be used in the film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen upon heating may be used in the film in contact with the semiconductor layer 21, and an insulating film that has the function of capturing or fixing hydrogen may be used in the film located on the conductive layer 23 side.

[0164] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film having an oxygen-diffusing material for the film in contact with the semiconductor layer 21, an insulating film having barrier properties against hydrogen and oxygen for the film located on the conductive layer 23 side, and an insulating film having the function of capturing or fixing hydrogen for the film located between these. Silicon oxide or silicon oxynitride can be used as the oxygen-diffusing material. With this configuration, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. In addition, the film located on the conductive layer 23 side prevents the diffusion of oxygen to the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0165] As insulating films that have barrier properties against oxygen, it is preferable to use aluminum oxide films, silicon nitride films, hafnium oxide films, hafnium silicate films, etc. As insulating films that have barrier properties against oxygen and hydrogen, it is preferable to use aluminum oxide films, silicon nitride films, hafnium oxide films, etc.

[0166] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film that has barrier properties against oxygen for the film in contact with the semiconductor layer 21, followed by an insulating film made of a material that allows oxygen to diffuse easily from the side closer to the semiconductor layer 21, an insulating film that has the function of capturing or fixing hydrogen, and an insulating film that has barrier properties against hydrogen and oxygen. In other words, in addition to the three-layer structure described above, a configuration can be adopted in which a film in contact with the semiconductor layer 21 is added. By using an insulating film that has barrier properties against oxygen for the film in contact with the semiconductor layer 21, the detachment of oxygen from the semiconductor layer 21 can be suppressed. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has barrier properties against oxygen but also has the function of capturing or fixing hydrogen, thus also preventing the diffusion of hydrogen into the semiconductor layer 21.

[0167] When the insulating layer 22 has a laminated structure, it is preferable that each insulating film is a thin film. For example, by setting the thickness of the insulating layer 22 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also called the S value) of the transistor can be reduced. Furthermore, the thickness of each insulating film is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and still preferably 1 nm or more and 3 nm or less.

[0168] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 21 side, with the thicknesses of these layers being 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0169] In this specification, barrier properties refer to the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). When hydrogen is described as the corresponding substance, it refers to, for example, hydrogen atoms, hydrogen molecules, and water molecules and OH -This refers to at least one substance bonded with hydrogen, such as [specific examples of hydrogen-containing substances]. Furthermore, when an impurity is described as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, and refers to at least one of the following: hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of the following: oxygen atoms, oxygen molecules, etc.

[0170] Here, transistors using metal oxide films can have their electrical properties stabilized by surrounding them with an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen. Examples of insulating films that have the function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or oxides containing aluminum and hafnium (hafnium aluminate). Nitrides such as aluminum nitride, silicon nitride, and silicon nitride can also be used.

[0171] Examples of insulating film materials having the function of capturing or fixing hydrogen include metal oxides such as hafnium-containing oxides, magnesium-containing oxides, aluminum-containing oxides, and aluminum and hafnium-containing oxides (hafnium aluminate). These metal oxides may also contain zirconium; for example, oxides containing hafnium and zirconium are examples. In metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, resulting in a high ability to capture or fix hydrogen. Therefore, it is preferable that these metal oxides have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Note that metal oxides may have one or both crystalline regions and / or grain boundaries in some parts.

[0172] <Conductive layer> The conductive layer 24 and conductive layer 25 are in contact with the semiconductor layer 21. Here, if an oxide semiconductor is used as the semiconductor layer 21, and an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or conductive layer 25 that is in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or conductive layer 25 and the semiconductor layer 21, which may hinder conductivity. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material in at least the portion of the conductive layer 24 and conductive layer 25 that is in contact with the semiconductor layer 21.

[0173] As the conductive film in contact with the semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. These are preferred because they are conductive materials that are resistant to oxidation, or materials that maintain conductivity even after oxidation.

[0174] Alternatively, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. Conductive oxides containing indium are particularly preferred due to their high conductivity. Alternatively, oxide materials such as In-Ga-Zn oxide, which can be applied to the semiconductor layer 21, can also be used as a conductive layer by increasing the carrier concentration.

[0175] Furthermore, the conductive layer 24 and conductive layer 25 may be made of a low-resistance conductive material that can be used in the conductive layer 23 described later. In particular, it is preferable that the conductive layer 24 and conductive layer 25 have a laminated structure in which a layer containing a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material is used, and a layer containing a low-resistance conductive material is used.

[0176] It is preferable to use a low-resistance conductive material for conductive layers 23, 26, 51, 55, etc. For example, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing such a metal element. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0177] Furthermore, the conductive layers 23, 26, 51, 55, etc., may be made of nitrides and oxides that can be used for the conductive layers 24 and 25.

[0178] Since conductive layers 23, 24, and 25 also function as wiring, it is preferable to use low-resistance conductive materials in a laminated manner. For example, the conductive film 24a and conductive layer 25 can also be made of the same low-resistance conductive material that can be used for the conductive layer 23 described above.

[0179] <Insulating layer> The insulating layer 41 can be used as an interlayer insulating film. For example, it is preferable to form it using a film deposition method such as sputtering or plasma CVD. In particular, using the sputtering method eliminates the need to use hydrogen as a deposition gas, thus allowing for a film with an extremely low hydrogen content. This suppresses the supply of hydrogen to the semiconductor layer 21, thereby stabilizing the electrical characteristics of the transistor 10.

[0180] Since the insulating layer 41 is in contact with the channel formation region of the semiconductor layer 21, it is preferable to use an oxide insulating film. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. As the insulating layer 41, an oxide insulating film that can be used for the gate insulating layer described above can be applied.

[0181] Furthermore, since the insulating layer 41 functions as an interlayer insulating layer, it is preferable to use a film deposition method that allows for film deposition at a higher rate compared to other insulating layers. For example, as the insulating layer 41, a silicon oxide film (also called a TEOS film) deposited using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) by plasma CVD may be used. This can improve productivity.

[0182] The insulating layer 11, insulating layer 44, insulating layer 46, etc., each function as an interlayer insulating layer. Insulating materials that can be used for the insulating layer 41 can be used for the insulating layer 11, insulating layer 44, insulating layer 46, etc.

[0183] The insulating layer 52 functions as a dielectric for the capacitive element 30. The insulating layer 52 can be made from the same insulating material as the insulating layer 22. Furthermore, by using a ferroelectric material for the insulating layer 52, the capacitive element 30 can be made into a ferroelectric capacitor, thereby realizing a non-volatile memory device. Additionally, a resistive-type memory element utilizing the colossal electro-resistance (CER) effect can be used as the capacitive element 30.

[0184] The above is an explanation of the constituent elements.

[0185] [Example of manufacturing method] The following describes an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. Here, we will explain using a semiconductor device including the memory cell 15 exemplified in the above configuration example as an example.

[0186] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition.

[0187] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0188] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0189] CVD methods can be classified into plasma-enhanced chemical vapor deposition (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo-CVD, which utilizes light. Furthermore, they can be divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) methods depending on the source gas used.

[0190] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. Furthermore, thermal CVD avoids plasma damage during film formation, resulting in films with fewer defects.

[0191] ALD methods include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants.

[0192] Unlike sputtering, CVD and ALD are film deposition methods that are less affected by the shape of the workpiece and provide good step-level coverage. In particular, ALD is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coverage and excellent thickness uniformity. However, since ALD has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods that have a faster deposition rate, such as CVD.

[0193] In the CVD method, films of any composition can be deposited by changing the flow rate ratio of the raw material gases. For example, in the CVD method, by changing the flow rate ratio of the raw material gases while the film is being deposited, films with continuously changing compositions can be deposited. When depositing films while changing the flow rate ratio of the raw material gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time required for transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0194] In the ALD method, films of any composition can be deposited by using multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, films of any composition can be deposited by controlling the number of cycles for each precursor. Furthermore, similar to the CVD method, films with continuously changing compositions can be deposited.

[0195] Furthermore, the thin films constituting the semiconductor device can be processed using methods such as photolithography. Alternatively, the thin films may be processed by methods such as nanoimprint lithography, sandblasting, or lift-off lithography. In addition, island-shaped thin films may be directly formed using a film deposition method that utilizes a shielding mask such as a metal mask.

[0196] There are two main methods of photolithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0197] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure may also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays may be used as the light source for exposure. An electron beam can also be used instead of the light source for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0198] For etching thin films, methods such as dry etching, wet etching, and sandblasting can be used.

[0199] Figures 12(A) to 17(B) are schematic cross-sectional diagrams corresponding to each step in the manufacturing method illustrated below. In each figure, the cross-section to the left of the dashed line corresponds to Figure 3, and the cross-section to the right of the dashed line corresponds to Figure 4.

[0200] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0201] As the substrate, a substrate with sufficient heat resistance to withstand subsequent heat treatment can be used.

[0202] As the insulating layer 11, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. The insulating layer 11 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. If the surface on which the insulating layer 11 is formed is not flat, a planarization treatment may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0203] Next, a conductive film that will become the conductive layer 55 is formed on the insulating layer 11. The conductive film can be formed by a film deposition method such as sputtering, ALD, or CVD. Subsequently, a resist mask is formed on the conductive film, and the conductive layer 55 is formed by etching away the unnecessary parts of the conductive film. The conductive layer 55 can be in the shape of a plate, line, or grid.

[0204] Next, an insulating layer 46 is formed over the conductive layer 55 (Figure 12(A)). The insulating layer 46 can be formed using film deposition methods such as sputtering, ALD, or CVD.

[0205] In forming the insulating layer 46, an uneven surface reflecting the shape of the conductive layer 55 may be formed on the upper surface of the insulating layer 46. Therefore, it is preferable to perform a planarization treatment on the upper surface of the insulating layer 46. For example, the planarization treatment can be performed by CMP (Chemical Mechanical Polishing) or dry etching.

[0206] Next, an opening 40 reaching the conductive layer 55 is formed in the insulating layer 46. At this time, a part of the upper surface of the conductive layer 55 may be etched. It is preferable to etch the conductive layer 55 so that a curved surface is formed on its upper surface.

[0207] Next, a conductive film 51f is formed to cover the upper surface of the insulating layer 46, the side surface of the insulating layer 46 within the opening 40, and the upper surface of the conductive layer 55, forming the conductive layer 51 (Figure 12(B)). The conductive film 51f can be formed using methods such as CVD, ALD, or sputtering. From the viewpoint of coverage, it is particularly preferable to form it using the CVD method.

[0208] A sacrificial layer is formed on the conductive film so as to cover the recess of the opening 40, and after a planar treatment is performed until the upper surface of the insulating layer 46 is exposed, the sacrificial layer is removed to form a conductive layer 51 that is located only inside the opening 40.

[0209] In this case, during the planarization process or removal of the sacrificial layer, the height of the upper surface of the conductive layer 51 may become lower than the height of the upper surface of the insulating layer 46. Also, the corners of the upper end of the conductive layer 51 and the upper end of the opening 40 of the insulating layer 46 may be rounded off.

[0210] Next, an insulating layer 52 is formed along the surfaces of the insulating layer 46 and the conductive layer 51 (Figure 12(C)). The insulating layer 52 can be formed by a film deposition method such as sputtering, ALD, or CVD. From the viewpoint of coverage, it is preferable to use the ALD method. Next, a conductive film that will become the conductive film 24a is formed on the insulating layer 52 so as to fill the recess in the opening 40 of the insulating layer 46. At this time, an uneven shape reflecting the shape of the opening 40 is formed on the upper surface of the conductive film, so it is preferable to flatten the upper surface of the conductive film. Next, a conductive film that will become the conductive film 24b is formed on the conductive film. The conductive film that will become the conductive film 24a and the conductive film that will become the conductive film 24b can each be formed independently by a film deposition method such as sputtering, ALD, or CVD.

[0211] Next, unnecessary portions of the conductive film that will become conductive film 24b and the conductive film that will become conductive film 24a are removed by etching to form a conductive layer 24 including conductive film 24a and conductive film 24b (Figure 12(D)). At this point, the capacitive element 30 can be formed.

[0212] Next, an insulating layer 41a is formed by covering the conductive layer 24, and then the upper surface is planarized. Subsequently, insulating layers 41b and 41c are laminated on the insulating layer 41a (Figure 13(A)). The insulating layers 41a, 41b, and 41c can be formed using film deposition methods such as sputtering, ALD, and CVD.

[0213] It is preferable that the insulating layer 41a and insulating layer 41c use films that have barrier properties against oxygen and hydrogen.

[0214] Furthermore, it is preferable to use an oxide film for the insulating layer 41b that contains a large amount of oxygen, to the extent that oxygen is released by heating, and has a low hydrogen content. The insulating layer 41 can be formed by a film deposition method such as PECVD, sputtering, or ALD. Sputtering is particularly preferred for film deposition. In particular, by using a gas that does not contain hydrogen as the deposition gas and uses a gas that contains oxygen, it is possible to deposit an insulating film with an extremely low hydrogen content and an excess of oxygen. By depositing the insulating layer 41b in this way, oxygen can be supplied to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies in the semiconductor layer 21.

[0215] Next, a heat treatment may be performed. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. By performing the heat treatment as described above, impurities such as water and hydrogen contained in the insulating layer 41a, insulating layer 41b, insulating layer 41c, etc., can be reduced before the deposition of the oxide semiconductor film that will become the semiconductor layer.

[0216] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulating layer 41, etc.

[0217] After forming the insulating layer 41b, an oxygen supply treatment may be performed. This can increase the amount of oxygen in the insulating layer 41b. When performing the oxygen supply treatment, it can be done after forming the insulating layer 41b but before forming the insulating layer 41c. Also, when performing the above heat treatment, the heat treatment can be performed after forming the insulating layer 41b, and then the oxygen supply treatment can be performed to replenish the oxygen that has been removed by the heat treatment.

[0218] Examples of processes for supplying oxygen include heating in an oxygen-containing atmosphere and plasma treatment (including microwave plasma) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method. The deposited oxide film may be removed immediately or left in place. The oxygen-containing atmosphere includes not only oxygen gas (O2) but also atmospheres containing oxygen-containing compound gases such as ozone (O3) and nitrous oxide (N2O).

[0219] Next, slits 20 reaching the conductive layer 24 are formed in the insulating layer 41c, insulating layer 41b, and insulating layer 41a (Figure 13(B)). Preferably, the slits 20 are formed in a shape such that their width decreases from the top to the bottom. This eliminates the need to pre-make the width of the conductive layer 24 larger than the opening width of the resist mask used for processing the slits 20, and allows them to be processed with the same width, thus enabling high-density arrangement of memory cells.

[0220] When forming the slit 20, it is preferable to process it by anisotropic dry etching. At this time, it is preferable to process the sidewall of the slit 20 (the side surface of the insulating layer 41) so that it is inclined with respect to the direction perpendicular to the surface to be formed, and has a tapered shape. For example, in the etching process for forming the slit 20, by etching under conditions in which deposits adhere to the side surface of the resist mask, it is possible to form a slit 20 having a shape in which the width continuously decreases from the top to the bottom by utilizing the fact that the opening width of the resist mask becomes smaller (narrower) as etching progresses. Alternatively, in the etching process for forming the slit 20, it is also possible to form a slit 20 having the shape described above by utilizing the fact that the etching rate decreases as the depth increases.

[0221] Next, a semiconductor film 21f, which will become the semiconductor layer 21, is formed along the upper surface of the insulating layer 41, the side surface of the insulating layer 41 within the slit 20, and the upper surface of the conductive layer 24 (Figure 14(A)).

[0222] As the semiconductor film 21f, a metal oxide (oxide semiconductor) film having semiconductor properties can be used. The metal oxide film can be deposited using sputtering, CVD, MBE, PLD, ALD, or other appropriate methods. Here, it is preferable that the metal oxide film is formed in contact with the side surface that is roughly perpendicular to the insulating layer 41. Therefore, it is preferable to use a film deposition method that provides good coverage for the metal oxide film, and it is more preferable to use the ALD method.

[0223] The metal oxide film preferably has crystalline properties. In particular, the metal oxide film of one aspect of the present invention preferably has a metal oxide having a single-crystal structure, a polycrystalline structure, or a CAAC structure.

[0224] Furthermore, it is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after its formation. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Multiple of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment can be performed simultaneously. Alternatively, heat treatment can be performed followed by microwave plasma treatment.

[0225] Furthermore, it is preferable to perform the process of increasing the crystallinity of the metal oxide film multiple times during the deposition of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform microwave plasma treatment each time an atomic layer is formed. Alternatively, it is preferable to perform the crystallinity-enhancing treatment each time a metal oxide film of a predetermined thickness is formed, as this can increase productivity. Specifically, it is preferable to form a first metal oxide film of 1 nm to 10 nm thickness, perform a first microwave plasma treatment, and then form a second metal oxide film of 1 nm to 10 nm thickness and perform a second microwave plasma treatment.

[0226] There are no particular limitations on the method for forming the first and second metal oxide films; ALD or sputtering methods can be used, respectively. Forming the first metal oxide film by ALD is particularly preferable because it prevents the mixing (also known as contamination) of elements from the layers constituting the surface to be formed into the first and second metal oxide films. This is especially preferable when the elements contained in the layers constituting the surface to be formed inhibit the crystallization of the metal oxide (for example, when silicon, carbon, etc. are included). Furthermore, the first and second metal oxide films may have different compositions. While a laminated structure of the first and second metal oxide films is illustrated here, the invention is not limited to this. The same treatment can be applied to single-layer or multi-layered metal oxide films of three or more layers.

[0227] Furthermore, treatments to enhance the crystallinity of the metal oxide film may be performed after the metal oxide film has been formed. Specifically, this treatment may be performed directly on the metal oxide film after formation, or it may be performed via another film, such as an insulating film formed on the metal oxide film. For example, microwave plasma treatment may be performed after the metal oxide film has been formed, or an insulating film (e.g., silicon nitride film, silicon oxide film, aluminum oxide film, etc.) may be formed after the metal oxide film has been formed, and then heat treatment or microwave plasma treatment may be performed on the metal oxide film via the insulating film.

[0228] Furthermore, the above-mentioned treatment to enhance the crystallinity of the metal oxide film can also serve as a treatment to remove impurities contained in the metal oxide film. For example, impurities such as hydrogen contained in the metal oxide film can be suitably removed. Alternatively, by performing the treatment to enhance the crystallinity of the metal oxide film in an oxygen gas atmosphere, oxygen deficiencies in the metal oxide film can be reduced.

[0229] When performing a treatment to improve the crystallinity of a metal oxide film, it is preferable to set the heat treatment temperature (or substrate temperature) to room temperature (e.g., 25°C) or higher, 100°C to 700°C, 100°C to 600°C, or 300°C to 450°C.

[0230] By improving the crystallinity of metal oxide films, it is possible to realize transistors with good reliability.

[0231] Metal oxide films can be formed, for example, by a sputtering method using a metal oxide target.

[0232] It is preferable that the metal oxide film be a dense film with as few defects as possible. Furthermore, it is preferable that the metal oxide film be a high-purity film with impurities such as hydrogen and water reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0233] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (for example, helium gas, argon gas, xenon gas, etc.). The higher the proportion of oxygen gas in the total deposition gas (hereinafter also referred to as the oxygen flow rate ratio) when forming the metal oxide film, the higher the crystallinity of the metal oxide film can be, resulting in a more reliable transistor. Conversely, a lower oxygen flow rate ratio results in lower crystallinity of the metal oxide film, allowing for a transistor with a higher on-current.

[0234] When forming a metal oxide film, higher substrate temperatures result in a more crystalline and dense metal oxide film. Conversely, lower substrate temperatures result in a less crystalline and more electrically conductive metal oxide film.

[0235] For metal oxide film formation, the substrate temperature should be between room temperature and 250°C, preferably between room temperature and 200°C, and more preferably between room temperature and 140°C. For example, setting the substrate temperature between room temperature and 140°C is preferable as it increases productivity. Furthermore, crystallinity can be reduced by forming the metal oxide film at room temperature or without intentional heating.

[0236] When using the ALD method, it is preferable to use a film deposition method such as thermal ALD or PEALD. Thermal ALD is preferred because it exhibits extremely high step coverage. PEALD is also preferred because, in addition to exhibiting high step coverage, it allows for low-temperature film deposition.

[0237] For example, when a metal oxide is used for the semiconductor layer 21, the film can be deposited by ALD using a precursor containing the constituent metal elements and an oxidizing agent.

[0238] For example, when depositing an indium oxide film, an indium-containing precursor can be used.

[0239] For example, when depositing an In-Ga-Zn oxide film, three precursors can be used: one containing indium, one containing gallium, and one containing zinc. Alternatively, two precursors may be used: one containing indium, and one containing both gallium and zinc.

[0240] Indium-containing precursors that can be used include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0241] Furthermore, gallium-containing precursors such as trimethylgallium, triethylgallium, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride can be used.

[0242] Furthermore, zinc-containing precursors such as dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride can be used.

[0243] Examples of oxidizing agents that can be used include ozone (O3), oxygen (O2), water (H2O), nitrogen dioxide (NO2), nitrous oxide (N2O), and hydrogen peroxide (H2O2), and two or more of these may be used.

[0244] To reduce the hydrogen and nitrogen concentrations in the film, it is preferable to use O2 or O3 as an oxidizing agent, and more preferably O3. On the other hand, when forming single crystals or polycrystalline films with large grain sizes, it is preferable to use an oxidizing agent containing hydrogen to suppress the formation of crystal nuclei in the initial stages of film formation. For example, it is preferable to use H2O or H2O2. After forming a film with few crystal nuclei, a single crystal film or a polycrystalline film with large grain sizes can be formed by growing crystals using the heat applied during film formation or by heat treatment after film formation.

[0245] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the duration of the source gas flow, and the order in which the source gases are flowed. By adjusting these factors, it is also possible to deposit films with continuously changing compositions. Furthermore, it becomes possible to deposit two or more films with different compositions in succession.

[0246] It is preferable to perform a heat treatment after the formation of the metal oxide film. The heat treatment should be performed within a temperature range in which the metal oxide film does not undergo polycrystallization, preferably between 250°C and 650°C, and more preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to use an oxygen gas concentration of about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, the heat treatment may be performed again in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0247] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the metal oxide film, etc.

[0248] Although the drawing shows the semiconductor film 21f as a single layer, it may also be a multilayer structure. For example, it can be a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer by the sputtering method and the third layer by either the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it can also be formed by the sputtering method. The semiconductor film 21f may also be a multilayer structure of four or more layers.

[0249] Next, a resist mask is formed on the semiconductor film 21f. At this time, in order to suppress variations in the thickness of the resist mask, an organic or inorganic material formed by a coating method may be provided between the resist mask and the semiconductor film 21f as a planarization film that fills the slit 20. More specifically, a coating-type insulating film such as an SOC (Spin On Carbon) film or an SOG (Spin On Glass) film can be used.

[0250] Next, the semiconductor layer 21 can be formed by removing the portion of the semiconductor film 21f not covered by the resist mask by etching, and then removing the resist mask (and planarization film) (Figure 14(B)). Etching the semiconductor film 21f is difficult with anisotropic dry etching alone because it is difficult to remove the portion in contact with the side surface of the insulating layer 41. Therefore, it is preferable to etch by combining isotropic dry etching and wet etching. Alternatively, the region of the semiconductor film 21f not covered by the resist mask may be treated in advance to alter a part of the semiconductor film 21f and make it easier to etch. Examples of such treatments include plasma treatment, doping (including ion implantation), and wet treatment.

[0251] Here, when forming the conductive layer 25 exemplified in FIG. 7(A) and the like, after forming a conductive film that will become the conductive layer 25 on the insulating layer 41c, when forming the slit 20, the conductive film and the insulating layer 41 are processed using the same resist mask. Further, when processing the semiconductor film 21f, the conductive layer 25 can be formed by etching the conductive film using the same resist mask.

[0252] Subsequently, an insulating layer 22 is formed to cover the semiconductor layer 21 and the insulating layer 41. The insulating layer 22 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. The insulating layer 22 is preferably provided on the surface of the vertical portion of the semiconductor layer 21 with as uniform a thickness as possible. Therefore, it is particularly preferable to form the insulating layer 22 by the ALD method, which is a film formation method with excellent coating properties. Since the side wall of the insulating layer 41 is tapered, the insulating layer 22 can also be formed using a film formation method such as a sputtering method or a CVD method.

[0253] Subsequently, a conductive film 23f that will become the conductive layer 23 is formed to cover the insulating layer 22 (FIG. 15(A)). The conductive film 23f can be formed by a CVD method, an ALD method, a sputtering method, or the like. From the viewpoints of coating properties and embedding properties, it is particularly preferably formed by a CVD method. <O000899>

[0254] Subsequently, the upper part of the conductive film 23f is etched without using a photomask until the upper surface of the insulating layer 22 is exposed, whereby the conductive layer 23 embedded inside the slit 20 can be formed (FIG. 15(B)).

[0255] At this time, the upper surface of the conductive layer 23 is processed so as to be lower than the height of the upper surface of the insulating layer 41c. For example, after performing processing using the CMP method until the upper surface of the insulating layer 22 is exposed, the processing is continued to etch the upper part of the conductive layer 23. Alternatively, after performing planarization processing until the upper surface of the insulating layer 22 is exposed, the upper part of the conductive layer 23 can also be etched by a dry etching method or a wet etching method.

[0256] In this case, it is preferable to process the conductive layer 23 so that its upper surface is not lower than the height of the upper surface of the insulating layer 41b. The portion of the semiconductor layer 21 that is in contact with the insulating layer 41b has reduced oxygen vacancies and is a high-resistance portion. If a sufficient gate electric field is not applied to this portion, it may become a resistive component, potentially reducing the current that the transistor can supply. Therefore, it is preferable to process the conductive layer 23 so that its upper surface is lower than the upper surface of the insulating layer 41c and higher than the upper surface of the insulating layer 41b.

[0257] Next, insulating layer 43 and insulating layer 44 are formed in sequence by covering the insulating layer 22 and conductive layer 23 (Figure 16(A)). Insulating layer 43 and insulating layer 44 can each be formed independently by a film deposition method such as CVD, ALD, or sputtering.

[0258] Next, by performing a planarization process until the semiconductor layer 21 is exposed, insulating layers 43 and 44 located inside the slit 20 and on the conductive layer 23 can be formed (Figure 16(B)).

[0259] Next, a conductive film is formed in contact with the upper surfaces of the semiconductor layer 21, insulating layer 22, insulating layer 43, and insulating layer 44 to form the conductive layer 26, and the unnecessary parts are etched to form the conductive layer 26 (Figure 17(A)).

[0260] Through the above process, a memory cell 15 having a transistor 10 and a capacitive element 30 can be fabricated.

[0261] Subsequently, an insulating layer 47 is formed by covering the conductive layer 26, insulating layer 22, insulating layer 43, and insulating layer 44. The insulating layer 47 can be formed using methods such as sputtering, ALD, or CVD.

[0262] The above is an explanation of an example of the manufacturing method.

[0263] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0264] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0265] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0266] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0267] This section describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO. Figure 18(A) shows the carrier concentration dependence of silicon (Si) and indium oxide (InO X Figure 18(B) is a schematic diagram of the carrier concentration dependence of hole mobility for IGZO.

[0268] First, as indicated by the arrows in Figure 18(B), IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 18(A), indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 1). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 18(A) are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 18(A).

[0269] In Figure 18(A), the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is such that the carrier concentration value is 1 × 10⁻⁶. 15 cm -3 This range includes, for example, 1 × 10 14 cm -3 The above is 1 x 10 18 cm -3 The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. 2 It can be expected to be raised to the level of (V·s).

[0270] Furthermore, in indium oxide, the region where the carrier concentration is within the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0271] On the other hand, the range R2, where the carrier concentration is high, has low electrical resistance and is suitable for applications such as the source and drain regions of a transistor, resistors, or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. 20 cm -3 This range includes, for example, 1 × 10 19 cm -3 The above is 1 x 10 22 cm -3 The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. -4 It is expected that the level can be reduced to below Ω·cm.

[0272] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0273] Thus, in indium oxide, the region with a low carrier concentration is used for the transistor's channel formation region, while the region with a high carrier concentration is used for the transistor's source and drain regions. In other words, indium oxide can be considered an oxide in which valence electron control is possible. Note that in IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with the IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 18(A) within the indium oxide film, a so-called nin junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived.

[0274] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0275] Next, the indium oxide film applied to the transistor will be described. The indium oxide film preferably has crystallinity (that is, has crystal grains). Examples of the film having crystal grains include a single crystal film, a polycrystalline film, or an amorphous film containing crystal grains (also referred to as a microcrystalline film). In particular, the indium oxide film is preferably a polycrystalline film, more preferably a single crystal film. The single crystal film has no grain boundaries (also referred to as grain boundaries). Impurities that inhibit the flow of carriers (typically insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. By using a single crystal film, carrier scattering at grain boundaries and the like can be suppressed, and a transistor exhibiting high field-effect mobility can be realized. In addition, there is an excellent effect that variations in transistor characteristics due to the grain boundaries can be suppressed.

[0276] Also, compared with a microcrystalline film or an amorphous film, the polycrystalline film can reduce carrier scattering and is preferable because it exhibits high field-effect mobility. When using a polycrystalline film, it is preferable to use a film with as large crystal grain size as possible and few grain boundaries. In a transistor to which a polycrystalline film of indium oxide is applied, when the channel formation region has no grain boundaries or no grain boundaries are observed, since the channel formation region is located within the single crystal region contained in the polycrystalline film, it can be regarded as a transistor to which single crystal indium oxide is applied.

[0277] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Or, analysis may be performed by combining a plurality of these.

[0278] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0279] The channel formation region refers to the region within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0280] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0281] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0282] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². 2 / (V·s) or more, preferably 100cm 2 / (V·s) or more, more preferably 150cm 2 / (V·s) or more, more preferably 200cm 2 / (V·s) or more, more preferably 250cm 2 It can be set to (V·s) or more.

[0283] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 18(C), indium oxide films (InO X Oxygen (O) diffusing into an oxygen vacancy (V) permeates the indium oxide membrane and is released as oxygen molecules (O2). It may also be released as water molecules (H2O) by reacting with hydrogen contained in the membrane. Furthermore, oxygen vacancies (V) in the membrane... O If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films can be said to be more efficient at filling oxygen deficiencies compared to IGZO films because oxygen diffuses easily.

[0284] Thus, because indium oxide films are more prone to reducing oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0285] Furthermore, as shown in Figure 18(C), the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules (H2). Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0286] A transistor using an indium oxide film is a storage-type transistor that uses electrons as the majority carrier. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0287] Table 1 shows the effective masses of single-crystal indium oxide (here, In2O3) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-response) can be realized. In addition, because of the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. -15 A) Less than or equal to, or 1aA(1 × 10 -18 A) is less than or equal to 1aA(1 × 10) under room temperature (25°C) conditions. -18 A) Less than or equal to 1zA(1×10) -21 A) The following is possible. Furthermore, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0288] [Table 1]

[0289] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This can improve the crystallinity of the indium oxide film. A substrate (for example, a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0290] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] between the crystals of the seed layer and the crystals of the formed film (indium oxide film in this case) is calculated as Δa = ((L1 - L2) / L2) × 100. Here, L1 is the length of the unit cell vector or lattice constant of the crystals of the formed film, and L2 is the length of the unit cell vector or lattice constant of the crystals of the seed layer.

[0291] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably 0. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0292] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0293] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For instance, by setting the crystal orientation of the surface of the seed layer to

[0001] and the crystal orientation of the underside of the indium oxide film to

[0111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures, YbFe2O4-type structures, Yb2Fe3O7-type structures, and modified forms thereof. An example of a crystal having a YbFe2O4-type or Yb2Fe3O7-type structure is IGZO.

[0294] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0295] (Embodiment 3) In this embodiment, a semiconductor device 900 according to an aspect of the present invention different from the above embodiment will be described. The semiconductor device 900 can function as a storage device.

[0296] Figure 19 shows a block diagram illustrating an example configuration of a semiconductor device 900. The semiconductor device 900 shown in Figure 19 includes a drive circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Figure 19 shows an example in which the memory array 920 has multiple memory cells 950 arranged in a matrix.

[0297] The memory cell 950 can be replaced with the memory cell 15 or the like exemplified in the above embodiment.

[0298] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0299] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0300] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.

[0301] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 so that this operating mode is executed.

[0302] The voltage generation circuit 928 has the function of generating a negative voltage. The WAKE signal has the function of controlling the input of the CLK signal to the voltage generation circuit 928. For example, when a high-level signal is given as the WAKE signal, the CLK signal is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0303] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0304] The row decoder 941 and column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying the row to access, and the column decoder 942 is a circuit for specifying the column to access. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, reading data from the memory cell 950, and holding the read data, etc.

[0305] The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read by the column driver 924 from the memory cell 950 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. In addition, the output circuit 926 has the function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

[0306] PSW931 has the function of controlling the supply of VDD to peripheral circuit 915. PSW932 has the function of controlling the supply of VHM to row driver 923. Here, the high power supply voltage of semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW931 is controlled by signal PON1, and the on / off state of PSW932 is controlled by signal PON2. In Figure 19, the number of power supply domains to which VDD is supplied in peripheral circuit 915 is set to 1, but it can be multiple. In this case, it is preferable to provide a power switch for each power supply domain.

[0307] Using Figures 20(A) through (H), examples of other memory cell configurations that can be applied to memory cell 950 will be explained.

[0308] In the following, when two components are described as being connected, this includes being electrically connected via a circuit element (such as a transistor, switch, diode, or resistor). An electrical connection means that an electric current can flow between the two components. Furthermore, when two components are connected via a switch or transistor, an electric current can flow when these are in the ON state, and therefore this is also considered an electrical connection.

[0309] [DOSRAM] Figure 20(A) shows an example of the circuit configuration of a memory cell in a DRAM (Dynamic Random Access Memory). In this specification, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 has a transistor M1 and a capacitive element CA.

[0310] Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate may be connected.

[0311] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring CAL.

[0312] The BIL wiring functions as a bit line, and the WOL wiring functions as a word line. The CAL wiring functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the CAL wiring.

[0313] Data writing and reading are performed by applying a high-level potential to the wiring WOL, turning on transistor M1, and creating a conductive state (a state in which current can flow) between the wiring BIL and the first terminal of the capacitive element CA.

[0314] Furthermore, the memory cell that can be used in memory cell 950 is not limited to memory cell 951, and the circuit configuration can be changed. For example, a memory cell 952 configuration as shown in Figure 20(B) is also possible. Memory cell 952 is an example in which there is no capacitive element CA and wiring CAL. The first terminal of transistor M1 is electrically floating.

[0315] In memory cell 952, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0316] Furthermore, it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, the written data can be held by transistor M1 for a long time, so the frequency of memory cell refresh can be reduced. Alternatively, the memory cell refresh operation can be made unnecessary. In addition, because the leakage current is very low, multi-level data or analog data can be held in memory cells 951 and 952.

[0317] [NOSRAM] Figure 20(C) shows an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 953 has a transistor M2, a transistor M3, and a capacitance element CB. In this specification and elsewhere, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 is called NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0318] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0319] Wiring WBL functions as the write bit line, wiring RBL functions as the read bit line, and wiring WOL functions as the word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0320] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M2, and creating a conductive state between the wiring WBL and the first terminal of the capacitive element CB. Specifically, when transistor M2 is ON, a potential corresponding to the information to be recorded is applied to the wiring WBL, and this potential is written to the first terminal of the capacitive element CB and the gate of transistor M3. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitive element CB and the gate of transistor M3.

[0321] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3, and the potential of the first terminal of transistor M3, are determined by the potential of the gate and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3).

[0322] Alternatively, for example, the wiring WBL and wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 20(D). Memory cell 954 is configured such that the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to this wiring BIL. In other words, memory cell 954 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0323] The memory cell 955 shown in Figure 20(E) is an example where the capacitive element CB and wiring CAL in memory cell 953 are omitted. Similarly, the memory cell 956 shown in Figure 20(F) is an example where the capacitive element CB and wiring CAL in memory cell 954 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0324] Furthermore, it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3.

[0325] Because the OS transistor has the characteristic of having an extremely low off-current, the written data can be held by transistor M2 for a long time, thus reducing the frequency of memory cell refreshes. Alternatively, it may be possible to eliminate the need for memory cell refresh operations altogether. Furthermore, because the leakage current is very low, multi-level data or analog data can be held in memory cells 953, 954, 955, and 956.

[0326] Memory cells 953, 954, 955, and 956, which use an OS transistor as transistor M2, represent one form of NOSRAM.

[0327] Furthermore, a Si transistor may be used as transistor M3. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0328] Furthermore, if an OS transistor is used as transistor M3, the memory cell can be constructed using only n-type transistors.

[0329] Figure 20(G) also shows a gain cell type memory cell 957 with three transistors and one capacitance element. The memory cell 957 has transistors M4 to M6 and a capacitance element CC.

[0330] The first terminal of transistor M4 is connected to the first terminal of capacitive element CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitive element CC is connected to the first terminal of transistor M5 and to wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitive element CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0331] The BIL wire functions as a bit line, the WOL wire functions as a write word line, and the RWL wire functions as a read word line. The GNDL wire provides a low level potential.

[0332] Data writing is performed by applying a high-level potential to the WOL wiring, turning on transistor M4, and creating a conductive state between the BIL wiring and the first terminal of the CC capacitor. Specifically, when transistor M4 is ON, a potential corresponding to the information to be recorded in the BIL wiring is applied, and this potential is written to the first terminal of the CC capacitor and the gate of transistor M5. Subsequently, a low-level potential is applied to the WOL wiring, turning off transistor M4, thereby maintaining the potential of the first terminal of the CC capacitor and the gate of transistor M5.

[0333] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 turns ON, and the wiring BIL and the second terminal of transistor M5 become conductive. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5).

[0334] Furthermore, it is preferable to use an OS transistor for at least transistor M4.

[0335] Note that Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.

[0336] Furthermore, if OS transistors are used as transistors M5 and M6, the memory cell can be constructed using only n-type transistors.

[0337] [OS-SRAM] Figure 20(H) shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification and elsewhere, SRAM using an OS transistor is referred to as OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 958 shown in Figure 20(H) is a memory cell of a backup-capable SRAM.

[0338] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0339] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0340] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0341] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0342] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0343] Wiring BIL and BILB function as bit lines, wiring WOL functions as a word line, and wiring BRL controls the on and off states of transistors M9 and M10.

[0344] Wiring VDL is a wire that provides a high potential, and wiring GNDL is a wire that provides a low potential.

[0345] Data is written by applying a high-level potential to the WOL wiring and also to the BRL wiring. Specifically, when transistor M10 is ON, a potential corresponding to the information to be recorded in the BIL wiring is applied, and this potential is written to the second terminal side of transistor M10.

[0346] Incidentally, since the memory cell 958 is configured in an inverter loop by transistors MS1 to MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of transistor M8. Because transistor M8 is ON, the inverted signal of the potential applied to wiring BIL, i.e., the signal input to wiring BIL, is output to wiring BILB. Also, because transistors M9 and M10 are ON, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and turning off transistors M7 to M10, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are held.

[0347] The data reading process is described below. First, wiring BIL and wiring BILB are precharged to a predetermined potential. Next, a high-level potential is applied to wiring WOL and wiring BRL. At this time, the potential of the first terminal of capacitive element CD1 is refreshed by the inverter loop of memory cell 958 and output to wiring BILB. Also, the potential of the first terminal of capacitive element CD2 is refreshed by the inverter loop of memory cell 958 and output to wiring BIL. In wiring BIL and wiring BILB, the potential changes from the precharged potential to the potential of the first terminal of capacitive element CD2 and the potential of the first terminal of capacitive element CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0348] Furthermore, it is preferable to use OS transistors as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes, or even eliminating the need for memory cell refresh operations altogether.

[0349] Note that Si transistors may be used as transistors MS1 through MS4.

[0350] The drive circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in Figure 21(A), the drive circuit 910 and memory array 920 may be stacked on top of each other. By stacking the drive circuit 910 and memory array 920, the signal propagation distance can be shortened. Furthermore, as shown in Figure 21(B), multiple memory arrays 920 may be stacked on top of the drive circuit 910.

[0351] Next, an example of a processing unit that can be equipped with the above-mentioned memory device and other semiconductor devices will be described.

[0352] Figure 22 shows a block diagram of the arithmetic unit 960. The arithmetic unit 960 shown in Figure 22 can be applied to a CPU, for example. The arithmetic unit 960 can also be applied to processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units) that have a large number of processor cores capable of parallel processing (tens to hundreds of cores) that are more capable than a CPU.

[0353] The arithmetic unit 960 shown in Figure 22 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may be provided on a separate chip.

[0354] Cache 999 is connected to main memory located on a separate chip via a cache interface 989. The cache interface 989 has the function of supplying a portion of the data held in main memory to cache 999. The cache interface 989 also has the function of outputting a portion of the data held in cache 999 to ALU 991 or register 996, etc., via bus interface 998.

[0355] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have the function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 is included in part of the cache interface 989.

[0356] Alternatively, it is possible to use only memory array 920 as a cache without providing cache 999.

[0357] The arithmetic unit 960 shown in Figure 22 is merely a simplified example of its configuration, and actual arithmetic units 960 have a wide variety of configurations depending on their application. For example, it is preferable to have a so-called multi-core configuration in which the configuration including the arithmetic unit 960 shown in Figure 22 is considered one core, and multiple such cores are included, with each core operating in parallel. The more cores there are, the higher the computational performance can be. While a larger number of cores is preferable, it is preferable to have, for example, 2, preferably 4, more preferably 8, even more preferably 12, and even more preferably 16 or more cores. Furthermore, in cases where very high computational performance is required, such as for server applications, it is preferable to have a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores. In addition, the number of bits that the arithmetic unit 960 can handle in its internal arithmetic circuitry, data bus, etc., can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0358] Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0359] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. The interrupt controller 994 processes interrupt requests from external input / output devices and peripheral circuits during program execution of the arithmetic unit 960, based on their priority, mask state, etc. The register controller 997 generates the address of register 996 and performs read and write operations on register 996 according to the state of the arithmetic unit 960.

[0360] Furthermore, the timing controller 995 generates signals that control the timing of the operation of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits mentioned above.

[0361] In the arithmetic unit 960 shown in Figure 22, the register controller 997 selects a data retention operation in register 996 according to instructions from ALU 991. That is, it selects whether to retain data in the memory cell of register 996 using a flip-flop or a capacitive element. If data retention using a flip-flop is selected, power voltage is supplied to the memory cell in register 996. If data retention using a capacitive element is selected, data is rewritten to the capacitive element, and the power voltage supply to the memory cell in register 996 can be stopped.

[0362] The memory array 920 and the arithmetic unit 960 can be mounted on top of each other. Figures 23(A) and (B) show perspective views of the semiconductor device 970A. The semiconductor device 970A has a layer 930 on which memory arrays are provided on the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, Figure 23(B) shows the arithmetic unit 960 and layer 930 separately.

[0363] By stacking the layer 930 containing the memory array and the arithmetic unit 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, power consumption can be reduced due to the short connection distance.

[0364] As a method for stacking the layer 930 having the memory array and the arithmetic unit 960, one may use a method in which the layer 930 having the memory array is directly stacked on the arithmetic unit 960 (also called monolithic stacking), or one may use a method in which the arithmetic unit 960 and the layer 930 are formed on separate substrates, the two substrates are bonded together, and they are connected using through-via or conductive film bonding technology (such as Cu-Cu bonding). The former does not require consideration of positional misalignment during bonding, so not only can the chip size be reduced, but manufacturing costs can also be reduced.

[0365] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in layer 930 can each be used as caches. In this case, for example, memory array 920L1 can be used as an L1 cache (also called a level 1 cache), memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Also, memory array 920L1 has the smallest capacity and the highest access frequency.

[0366] Furthermore, when the cache 999 provided in the arithmetic unit 960 is used as the L1 cache, each memory array provided in layer 930 can be used as a lower-level cache or main memory, respectively. Main memory has a larger capacity than cache and is accessed less frequently.

[0367] Furthermore, as shown in Figure 23(B), drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

[0368] Note that while this example shows three memory arrays functioning as a cache, it is also possible to use one or two, or even four or more.

[0369] When the memory array 920L1 is used as a cache, the drive circuit 910L1 may function as part of the cache interface 989, or the drive circuit 910L1 may be configured to be connected to the cache interface 989. Similarly, the drive circuits 910L2 and 910L3 may also function as part of the cache interface 989, or be configured to be connected to it.

[0370] Whether the memory array 920 functions as a cache or as main memory is determined by the control circuit 912 of each drive circuit 910. Based on signals supplied from the arithmetic unit 960, the control circuit 912 can make some of the multiple memory cells 950 of the semiconductor device 900 function as RAM.

[0371] The semiconductor device 900 can have some of its multiple memory cells 950 function as a cache and the other part function as main memory. In other words, the semiconductor device 900 can have both cache and main memory functions. A semiconductor device 900 according to one aspect of the present invention can function as a universal memory, for example.

[0372] Alternatively, a layer 930 having a single memory array 920 may be superimposed on the arithmetic unit 960. Figure 24(A) shows a perspective view of the semiconductor device 970B.

[0373] In the semiconductor device 970B, a single memory array 920 can be divided into multiple areas, each used for a different function. Figure 24(A) shows an example where area L1 is used as the L1 cache, area L2 as the L2 cache, and area L3 as the L3 cache.

[0374] Furthermore, the semiconductor device 970B allows the capacity of each region L1 through L3 to be changed according to the situation. For example, if the capacity of the L1 cache is to be increased, this can be achieved by increasing the area of ​​region L1. This configuration makes arithmetic processing more efficient and improves processing speed.

[0375] Furthermore, multiple memory arrays may be stacked. Figure 24(B) shows a perspective view of the semiconductor device 970C.

[0376] The semiconductor device 970C has a stacked structure consisting of a layer 930L1 with a memory array 920L1, a layer 930L2 with a memory array 920L2 on top of it, and a layer 930L3 with a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as the upper cache, and the memory array 920L3, which is furthest away, can be used as the lower cache or main memory. By using this configuration, the capacity of each memory array can be increased, thereby improving processing power.

[0377] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0378] (Embodiment 4) This embodiment describes an application example of a semiconductor device according to one aspect of the present invention. A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, electronic devices, large computers, space equipment, and data centers (also referred to as DCs). Electronic components, electronic devices, large computers, space equipment, and data centers using a semiconductor device according to one aspect of the present invention are effective in achieving high performance, such as reduced power consumption.

[0379] [Electronic components] Figure 25(A) shows a perspective view of a substrate (mounted substrate 704) on which electronic components 700 are mounted. The electronic component 700 shown in Figure 25(A) has a semiconductor device 710 inside a mold 711. Some details are omitted in Figure 25(A) to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 via a wire 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted substrate 704.

[0380] Furthermore, the semiconductor device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 715 and the storage layer 716 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the storage layer 716 in a monolithic stack configuration, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0381] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-electrodes such as TSV, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0382] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 716 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 716, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0383] Furthermore, the semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0384] Next, a perspective view of the electronic component 730 is shown in Figure 25(B). The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). The electronic component 730 has an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0385] Electronic component 730 shows an example of using semiconductor device 710 as high-bandwidth memory (HBM). Furthermore, semiconductor device 735 can be used in integrated circuits such as CPUs, GPUs, NPUs, or FPGAs (Field Programmable Gate Arrays).

[0386] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0387] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0388] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0389] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0390] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of electronic component 730, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0391] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 735.

[0392] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 25(B) shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0393] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0394] [Large computer] Figure 26(A) shows a perspective view of the large-scale computer 5600. The large-scale computer 5600 contains multiple rack-mount type computers 5620 housed in rack 5610. The large-scale computer 5600 may also be referred to as a supercomputer.

[0395] Figure 26(B) shows a perspective view of an example of the computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0396] Figure 26(C) shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, GPU, and memory device. The PC card 5621 has a board 5622 and connectors 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Figure 26(C) shows components other than electronic components 5626, 5627, and 5628.

[0397] The connector 5629 has a shape that allows it to be inserted into slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0398] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0399] The electronic component 5626 has terminals (not shown) for inputting and outputting signals, and by inserting these terminals into a socket (not shown) on the board 5622, the electronic component 5626 and the board 5622 can be electrically connected.

[0400] Electronic components 5627 and 5628 have multiple terminals, and these terminals can be mounted to the wiring provided on board 5622 by, for example, reflow soldering. Examples of electronic component 5627 include FPGAs, GPUs, and CPUs. For example, electronic component 730 can be used as electronic component 5627. Examples of electronic component 5628 include memory devices. For example, electronic component 700 can be used as electronic component 5628.

[0401] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0402] [Space equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment.

[0403] One embodiment of the present invention includes an OS transistor. The OS transistor exhibits small fluctuations in electrical properties due to radiation exposure. In other words, it has high resistance to radiation and can be suitably used in environments where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device installed in a space shuttle, artificial satellite, or space probe. Examples of radiation include X-rays and neutrons. Outer space refers to, for example, an altitude of 100 km or more, but outer space as described herein includes one or more of the thermosphere, mesosphere, and stratosphere.

[0404] Figure 27(A) shows satellite 6800 as an example of space equipment. Satellite 6800 consists of a body 6801, solar panels 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 27(A), planet 6804 is shown as an example in outer space.

[0405] Furthermore, although not shown in Figure 27(A), a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0406] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutrons, protons, heavy ions, and mesons.

[0407] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel does not receive sunlight, or if the amount of sunlight hitting the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to install a secondary battery 6805 on the satellite 6800. Note that solar panels are sometimes called solar cell modules.

[0408] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0409] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 6807. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, they are highly reliable and can be suitably used even in environments where radiation may be incident.

[0410] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected off objects on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0411] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes.

[0412] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0413] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as ensuring data immutability. Managing data over the long term necessitates the installation of storage and servers to store vast amounts of data, securing a stable power supply to maintain the data, and securing cooling equipment required for data retention, which necessitates the construction of larger buildings.

[0414] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. Therefore, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. This, in turn, contributes to space savings in the data center.

[0415] Furthermore, because the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0416] Figure 27(B) shows a storage system applicable to a data center. The storage system 6000 shown in Figure 27(B) has multiple servers 6001sb as hosts 6001 (shown as Host Computer) and multiple storage devices 6003md as storage 6003 (shown as Storage). The host 6001 and storage 6003 are connected via a storage area network 6004 (shown as SAN) and a storage control circuit 6002 (shown as Storage Controller).

[0417] Host 6001 corresponds to a computer that accesses data stored in storage 6003. The hosts 6001 may be connected to each other via a network.

[0418] While Storage 6003 shortens data access speed, i.e., the time required for data storage and retrieval, by using flash memory, this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage. To address the problem of the long access speed of Storage 6003, storage systems typically include cache memory within the storage to shorten the time required for data storage and retrieval.

[0419] The aforementioned cache memory is used within the storage control circuit 6002 and storage 6003. Data exchanged between the host 6001 and storage 6003 is stored in the cache memory within the storage control circuit 6002 and storage 6003, and then output to the host 6001 or storage 6003.

[0420] By using OS transistors as the transistors for storing the aforementioned cache memory data, and configuring them to maintain a potential corresponding to the data, the refresh frequency can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking the memory cell arrays.

[0421] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, it is expected that power consumption will be reduced. Therefore, as energy demand is expected to increase due to the increased performance or integration of semiconductor devices, it will also be possible to reduce greenhouse gas emissions, such as carbon dioxide (CO2), by using a semiconductor device according to one aspect of the present invention. In addition, because a semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0422] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. [Explanation of Symbols]

[0423] 10: Transistor, 10a: Transistor, 11: Insulating layer, 15: Memory cell, 20: Slit, 21: Semiconductor layer, 21f: Semiconductor film, 22: Insulating layer, 23: Conductive layer, 23f: Conductive film, 24: Conductive layer, 24a: Conductive film, 24b: Conductive film, 25: Conductive layer, 26: Conductive layer, 30: Capacitive element, 40: Aperture, 41: Insulating layer, 41a: Insulating layer, 41b: Insulating layer, 41c: Insulating layer, 43: Insulating layer, 44: Insulating layer, 45: Insulating layer, 46: Insulating layer, 47: Insulating layer Edge layer, 48: insulating layer, 50: semiconductor device, 51: conductive layer, 51f: conductive film, 52: insulating layer, 55: conductive layer, 80[1]: layer, 80: layer, 81: conductive layer, 82: plug, 83: plug, 84: conductive layer, 85: plug, 86: insulating layer, 87: insulating layer, 88: insulating layer, 89: plug, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 96: insulating layer, 98: element isolation layer

Claims

1. It comprises a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer covers the first conductive layer and has slits that reach the first conductive layer. The semiconductor layer has a portion located on the first insulating layer, a portion inside the slit that runs along the side surface of the first insulating layer, and a portion that is in contact with the first conductive layer. The second insulating layer covers the semiconductor layer inside the slit. The second conductive layer covers the second insulating layer inside the slit. The third insulating layer overlaps with the slit and is located on the second conductive layer. The third conductive layer is in contact with the upper surface of the semiconductor layer in the portion that overlaps with the first insulating layer, and is in contact with the upper surface of the third insulating layer in the portion that overlaps with the slit. The slit, the second conductive layer, and the third insulating layer extend in the first direction. The third conductive layer extends in a second direction intersecting the first direction. Semiconductor equipment.

2. In claim 1 The angle between the side surface of the first insulating layer inside the slit and the upper surface of the first conductive layer that is in contact with the first insulating layer is 60 degrees or more and less than 90 degrees. Semiconductor equipment.

3. In claim 1, The semiconductor layer includes a metal oxide. Semiconductor equipment.

4. In claim 1, The semiconductor layer comprises an oxide containing indium, Semiconductor equipment.

5. In claim 1, The first conductive layer has a recess that overlaps with the slit, The semiconductor layer, the second insulating layer, and the second conductive layer each have their bottoms provided along the recess. Semiconductor equipment.

6. In claim 1, The semiconductor layer comprises a first metal oxide, The first conductive layer comprises a second metal oxide, The first metal oxide and the second metal oxide each contain indium. Semiconductor equipment.

7. In claim 1, A fourth conductive layer is provided between the upper surface of the first insulating layer and the semiconductor layer. The fourth conductive layer is in contact with the semiconductor layer. Semiconductor equipment.

8. In claim 1, The material has a fourth conductive layer and a fourth insulating layer below the first conductive layer, The fourth insulating layer has a portion located between the first conductive layer and the fourth conductive layer. Semiconductor equipment.

9. In claim 8, The fourth conductive layer has a recess, The fourth insulating layer has a portion provided along the recess, The first conductive layer has a portion located within the recess via the fourth insulating layer. Semiconductor equipment.

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