Package substrate, semiconductor package including the package substrate, and method for manufacturing the same.

Abstract

The present invention provides a package substrate, a semiconductor package including the package substrate, and a method for manufacturing the same. [Solution] The technical concept of the present invention provides a package substrate comprising: a base layer including a first surface and a second surface opposite thereto; a wiring structure located within the base layer; a bump pad electrically connected to the wiring structure and located on the first surface of the base layer; a connecting terminal attached to the bump pad, containing tin and having a melting point of a first temperature; and a metal protective film located on the surface of the connecting terminal, containing tin and having a melting point of a second temperature; wherein the first temperature is lower than the second temperature.

Description

Technical Field

[0001] The present invention relates to a package substrate, a semiconductor package including the package substrate, and a method for manufacturing the same, and more particularly, to a package substrate to which connection terminals are attached.

Background Art

[0002] Recently, due to the remarkable development of the electronics industry and user requirements, electronic devices have become further miniaturized, multifunctional, and large-capacity, and highly integrated semiconductor chips are required. Therefore, a semiconductor package has been devised that includes a highly integrated semiconductor chip with an increased number of connection terminals for input / output (I / O) while ensuring connection reliability.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved by the present invention is to provide a package substrate including connection terminals having a low melting point and a semiconductor package including the package substrate.

[0004] However, the problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those having ordinary knowledge in the technical field from the following description.

Means for Solving the Problems

[0005] To solve the aforementioned problems, the technical concept of the present invention provides a package substrate comprising: a base layer including a first surface and a second surface opposite thereto; through vias extending from the first surface of the base layer to the second surface and penetrating through it; a first wiring structure located on the first surface of the base layer and including a first wiring pattern and a first interlayer insulating layer surrounding the first wiring pattern; a first bump pad located on the first wiring structure so as to be electrically connected to the first wiring pattern of the first wiring structure and to be separated from the base layer across the first wiring structure; a first passivation layer located on the first wiring structure and surrounding the first bump pad, and including an opening that overlaps the first bump pad perpendicularly; a first connecting terminal located in the opening of the first passivation layer and on the first bump pad, containing tin and having a melting point of a first temperature; and a metal protective film located on the surface of the first connecting terminal, containing tin and having a melting point of a second temperature; wherein the first temperature is lower than the second temperature.

[0006] To solve the aforementioned problems, the technical concept of the present invention is a base layer including a first surface and a second surface opposite thereto; through vias extending from the first surface of the base layer to the second surface and penetrating through it; a first wiring structure located on the first surface of the base layer and including a first wiring pattern and a first interlayer insulating layer surrounding the first wiring pattern; a first bump pad located on the first wiring structure so as to be electrically connected to the first wiring pattern of the first wiring structure and to be separated from the base layer across the first wiring structure; and a first bump located on the first wiring structure The present invention provides a package substrate comprising: a first passivation layer surrounding a pad and including an opening that overlaps perpendicularly with the first bump pad; a first connecting terminal located at the opening in the first passivation layer and on the first bump pad, containing tin and having a first hardness; a metal compound film located on the surface of each of the first connecting terminals; and a metal protective film located on the surfaces of the first connecting terminals and the metal compound film, containing tin and having a second hardness higher than the first hardness; wherein the melting point of the first bump pad is lower than the melting point of the metal protective film.

[0007] To solve the aforementioned problems, the technical concept of the present invention is a package substrate including a base layer having a first surface and a second surface opposite thereto; a first wiring structure located on the first surface of the base layer; a second wiring structure located on the second surface of the base layer; through vias penetrating the base layer and electrically connecting the first wiring structure and the second wiring structure; a first bump pad located on the lower surface of the first wiring structure; a second bump pad located on the upper surface of the second wiring structure; and a first passivation layer surrounding the first bump pad and including an opening that overlaps the first bump pad perpendicularly; and a main substrate configured to mount the package substrate on its upper surface and including a substrate bump pad located on its upper surface; The present invention provides a semiconductor package comprising: substrate connection terminals located between the package substrate and the main substrate, electrically and physically connecting the first bump pad of the package substrate and the substrate bump pad of the main substrate, and having a melting point of a first temperature; metal protective film fragments located inside each of the first connection terminals, having a melting point of a second temperature higher than the first temperature; a semiconductor chip mounted on the upper surface of the second wiring structure of the package substrate; chip connection terminals located between the package substrate and the semiconductor chip, electrically and physically connecting the second bump pad of the package substrate and the chip pad of the semiconductor chip; and a molding layer located on the package substrate and surrounding the semiconductor chip.

[0008] To solve the aforementioned problems, the technical concept of the present invention provides a semiconductor package manufacturing method comprising the steps of: manufacturing a package substrate including a base layer, a first wiring structure located on a first surface of the base layer, a first bump pad located on the first wiring structure, and a second wiring structure located on a second surface facing the first surface of the base layer; and mounting a semiconductor chip on the second wiring structure of the package substrate, wherein the step of manufacturing the package substrate includes the steps of: attaching a first connecting terminal to the first bump pad; forming a protective layer on the first wiring structure such that at least a portion of the surface of the first connecting terminal is exposed; forming a metal protective film having a higher melting point than the first connecting terminal on the first connecting terminal; and removing the protective layer.

[0009] In one embodiment, the method further includes the step of applying heat to the package substrate to adhere it to the main substrate, and in the step of adhering the package substrate to the main substrate, the metal protective film of the package substrate and the first connecting terminal are fused together and can become a substrate connecting terminal that electrically and physically connects the package substrate and the main substrate.

[0010] In one embodiment, at the stage of attaching the package substrate to the main substrate, a portion of the metal protective film may not fuse with the first connecting terminal and may become fragments of the metal protective film located inside the substrate connecting terminal.

[0011] In one embodiment, each of the first connecting terminals contains 30 WT% to 60 WT% of tin, and each of the metal protective films contains 95 WT% to 99 WT% of tin.

[0012] In one embodiment, a metal compound film may be formed on the surface of the connecting terminal when the first connecting terminal is attached.

[0013] In one embodiment, if the protective layer comes into contact with a part of the surface of the first connecting terminal during the process of forming the metal protective film, the metal protective film is not formed on the portion where the protective layer and the first connecting terminal come into contact.

[0014] In one embodiment, each of the first connecting terminals has a first hardness and a first tensile strength, each of the metal protective films has a second hardness greater than the first hardness and a second tensile strength greater than the first tensile strength, and the thickness of the metal protective film may be 3 μm to 10 μm. [Brief explanation of the drawing]

[0015] [Figure 1A] This is a schematic cross-sectional view showing a package substrate according to an exemplary embodiment. [Figure 1B] This is a schematic cross-sectional view showing a package substrate according to an exemplary embodiment. [Figure 2] This is a magnified view showing a schematic representation of the "EX" portion of the package substrate in Figure 1A. [Figure 3] This is an enlarged view illustrating a schematic, enlarged portion of a package substrate according to an exemplary embodiment. [Figure 4] This is an enlarged view illustrating a schematic, enlarged portion of a package substrate according to an exemplary embodiment. [Figure 5] This is an enlarged view illustrating a schematic, enlarged portion of a package substrate according to an exemplary embodiment. [Figure 6] This is an enlarged view illustrating a schematic, enlarged portion of a package substrate according to an exemplary embodiment. [Figure 7] This is an enlarged view illustrating a schematic, enlarged portion of a package substrate according to an exemplary embodiment. [Figure 8] This is an enlarged view illustrating a schematic, enlarged portion of a package substrate according to an exemplary embodiment. [Figure 9] This is an enlarged view illustrating a schematic, enlarged portion of a package substrate according to an exemplary embodiment. [Figure 10] This is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment. [Figure 11] This is a flowchart illustrating the process of a semiconductor package manufacturing method according to one embodiment of the technical concept of the present invention. [Figure 12A] Cross-sectional views sequentially showing a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 12B] Cross-sectional views sequentially showing a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 12C] Cross-sectional views sequentially showing a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 12D] Cross-sectional views sequentially showing a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 12E] Cross-sectional views sequentially showing a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 12F] Cross-sectional views sequentially showing a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 13] A flowchart schematically showing the process of a semiconductor package testing method according to an embodiment of the technical idea of the present invention. [Figure 14A] A drawing showing a part of a semiconductor package testing method according to an exemplary embodiment. [Figure 14B] A drawing showing a part of a semiconductor package testing method according to an exemplary embodiment. [Figure 15] A cross-sectional view showing a part of a semiconductor package testing method according to an exemplary embodiment. [Figure 16] A cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment.

DETAILED DESCRIPTION OF THE INVENTION

[0016] Exemplary embodiments of the present invention are provided to more fully explain the present invention to those having ordinary knowledge in the technical field to which the concept of the present invention belongs. The following embodiments can be modified into various other forms, and the scope of the present invention is not limited to the following embodiments. Rather, these embodiments are provided to further enrich and complete the present disclosure and to fully convey the idea of the present invention to those having ordinary knowledge.

[0017] Figures 1A and 1B are schematic cross-sectional views showing package substrates 100 and 100R according to exemplary embodiments. Figure 2 is a schematic enlarged view showing the "EX" portion of the package substrate 100 in Figure 1A.

[0018] Referring to Figures 1A and 2, the package substrate 100 may include a base layer 110, through-vias 110_V, a first wiring structure 121, a second wiring structure 122, a first bump pad 130, a second bump pad 160, a first connecting terminal 140, and a metal protective film 150. In one embodiment, the package substrate 100 may be a printed circuit board (PCB) or a module substrate on which semiconductor chips are mounted.

[0019] Hereinafter, unless otherwise defined, the direction parallel to the upper surface of the base layer 110 is defined as the first horizontal direction (X direction), the direction perpendicular to the upper surface of the base layer 110 is defined as the vertical direction (Z direction), and the direction perpendicular to the first horizontal direction (X direction) and the vertical direction (Z direction) is defined as the second horizontal direction (Y direction). The horizontal direction is defined as the direction obtained by combining the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0020] The base layer 110 includes a first surface 110_1 and a second surface 110_2 that are opposite to each other, and the first surface 110_1 and the second surface 110_2 of the base layer 110 may each be planar. The base layer 110 may have a substantially flat or panel-like shape. For example, referring to Figure 1, the first surface 110_1 of the base layer 110 refers to the bottom surface of the base layer 110, and the second surface 110_2 refers to the top surface of the base layer 110.

[0021] The base layer 110 may contain at least one substance selected from phenolic resin, epoxy resin, and polyimide. For example, the base layer 110 may contain at least one substance selected from prepreg, polyimide, FR-4 (Flame Retardant 4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (bismaleimide triazine), thermostat, cyanate ester, and liquid crystal polymer.

[0022] The base layer 110 may further include through vias 110_V. The through vias 110_V penetrate the base layer 110 and extend from the first surface 110_1 to the second surface 110_2 of the base layer 110. The through vias 110_V can electrically connect the first wiring structure 121 and the second wiring structure 122. For example, the first portion of the through via 110_V may be in contact with the first wiring pattern 121_P of the first wiring structure 121, and the second portion may be in contact with the second wiring pattern 122_P of the second wiring structure 122.

[0023] For example, through vias 110_V can be formed conformally on the side surface of a through hole after a through hole has been formed extending from the first surface 110_1 of the base layer 110 to the second surface 110_2 of the base layer 110. For example, through vias 110_V can be formed through an electroplating process.

[0024] The first wiring structure 121 may be located on the first surface 110_1 of the base layer 110. The first wiring structure 121 may include multiple wiring layers. For example, the first wiring structure 121 may include 4 to 8 wiring layers. However, the number of layers in the first wiring structure 121 is not limited thereto.

[0025] The thickness of the first wiring structure 121 may vary depending on the number of wiring layers included in the first wiring structure 121. In one embodiment, the thickness of the first wiring structure 121 may be 100 to 1000 μm.

[0026] Each of the multiple wiring layers of the first wiring structure 121 may include a corresponding first wiring pattern 121_P and a first interlayer insulating layer 121_D surrounding the first wiring pattern 121_P. The first wiring pattern 121_P may include a first wiring line 121_L extending horizontally from the first interlayer insulating layer 121_D and a first wiring via 121_V extending vertically (Z direction) from the first wiring line 121_L. In one embodiment, the first interlayer insulating layers 121_D of each of the multiple wiring layers of the first wiring structure 121 can form a one-body without any interfaces between them.

[0027] For example, the first interlayer insulating layer 121_D can insulate first wiring lines 121_L located in different wiring layers. The first wiring via 121_V can penetrate the first interlayer insulating layer 121_D and be electrically connected to the first wiring lines 121_L located in different wiring layers.

[0028] The second wiring structure 122 may be formed on the second surface 110_2 of the base layer 110. The second wiring structure 122 may include multiple wiring layers. For example, the second wiring structure 122 may include 4 to 8 wiring layers. However, the number of layers in the second wiring structure 122 is not limited thereto.

[0029] The thickness of the second wiring structure 122 may vary depending on the number of wiring layers included in the second wiring structure 122. In one embodiment, the number of wiring layers in the second wiring structure 122 and the number of wiring layers in the first wiring structure 121 may be the same or different. In one embodiment, the thickness of the second wiring structure 122 may be 100 μm to 1000 μm.

[0030] Each of the multiple wiring layers of the second wiring structure 122 may include a corresponding second wiring pattern 122_P and a second interlayer insulating layer 122_D surrounding the second wiring pattern 122_P. The second wiring pattern 122_P may include a second wiring line 122_L extending horizontally from the second interlayer insulating layer 122_D and a second wiring via 122_V extending vertically (Z-direction) from the second wiring line 122_L. In one embodiment, the second interlayer insulating layers 122_D of each of the multiple wiring layers of the second wiring structure 122 may form a one-body without any interfaces between them.

[0031] For example, the second interlayer insulating layer 122_D can insulate second wiring lines 122_L located on different wiring layers. Second wiring vias 122_V can penetrate the second interlayer insulating layer 122_D and be electrically connected to second wiring lines 122_L located on different wiring layers.

[0032] In one embodiment, the first wiring pattern 121_P and the second wiring pattern 122_P may contain metals or alloys thereof such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru). In one embodiment, the first interlayer insulating layer 121_D and the second interlayer insulating layer 122_D may contain PPG (Polypropylene Glycol). Of course, the material of the second interlayer insulating layer is not limited to PPG.

[0033] The first bump pad 130 is positioned on the first wiring structure 121 and may be electrically connected to the first wiring pattern 121_P of the first wiring structure 121. For example, the first bump pad 130 may be positioned on the first wiring structure 121, separated from the base layer 110. The first bump pad 130 may be positioned on the lower surface of the first wiring structure 121.

[0034] The second bump pad 160 may be placed on the second wiring structure 122 and electrically connected to the second wiring pattern 122_P of the second wiring structure 122. The second bump pad 160 may be spaced apart from the base layer and placed on the second wiring structure 122. The second bump pad 160 may be placed on the upper surface of the second wiring structure 122.

[0035] In one embodiment, the first bump pad 130 may be referred to as the lower bump pad, and the second bump pad 160 may be referred to as the upper bump pad. In one embodiment, the first bump pad 130 may be part of the first wiring pattern 121_P, and the second bump pad 160 may be part of the second wiring pattern 122_P. For example, the first bump pad 130 may be part of the first wiring line 121_L located in the lowest wiring layer, and the second bump pad 160 may be part of the second wiring line 122_L located in the uppermost wiring layer.

[0036] For example, the first bump pad 130 and the second bump pad 160 may contain conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0037] The first passivation layer 130_P is located on the first wiring structure 121 and may surround the first bump pad 130. The first passivation layer 130_P may include an opening that overlaps the first bump pad 130 perpendicularly (in the Z direction). The lower surface of the first bump pad 130 may be exposed to the outside through the opening in the first passivation layer 130_P.

[0038] In one embodiment, the thickness of the first passivation layer 130_P is greater than the thickness of each of the first bump pads 130. The sides of the first passivation layer 130_P may be aligned perpendicularly (in the Z direction) to the sides of the first wiring structure 121. In one embodiment, the width of each opening in the first passivation layer 130_P is smaller than the width of each of the first bump pads 130.

[0039] The second passivation layer 160_P is located on the second wiring structure 122 and may surround the second bump pad 160. In one embodiment, the second passivation layer 160_P may include an opening that overlaps the second bump pad 160 perpendicularly (in the Z direction). The upper surface of the second bump pad 160 may be exposed to the outside through the opening in the second passivation layer 160_P. The sides of the second passivation layer 160_P may be aligned perpendicularly (in the Z direction) with the sides of the second wiring structure 122. In one embodiment, the width of each opening in the first passivation layer 130_P is smaller than the width of each of the first bump pads 130.

[0040] Each of the first connecting terminals 140 may be positioned on each of the first bump pads 130. For example, each of the first connecting terminals 140 may be positioned inside an opening in the first passivation layer 130_P and in contact with the first bump pad 130. For example, each of the first connecting terminals 140 may be in contact with a side wall of the first passivation layer 130_P that defines an opening in the first passivation layer 130_P.

[0041] Each of the first connecting terminals 140 may include a first surface 140_1 and a second surface 140_2. The first surface 140_1 of the first connecting terminal 140 is the portion that contacts one of the first bump pad 130 and the first passivation layer 130_P, and the second surface 140_2 of the first connecting terminal 140 may be the other portion.

[0042] The first connecting terminal 140 may be configured to electrically and physically connect the package substrate 100 to the external equipment on which the package substrate 100 is mounted. For example, the first connecting terminal 140 may be formed from a solder ball or a solder bump. For example, the first connecting terminal 140 may be a low-melting-point solder ball or a low-melting-point solder bump with a relatively low melting point.

[0043] Each metal protective film 150 may be placed on the second surface 140_2 of each first connecting terminal 140. For example, each metal protective film 150 may cover the second surface 140_2 of the corresponding connecting terminal among the first connecting terminals 140. In one embodiment, the first surface 140_1 of the first connecting terminal 140 may be in contact with the first bump pad 130 or the first passivation layer 130_P, and the second surface 140_2 of the first connecting terminal 140 may be in contact with the metal protective film 150. In one embodiment, the first connecting terminal 140 and the metal protective film 150 together may be referred to as a bump.

[0044] In one embodiment, the first connecting terminal 140 may be a solder ball having a diameter of 100 μm to 600 μm. For example, the maximum width of each first connecting terminal 140 may be 100 μm to 600 μm. In this specification, the width of each first connecting terminal 140 may mean the horizontal length of each first connecting terminal 140.

[0045] For example, each metal protective film 150 may conformally form on the second surface 140_2 of the corresponding first connecting terminal 140. For example, the first connecting terminal 140 may be completely covered by the metal protective film 150 and not exposed to the outside.

[0046] In one embodiment, each metal protective film 150 may have a thickness of 3 μm to 10 μm. In this specification, when the surface of the metal protective film 150 that is in contact with each of the first connecting terminals 140 is referred to as the inner surface, and the surface of the metal protective film 150 that is exposed to the outside is referred to as the outer surface, the distance from the inner surface of the metal protective film 150 to the outer surface of the metal protective film 150 may be referred to as the thickness of the metal protective film 150. In this specification, conformally formed metal protective films 150 mean that each metal protective film 150 is formed to have a constant thickness.

[0047] Each of the first connecting terminals 140 and the metal protective film 150 may contain tin (Sn) as a constituent material. The melting point of each of the first connecting terminals 140 may be the first temperature, and the melting point of each of the metal protective films 150 may be the second temperature. For example, the first temperature is lower than the second temperature. Each of the metal protective films 150 has a higher melting point than the first connecting terminals 140. In one embodiment, the first temperature is 140 to 180°C, and the second temperature is 200 to 240°C.

[0048] In one embodiment, each of the first connecting terminals 140 has a first hardness, and each of the metal protective films 150 has a second hardness. The first hardness is lower than the second hardness. For example, the metal protective film 150 has a higher hardness than the first connecting terminals 140, and is less susceptible to deformation by external forces than the first connecting terminals 140. In one embodiment, the first hardness may be 60% to 75% of the second hardness at the temperature during which the burn-in test is performed.

[0049] In one embodiment, each of the first connecting terminals 140 may have a first tensile strength, and each of the metal protective films 150 may have a second tensile strength. The first tensile strength is lower than the second tensile strength. For example, the metal protective film 150 has a higher tensile strength than the first connecting terminals 140 and is less likely to break due to external forces than the first connecting terminals 140. In one embodiment, at the temperature during the burn-in test, the first tensile strength is 50% to 75% of the second tensile strength.

[0050] For example, each of the first connecting terminals 140 may be a solder alloy containing 30 WT% to 60 WT% of tin. Each of the metal protective films 150 may be a solder alloy containing 96 WT% to 99 WT% of tin. For example, the first connecting terminals 140 may be a tin-bismuth (Sn-Bi) based solder alloy, and the metal protective film 150 may be a tin-silver-copper (SAC) based solder alloy.

[0051] The first connecting terminals 140 attached to the package substrate 100 have a relatively low melting point, which can improve the reliability of adhesion during the process of mounting the package substrate 100 to external equipment. However, in a burn-in test to test the performance of the package substrate 100, the first connecting terminals 140 of the package substrate 100 may melt, deform their shape, and contaminate the burn-in test equipment. In the package substrate 100 according to the technical concept of the present invention, the metal protective film 150 surrounding the surface of the first connecting terminals 140 has a higher melting point than the first connecting terminals 140, so even if the first connecting terminals 140 melt, contamination of the burn-in test equipment can be suppressed. Moreover, in the package substrate 100 according to the technical concept of the present invention, the phenomenon of scratches or cracks occurring on the first connecting terminals 140 and the metal protective film 150 can be suppressed through the metal protective film 150, which has higher tensile strength and hardness than the first connecting terminals 140.

[0052] Referring to Figure 1B, the package substrate 100R may include a base layer 110R, a wiring structure 120R, a first bump pad 130R, a second bump pad 160R, a first connecting terminal 140, and a metal protective film 150. In one embodiment, the package substrate 100 may be an interposer substrate or a re-distribution layer (RDL).

[0053] The base layer 110R may be a multilayer structure in which a wiring structure 120R is located in each layer. For example, the base layer 110R may consist of an insulating material, such as a photo-imaginable dielectric (PID) resin. In this case, the base layer 110R may further contain an inorganic filler.

[0054] The wiring structure 120R may be located within the base layer 110R. The wiring structure 120R may include wiring lines 120R_L extending horizontally from the upper or lower surface of each layer of the base layer 110R and wiring vias 120_V extending vertically (in the Z direction) from the wiring lines 120R_L. For example, the wiring vias 120R_V may electrically connect wiring lines 120R_L that are located at different vertical levels and penetrate at least a portion of the base layer 110R.

[0055] In one embodiment, a portion of the wiring lines 120R_L of the wiring structure 120R may be located on the first surface 110R_1 of the base layer 110R, and a portion of the wiring lines 120R_L of the wiring structure 120R may be located on the second surface 110R_2 of the base layer 110R. The wiring structure 120R may be electrically connected to external equipment on which the package substrate 100R is mounted, and may be electrically connected to external equipment mounted on the package substrate 100R.

[0056] The wiring structure 120R may contain conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0057] The first bump pad 130R may be located on the first surface 110R_1 of the base layer 110R, and the second bump pad 160R may be located on the second surface 110R_2 of the base layer 110R. The first bump pad 130R and the second bump pad 160R may be electrically connected to the wiring structure 120R. In one embodiment, the first bump pad 130R may be referred to as the lower bump pad, and the second bump pad 160R may be referred to as the upper bump pad.

[0058] Each of the first connecting terminals 140 may be located on each of the first bump pads 130R. The metal protective film 150 may be located on the surface of the first connecting terminals 140. For example, the first connecting terminals 140 and metal protective film 150 are substantially identical to the first connecting terminals 140 and metal protective film 150 described in Figure 1A.

[0059] Figure 3 is an enlarged schematic view showing a portion of the package substrate 100a according to an exemplary embodiment. Figure 4 is an enlarged schematic view showing a portion of the package substrate 100b according to an exemplary embodiment. Figure 5 is an enlarged schematic view showing a portion of the package substrate 100c according to an exemplary embodiment.

[0060] Most of the components and materials that make up the package substrates 100a, 100b, and 100c described below are substantially the same as, or similar to, those described in Figure 2. Therefore, for the sake of explanation, the differences between the package substrates 100a, 100b, and 100c in Figures 3 to 5 and the package substrate 100 in Figure 2 described above will be the focus of this explanation.

[0061] Referring to Figure 3 together with Figure 1, the package substrate 100a may include a base layer 110, through-vias 110_V, a first wiring structure 121, a second wiring structure 122, a first bump pad 130, a second bump pad 160, a first connecting terminal 140, and a metal protective film 150a.

[0062] The first connecting terminal 140 may be attached to a first bump pad 130 located on the lower surface of the first wiring structure 121. The first connecting terminals 140 may be attached to different first bump pads 130. The first connecting terminals 140 may be low-melting-point solder balls or low-melting-point solder bumps.

[0063] Each of the metal protective films 150a may be placed on the respective surface of the first connecting terminal 140. For example, each of the metal protective films 150a may cover the surface of the corresponding connecting terminal of the first connecting terminal 140. The first connecting terminal 140 is covered by the metal protective film 150a and is not exposed to the outside.

[0064] The melting point of the metal protective film 150a is higher than that of the first connecting terminal 140. The tensile strength and hardness of the metal protective film 150a are higher than those of the first connecting terminal 140. The weight ratio of tin contained in each of the metal protective films 150a is greater than the weight ratio of tin contained in each of the first connecting terminals 140.

[0065] For example, the metal protective film 150a becomes thicker the further it is from the first passivation layer 130_P. For example, the thickness of the metal protective film 150a is not constant.

[0066] For example, each of the metal protective films 150a has a relatively greater thickness at the part located below the first connecting terminal 140 than at the part located on each side of the first connecting terminal 140, and the degree of deformation of the metal protective film 150a due to external force applied from below the first connecting terminal 140 is relatively small.

[0067] Referring to Figure 4 together with Figure 1, the package substrate 100b may include a base layer 110, through-vias 110_V, a first wiring structure 121, a second wiring structure 122, a first bump pad 130, a second bump pad 160, a first connecting terminal 140, and a metal protective film 150b.

[0068] The metal protective film 150b may be positioned on the surface of the first connecting terminal 140 attached to the first bump pad 130. The metal protective film 150b and the first passivation layer 130_P may be separated in the vertical direction (Z direction) to form a gap G between each of the metal protective film 150b and each of the first passivation layer 130_P. The gap G may be ring-shaped surrounding the first connecting terminal 140. In one embodiment, the length of the gap G in the vertical direction (Z direction) may be 10 μm to 70 μm.

[0069] For example, a portion of each of the first connecting terminals 140 may be exposed to the outside through a gap G. For example, a gap G may be placed on a portion of the second surface 140_2 of each of the first connecting terminals 140, and a portion of the second surface 140_2 may be exposed to the outside. For example, a gap G may be placed on a portion of the second surface 140_2 of the first connecting terminal 140, and a metal protective film 150b may be formed on the remainder. For example, in the process of forming the metal protective film 150b, a portion of the second surface 140_2 of the first connecting terminal 140 may be covered by a protective layer PL (see Figure 12D) described later, and a gap G may be formed where the metal protective film 150b is not formed.

[0070] The metal protective film 150b may be conformally formed on the second surface 140_2 of the first connecting terminal 140. For example, the thickness of each metal protective film 150b is constant. In one embodiment, each metal protective film 150b may have a thickness of 3 μm to 10 μm.

[0071] Referring to Figure 5 together with Figure 1, the package substrate 100c may include a base layer 110, through-vias 110_V, a first wiring structure 121, a second wiring structure 122, a first bump pad 130, a second bump pad 160, a first connecting terminal 140, and a metal protective film 150c.

[0072] The metal protective film 150c may be placed on the surface of the first connecting terminal 140 attached to the first bump pad 130. The metal protective film 150c may be separated from the first bump pad 130 in the perpendicular direction (Z direction), forming a gap G. For example, a portion of the surface of the first connecting terminal 140 may be exposed to the outside through the gap G. For example, the gap G may be in the shape of a ring of a certain length in the perpendicular direction (Z direction).

[0073] The thickness of the metal protective film 150c increases with distance from the first passivation layer 130_P. For example, the thickness of the metal protective film 150c formed on the first connecting terminal 140 is not constant. For example, the thickness of each metal protective film 150c is relatively greater at the bottom of the first connecting terminal 140 than at the sides of the first connecting terminal 140.

[0074] Figure 6 is an enlarged view schematically showing a portion of the package substrate 100d according to an exemplary embodiment.

[0075] Most of the components and materials that make up the package substrate 100d described below are substantially the same as, or similar to, those described in Figure 2 above. Therefore, for the sake of explanation, the differences between the package substrate 100d in Figure 6 and the package substrate 100 in Figure 2 above will be the focus of this explanation.

[0076] Referring to Figure 6 together with Figure 1, the package substrate 100d may include a base layer 110, through-vias 110_V, a first wiring structure 121, a second wiring structure 122, a first bump pad 130, a second bump pad 160, a first connecting terminal 140', a metal compound film 145, and a metal protective film 150a.

[0077] The first bump pad 130 is electrically connected to the first wiring structure 121 and may be formed on the lower surface of the first wiring structure 121. Each of the first connecting terminals 140' is positioned within an opening in the first passivation layer 130_P and may be attached to each of the first bump pads 130.

[0078] Each surface of the first connecting terminal 140' may be divided into a first surface 140'_1 and a second surface 140'_2. For example, the first surface 140'_1 of the first connecting terminal 140' may be the portion that contacts the first bump pad 130 and one of the first passivation layers 130_P, while the second surface 140'_2 of the first connecting terminal 140' may be the portion that does not contact the first bump pad 130. Each metal compound film 145 may be placed on each surface of the first connecting terminal 140'. For example, each metal compound film 145 may be placed on each second surface 140'_2 of the first connecting terminal 140'. For example, since the area of ​​each metal compound film 145 is smaller than the area of ​​each second surface 140'_2 of the first connecting terminal 140', each metal compound film 145 cannot completely cover the second surface 140'_2 of the first connecting terminal 140'.

[0079] In one embodiment, the metal compound film 145 may be formed on the second surface 140'_2 of the first connecting terminal 140' by a chemical reaction between the first connecting terminal 140' and the first bump pad 130 during the process of attaching the first connecting terminal 140' to the first bump pad 130. For example, the metal compound film 145 may contain gold (Au) as a constituent material.

[0080] The metal protective film 150 may be located on the second surface 140'_2 of the first connecting terminal 140' and on the metal compound film 145. For example, the metal protective film 150 may surround the first connecting terminal 140' and the metal compound film 145. The metal compound film 145 may be interposed between the metal protective film 150 and the first connecting terminal 140'. For example, the metal compound film 145 may be completely covered by the metal protective film 150 and not exposed to the outside.

[0081] For example, each of the metal protective films 150 may conformally form on the second surface 140'_2 of the corresponding connecting terminal among the first connecting terminals 140' and on the metal compound film 145. In one embodiment, each of the metal protective films 150 may have a thickness of 3 μm to 10 μm.

[0082] In one embodiment, the first connecting terminal 140' may be a low-melting-point solder ball or a low-melting-point solder bump. Parts of each surface of the first connecting terminal 140' may be angular. For example, parts of each second surface 140'_2 of the first connecting terminal 140' may be angular. For example, the first connecting terminal 140' may be spherical with a portion cut off. For example, during the process of the first connecting terminal 140' being attached to the first bump pad 130, a chemical reaction between the first connecting terminal 140' and the first bump pad 130 may cause a portion of the second surface 140'_2 of the first connecting terminal 140' to become angular.

[0083] The melting point of the metal protective film 150 is higher than that of the first connecting terminal 140'. The tensile strength and hardness of the metal protective film 150 are higher than those of the first connecting terminal 140'. The weight ratio of tin contained in each of the metal protective films 150 is greater than the weight ratio of tin contained in each of the first connecting terminals 140'.

[0084] For example, the melting point of each first connecting terminal 140' is 140-180°C, and the melting point of each metal protective film 150 is 200-240°C. At the temperature at which the burn-in test is performed, the hardness of each first connecting terminal 140' is 60%-75% of the hardness of each metal protective film 150. At the temperature at which the burn-in test is performed, the tensile strength of each first connecting terminal 140' is 50%-75% of the tensile strength of each metal protective film 150. Each first connecting terminal 140' may be a solder alloy containing 30 WT%-60 WT% tin. Each metal protective film 150 may be a solder alloy containing 96 WT%-99 WT% tin.

[0085] The metal compound film 145 may have a first reflectance, and the metal protective film 150 may have a second reflectance. For example, the first reflectance is higher than the second reflectance. Moreover, the metal compound film 145 has a higher reflectance than the metal protective film 150 and the first connecting terminal 140. That is, when the same amount of light is incident on the metal compound film 145 and the metal protective film 150 respectively, the metal compound film 145 may reflect more light than the metal protective film 150.

[0086] During the process of visual testing to determine whether bumps are attached to the package substrate 100d, when the metal compound film 145 is exposed to the outside, the metal compound film 145 reflects a large amount of light, reducing the reliability of the visual test. The metal compound film 145 is covered by the metal protective film 150 and is not exposed to the outside. Therefore, in the present invention, the package substrate 100d has the metal compound film 145 covered by the metal protective film 150, which reduces the amount of light reflected during testing and can improve the reliability of the visual test.

[0087] Figure 7 is an enlarged schematic view showing a portion of the package substrate 100e according to an exemplary embodiment. Figure 8 is an enlarged schematic view showing a portion of the package substrate 100f according to an exemplary embodiment. Figure 9 is an enlarged schematic view showing a portion of the package substrate 100g according to an exemplary embodiment.

[0088] Most of the components and materials that make up the package substrates 100e, 100f, and 100g described below are substantially the same as, or similar to, those described in Figure 6. Therefore, for the sake of explanation, the differences between the package substrates 100e, 100f, and 100g in Figures 7 to 9 and the package substrate 100d in Figure 6 will be explained in detail.

[0089] Referring to Figure 7 together with Figure 1, the package substrate 100e may include a base layer 110, through-vias 110_V, a first wiring structure 121, a second wiring structure 122, a first bump pad 130, a second bump pad 160, a first connecting terminal 140', a metal compound film 145, and a metal protective film 150e.

[0090] The first connecting terminal 140' is attached to the first bump pad 130 located on the lower surface of the first wiring structure 121 and may be located inside the opening of the first passivation layer 130_P. The first connecting terminal 140' may be a low-melting-point solder ball or a low-melting-point solder bump.

[0091] Each metal protective film 150e may be located on the second surface 140'_2 and the metal compound film 145 of each first connecting terminal 140'. The second surface 140'_2 and the metal compound film 145 of the first connecting terminal 140' are covered by the metal protective film 150e and are not exposed to the outside.

[0092] The metal protective film 150e becomes thicker the further it is from the first passivation layer 130_P. For example, the thickness of the metal protective film 150e is not constant.

[0093] For example, each of the metal protective films 150e has a relatively greater thickness at the bottom of the first connecting terminal 140' than at the sides of the first connecting terminal 140', resulting in a relatively smaller degree of deformation of the metal protective film 150e due to external forces applied from the bottom of the first connecting terminal 140'.

[0094] Referring to Figure 8 together with Figure 1, the package substrate 100f may include a base layer 110, through-vias 110_V, a first wiring structure 121, a second wiring structure 122, a first bump pad 130, a second bump pad 160, a first connecting terminal 140', a metal compound film 145, and a metal protective film 150f.

[0095] The metal protective film 150f may be positioned on the second surface 140'_2 of the first connecting terminal 140' attached to the first bump pad 130 and on the metal compound film 145. The metal protective film 150f and the first passivation layer 130_P may be separated in the vertical direction (Z direction) to form a gap G between each of the metal protective film 150f and each of the first bump pads 130. The gap G may be ring-shaped surrounding the first connecting terminal 140'. In one embodiment, the length of the gap G in the vertical direction (Z direction) may be 10 μm to 70 μm.

[0096] For example, a portion of each of the first connecting terminals 140' may be exposed to the outside through the gap G. For example, a gap G may be located on a portion of the second surface 140'_2 of each of the first connecting terminals 140', and a portion of the second surface 140'_2 may be exposed to the outside. In one embodiment, the portion of the metal compound film 145 on which the gap G is located may be exposed to the outside.

[0097] The metal protective film 150f may be conformally formed on the second surface 140'_2 of the first connecting terminal 140'. For example, the thickness of each metal protective film 150f is constant. In one embodiment, each metal protective film 150f may have a thickness of 3 μm to 10 μm.

[0098] Referring to Figure 9 together with Figure 1, the package substrate 100g may include a base layer 110, through-vias 110_V, a first wiring structure 121, a second wiring structure 122, a first bump pad 130, a second bump pad 160, a first connecting terminal 140', a metal compound film 145, and a metal protective film 150g.

[0099] The metal protective film 150g may be placed on the second surface 140'_2 of the first connecting terminal 140' which is attached to the first bump pad 130. The metal protective film 150g may be separated from the first bump pad 130 in the direction perpendicular to the first bump pad (Z direction), forming a gap G. For example, a portion of the surface of the first connecting terminal 140' may be exposed to the outside through the gap G. For example, the gap G may be in the shape of a ring of a certain length in the direction perpendicular to the first bump pad (Z direction).

[0100] The thickness of the metal protective film 150g increases with distance from the first passivation layer 130_P. For example, the thickness of the metal protective film 150g formed on the first connecting terminal 140' is not constant. For example, each portion of the metal protective film 150g is relatively thicker at the bottom of the first connecting terminal 140' than at the sides of the first connecting terminal 140'.

[0101] Figure 10 is a schematic cross-sectional view showing a semiconductor package 1000 according to an exemplary embodiment.

[0102] Referring to Figure 10, the semiconductor package 1000 may include a package substrate 100 to which first connecting terminals 140 and a metal protective film 150 are attached, a semiconductor chip 200, and a molding layer ML.

[0103] The package substrate 100 may include a base layer 110 including a first surface 110_1 and a second surface 110_2 opposite to it, a first wiring structure 121 located on the first surface 110_1 of the base layer 110, a second wiring structure 122 located on the second surface 110_2 of the base layer 110, through vias 110_V that penetrate the base layer 110 and are electrically connected to the first wiring structure 121 and the second wiring structure 122, a first bump pad 130 located on the lower surface of the first wiring structure 121, and a second bump pad 160 located on the upper surface of the second wiring structure 122.

[0104] The first connecting terminal 140 is attached to the first bump pad 130 of the package substrate 100, and the metal protective film 150 may be located on the surface of the first connecting terminal 140. The melting point of the first connecting terminal 140 is lower than the melting point of the metal protective film 150. The hardness of the first connecting terminal 140 is lower than the hardness of the metal protective film 150. The tensile strength of the first connecting terminal 140 is lower than the tensile strength of the metal protective film 150.

[0105] The package substrate 100 may be one of the package substrates 100, 100R, 100a, 100b, 100c, 100d, 100e, 100f, and 100g shown in Figures 1A, 1B, and 2 through 9.

[0106] The semiconductor chip 200 may be located on the second wiring structure 122 of the package substrate 100. The semiconductor chip 200 may include an active surface and an inactive surface opposite it. The semiconductor chip 200 may be placed on the second surface 110_2 of the base layer 110 of the package substrate 100 such that the active surface faces the package substrate 100. For example, the semiconductor chip 200 may be placed on the package substrate 100 in a face-down manner.

[0107] The semiconductor chip 200 may contain semiconductor materials such as silicon (Si) or germanium (Ge). Alternatively, the semiconductor chip 200 may contain compound semiconductor materials such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The semiconductor chip 200 may contain wells doped with impurities that constitute conductive regions. The semiconductor chip 200 may have various element isolation structures, such as a shallow trench isolation (STI) structure.

[0108] A semiconductor element comprising multiple individual devices of various types may be formed on the active surface of the semiconductor chip 200. These multiple individual devices may be included in the conductive region of the semiconductor chip 200.

[0109] The semiconductor device may further include conductive wiring or conductive plugs that electrically connect the plurality of discrete elements and the conductive region of the semiconductor chip 200. Furthermore, the plurality of discrete elements may be electrically isolated from other adjacent discrete elements by their respective insulating films.

[0110] In one embodiment, the semiconductor chip 200 may include logic elements. For example, the semiconductor chip 200 may be a central processing unit chip, a graphics processing unit chip, or an AP (Application Processor). In another embodiment, if the semiconductor package 1000 includes a plurality of semiconductor chips 200, one of the plurality of semiconductor chips 200 may be a central processing unit chip, a graphics processing unit chip, or an application processor chip, and another may be a memory semiconductor chip including memory elements.

[0111] For example, the memory element may be a non-volatile memory element such as flash memory, PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory). In one embodiment, the memory element may be a volatile memory element such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).

[0112] In one embodiment, the semiconductor chip 200 may further include a chip pad 210. The chip pad 210 may be electrically connected to the conductive region and the plurality of discrete elements through the wiring pattern of the semiconductor chip 200. For example, the chip pad 210 may be made of a conductive material, such as aluminum (Al).

[0113] Chip connection terminals 220 may be positioned between the semiconductor chip 200 and the package substrate 100. Each of the chip connection terminals 220 may be positioned between the second bump pad 160 of the package substrate 100 and the chip pad 210 of the semiconductor chip 200. The semiconductor chip 200 may be physically and electrically connected to the package substrate 100 through the chip connection terminals 220. However, it is not limited to this, and the semiconductor chip 200 may also be physically and electrically connected to the package substrate 100 via hybrid bonding, direct bonding, conductive adhesive film, etc.

[0114] The molding layer ML is located on the package substrate 100 and may surround the semiconductor chip 200. The sides of the molding layer ML may be aligned perpendicularly (in the Z direction) to the sides of the base layer 110 of the package substrate 100. The top surface of the molding layer ML may be coplane with the top surface of the semiconductor chip 200. For example, the top surface of the semiconductor chip 200 may be exposed to the outside.

[0115] In one embodiment, the molding layer ML may include an epoxy resin or a polyimide resin. The molding layer ML may be composed of, for example, an epoxy molding compound (EMC).

[0116] Figure 11 is a flowchart schematically showing the process of a semiconductor package manufacturing method (S100) according to one embodiment of the technical concept of the present invention. Figures 12A to 12F are cross-sectional views sequentially showing a method for manufacturing a semiconductor package 1000 according to an exemplary embodiment.

[0117] Referring to Figure 11, the semiconductor package manufacturing method (S100) may include the steps of mounting a semiconductor chip 200 on a second wiring structure 122 of a package substrate 100 (S110), attaching a first connecting terminal 140 to a first bump pad 130 of a package substrate 100 (S120), forming a protective layer PL on a first wiring structure 121 of a package substrate 100 (S130), forming a metal protective film 150 on the first connecting terminal 140 (S140), and removing the protective layer PL (S150).

[0118] Referring to Figure 12A, the package substrate 100 is prepared.

[0119] The package substrate 100 may include a base layer 110, a first wiring structure 121 located on the first surface 110_1 of the base layer 110, a second wiring structure 122 located on the second surface 110_2 of the base layer 110, through vias 110_V that penetrate the base layer 110 and electrically connect the first wiring structure 121 and the second wiring structure 122, a first bump pad 130 located on the lower surface of the first wiring structure 121, a second bump pad 160 located on the upper surface of the second wiring structure 122, a first passivation layer 130_P disposed on the lower surface of the first wiring structure 121, surrounding the first bump pad 130 and including an opening that overlaps with the first bump pad 130 in the vertical direction (Z direction), and a second passivation layer 160_P disposed on the upper surface of the second wiring structure 122 and surrounding the second bump pad 160.

[0120] The base layer 110 may include a first surface 110_1 and a second surface 110_2 opposite to it. Depending on the orientation in which the base layer 110 is positioned, the first surface 110_1 of the base layer 110 may be referred to as the bottom surface of the base layer 110, and the second surface 110_2 of the base layer 110 may be referred to as the top surface of the base layer 110.

[0121] Figure 12B shows the step (S110) of mounting the semiconductor chip 200 on the upper surface of the second wiring structure 122 in Figure 11. Referring to Figure 12B, the semiconductor chip 200 can be mounted on the package substrate 100 such that the chip pads 210 of the semiconductor chip 200 correspond to the second bump pads 160 of the package substrate 100.

[0122] The chip pad 210 and the second bump pad 160 of the semiconductor chip 200 can be physically and electrically connected through the chip connection terminal 220. The semiconductor chip 200 can be mounted on the base layer 110 in a face-down manner, such that the active surface of the semiconductor chip 200 faces the base layer 110.

[0123] Thereafter, a molding layer ML can be formed on the second surface 110_2 of the base layer 110 so as to cover the semiconductor chip 200. The upper part of the molding layer ML can be removed until the upper surface of the semiconductor chip 200 is exposed.

[0124] In this specification, the semiconductor chip 200 is mounted on the second wiring structure 122 before the first connecting terminal 140 and the metal protective film 150 are formed on the first bump pad 130. However, the specification is not limited to this, and the semiconductor chip 200 can be mounted on the second wiring structure 122 after the first connecting terminal 140 and the metal protective film 150 have been formed on the first bump pad 130.

[0125] Figure 12C shows the step (S120) in which the first connecting terminal 140 is attached to the base layer 110 of Figure 11. Referring to Figure 12C, the first connecting terminal 140 can be attached to the first bump pad 130.

[0126] The first connecting terminal 140 may be a solder ball or solder bump with a relatively low melting point. For example, the melting point of the first connecting terminal 140 may be 140 to 180°C. For example, the first connecting terminal 140 may be a solder alloy containing 30 WT% to 60 WT% tin. For example, the first connecting terminal 140 may be a tin-bismuth (Sn-Bi) based solder alloy.

[0127] For example, after placing the first connecting terminal 140 on the first bump pad 130, the first connecting terminal 140 can be attached to the first bump pad 130 through a reflow process.

[0128] In one embodiment, if the first bump pad 130 contains gold (Au), a chemical reaction may occur between the first connecting terminal 140 and the first bump pad 130 during the process of attaching the first connecting terminal 140 to the first bump pad 130 through a reflow process. For example, a chemical reaction may occur between the first connecting terminal 140 and the first bump pad 130, forming a metal compound film 145 (see Figure 6) on the surface of the first connecting terminal 140. For example, a chemical reaction may occur between the first connecting terminal 140 and the first bump pad 130, causing a portion of the second surface 140'_2 (see Figure 6) of each of the first connecting terminals 140 to be angular.

[0129] Figure 12D shows the step (S130) of forming a protective layer PL on the first passivation layer 130_P shown in Figure 11. Referring to Figure 12D, the protective layer PL can be formed on the upper surface of the first passivation layer 130_P.

[0130] The protective layer PL covers the upper surface of the first passivation layer 130_P and a portion of the side surface of the first bump pad 130. The protective layer PL may include ultraviolet tape (UV tape). For example, the thickness of the protective layer PL may be 30 μm to 150 μm.

[0131] Figure 12E shows the step (S140) of forming the metal protective film 150 on the first connecting terminal 140 of Figure 11. Referring to Figure 12E, the metal protective film 150 can be formed on the second surface 140_2 (see Figure 2) of the first connecting terminal 140.

[0132] A metal protective film 150 can be formed on the surface of each of the first connecting terminals 140 that is exposed to the outside. The metal protective film 150 can be formed on the surface of each of the first connecting terminals 140 such that its thickness is 3 μm to 10 μm.

[0133] In one embodiment, when the protective layer PL is in contact with the first connecting terminal 140, the metal protective film 150 is not formed on the portion of the surface of the first connecting terminal 140 that is in contact with the protective layer PL. For example, when the protective layer PL is in contact with a part of the side surface of the first connecting terminal 140, the metal protective film 150 may be separated from the upper surface of the first passivation layer 130_P in the direction perpendicular to the Z direction. For example, when the protective layer PL is in contact with the side surface of the first connecting terminal 140, the protective layer may be located between the metal protective film 150 and the first passivation layer 130_P.

[0134] The melting point of the metal protective film 150 is greater than that of the first connecting terminal 140. The melting point of the metal protective film 150 is 200-240°C. The metal protective film 150 may contain 95 WT%-99 WT% tin. The metal protective film 150 may also be a tin-silver-copper (SAC) based solder alloy. The hardness of the metal protective film 150 is higher than that of the first connecting terminal 140. The tensile strength of the metal protective film 150 is higher than that of the first connecting terminal 140.

[0135] In one embodiment, if a metal compound film 145 (see Figure 6) is formed on the surface of the first connecting terminal 140, the metal protective film 150 may be formed on the first connecting terminal 140, covering the metal compound film 145. For example, as shown in Figure 6, the metal compound film 145 is covered by the metal protective film 150 and not exposed to the outside. The metal compound film 145 may be interposed between the metal protective film 150 and the first connecting terminal 140.

[0136] The reflectance of each metal protective film 150 and each first connecting terminal 140 is lower than the reflectance of each metal compound film 145. For example, each metal protective film 150 may reflect less light than each metal compound film 145 when the same light is incident on it.

[0137] In one embodiment, a metal protective film 150 may be formed on the surface of the first connecting terminal 140 through a sputtering process. In one embodiment, the metal protective film 150 may be conformally formed on the exposed surface of the first connecting terminal 140. In one embodiment, the thickness of the metal protective film 150 increases with distance from the first passivation layer 130_P.

[0138] Figure 12F shows the step (S150) of removing the protective layer PL shown in Figure 11. Referring to Figure 12F, the protective layer PL can be removed from the base layer 110.

[0139] In one embodiment, the protective layer PL is irradiated with ultraviolet light to weaken its adhesive strength, allowing the protective layer PL to be removed from the first passivation layer 130_P without damaging the first passivation layer 130_P and the first connecting terminal 140.

[0140] In one embodiment, if the protective layer PL is in contact with a portion of each side surface of the first connecting terminal 140, removing the protective layer PL from the first passivation layer 130_P may form a gap G between the metal protective film 150 and the first passivation layer 130_P, as shown in Figure 4.

[0141] Figure 13 is a flowchart schematically showing the process of a semiconductor package test method (S1000) according to one embodiment of the technical concept of the present invention. Figures 14A and 14B are drawings showing a part of the semiconductor package test method (S1000) according to an exemplary embodiment. Figure 15 is a cross-sectional view showing a part of the semiconductor package test method (S1000) according to an exemplary embodiment.

[0142] Referring to Figure 13, the semiconductor package testing method (S1000) may include the steps of: fabricating a semiconductor package 1000 including a metal protective film 150 (S100'); performing an appearance test on the semiconductor package 1000 via imaging equipment Ca (S200); and performing a burn-in test on the semiconductor package 1000 via burn-in tester BT (S300).

[0143] The step of manufacturing a semiconductor package 1000 including a metal protective film 150 (S100') may be the step of manufacturing a semiconductor package 1000 by the semiconductor package manufacturing method (S100) described in Figures 12A to 12F.

[0144] Figures 14A and 14B show the steps (S200) of an appearance test on the semiconductor package 1000 via the imaging equipment Ca shown in Figure 13. Referring to Figures 14A and 14B, an appearance test of the semiconductor package 1000 can be performed. For example, the appearance of the semiconductor package 1000 can be photographed via the imaging equipment Ca to check for any abnormalities in the semiconductor package 1000. For example, the imaging equipment Ca may be part of an AVI (Auto Vision) system.

[0145] In one embodiment, the imaging equipment Ca can photograph the first connecting terminal 140 of the semiconductor package 1000. For example, the lower part of the semiconductor package 1000 can be photographed to confirm whether the first connecting terminal 140 has detached or fallen off the first bump pad 130. The imaging equipment Ca can photograph the first connecting terminal 140 located on the first surface 110_1 of the base layer 110 of the semiconductor package 1000. Thereafter, it can be confirmed whether or not the first connecting terminal 140 is attached to the first bump pad 130 through the photograph taken by the imaging equipment Ca.

[0146] Referring to Figure 6, the first connecting terminal 140 and the first bump pad 130, which have relatively low melting points, can chemically react to form a metal compound film 145 on the surface of the first connecting terminal 140. As a result, in the absence of the metal protective film 150, the metal compound film 145 can be photographed by the imaging equipment Ca. The metal compound film 145 has a higher reflectivity than the metal protective film 150 and the first connecting terminal 140.

[0147] For example, the imaging equipment Ca may determine that the position where the metal compound film 145 is photographed due to a large amount of light reflected by the metal compound film 145 is a position where the first connecting terminal 140 is not attached, and thus determine that a semiconductor package 1000 in which the first connecting terminal 140 is properly attached is a defective product. Therefore, when conducting an appearance test of a semiconductor package 1000 in which the metal protective film 150 has not been formed, it is difficult to confirm whether the first connecting terminal 140 has been properly attached to the first bump pad 130 by the metal compound film 145.

[0148] In the case of a semiconductor package 1000 that includes a metal protective film 150 with a lower reflectivity than the metal compound film 145, the metal compound film 145 is covered by the metal protective film 150 and not exposed to the outside. As a result, even when the appearance of the semiconductor package 1000 is photographed with imaging equipment Ca, the metal protective film 150 reflects relatively less light, making it possible to confirm whether the first connecting terminal 140 is properly attached to the first bump pad 130. Therefore, the reliability of the appearance test of the semiconductor package 1000 can be improved by the metal protective film 150.

[0149] Figure 15 shows the stage (S300) in which the burn-in test is performed on the semiconductor package 1000 via the burn-in tester BT shown in Figure 13. The burn-in test can test the performance of the semiconductor package 1000 under high temperature conditions. For example, the test temperature at which the burn-in test is performed may be approximately 125°C.

[0150] The burn-in tester BT may include a burn-in board BB and a socket S mounted on the burn-in board BB, on which a semiconductor package 1000 is mounted. The socket S may include pins SP that are electrically connected to the semiconductor package 1000 when the semiconductor package 1000 is mounted. However, the socket S may include pogo pins or clamps instead of pins SP.

[0151] In the case of a semiconductor package without a metal protective film 150, the first connecting terminal 140, which has a relatively low melting point, may come into direct contact with the socket S. Therefore, at the test temperature during the burn-in test, a portion of the first connecting terminal 140 may melt and contaminate the socket S.

[0152] In the semiconductor package 1000 of the present invention, the first connecting terminal 140 is located inside a metal protective film 150 with a higher melting point than the first connecting terminal 140, so that the first connecting terminal 140 does not come into direct contact with the socket S. As a result, even if the first connecting terminal 140 melts, the phenomenon of contamination of the socket S can be suppressed.

[0153] In the case of a semiconductor package without a metal protective film 150, the first connecting terminal 140, which is relatively soft with low hardness and tensile strength, may come into direct contact with the pin SP of the socket S. Therefore, cracks and scratches may occur on the surface of the first connecting terminal 140 during the burn-in test.

[0154] The semiconductor package 1000 of the present invention has a metal protective film 150 that is relatively hard, with higher hardness and tensile strength than the first connecting terminal 140, surrounding the first connecting terminal 140, thereby suppressing and preventing scratches and cracks from occurring on the first connecting terminal 140. The relatively hard metal protective film 150 is less prone to scratches and cracks on the surface than the first connecting terminal 140, which can improve the reliability of the semiconductor package 1000 when it is attached to external equipment.

[0155] Figure 16 is a schematic cross-sectional view showing a semiconductor package 2000 according to an exemplary embodiment.

[0156] Referring to Figure 16, the semiconductor package 2000 may include a package substrate 100, a main substrate 300 configured to mount the package substrate 100, a semiconductor chip 200 configured to be mounted on the package substrate 100, and a molding layer ML.

[0157] The semiconductor package 2000 may further include a substrate connection terminal 140_R that electrically and physically connects the package substrate 100 and the main substrate 300, a metal protective film fragment 150_P located inside the substrate connection terminal 140_R, and a chip connection terminal 220 that electrically and physically connects the package substrate 100 and the semiconductor chip 200.

[0158] The main board 300 may be an external device on which the package board 100 is mounted. The main board 300 may include a board bump pad 310 on its upper surface and further include internal wiring that electrically connects the board bump pad 310. For example, various semiconductor devices other than the package board 100 may be mounted on the main board 300. The main board 300 can electrically connect the package board 100 and the semiconductor devices mounted on the main board 300.

[0159] The package substrate 100, which is placed on the upper surface of the main substrate 300, may include a base layer 110, a first wiring structure 121, a second wiring structure 122, through-vias 110_V, a first bump pad 130, a second bump pad 160, a first passivation layer 130_P, and a second passivation layer 160_P.

[0160] Most of the components of the package substrate 100 and the materials that make up those components are substantially the same as or similar to those described above. Therefore, for the sake of clarity, any content that overlaps with what has been described above will be omitted.

[0161] A substrate connection terminal 140_R may be placed between the substrate bump pad 310 of the main substrate 300 and the first bump pad 130 of the package substrate 100. In one embodiment, a metal protective film fragment 150_P may be placed inside the substrate connection terminal 140_R.

[0162] The melting point of each metal protective film fragment 150_P is higher than the melting point of each substrate connecting terminal 140_R. The tensile strength and hardness of each metal protective film fragment 150_P are higher than the tensile strength and hardness of each substrate connecting terminal 140_R. For example, each substrate connecting terminal 140_R may contain 30 WT% to 60 WT% of tin, while each metal protective film fragment may contain 95 WT% to 99 WT% of tin.

[0163] After applying low-melting-point solder paste to the substrate bump pads 310 of the main substrate 300, heat is applied to the package substrate 100, which has the first connecting terminals 140 (see Figure 1) and metal protective film 150 (see Figure 1) formed on it, to adhere the package substrate 100 to the main substrate 300. For example, the low-melting-point solder paste on the substrate bump pads 310 of the main substrate 300 and the first connecting terminals and metal protective film of the package substrate 100 may be fused together through a reflow process. The fused low-melting-point solder paste, first connecting terminals, and metal protective film may be referred to as the substrate connecting terminals 140_R.

[0164] For example, during the process of applying heat to the package substrate 100, the metal protective film 150 (see Figure 1) diffuses into the first connecting terminal 140 (see Figure 1), melts, and loses its shape. However, it is not limited to this, and in one embodiment, a portion of the metal protective film may not fuse with the first connecting terminal, maintain its shape, and become metal protective film fragments 150_P.

[0165] The semiconductor chip 200 may be placed on the upper surface of the second wiring structure 122 of the package substrate 100. Chip connection terminals 220 may be placed between the semiconductor chip 200 and the package substrate 100. Each of the chip connection terminals 220 may be placed between the second bump pad 160 of the package substrate 100 and the chip pad 210 of the semiconductor chip 200.

[0166] In one embodiment, the weight ratio of tin contained in each of the chip connection terminals 220 is lower than the weight ratio of tin contained in each of the substrate connection terminals 140_R.

[0167] The molding layer ML is located on the package substrate 100 and may surround the semiconductor chip 200. The sides of the molding layer ML may be aligned perpendicularly (in the Z direction) to the sides of the base layer 110 of the package substrate 100. The top surface of the molding layer ML may be coplane with the top surface of the semiconductor chip 200. For example, the top surface of the semiconductor chip 200 may be exposed to the outside.

[0168] Although the present invention has been described above based on the embodiments illustrated in the drawings, these are merely examples, and a person with ordinary skill in the art will understand that a variety of modifications and equivalent other embodiments are possible. Therefore, the true scope of technical protection of the present invention must be determined by the technical idea of ​​the claims. [Explanation of Symbols]

[0169] 1000 semiconductor packages 100 Package Substrates 110 Base Layer 120R Wiring Structure 130 First Bump Pad 140 connecting terminals 150 Metal protective film 160 Second Bump Pad

Claims

1. A base layer including the first surface and the second surface opposite it, A through via extending from the first surface to the second surface of the base layer and penetrating through, A first wiring structure is disposed on the first surface of the base layer and includes a first wiring pattern and a first interlayer insulating layer surrounding the first wiring pattern, A first bump pad is electrically connected to the first wiring pattern of the first wiring structure and is disposed on the first wiring structure so as to be separated from the base layer with the first wiring structure in between; A first passivation layer is disposed on the first wiring structure, surrounds the first bump pad, and includes an opening that overlaps the first bump pad perpendicularly; A first connecting terminal is provided, which is located in the opening of the first passivation layer and on the first bump pad, contains tin, and has a melting point of a first temperature. The first connecting terminal includes a metal protective film disposed on its surface, containing tin and having a melting point at a second temperature, The first temperature is lower than the second temperature of the package substrate.

2. Each of the first connecting terminals has a first hardness, The package substrate according to claim 1, wherein each of the metal protective films has a second hardness greater than the first hardness.

3. Each of the first connecting terminals has a first tensile strength, The package substrate according to claim 1, wherein each of the metal protective films has a second tensile strength greater than the first tensile strength.

4. Each of the first connecting terminals contains 30 WT% to 60 WT% of tin. The package substrate according to claim 1, wherein each of the metal protective films contains 95 WT% to 99 WT% of tin.

5. The package substrate according to claim 1, wherein each of the metal protective films has a thickness of 3 μm to 10 μm.

6. The package substrate according to claim 5, wherein the maximum width of each of the first connecting terminals is 100 μm to 600 μm.

7. The package substrate according to claim 1, wherein the metal protective film is conformally arranged on each surface of the first connecting terminal, excluding the surface that is in contact with one of the first bump pads or the first passivation layer.

8. The package substrate according to claim 1, wherein the thickness of each of the metal protective films increases with increasing distance from the first passivation layer.

9. The metal protective film is separated vertically from the first bump pad and has a gap. The package substrate according to claim 1, wherein a portion of each of the first connecting terminals is exposed to the outside through the gap.

10. The package substrate according to claim 9, wherein the thickness of each of the metal protective films increases with increasing distance from the first passivation layer.

11. The first temperature is 140 to 180°C. The package substrate according to claim 1, wherein the second temperature is 200 to 240°C.

12. The width of each of the openings in the first passivation layer is smaller than the horizontal width of the first bump pad. The package substrate according to claim 1, wherein the sidewalls of the first passivation layer defining each of the openings are in contact with each of the first connecting terminals.

13. A base layer including the first surface and the second surface opposite it, A through via extending from the first surface to the second surface of the base layer and penetrating through, A first wiring structure is disposed on the first surface of the base layer and includes a first wiring pattern and a first interlayer insulating layer surrounding the first wiring pattern, A first bump pad is electrically connected to the first wiring pattern of the first wiring structure and is disposed on the first wiring structure so as to be separated from the base layer with the first wiring structure in between; A first passivation layer is disposed on the first wiring structure, surrounds the first bump pad, and includes an opening that overlaps the first bump pad perpendicularly; A first connecting terminal, which is disposed in the opening of the first passivation layer and on the first bump pad, contains tin and has a first hardness, A metal compound film is disposed on the surface of each of the first connecting terminals, A metal protective film is disposed on the surface of the first connecting terminal and the metal compound film, containing tin and having a second hardness higher than the first hardness, Includes, A package substrate wherein the melting point of the first bump pad is lower than the melting point of the metal protective film.

14. The package substrate according to claim 13, wherein the reflectance of each of the metal protective films is lower than the reflectance of the metal compound film.

15. The package substrate according to claim 13, wherein each of the metal compound films is interposed between the first connecting terminal and the metal protective film.

16. The package substrate according to claim 15, wherein each of the metal compound films is completely covered by each of the metal protective films and is not exposed to the outside.

17. The metal protective film is separated vertically from the first bump pad and has a gap. The package substrate according to claim 13, wherein a portion of each of the first connecting terminals is exposed to the outside through the gap.

18. The package substrate according to claim 17, wherein a portion of each of the metal compound films is exposed to the outside through the gap.

19. The package substrate according to claim 13, wherein each of the first connecting terminals has a part of its surface, excluding the surface in contact with the base layer, that is angular.

20. Each of the first connecting terminals contains 30 WT% to 60 WT% of tin. Each of the aforementioned metal protective films contains 95 WT% to 99 WT% of tin. The package substrate according to claim 13, wherein each of the metal compound films contains gold (Au).

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