Semiconductor device and method for manufacturing the same

Abstract

To improve the reliability of semiconductor devices. [Solution] A gate electrode GE is formed inside the trench TR. An insulating film IF3 is formed on the gate electrode GE so as to protrude from the upper surface TS of the semiconductor substrate SUB. Sidewall spacers SW are formed on the side surface of the insulating film IF3 and on the upper surface TS of the semiconductor substrate SUB. Holes CH are formed in the semiconductor substrate SUB in the areas exposed from the insulating film IF3 and the sidewall spacers SW. A barrier metal film is formed inside the holes CH. The opening width W2 of the hole CH at the second position 12, which corresponds to the junction surface between the body region PB and the source region NS, is greater than the opening width W1 of the hole CH at the first position 11, which corresponds to the upper surface TS of the semiconductor substrate SUB. The barrier metal film BM includes a silicide film and a metal film.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for manufacturing a semiconductor device having a gate electrode inside a trench.

Background Art

[0002] In a semiconductor device including a semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a trench gate structure in which a gate electrode is formed inside a trench is applied. A body region is formed in a semiconductor substrate located on a side surface of the trench, and a source region is formed in the body region. A portion of the body region adjacent to the gate electrode via a gate insulating film functions as a channel region.

[0003] Generally, in order to electrically connect the body region and the source region to a source electrode, a hole is formed that penetrates the source region and reaches the body region.

[0004] For example, Patent Document 1 discloses a technique for forming a hole in a self-aligned manner. First, a cap film made of an insulating film is formed inside the trench and on the gate electrode. Next, an etching process is performed using the cap film as a mask to recess the upper surface of the semiconductor substrate. As a result, the cap film protrudes from the upper surface of the semiconductor substrate. Next, a body region is formed in the semiconductor substrate exposed from the cap film, and a source region is formed in the body region. Next, a sidewall spacer is formed on a side surface of the cap film. Next, an etching process is performed using the cap film and the sidewall spacer as masks to form a hole in the semiconductor substrate. Next, a high-concentration contact region is formed in the semiconductor substrate near the bottom of the hole. Next, a source electrode is formed on the cap film and on the sidewall spacer so as to fill the inside of the hole.

[0005] Furthermore, as shown in Patent Document 2, a technique is known in which a plug is formed inside the hole, and then a source electrode is formed to be electrically connected to the plug. The plug is composed of a laminated film including a barrier metal film and a main conductor film.

[0006] Patent Document 2 uses a laminated film containing a metal film and a metal nitride film as a barrier metal film. The metal film is a titanium film, and the metal nitride film is a titanium nitride film. First, the metal film is formed inside the pores. Next, the metal nitride film is formed on the metal film. Next, a silicide film is formed by reacting the metal film with silicon contained in the semiconductor substrate through heat treatment. Next, a tungsten film is formed to fill the inside of the pores via such a barrier metal film. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2002-246596 [Patent Document 2] Japanese Patent Publication No. 2024-128687 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] In recent years, with the miniaturization of semiconductor devices, there has been a demand for smaller pore opening widths. Therefore, when a silicide film is formed on the side of a pore, the silicide film tends to extend close to the channel region. Furthermore, during silicide film formation, aggregation of the silicide film can occur, and stress from the silicide film can cause cracks in the metal nitride film. These problems can reduce the reliability of semiconductor devices.

[0009] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0010] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0011] In one embodiment, the semiconductor device includes a semiconductor substrate of a first conductivity type having an upper surface, a trench formed in the semiconductor substrate, a gate electrode formed inside the trench, an insulating film formed on the gate electrode so as to protrude from the upper surface of the semiconductor substrate, a body region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate, a source region of the first conductivity type formed in the body region, a sidewall spacer formed on the side surface of the insulating film and on the upper surface of the semiconductor substrate, a hole formed in the semiconductor substrate in a portion exposed from the insulating film and the sidewall spacer so as to penetrate the source region and reach the body region, and a barrier metal film formed inside the hole. The opening width of the hole at a second position corresponding to the junction surface between the body region and the source region is greater than the opening width of the hole at a first position corresponding to the upper surface of the semiconductor substrate. The barrier metal film includes a silicide film formed inside the hole and a second metal film formed on the silicide film.

[0012] In one embodiment, the method for manufacturing a semiconductor device comprises: (a) the step of preparing a semiconductor substrate of a first conductivity type having an upper surface; (b) the step of forming a trench in the semiconductor substrate; (c) the step of forming a gate electrode inside the trench; (d) the step of forming an insulating film inside the trench and on the gate electrode; (e) the step of performing an etching process on the semiconductor substrate using the insulating film as a mask to lower the position of the upper surface of the semiconductor substrate to the position of the upper surface of the insulating film; (f) the step of forming a body region of a second conductivity type opposite to the first conductivity type in a portion of the semiconductor substrate that is exposed from the insulating film; (g) the step of forming a source region of a first conductivity type in the body region; (h) the step of forming a sidewall spacer on the side surface of the insulating film and on the upper surface of the semiconductor substrate; (i) the step of performing an etching process on the semiconductor substrate using the insulating film and the sidewall spacer as a mask to form a hole that penetrates the source region and reaches the body region; and (j) the step of forming a barrier metal film inside the hole. Prior to step (j), the opening width of the hole at the second position corresponding to the joint surface between the body region and the source region is greater than the opening width of the hole at the first position corresponding to the upper surface of the semiconductor substrate. Step (j) comprises (j1) forming a first metal film inside the hole using a sputtering method, (j2) forming a second metal film on the first metal film using a sputtering method, and (j3) forming a silicide film by reacting the first metal film with silicon contained in the semiconductor substrate by heat treatment. [Effects of the Invention]

[0013] According to one embodiment, the reliability of semiconductor devices can be improved. [Brief explanation of the drawing]

[0014] [Figure 1] This is a plan view showing the semiconductor device in Embodiment 1. [Figure 2]It is a cross-sectional view showing the main part of the semiconductor device in Embodiment 1. [Figure 3] It is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1. [Figure 4] It is a cross-sectional view showing the manufacturing process following FIG. 3. [Figure 5] It is a cross-sectional view showing the manufacturing process following FIG. 4. [Figure 6] It is a cross-sectional view showing the manufacturing process following FIG. 5. [Figure 7] It is a cross-sectional view showing the manufacturing process following FIG. 6. [Figure 8] It is a cross-sectional view showing the manufacturing process following FIG. 7. [Figure 9] It is a cross-sectional view showing the manufacturing process following FIG. 8. [Figure 10] It is a cross-sectional view showing the manufacturing process following FIG. 9. [Figure 11] It is a cross-sectional view showing the manufacturing process following FIG. 10. [Figure 12] It is a cross-sectional view showing the manufacturing process following FIG. 11. [Figure 13] It is a cross-sectional view showing the manufacturing process following FIG. 12. [Figure 14] It is a cross-sectional view showing the manufacturing process following FIG. 13. [Figure 15] In Embodiment 1, it is a cross-sectional view showing the hole before forming the barrier metal film. [Figure 16] In Embodiment 1, it is a cross-sectional view showing the hole immediately after forming two metal films which are the barrier metal film. [Figure 17] In Embodiment 1, it is a cross-sectional view showing the hole immediately after forming the silicide film. [Figure 18] In Embodiment 1, it is a cross-sectional view showing the hole after forming the barrier metal film. [Figure 19] In Embodiment 1, it is a cross-sectional view showing the hole immediately after forming a further metal film as the barrier metal film. [Figure 20] In Embodiment 1, it is a cross-sectional view showing the hole after forming the barrier metal film. [Figure 21]This is a cross-sectional view showing the hole after the plug has been formed in Embodiment 1. [Figure 22] This is a cross-sectional view showing the pores before the barrier metal film is formed in the example shown. [Figure 23] This is a cross-sectional view showing the pore immediately after the formation of the two metal films that constitute the barrier metal film in the example. [Figure 24] This is a cross-sectional view showing the pore immediately after the formation of the silicide film in the example. [Figure 25] This is a cross-sectional view showing the hole after the plug has been formed in the example. [Modes for carrying out the invention]

[0015] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0016] Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. Also, expressions such as "plan view" or "planar view" used in this application mean that the plane formed by the X and Y directions is called a "plane," and this "plane" is viewed from the Z direction.

[0017] (Embodiment 1) <Structure of a semiconductor device> The semiconductor device 100 in Embodiment 1 will be described below with reference to Figures 1 and 2. The semiconductor device 100 includes a MOSFET having a trench gate structure as a semiconductor element. The MOSFET in Embodiment 1 has a split gate structure comprising a gate electrode GE and a field plate electrode FP.

[0018] The main features of Embodiment 1 lie in the structure and manufacturing method of the pores CH and the barrier metal film BM formed inside the pores CH, which will be described in detail later.

[0019] Figure 1 is a plan view of a semiconductor chip, which is a semiconductor device 100. Figure 2 shows the cross-sectional structure of region 1A shown in Figure 1.

[0020] Figure 1 shows the wiring pattern mainly formed on top of the semiconductor substrate SUB. The majority of the semiconductor device 100 is covered by the source electrode SE. In a plan view, the gate wiring GW surrounds the source electrode SE.

[0021] Although not shown in the diagram, the source electrode SE and gate wiring GW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film. The portion of the source electrode SE exposed at the opening functions as a source pad SP. Similarly, the portion of the gate wiring GW exposed at the opening functions as a gate pad GP. By connecting external connection members to the source pad SP and gate pad GP, the semiconductor device 100 is electrically connected to other semiconductor chips, lead frames, or wiring boards. The external connection members are, for example, wires made of aluminum, gold, or copper, or clips made of copper plates.

[0022] As shown in Figure 2, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB may be, for example, a laminate of an n-type silicon substrate ND and an n-type silicon layer NV formed on the n-type silicon substrate ND. The impurity concentration of the n-type silicon substrate ND is higher than the impurity concentration of the n-type silicon layer NV.

[0023] A drain electrode DE is formed on the underside BS of the semiconductor substrate SUB. The drain electrode DE consists of a single layer of metal film, such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a multilayer film formed by appropriately stacking these metal films. A drain potential is supplied to the semiconductor substrate SUB (silicon substrate ND, silicon layer NV) from the drain electrode DE.

[0024] Multiple trenches TR are formed in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB. Each of the multiple trenches TR extends in the Y direction. A field plate electrode FP is formed inside each of the multiple trenches TR via an insulating film IF1.

[0025] Within each of the multiple trenches TR, a gate insulating film GI is formed on an insulating film IF1. An insulating film IF2 is formed to cover the field plate electrode FP exposed from the insulating film IF1. A gate electrode GE is formed on the field plate electrode FP via the insulating film IF2. The field plate electrode FP and the gate electrode GE are, for example, polycrystalline silicon films into which n-type impurities have been introduced.

[0026] Insulating film IF1 is formed between the semiconductor substrate SUB and the field plate electrode FP. Insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. Gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. Insulating films IF1, IF2, and GI electrically insulate the semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP from each other. Insulating films IF1, IF2, and GI are, for example, silicon oxide films.

[0027] An insulating film IF3 is formed on the gate electrode GE. The insulating film IF3 protrudes from the upper surface TS of the semiconductor substrate SUB. In other words, the position of the upper surface of the insulating film IF3 is higher than the position of the upper surface TS of the semiconductor substrate SUB. The insulating film IF3 is, for example, a silicon oxide film (HDP film).

[0028] Within the semiconductor substrate SUB, p-type body regions PB are formed in the areas exposed from the insulating film IF3. The depth of the body regions PB from the top surface TS of the semiconductor substrate SUB is shallower than the depth of the trenches TR from the top surface TS of the semiconductor substrate SUB. Within the body regions PB, n-type source regions NS are formed. The source regions NS have a higher impurity concentration than the silicon layer NV.

[0029] Sidewall spacers SW are formed on the side surface of the insulating film IF3 and on the top surface TS of the semiconductor substrate SUB. The sidewall spacers SW are, for example, silicon oxide films (TEOS films). Pores CH are formed in the semiconductor substrate SUB in the areas exposed from the insulating film IF3 and the sidewall spacers SW. The pores CH penetrate the source region NS and reach the body region PB.

[0030] A p-type contact region PR is formed within the body region PB surrounding the pore CH. The contact region PR is located below and separate from the source region NS. The impurity concentration in the contact region PR is higher than that of the body region PB.

[0031] A plug PG is formed inside the pore CH. The plug PG is located above the pore CH and is also formed in the space adjacent to the sidewall spacer SW. As will be explained in detail later, the plug PG includes a barrier metal film BM and a metal film MF4. The barrier metal film BM includes a silicide film SI formed inside the pore CH and a metal film MF2 formed on the silicide film SI. The barrier metal film BM may also include a metal film MF3. The silicide film SI is formed between the metal film MF2 and the semiconductor substrate SUB.

[0032] Source electrodes SE are formed on the insulating film IF3 and the sidewall spacer SW. The source electrodes SE are electrically connected to the source region NS, body region PB, and contact region PR via plugs PG, supplying source potential to these impurity regions.

[0033] Although not shown in the diagram, the gate electrode GE, insulating film IF3, and interlayer insulating film are located below the gate wiring GW. Other holes are formed in the insulating film IF3, and plugs PG are formed inside these holes. The gate wiring GW is electrically connected to the gate electrode GE via plugs PG and supplies the gate potential to the gate electrode GE.

[0034] Although not shown in the diagram, in some parts of the trench TR, the gate electrode GE is not formed inside the trench TR, and the field plate electrode FP and insulating film IF3 are formed inside the trench TR. Further pores are formed in the insulating film IF3, and plugs PG are formed inside these pores. The source electrode SE is electrically connected to the field plate electrode FP via the plugs PG and supplies the source potential to the field plate electrode FP.

[0035] The source electrode SE and gate wiring GW may consist, for example, of a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium-tungsten film. The conductive film is, for example, an aluminum alloy film with copper or silicon added.

[0036] <Manufacturing method for semiconductor devices> The following describes each manufacturing process included in the manufacturing method of the semiconductor device 100, using Figures 3 to 14.

[0037] As shown in Figure 3, first, an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS is prepared. As described above, the semiconductor substrate SUB may be a laminate of an n-type silicon substrate ND and an n-type silicon layer NV formed on the n-type silicon substrate ND using an epitaxial growth method.

[0038] Next, a silicon oxide film is formed on the semiconductor substrate SUB, for example, using a CVD (Chemical Vapor Deposition) method. Then, a hard mask HM is formed by patterning the silicon oxide film using photolithography and anisotropic etching. Next, trenches TR are formed in the semiconductor substrate SUB to a predetermined depth from the top surface TS of the semiconductor substrate SUB by performing anisotropic etching using the hard mask HM as a mask. After that, the hard mask HM is removed by isotropic etching using, for example, a solution containing hydrofluoric acid.

[0039] As shown in Figure 4, an insulating film IF1 is formed inside the trench TR and on the upper surface TS of the semiconductor substrate SUB, for example, by thermal oxidation treatment.

[0040] As shown in Figure 5, first, a conductive film is formed on the insulating film IF1, for example, using the CVD method. The conductive film is, for example, an n-type polycrystalline silicon film. Next, the conductive film located outside the trench TR is removed by polishing using the CMP (Chemical Mechanical Polishing) method or by anisotropic etching. Then, by further anisotropic etching, the upper surface of the conductive film located inside the trench TR is recessed, and a field plate electrode FP is formed inside the trench TR.

[0041] As shown in Figure 6, isotropic etching removes the insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB, and retracts the insulating film IF1 located inside the trench TR so that the position of the upper surface of the insulating film IF1 located inside the trench TR is lower than the position of the upper surface of the field plate electrode FP.

[0042] As shown in Figure 7, thermal oxidation treatment forms a gate insulating film GI on the upper surface TS of the semiconductor substrate SUB and inside the trench TR located on the insulating film IF1, and also forms an insulating film IF2 to cover the field plate electrode FP exposed from the insulating film IF1.

[0043] The insulating film IF2 may also be formed by the following method: An insulating film (HDP film) is formed on the field plate electrode FP and the insulating film IF1, for example, using plasma CVD, so as to fill the inside of the trench TR. Next, the insulating film located outside the trench TR is removed by polishing using CMP or anisotropic etching. After that, the insulating film IF2 may be formed by reducing the thickness of the insulating film by wet etching or the like.

[0044] As shown in Figure 8, first, conductive films are formed on the gate insulating film GI, insulating film IF2, and insulating film IF1, for example, using a CVD method, so as to fill the inside of the trench TR. The conductive films are, for example, n-type polycrystalline silicon films.

[0045] Next, an anisotropic etching treatment is performed on the conductive film to remove the conductive film located outside the trench TR and to recede the upper surface of the conductive film located inside the trench TR. In this way, a gate electrode GE is formed inside the trench TR. At this point, the position of the upper surface of the gate electrode GE is lower than the position of the upper surface TS of the semiconductor substrate SUB.

[0046] As shown in Figure 9, first, an insulating film (HDP film) IF3 is formed on the gate electrode GE and the gate insulating film GI, for example, using plasma CVD, to fill the inside of the trench TR. Next, the insulating film IF3 located outside the trench TR is removed by polishing using CMP or anisotropic etching. At this time, the gate insulating film GI that was formed outside the trench TR is also removed. In this way, the insulating film IF3 is formed on the gate electrode GE inside the trench TR.

[0047] As shown in Figure 10, by performing anisotropic etching on the semiconductor substrate SUB using the insulating film IF3 as a mask, the position of the upper surface TS of the semiconductor substrate SUB is lowered to be lower than the position of the upper surface of the insulating film IF3. In other words, the insulating film IF3 is made to protrude from the upper surface TS of the semiconductor substrate SUB.

[0048] As shown in Figure 11, first, a p-type body region PB is formed in the portion of the semiconductor substrate SUB exposed from the insulating film IF3 using photolithography and ion implantation techniques. The body region PB is formed such that its depth from the top surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR. Next, an n-type source region NS is formed within the body region PB using photolithography and ion implantation techniques.

[0049] As shown in Figure 12, first, an insulating film is formed on the upper surface TS of the semiconductor substrate SUB, for example, using a CVD method, so as to cover the insulating film IF3. The insulating film is, for example, a silicon oxide film. Next, the insulating film is subjected to anisotropic etching, leaving the insulating film on the side surface of the insulating film IF3 and on the upper surface TS of the semiconductor substrate SUB. In this way, a sidewall spacer SW is formed on the side surface of the insulating film IF3 and on the upper surface TS of the semiconductor substrate SUB.

[0050] As shown in Figure 13, first, the semiconductor substrate SUB is etched using the insulating film IF3 and sidewall spacer SW as masks to form holes CH that penetrate the source region NS and reach the body region PB. As will be explained in detail later, this etching process includes anisotropic etching and isotropic etching. Next, p-type contact regions PR are formed in the body region PB located around the holes CH by ion implantation.

[0051] As shown in Figure 14, first, a plug PG is formed inside the hole CH. The plug PG is located above the hole CH and is also formed in the space adjacent to the sidewall spacer SW. The detailed manufacturing process of the plug PG will be explained later.

[0052] Next, a conductive film is formed on the plug PG using the sputtering method. The conductive film is, for example, an aluminum alloy film with copper or silicon added. Then, the source electrode SE and gate wiring GW are formed by patterning the conductive film.

[0053] Subsequently, the structure shown in Figure 2 is obtained through the following manufacturing process.

[0054] First, a protective film, for example, made of a polyimide film, is formed on the source electrode SE and gate wiring GW using a coating method. Next, openings are formed in a part of the protective film to expose the source pad SP and gate pad GP of the source electrode SE and gate wiring GW. Next, the bottom surface BS of the semiconductor substrate SUB is polished as needed. Finally, a drain electrode DE is formed on the bottom surface BS of the semiconductor substrate SUB using a sputtering method.

[0055] <Main features of Embodiment 1> The structure of the pore CH and the barrier metal film BM in Embodiment 1, as well as the manufacturing methods for the pore CH and barrier metal BM, will be described in detail below with reference to Figures 15 to 21. Figure 15 is an enlarged cross-sectional view of the area around the pore CH, showing the state before the formation of the barrier metal film BM.

[0056] As shown in Figure 15, the first position 11 corresponds to the position TS on the upper surface of the semiconductor substrate SUB. The second position 12 corresponds to the position of the junction surface between the body region PB and the source region NS. The third position 13 corresponds to a position 30 nm above the deepest part 10 of the hole CH.

[0057] In Embodiment 1, the hole CH has a Boeing shape. In other words, the opening width W3 of the hole CH at the third position 13 is smaller than the opening width W2 of the hole CH at the second position 12, and larger than the opening width W1 of the hole CH at the first position 11.

[0058] In the following explanation, the portion of the pore CH extending from the first position 11 to the third position 13 is referred to as the side portion CHs of the pore CH, and the portion of the pore CH extending from the third position 13 to the deepest part 10 of the pore CH is referred to as the bottom portion CHb of the pore CH. In other words, the inner wall surface of the pore CH is composed of the side portion CHs and the bottom portion CHb.

[0059] Furthermore, in order to form such pores CH, the semiconductor substrate SUB is etched using the insulating film IF3 and sidewall spacer SW as masks, as explained in Figure 13. This etching process includes at least anisotropic etching and may also include isotropic etching.

[0060] In the anisotropic etching process described above, Cl2 gas and O2 gas are used. The value of "Cl2 gas flow rate / O2 gas flow rate" is, for example, 6 or more and 13 or less. Specifically, the Cl2 gas flow rate is 60 sccm or more and 80 sccm or less, and the O2 gas flow rate is 6 sccm or more and 10 sccm or less. By performing such anisotropic etching, it becomes easier to make the aperture width W2 larger than the aperture width W1.

[0061] In the above isotropic etching process, buffered hydrofluoric acid is used. Buffered hydrofluoric acid is a solution containing hydrofluoric acid (HF), ammonium fluoride (NH4F), and water. In this isotropic etching process, both silicon and silicon oxide are etched. At the interface between the upper surface TS of the semiconductor substrate SUB and the sidewall spacer SW, the etching rate is slower compared to the areas where the semiconductor substrate SUB is exposed. Therefore, it becomes easier to make the aperture width W3 larger than the aperture width W1.

[0062] The reason for forming the pore CH in Embodiment 1 in this shape will be explained below using the examples shown in Figures 22 to 25.

[0063] As shown in Figure 22, in this example, unlike Embodiment 1, the opening width W1 of the pore CH at the first position 11 is larger than the opening width W2 of the pore CH at the second position 12, and the opening width W2 of the pore CH at the second position 12 is larger than the opening width W3 of the pore CH at the third position 13. In this state, a barrier metal film BM is formed inside the pore CH.

[0064] As shown in Figure 23, metal films MF1 and MF2 are sequentially formed as barrier metal films BM inside the pore CH using, for example, a sputtering method or a CVD method. Metal film MF1 is, for example, a titanium film. Metal film MF2 is, for example, a titanium nitride film. Next, as shown in Figure 24, a heat treatment is performed to react metal film MF1 with silicon contained in the semiconductor substrate SUB to form a silicide film SI. The barrier metal film BM includes the silicide film SI and the metal film MF2.

[0065] Next, as shown in Figure 25, a metal film MF4 is formed inside the pore CH via a barrier metal film BM, for example, using a CVD method. The metal film MF4 is, for example, a tungsten film. In this way, a plug PG containing the barrier metal film BM and the metal film MF4 is formed inside the pore CH.

[0066] As described above, with the miniaturization of semiconductor devices 100 in recent years, there is a need to reduce the opening width of the pores CH. Therefore, when a silicide film SI is formed on the side CHs of the pores CH, there is a problem in that the silicide film SI tends to form near the channel region.

[0067] Furthermore, when forming the silicide film SI, aggregation may occur in the silicide film SI, or cracks may occur in the metal film MF2 due to stress from the silicide film SI. When forming a tungsten film as the metal film MF4 using the CVD method, WF6 gas is used. If cracks occur in the metal film MF2, WF6 gas can enter through the cracks, making it easier for defects such as "wormholes" or "volcanoes" to occur.

[0068] One of the purposes of forming the silicide film SI is to create ohmic contact between the body region PB and the contact region PR at the bottom CHb of the pore CH. Therefore, the formation conditions for the silicide film SI are optimized to prevent problems related to aggregation of the silicide film SI and cracking of the metal film MF2 at the bottom CHb of the pore CH.

[0069] For example, in the case of a titanium silicide film, if the thickness of the titanium film is too small, the temperature at which aggregation occurs will be low, and if the thickness of the titanium film is too large, unreacted titanium film is more likely to remain. The unreacted titanium film will undergo silicide reaction again due to the heat load in subsequent manufacturing processes, applying stress to the metal film MF2 and causing cracks in the metal film MF2. Therefore, adjustments are made to the thickness of the metal film MF1 and the temperature of the heat treatment when forming the silicide film SI. This adjustment is made to suppress the above problem that may occur at the bottom CHb of the pore CH, so it is difficult to suppress the above problem at the side CHs of the pore CH.

[0070] In Embodiment 1, the conditions for forming the silicide film SI at the bottom CHb of the pore CH are prioritized and optimized, while the barrier metal film BM is formed relatively thinly or not formed at the side CHs of the pore CH. This suppresses problems related to aggregation of the silicide film SI and cracking of the metal film MF2 at the side CHs of the pore CH.

[0071] As shown in Figure 16, metal films MF1 and MF2 are formed as barrier metal films BM inside the pore CH, on the sidewall spacer SW, and on the insulating film IF3. First, metal film MF1 is formed inside the pore CH, on the sidewall spacer SW, and on the insulating film IF3, for example, using a sputtering method. Next, metal film MF2 is formed on metal film MF1, for example, using a sputtering method. Metal film MF1 is, for example, a titanium film. Metal film MF2 is, for example, a titanium nitride film.

[0072] The thickness of the metal film MF1 is, for example, 5 nm or more and 10 nm or less after deposition. The thickness of the metal film MF2 is greater than the thickness of the metal film MF1, for example, 10 nm or more and 20 nm or less after deposition. These values ​​are measured above the deepest part 10 of the pore CH. Similarly, the thickness of the silicide film SI and the metal film MF3, which will be explained later, are also measured above the deepest part 10 of the pore CH.

[0073] Furthermore, as shown in Figure 16, the fourth position 14 corresponds to the position of the upper surface of the barrier metal film BM formed above the deepest part 10 of the pore CH. The opening width W4 of the pore CH at the fourth position 14 is smaller than the opening width W2 and larger than the opening width W1.

[0074] In the following explanation, the portion of hole CH extending from the first position 11 to the fourth position 14 is referred to as the side portion CHs of hole CH, and the portion of hole CH extending from the fourth position 14 to the deepest part 10 of hole CH is referred to as the bottom portion CHb of hole CH.

[0075] Here, the thickness of the barrier metal film BM formed inside the pore CH from the first position 11 to the fourth position 14 is smaller than the thickness of the barrier metal film BM formed inside the pore CH from the fourth position 14 to the deepest part 10. In other words, the thickness of the barrier metal film BM formed on the side CHs of the pore CH is smaller than the thickness of the barrier metal film BM formed on the bottom CHb of the pore CH. There are areas on the side CHs of the pore CH where the thickness of the barrier metal film BM is 0 nm. That is, there are areas on the side CHs of the pore CH where the barrier metal film BM is not formed.

[0076] Note that the "thickness of barrier metal film BM" as described here refers to the thickness in the direction perpendicular to the inner wall surface of the pore CH (side CHs, bottom CHb). In the following explanation, the thicknesses of barrier metal film BM, metal film MF1, metal film MF2, and metal film MF3 may be compared individually. In that case as well, their thicknesses refer to the thickness in the direction perpendicular to the inner wall surface of the pore CH (side CHs, bottom CHb).

[0077] As shown in Figure 17, heat treatment is performed to react the metal film MF1 with the silicon contained in the semiconductor substrate SUB to form a silicide film SI. This heat treatment is carried out in an inert gas atmosphere, such as nitrogen, and under conditions such as 600 degrees Celsius or higher and 700 degrees Celsius or lower. The silicide film SI is, for example, a titanium silicide film. The thickness of the silicide film SI is, for example, 10 nm or more and 20 nm or less. The barrier metal film BM includes the silicide film SI formed inside the pores CH and the metal film MF2 formed on the silicide film SI. The silicide film SI may be formed on the sides CHs of the pores CH and on the metal film MF2, but there are also cases where neither the silicide film SI nor the metal film MF2 is formed on the sides CHs of the pores CH.

[0078] As shown in Figure 18, even after the formation of the silicide film SI, the opening width W4 of the pore CH at the fourth position 14 is smaller than the opening width W2 and larger than the opening width W1.

[0079] Furthermore, even after the silicide film SI is formed, the thickness of the barrier metal film BM formed inside the pore CH from the first position 11 to the fourth position 14 is smaller than the thickness of the barrier metal film BM formed inside the pore CH from the fourth position 14 to the deepest part 10. In other words, the thickness of the barrier metal film BM formed on the side CHs of the pore CH is smaller than the thickness of the barrier metal film BM formed on the bottom CHb of the pore CH. There may be areas on the side CHs of the pore CH where the thickness of the barrier metal film BM is 0 nm. That is, there may be areas on the side CHs of the pore CH where the barrier metal film BM is not formed.

[0080] Thus, in Embodiment 1, the barrier metal film BM is formed relatively thickly at the bottom CHb of the pore CH so that ohmic contact can be formed with the body region PB and the contact region PR. On the other hand, the barrier metal film BM is formed relatively thinly or not at the side CHs of the pore CH.

[0081] Therefore, the problem of the silicide film SI easily forming near the channel region can be resolved. In addition, the problems of aggregation occurring in the silicide film SI and the problems of cracks occurring in the metal film MF2 due to stress from the silicide film SI can be resolved. Consequently, the reliability of the semiconductor device 100 can be improved.

[0082] Furthermore, in the manufacturing process shown in Figure 16, it is also possible to form metal films MF1 and MF2 inside the pores CH using the CVD method. However, in the case of the CVD method, metal films MF1 and MF2 are also formed on the side parts CHs of the pores CH. Moreover, the thickness of each metal film MF1 and MF2 formed on the side parts CHs of the pores CH is approximately the same as the thickness of each metal film MF1 and MF2 formed on the bottom part CHb of the pores CH. Therefore, it is preferable to form metal films MF1 and MF2 using the sputtering method.

[0083] As shown in Figure 19, it is preferable to form a metal film MF3 inside the pore CH using the CVD method so as to cover the metal film MF2 and the silicide film SI. In this case, the barrier metal film BM includes not only the silicide film SI and the metal film MF2, but also the metal film MF3. The metal film MF3 is, for example, a titanium nitride film. The metal film MF3 is formed not only at the bottom CHb of the pore CH, but also at the sides CHs of the pore CH. Furthermore, the thickness of the metal film MF3 formed at the sides CHs of the pore CH is approximately the same as the thickness of the metal film MF3 formed at the bottom CHb of the pore CH.

[0084] When forming a tungsten film as the metal film MF4 using the CVD method during the manufacturing process of the metal film MF4 described later, WF6 gas is used. In Embodiment 1, there may be areas on the sides of the pores CHs where the metal film MF2 and silicide film SI are not formed, and the semiconductor substrate SUB may be directly exposed to the WF6 gas. Therefore, in order to protect the areas where the metal film MF2 and silicide film SI are not formed, the metal film MF3 is formed as part of the barrier metal film BM.

[0085] However, when forming the metal film MF3 using the CVD method, a heat treatment of approximately 600 degrees Celsius is applied. This heat treatment can cause stress to be applied from the silicide film SI to the metal film MF2, potentially leading to crack formation in the metal film MF2. Therefore, in order to minimize the deposition time of the metal film MF3, the thickness of the metal film MF3 is preferably such that it is sufficient to protect the semiconductor substrate SUB from WF6 gas, and is preferably as small as possible. The thickness of the metal film MF3 is smaller than the thickness of the silicide film SI and the metal film MF2, for example, between 2 nm and 5 nm.

[0086] As shown in Figure 20, when the metal film MF3 is formed, the fourth position 14 corresponds to the position of the upper surface of the barrier metal film BM (upper surface of the metal film MF3) formed above the deepest part 10 of the pore CH.

[0087] Subsequently, as shown in Figure 21, a metal film MF4 is formed inside the pore CH via a barrier metal film BM. This forms a plug PG inside the pore CH containing the barrier metal film BM and the metal film MF4.

[0088] First, a metal film MF4 is formed inside the pore CH, on the sidewall spacer SW, and on the insulating film IF3 using the CVD method. In this manufacturing process, WF6 gas is used, and the metal film MF4 is a tungsten film. Next, the metal film MF4 and barrier metal film BM located on the sidewall spacer SW and insulating film IF3 are removed by polishing or anisotropic etching using the CMP method.

[0089] Although the present invention has been specifically described above based on the above embodiments, the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention.

[0090] For example, in Embodiment 1, a titanium silicide film was used as an example to describe the silicide film SI, but similar problems may occur with other silicide films besides titanium silicide films. Therefore, the silicide film SI may be any silicide film other than titanium silicide film. [Explanation of Symbols]

[0091] 100 Semiconductor Devices 10. Deepest part of the hole 11 1st position 12 2nd position 13 3rd position 14 4th position 1A area BM barrier metal film BS semiconductor substrate bottom surface CH hole CHb hole bottom CHs hole side DE drain electrode FP field plate electrode GE Terminal GI gate insulating film GP Gate Pad GW gate wiring HM Hard Mask IF1, IF2, IF3 insulating film MF1, MF2, MF3, MF4 metal film ND silicon substrate NS source area (impurity area) NV silicon layer PB body region (impurity region) PR Contact area (impurity area) SE source electrode SI silicide membrane SP Source Pad SUB Semiconductor Substrate SW Sidewall Spacer TR Trench Top surface of TS semiconductor substrate

Claims

1. A first-type conductive semiconductor substrate having an upper surface, A trench formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate, A gate electrode formed inside the trench, An insulating film formed on the gate electrode so as to protrude from the upper surface of the semiconductor substrate, A body region of a second conductivity type opposite to the first conductivity type is formed in the portion of the semiconductor substrate that is exposed from the insulating film, The first conductivity type source region formed in the body region, A sidewall spacer formed on the side surface of the insulating film and on the upper surface of the semiconductor substrate, A hole is formed in the semiconductor substrate in a portion exposed from the insulating film and the sidewall spacer, so as to penetrate the source region and reach the body region. A barrier metal film formed inside the aforementioned hole, Equipped with, The opening width of the hole at the second position of the bonding surface between the body region and the source region is greater than the opening width of the hole at the first position on the upper surface of the semiconductor substrate. The barrier metal film comprises a silicide film formed inside the pore and a second metal film formed on the silicide film, wherein the semiconductor device is provided.

2. In the semiconductor device described in claim 1, A semiconductor device wherein the opening width of the hole at a fourth position on the upper surface of the barrier metal film formed above the deepest part of the hole is smaller than the opening width of the hole at the second position and larger than the opening width of the hole at the first position.

3. In the semiconductor device described in claim 2, A semiconductor device wherein the thickness of the barrier metal film formed inside the hole from the first position to the fourth position is smaller than the thickness of the barrier metal film formed inside the hole from the fourth position to the deepest part of the hole.

4. In the semiconductor device described in claim 1, The barrier metal film further includes a third metal film formed inside the pore so as to cover the second metal film and the silicide film. A semiconductor device wherein the thickness of the third metal film is smaller than the thickness of the silicide film and the thickness of the second metal film.

5. In the semiconductor device according to claim 4, The interior of the hole further comprises a tungsten film formed via the barrier metal film, The silicide film is a titanium silicide film. The second metal film is a titanium nitride film. The semiconductor device wherein the third metal film is a titanium nitride film.

6. (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface, (b) After step (a), a step of forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate, (c) After step (b), a step of forming a gate electrode inside the trench, (d) After step (c), a step of forming an insulating film inside the trench and on the gate electrode, (e) After step (d), a step of performing an etching process on the semiconductor substrate using the insulating film as a mask, thereby lowering the position of the upper surface of the semiconductor substrate to the position of the upper surface of the insulating film, (f) After step (e), a step of forming a body region of a second conductivity type opposite to the first conductivity type in the portion of the semiconductor substrate that is exposed from the insulating film, (g) After step (f), a step of forming the first conductivity type source region in the body region, (h) After step (g), a step of forming a sidewall spacer on the side surface of the insulating film and on the upper surface of the semiconductor substrate, (i) After step (h), the semiconductor substrate is subjected to an etching process using the insulating film and the sidewall spacer as a mask to form holes that penetrate the source region and reach the body region, (j) After step (i), a step of forming a barrier metal film inside the hole, Equipped with, Before step (j), the opening width of the hole at the second position of the bonding surface between the body region and the source region is greater than the opening width of the hole at the first position of the upper surface of the semiconductor substrate. The above step (j) is, (j1) A step of forming a first metal film inside the hole using a sputtering method, (j2) After step (j1), a step of forming a second metal film on the first metal film using a sputtering method, (j3) After step (j2), a step of reacting the first metal film with the silicon contained in the semiconductor substrate by heat treatment to form a silicide film, A method for manufacturing a semiconductor device having the following characteristics.

7. In the method for manufacturing a semiconductor device according to claim 6, A method for manufacturing a semiconductor device, wherein, after step (j), the opening width of the hole at the second position is greater than the opening width of the hole at the first position.

8. In the method for manufacturing a semiconductor device according to claim 6, A method for manufacturing a semiconductor device, wherein, prior to step (j), the opening width of the hole at a third position 30 nm above the deepest part of the hole is smaller than the opening width of the hole at the second position and larger than the opening width of the hole at the first position.

9. In the method for manufacturing a semiconductor device according to claim 8, A method for manufacturing a semiconductor device, wherein, after step (j2) and before step (j3), the thickness of the barrier metal film formed inside the hole from the first position to the fourth position is smaller than the thickness of the barrier metal film formed inside the hole from the fourth position to the deepest part of the hole.

10. In the method for manufacturing a semiconductor device according to claim 6, A method for manufacturing a semiconductor device, wherein, after step (j), the opening width of the hole at the fourth position on the upper surface of the barrier metal film formed above the deepest part of the hole is smaller than the opening width of the hole at the second position and larger than the opening width of the hole at the first position.

11. In the method for manufacturing a semiconductor device according to claim 10, A method for manufacturing a semiconductor device, wherein, after step (j), the thickness of the barrier metal film formed inside the hole from the first position to the fourth position is smaller than the thickness of the barrier metal film formed inside the hole from the fourth position to the deepest part of the hole.

12. In the method for manufacturing a semiconductor device according to claim 6, The above step (j) is, (j4) After step (j3), a third metal film is formed inside the pore using a CVD method so as to cover the second metal film and the silicide film. It further possesses, A method for manufacturing a semiconductor device, wherein the thickness of the third metal film is smaller than the thickness of the silicide film and the thickness of the second metal film.

13. In the method for manufacturing a semiconductor device according to claim 12, (k) After step (j), a step of forming a tungsten film inside the hole via the barrier metal film using the CVD method, Furthermore, The first metal film is a titanium film. The silicide film is a titanium silicide film. The second metal film is a titanium nitride film. A method for manufacturing a semiconductor device, wherein the third metal film is a titanium nitride film.

14. In the method for manufacturing a semiconductor device according to claim 6, The etching process in step (i) above is performed by Cl ２ Gas and O ２ This includes an anisotropic etching process using gas. "The aforementioned Cl ２ Gas flow rate / the above O ２ A method for manufacturing a semiconductor device, wherein the value of "gas flow rate" is 6 or more and 13 or less.

15. In the method for manufacturing a semiconductor device according to claim 14, The aforementioned Cl ２ The gas flow rate is 60 sccm or more and 80 sccm or less. The aforementioned O ２ A method for manufacturing a semiconductor device, wherein the gas flow rate is 6 sccm or more and 10 sccm or less.

16. In the method for manufacturing a semiconductor device according to claim 14, A method for manufacturing a semiconductor device, wherein the etching process in step (i) above includes an isotropic etching process using buffered hydrofluoric acid.

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