Memory system

Abstract

The problem that this invention aims to solve is to provide a memory system that enables a connected audio device to reproduce music information with higher quality. [Solution] To achieve the above objectives, the memory system of the embodiment comprises a memory controller that is connectable to a host and includes an interface capable of communicating with the host, and a non-volatile memory. When the interface receives music data during a first mode, the memory controller flags the music data and stores the music data in the non-volatile memory. When the interface receives the music data during a second mode different from the first mode, the memory controller performs encryption processing on the music data and stores the music data in the non-volatile memory.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system.

Background Art

[0002] A memory system including a NAND-type flash memory (hereinafter simply referred to as a NAND memory) as an example of a non-volatile memory and a memory controller that controls the NAND memory is known. As an example of a memory system, there is a Solid State Drive (hereinafter referred to as an SSD).

[0003] Also, an audio device that reads music information stored in a hard disk, a memory card, etc. and reproduces the read music information is known.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by the present invention is to provide a memory system for enabling a connected audio device to reproduce music information with higher quality.

Means for Solving the Problems

[0006] To achieve the above objectives, the memory system of the embodiment comprises a memory controller that is connectable to a host and includes an interface capable of communicating with the host, and a non-volatile memory. When the interface receives music data during a first mode, the memory controller flags the music data and stores the music data in the non-volatile memory. When the interface receives the music data during a second mode different from the first mode, the memory controller performs encryption processing on the music data and stores the music data in the non-volatile memory. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram showing an example configuration of an information processing system including a memory system according to the first embodiment. [Figure 2] A block diagram showing an example configuration of a memory system according to the first embodiment. [Figure 3] A flowchart illustrating the overview of writing music data to the comparative example memory system. [Figure 4] A flowchart illustrating the overview of reading music data from the comparative example memory system. [Figure 5] A flowchart illustrating the process of writing music data to the memory system according to the first embodiment. [Figure 6] A flowchart illustrating the process of reading music data from the memory system according to the first embodiment. [Figure 7] A flowchart showing a second overview of writing music data to the memory system according to the first embodiment. [Figure 8] A block diagram focusing on the host interface of the memory system according to the second embodiment. [Figure 9] A block diagram focusing on the NAND chip of the memory system according to the third embodiment. [Modes for carrying out the invention]

[0008] Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.

[0009] (First embodiment) Figure 1 is a block diagram showing an example configuration of an information processing system including a memory system according to the first embodiment. The information processing system 1 includes a host 2 and a memory system 3.

[0010] Host 2 may be an information processing device such as a personal computer or audio device, or a mobile terminal such as a tablet computer or smartphone. Memory system 3 is connected to host 2 by a communication line and functions as an external storage device for host 2.

[0011] Host 2 includes, for example, a host CPU 21, a host ROM 22, a host RAM 23, a memory interface (memory I / F) 24, an audio interface (audio I / F) 25, a speaker 251, an input device 26, a video I / F 27, a display 271, and a communication I / F 28. The host CPU 21, host ROM 22, host RAM 23, memory I / F 24, audio I / F 25, input device 26, video I / F 27, and communication I / F 28 are connected by buses.

[0012] The host CPU 21 is a CPU (Central Processing Unit) that comprehensively controls host 2. The host ROM 22 is a ROM (Read Only Memory) that stores programs such as boot programs, data update programs, and specific information acquisition programs. The host RAM 23 is a RAM (Random Access Memory) and is used as the work area for the host CPU 21. In other words, the host CPU 21 comprehensively controls host 2 by executing various programs stored in the host ROM 22 while using the host RAM 23 as its work area.

[0013] Memory I / F 24 controls the reading and writing of data to the memory system 3 according to the control of the host CPU 21, and transmits read requests, write requests, etc. to the memory system 3. Here, the write request specifies the write data, the logical address (starting logical address), and the size of the write data. The write request is a command for requesting the memory system 3 to write the write data to the storage area of the NAND memory 40 corresponding to the starting logical address and the size.

[0014] The read request specifies the logical address (starting logical address) and the size of the data to be read. The read request is a command for requesting the memory system 3 to read data from the storage area of the NAND memory 40 corresponding to the starting logical address and the size.

[0015] Examples of the write data specified in the write request include music data. Music data is also referred to as music piece data or voice data.

[0016] The audio I / F 25 is connected to the speaker 251 for audio output. From the speaker 251, audio obtained by D / A converting predetermined music data by the audio I / F 25 is output. Also, the audio I / F 25 may be connected to, for example, two speakers 251 for the right ear and left ear of the user.

[0017] The input device 26 includes a remote control, a keyboard, a touch panel, etc. having a plurality of keys for input of characters, numerical values, various instructions, etc. The input device 26 may be realized by any one of the remote control, the keyboard, and the touch panel, or may be realized by a plurality of elements.

[0018] The video I / F 27 is connected to the display 271. Specifically, the video I / F 27 is composed of, for example, a graphic controller that controls the entire display 271, a buffer memory such as VRAM (Video RAM) that temporarily records image information that can be immediately displayed, and a control IC that controls the display 271 based on the image data output from the graphic controller.

[0019] Various data such as icons, cursors, menus, windows, or characters and images are displayed on the display 271. Information about characters, images, and the playback time related to the above-described music information may be drawn on the display 271. As the display 271, for example, a liquid crystal display or the like can be used.

[0020] The communication I / F 28 is connected to a network via wireless and functions as an interface with the network. The communication I / F 28 is further connected to a communication network such as the Internet via wireless or wired and also functions as an interface between this communication network and the host CPU 21. And desired music data can be fetched from a server on the Internet.

[0021] The host CPU 21 can save music data by sending a write request to the memory system 3. Also, the host CPU 21 can read music data from the memory system 3 by sending a read request to the memory system 3.

[0022] The host CPU 21 executes a predetermined music playback program recorded in the host ROM 来22 or the like and controls each element in the host 2. That is, the host 2 can play back the music data read from the memory system 3 by executing the music playback program recorded in the host ROM 22.

[0023] Figure 2 is a block diagram showing a configuration example of the memory system according to the first embodiment.

[0024] The memory system 3 may be a memory card in which the memory controller 30 and NAND memory 40 are configured as a single package, or it may be an SSD.

[0025] The memory controller 30 controls the writing of data to the NAND memory 40 in accordance with write commands from the host 2. It also controls the reading of data from the NAND memory 40 in accordance with read requests from the host 2.

[0026] NAND memory 40 is an example of non-volatile memory. Non-volatile memory is not limited to NAND memory; NOR flash memory or other types of non-volatile memory may also be used. Non-volatile memory may have a two-dimensional structure or a three-dimensional structure.

[0027] The NAND memory 40 has multiple NAND chips. For example, the NAND memory 40 has four NAND chips (0) 42-0, NAND chip (1) 42-1, NAND chip (2) 42-2, and NAND chip (3) 42-3. When there is no need to distinguish between them, the NAND chips 42-0 to 42-3 are collectively referred to as NAND chip 42. Each NAND chip 42 has peripheral circuits 44 and multiple planes. For example, each NAND chip 42 has two planes (0) 46-0 and plane (1) 46-1. Each NAND chip 42 may have two or more planes. When there is no need to distinguish between planes 46-0 and 46-1, they are collectively referred to as plane 46.

[0028] The memory controller 30 includes a host interface (host I / F) 31, a control unit 32, a NAND interface (NAND I / F) 33, a data buffer 34, an ECC circuit 35, an encryption / decryption circuit 36, a music information detection unit 37, a flag detection unit 38, and a flag assignment unit 39. The host I / F 31, control unit 32, NAND I / F 33, data buffer 34, ECC circuit 35, encryption / decryption circuit 36, music information detection unit 37, flag detection unit 38, and flag assignment unit 39 are connected by an internal bus 300.

[0029] The host I / F31 performs processing according to the interface standard with host 2 and outputs commands received from host 2 to the internal bus 300. Interfaces for interconnecting host 2 and SSD3 include SCSI, Serial Attached SCSI (SAS), ATA, and Serial ATA (SAS). It can use technologies such as TA, PCI Express (PCIe), Ethernet (registered trademark), Fibre Channel, and NVM Express (NVMe) (registered trademark). The host I / F 31 also transmits user data read from the NAND memory 40, responses from the control unit 32, etc., to the host 2.

[0030] The control unit 32 comprehensively controls each component of the memory system 3. The control unit 32 may be implemented by hardware, or by a processor such as a CPU executing firmware. In the latter case, for example, when the memory system 3 receives power, the processor reads the firmware (control program) stored in a ROM (not shown) onto a data buffer 34 or RAM (not shown) in the control unit 32 and executes predetermined processing, thereby realizing the processing of the control unit 32. Here, the processor is also referred to as a core or processor core.

[0031] Furthermore, when the control unit 32 receives a write request from the host 2, it determines the storage area (memory area) on the NAND memory 40 for the user data specified in the write request. In other words, the control unit 32 manages the destination for writing user data. The correspondence between the logical address of the user data received from the host 2 and the physical address indicating the storage area on the NAND memory 40 where the user data is stored is stored as an address translation table. The control unit 32 also manages and stores the address translation table as management information, and also stores information for managing the memory system 3 other than the address translation table as part of the management information.

[0032] Furthermore, when the control unit 32 receives a read request from the host 2, it converts the logical address specified in the read request to a physical address using the address translation table described above, and instructs the NANDI / F33 to read from that physical address.

[0033] Furthermore, the control unit 32 performs various calculations. For example, the control unit 32 performs data encryption and randomization processes.

[0034] The NANDI / F33 controls the NAND memory 40. The NANDI / F33 erases the data stored in the NAND memory 40 according to the control of the control unit 32, etc.

[0035] The data buffer 34 temporarily stores user data received from the host 2 by the memory controller 30 until it is stored in the NAND memory 40. The data buffer 34 also temporarily stores user data read from the NAND memory 40 until it is sent to the host 2. The data buffer 34 is composed of general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). The data buffer 34 may be implemented within the memory controller 30, or it may be implemented outside the memory controller 30 independently of it.

[0036] The ECC circuit 35 includes an encoding circuit 50 and a decoding circuit 51. The control unit 32 uses the ECC circuit 35 to correct errors in the data. The control unit 32 uses the encoding circuit 50 to encode the data and generate a codeword having data and redundancy (parity), and instructs the NANDI / F33 to write the codeword to the NAND memory 40. The control unit 32 also uses the decoding circuit 51 to retrieve the codeword, which is the data read from the NAND memory 40, via the NANDI / F33, and decodes the retrieved codeword.

[0037] The encryption / decryption circuit 36 ​​performs encryption and decryption processes. The encryption process encrypts the data to be written to the NAND memory 40 with an encryption key to conceal it, according to security requirements. The decryption process decrypts the encrypted data read from the NAND memory 40 using the same encryption key as used for encryption, according to security requirements. If the encryption / decryption circuit 36 ​​fails to decrypt the encrypted data, it notifies the processor 22 of the decryption failure. The encryption / decryption circuit 36 ​​may also be implemented inside the host I / F 31. The flag detection unit 38 checks whether a flag has been assigned to the music data. This may be implemented internally in the NANDI / F33.

[0038] The flagging unit 39 assigns a flag to the music data. The flagging unit 39 may be implemented inside the host I / F 31.

[0039] In the memory system according to the first embodiment, the memory controller 30 accesses the NAND memory 40 when it receives a read request, write request, data erase request, data deletion request such as a trim command from the host 2, or when the memory controller 30 performs garbage collection, refresh, wear leveling, patrol read, direct memory access, etc. in the background.

[0040] Garbage collection is also called compaction. Because NAND memory 40 has different data erasure units and data read / write units, as the NAND memory 40 is rewritten, invalid data causes the blocks to become fragmented. As the number of such fragmented blocks increases, the number of usable blocks decreases. Garbage collection is a process to increase the number of usable blocks. For example, it means collecting valid data from multiple active blocks that contain both valid and invalid data, rewriting it into another block, and freeing up free blocks.

[0041] An active block is a block in which valid data is recorded. A free block is a block in which no valid data is recorded. After erasing, a free block can be reused as an erased block. In this embodiment, a free block includes both a block before erasure (in which no valid data is recorded) and an erased block. Valid data is data associated with a logical address, and invalid data is data not associated with a logical address. An erased block becomes an active block when data is written to it.

[0042] Refresh is a process that rewrites data in a block to another block when data degradation is detected, such as an increase in the number of correction bits in error correction processing.

[0043] Wear leveling is a process that equalizes the number of write cycles of blocks in NAND memory 40 by, for example, swapping data stored in blocks with a high number of write cycles or erase cycles with data stored in blocks with a low number of write cycles or erase cycles.

[0044] Patrol read is a process that, for example, reads data stored in the NAND memory 40 in predetermined units to detect blocks with increasing errors, and tests the read data based on the error correction results. In this test process, for example, the number of erroneous bits in the read data is compared with a threshold, and data with a number of erroneous bits exceeding the threshold is targeted for refresh.

[0045] Direct memory access is a process that, for example, directly transfers data between the host 2 and the memory system 3 without going through the control unit 32. For example, in data reading, direct memory access includes the process of transferring read data from the NAND memory 40 to the data buffer 34 and the process of transferring read data from the data buffer 34 to the host 2.

[0046] In the memory system 3 according to the first embodiment, clock gating technology is applied to the clock signal that controls the operation of the circuit. Clock gating technology restricts the supply of the system clock signal to each circuit block. The system clock signal is supplied to the necessary circuit block at the necessary timing, and the power consumption of the memory system 3 can be suppressed.

[0047] The overview of writing music data to the comparative example memory system is explained using the flowchart in Figure 3.

[0048] In step S31, the host sends music data and a write command to the memory system. In step S32, the memory controller encrypts the music data. In step S33, the memory controller writes the music data to the NAND memory.

[0049] The overview of reading music data from the comparative example memory system is explained using the flowchart in Figure 4.

[0050] In step S41, the host sends a command to read the music data. In step S42, the memory controller decrypts the encrypted music data. The encryption key used in this decryption process is the same as the encryption key used in the encryption process in step S32. In step S43, the memory controller sends the music data to the host, and the reading is completed.

[0051] In other words, when the comparative memory system reads music data from NAND memory, a decoding process is performed. Generally, the host reads music data while simultaneously playing it back at the same time. It is known that sudden power changes generate high-frequency noise, which degrades the sound quality during music playback. Therefore, if a process that may cause sudden power changes is performed within the memory system, the likelihood of high-frequency noise being generated within the memory system also increases.

[0052] Therefore, the memory system 3 of the first embodiment operates in either normal mode or high-quality mode. The host 2 switches between normal mode and high-quality mode by sending a command to the memory system 3. When the memory system 3 of the first embodiment is operating in high-quality mode, it stores music data without encryption.

[0053] The overview of writing music data in high-quality mode to the memory system 3 of the first embodiment will be explained using the flowchart in Figure 5. In step S51, if the user requests high-quality mode, the host 2 sends a command to the memory controller 30 requesting a transition to high-quality mode. In step S52, the memory controller 30 transitions to high-quality mode.

[0054] In step S53, the user selects the music data to be written in high-quality mode. In step S54, the host 2 sends the music data to the memory controller 30. In step S55, the memory system 3 adds a flag to the music data. Specifically, the flagging unit 39 adds a flag to the music data. In step S56, the memory controller 30 saves the music data to the NAND memory 40. At this time, the music data is not encrypted.

[0055] Once all the music data selected by the user has been written, in step S57 the host 2 requests the memory controller 30 to terminate the high-quality mode. In step S58 the memory controller 30 terminates the high-quality mode, and the writing of music data in high-quality mode is completed.

[0056] Here, the error correction process performed by the ECC circuit 35 and the encryption process performed by the encryption / decryption circuit 36 ​​are different. In the first embodiment, the memory system 3 does not perform encryption in high-quality mode. In the first embodiment, the memory system 3 performs encoding by the ECC circuit 35 after step S54 in which the host transmits music data to the memory controller 30, and before step S56 in which the memory controller 30 stores the music data in the NAND memory 40 is completed.

[0057] In the first embodiment, when in normal mode, music data is written to the NAND memory 40 in the same manner as in the comparative example. In this case, no flags are assigned to the music data.

[0058] The overview of reading music data from the memory system 3 of the first embodiment will be explained using the flowchart in Figure 6. In step S61, the host 2 requests the memory controller 30 to read music data. In step S62, the memory controller 30 reads the music data instructed by the host 2. In step S63, the memory controller 30 determines whether a flag has been assigned to the read music data. Specifically, the flag detection unit 38 may check the music data loaded into the data buffer 34. Alternatively, the flag detection unit 38 may check the music data that has passed through the NANDI / F 33.

[0059] If the music data contains a flag (Yes in step S63), the memory controller 30 sends the music data to the host 2 in step S64. At this time, the encryption / decryption circuit 36 ​​does not perform decryption processing, and the process proceeds to step S66. If the music data does not contain a flag (No in step S63), the encryption / decryption circuit 36 ​​in the memory controller 30 performs decryption processing on the music data in step S65. After that, the memory controller 30 sends the music data to the host 2.

[0060] In step S66, host 2 acquires music data. Then, for example, it plays the music data.

[0061] In the first embodiment, music data written in high-quality mode is not encrypted and is written to the NAND memory 40 with a flag attached. Therefore, the music data can be read without decryption. This reduces the possibility of high-frequency noise generation.

[0062] If the data to be written is music data, the memory controller 30 may write the music data to the NAND memory 40 without performing encryption. An overview of this case will be explained using the flowchart in Figure 7.

[0063] In step S71, the host 2 requests the memory controller 30 to write data. In step S72, the memory controller 30 determines whether the data to be written is music data or not. Specifically, the music information detection unit 37 within the memory controller 30 determines whether the data to be written is music data or not. If the data to be written is music data (Yes in step S72), in step S73 the memory controller 30 flags the music data and proceeds to step S75. If the data to be written is not music data (No in step S72), in step S74 the memory controller 30 performs data encryption. Then, in step S75 the memory controller 30 writes the data to the NAND memory 40.

[0064] (Second embodiment) The memory system according to the second embodiment will be described below. Parts of the memory system according to the second embodiment that are identical to those of the memory system according to the first embodiment will be denoted by the same reference numerals. A detailed explanation of the overlapping parts of the memory system according to the second embodiment and the memory system according to the first embodiment will be omitted.

[0065] Figure 8 is a block diagram focusing on the host I / F 31 of the memory system 3 in Embodiment 2. For example, the host I / F 31 includes host I / F lanes 310-0, 310-1, 310-2, and 310-3. Host I / F lanes 310-0 to 310-4 are collectively referred to as host I / F lane 310 when there is no need to distinguish between them. Although an example is given where there are four host I / F lanes 310, the number of host I / F lanes 310 is not limited to four; the number of host I / F lanes 310 can be a natural number.

[0066] In the normal mode of the memory system 3 of the second embodiment, the memory controller 30 sends and receives signals to and from the host 2 using host I / F lanes 310-0 to 310-4.

[0067] In the high-quality mode of the memory system 3 of the second embodiment, the number of host I / F lanes 310 used can be changed. For example, the memory controller 30 uses two host I / F lanes 310, host I / F lane 310-0 and host I / F lane 310-1, to send and receive signals with the host. Although the example shows two host I / F lanes 310 being used, the number of host I / F lanes 310 used is not limited to two. The number of host I / F lanes 310 used is a natural number smaller than the total number of host I / F lanes 310. In the high-quality mode of the memory system 3 of the second embodiment, it is sufficient to have performance that is capable of transmitting music data to the host.

[0068] In the second embodiment of the memory system 3, in normal mode, the host I / F 31 operates at its highest performance. Specifically, the memory controller 30 uses all host I / F lanes 310 to send and receive signals with the host 2. On the other hand, in high-quality mode, the second embodiment of the memory system 3 uses a number of host I / F lanes 31 sufficient to send music data to the host 2 to send and receive signals with the host 2. The speed of the host I / F 31 in high-quality mode is lower than the speed of the host I / F 31 in normal mode. In high-quality mode, by reducing the performance of the host I / F, abrupt power changes are suppressed, and the possibility of high-frequency noise generation in the memory system 3 can be reduced.

[0069] (Third embodiment) The memory system according to the third embodiment will be described below. Parts of the memory system according to the third embodiment that are the same as those of the memory system according to the first embodiment will be denoted by the same reference numerals. A detailed explanation of the overlapping parts of the memory system according to the third embodiment and the memory system according to the first embodiment will be omitted.

[0070] Figure 9 is a block diagram focusing on the NAND chip 42 of the memory system 3 of the third embodiment. In the memory system 3 of the third embodiment, a predetermined NAND chip 42 has a music data storage area 48. Only music data is stored in the music data storage area 48. Multiple NAND chips 42 may each have a music data storage area 48. Figure 9 illustrates the case where NAND chip 42-0 has a music data storage area 48, but is not limited to this.

[0071] In the normal mode of the memory system 3 of the third embodiment, the NANDI / F33 can transmit and receive signals with all NAND chips 42.

[0072] In the high-quality mode of the memory system 3 of the third embodiment, the functionality of the NAND chip 42 that does not have a music data storage area 48 is restricted. In other words, NANDI / F33 cannot send or receive signals to the NAND chip 42 that does not have a music data storage area 48. NANDI / F33 can only send and receive signals to the NAND chip 42-0 that has a music data storage area 48.

[0073] In the high-quality mode of the memory system 3 of the third embodiment, for example, the clock of the NAND chip 42 that does not have a music data storage area 48 is stopped by clock gating control. By limiting the functionality of the NAND chip 42 that does not have a music data storage area 48 in this way, the high-quality mode of the memory system 3 of the third embodiment is realized.

[0074] Furthermore, the memory system 3 of the third embodiment may be configured such that, for example, each NAND chip 42 has a different power supply circuit. In that case, the function is limited by turning off the power to the NAND chip 42 that does not have a music data storage area 48, thereby realizing a high-quality mode for the memory system 3 of the third embodiment.

[0075] In the high-quality mode of the memory system 3 of the third embodiment, only the NAND chips 42 having the music data storage area 48 function, and the NAND chips 42 that do not have the music data storage area 48 do not function. In high-quality mode, by reducing the performance of some of the NAND chips 42, abrupt power changes can be suppressed, thereby reducing the possibility of high-frequency noise generation in the memory system 3.

[0076] If the music data storage area 48 is always located within a predetermined NAND chip 42, the number of write cycles and erase cycles will be high only for that predetermined NAND chip 42, while the number of write cycles and erase cycles for the other NAND chips 42 will be low. Therefore, the NAND chip 42 having the music data storage area 48 may be configured to be changed at regular intervals.

[0077] In the third embodiment of the memory system 3, for example, a music data storage area (not shown) different from the music data storage area 48 is created on the NAND chip 42-1, which has a low number of write and erase cycles. The music data stored in the music data storage area 48 of the NAND chip 42-0 is stored in the music data storage area (not shown) of the NAND chip 42-1. The music data storage area 48 that the NAND chip 42-0 had is erased. By periodically swapping the music data storage areas in this way, the number of write cycles of the blocks in the NAND memory 40 can be equalized.

[0078] (Fourth embodiment) The memory system according to the fourth embodiment will be described below. Parts of the memory system according to the fourth embodiment that are identical to those of the memory system according to the first embodiment will be denoted by the same reference numerals. A detailed explanation of the overlapping parts between the memory system according to the fourth embodiment and the memory system according to the first embodiment will be omitted. In the fourth embodiment of the memory system 3, various background processes are not performed when in high-quality mode. Specifically, while the memory system 3 performs compaction, garbage collection, refresh, wear leveling, patrol read, and direct memory access at predetermined timings in normal mode, it reduces the frequency of these processes in high-quality mode. By not performing the above processes in high-quality mode, sharp power fluctuations in high-quality mode are suppressed, and the possibility of high-frequency noise generation in the memory system 3 is reduced.

[0079] It should be noted that the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention.

[0080] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0081] 1. Information Processing System 2. Host 3. Memory System 21...Host CPU 22...Host ROM 23. Host RAM 24..Memory I / F 25. Audio Interface 251...Speaker 26. Input Devices 27...Video I / F 271...Display 28. Communication Interface 30...Memory Controller 300...Internal bus 31. Host Interface 310...Host I / F Lane 32.. Control Unit 33···NANDI / F 34. Data buffer 35...ECC circuit 36. Encryption / Decryption Circuits 37. Music Information Detection Unit 38. Flag detection unit 39. Flag assignment section 40...NAND memory 42...NAND chips 44... Peripheral Circuits 46... Plain 48. Music data storage area 50...encoding circuit 51...Decoding circuit

Claims

1. Connectable to the host, A memory controller including an interface capable of communicating with the host, Non-volatile memory and Equipped with, The aforementioned memory controller When the interface receives music data during the first mode, it assigns a flag to the music data and stores the music data in the non-volatile memory. A memory system that, when the interface receives the music data during a second mode different from the first mode, performs encryption processing on the music data and stores the music data in the non-volatile memory.

2. The aforementioned memory system The system transitions between the first mode and the second mode based on instructions from the host. The memory system according to claim 1.

3. The memory system includes a plurality of non-volatile memories, The aforementioned memory controller The music data is stored in the first non-volatile memory among the plurality of non-volatile memories. The memory system according to claim 1.

4. The memory system further includes a flag detection unit, The aforementioned memory controller If the flag detection unit does not recognize the flag when reading the music data, it performs a decoding process and sends the music data to the host. When the flag detection unit recognizes the flag while reading the music data, it transmits the music data to the host without performing the decoding process. The memory system according to claim 1.

5. The speed of the interface in the first mode is less than the speed of the interface in the second mode. The memory system according to claim 1.

6. The aforementioned memory controller In the first mode, the supply of the system clock to the non-volatile memory, excluding the first non-volatile memory on which the music data is stored, The memory system according to claim 3.

7. The aforementioned memory controller After a certain period of time, a second non-volatile memory different from the first non-volatile memory is selected. The music data stored in the first non-volatile memory is moved to the second non-volatile memory. The music data received thereafter is stored in the second non-volatile memory. The memory system according to claim 3.

8. In the first mode, the memory controller Compared to the memory controller in the second mode, the frequency of compaction, garbage collection, refresh, wear leveling, patrol read, and direct memory access is lower. The memory system according to claim 1.

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