Laminated structure and method for manufacturing a laminated structure

Abstract

This invention provides a method for manufacturing a laminated structure that can stably bond metal electrodes together. [Solution] The disclosed manufacturing method is a method for manufacturing a laminated structure, comprising the steps of: (i) preparing a first substrate including a first insulating layer and a first metal electrode arranged on one main surface, and a second substrate including a second insulating layer and a second metal electrode arranged on one main surface; (ii) forming a recess in the adjacent portion of the first insulating layer by removing at least a portion of the adjacent portion of the first insulating layer adjacent to the first metal electrode; (iii) bonding the first substrate and the second substrate so that the first insulating layer and the second insulating layer are in contact; and (iv) joining the first metal electrode and the second metal electrode while the first substrate and the second substrate are bonded together. At least one of the first substrate and the second substrate includes a semiconductor element.

Description

Technical Field

[0001] The present disclosure relates to a laminated structure and a method for manufacturing the laminated structure.

Background Art

[0002] Conventionally, the high density of semiconductor chips has been advanced. Also, as a technology related to semiconductor chips, chiplet technology has attracted attention. Claim 1 of Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2020-170740) states, "A method for manufacturing a laminated device chip including a first device formed in each region on the surface of a first wafer partitioned by a plurality of planned division lines and a second device formed in each region on the surface of a second wafer partitioned by a plurality of planned division lines, forming a plurality of first chips by dividing the first wafer of a work set including a ring frame, an adhesive tape adhered to the ring frame so as to close the opening of the ring frame, and the first wafer whose back surface is adhered to the adhesive tape, along the planned division lines; a first wafer dividing step; after the first wafer dividing step, a polishing step of removing processing debris from the first surface by polishing the first surface including the first device that becomes the bonding surface in the plurality of first chips, with a polishing pad; after the polishing step, a cleaning step of cleaning the first chip by supplying cleaning water to the first surface side of the first chip; after the cleaning step, a pickup step of separating the first chip from the adhesive tape; a preparation step of performing preparation for making the first surface of the first chip and the second surface that is the bonding surface of the second device in the second wafer bondable; a bonding step of facing the first surface of the first chip to the second surface of the second device and bonding the second surface and the first surface; A stacked device chip manufacturing process for manufacturing individual stacked device chips by dividing the second wafer along the planned division line of the second wafer after the bonding process, The document discloses a method for manufacturing a stacked device chip, including [the specified component].

[0003] Claim 1 of Patent Document 2 (Japanese Patent Publication No. 2021-197430) is "a step of preparing a first semiconductor substrate having a first substrate body, a first insulating film and a first electrode provided on one surface of the first substrate body, A step of preparing a second semiconductor substrate having a second substrate body, a second insulating film provided on one surface of the second substrate body, and a plurality of second electrodes, A step of polishing at least one of the one side of the first semiconductor substrate and the one side of the second semiconductor substrate, A step of separating the second semiconductor substrate into individual pieces to obtain a plurality of semiconductor chips, each of which is provided with an insulating film portion corresponding to the second insulating film and at least one of the second electrodes, A step of aligning the second electrode of at least one semiconductor chip among the plurality of semiconductor chips with respect to the first electrode of the first semiconductor substrate, A step of bonding the first insulating film of the first semiconductor substrate and the insulating film portion of the semiconductor chip to each other, The process includes a step of joining the first electrode of the first semiconductor substrate to the second electrode of the semiconductor chip, At least one of the first insulating film and the second insulating film contains an organic material. The document discloses "a method for manufacturing a semiconductor device."

[0004] Chiplet technology requires bonding the substrate and the semiconductor chip. Currently, hybrid bonding and other methods are attracting attention as ways to bond the substrate and the semiconductor chip. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-170740 [Patent Document 2] Japanese Patent Publication No. 2021-197430 [Overview of the project] [Problems that the invention aims to solve]

[0006] In hybrid bonding, copper electrodes on a substrate and copper electrodes on a semiconductor chip are joined together. However, the bond between copper electrodes can sometimes be unstable. In such situations, one of the objectives of this disclosure is to provide a method for manufacturing a laminated structure that can stably bond metal electrodes together. [Means for solving the problem]

[0007] One aspect of this disclosure is a method for manufacturing a laminated structure, Step (i) of preparing a first substrate including a first insulating layer and a first metal electrode arranged on one main surface, and a second substrate including a second insulating layer and a second metal electrode arranged on one main surface, (ii) A step of forming a recess in the adjacent portion of the first insulating layer by removing at least a portion of the adjacent portion of the first insulating layer adjacent to the first metal electrode, (iii) A step of bonding the first substrate and the second substrate together such that the first insulating layer and the second insulating layer are in contact, The process includes (iv) a step of bonding the first metal electrode and the second metal electrode while the first substrate and the second substrate are bonded together, The present invention relates to a method for manufacturing a stacked structure in which at least one of the first substrate and the second substrate includes a semiconductor element.

[0008] Another aspect of this disclosure is a laminated structure, A first substrate including a first insulating layer and a first metal electrode arranged on one main surface, It includes a second substrate having a second insulating layer and a second metal electrode arranged on one main surface, At least one of the first substrate and the second substrate includes a semiconductor element. At least a part of the first insulating layer and at least a part of the second insulating layer are in close contact with each other. An adjacent portion of the first insulating layer adjacent to the first metal electrode is thinner than portions other than the adjacent portion. There is a gap between the adjacent portion and the second insulating layer. Regarding a laminated structure, at least a part of at least one of the first metal electrode and the second metal electrode penetrates into the gap.

Advantages of the Invention

[0009] According to the present disclosure, a laminated structure in which metal electrodes are stably joined to each other can be obtained.

Brief Description of the Drawings

[0010] [Figure 1] FIG. 1 is a cross-sectional view schematically showing an example of a manufacturing method according to the present embodiment. [Figure 2] FIG. 2 is a side view schematically showing an example of an apparatus used in the manufacturing method according to the present embodiment. [Figure 3] FIG. 3 is a cross-sectional view schematically showing an example of a step of the manufacturing method according to the present embodiment. [Figure 4] [[ID=三十]] [Figure 4] FIG. 4 is a cross-sectional view schematically showing another example of a step of the manufacturing method according to the present embodiment. [Figure 5] FIG. 5 is a cross-sectional view schematically showing an example of a laminated structure manufactured in the present embodiment. [Figure 6] FIG. 6 is a diagram schematically showing the flow of an example of the manufacturing method according to the present embodiment. [Figure 7] FIG. 7 is a cross-sectional view schematically showing an example of a step of the manufacturing method according to the present embodiment. [Figure 8] FIG. 8 is a cross-sectional view schematically showing an example of a step of the manufacturing method according to the present embodiment.

Modes for Carrying Out the Invention

[0011] The embodiments of this disclosure will be described below with examples, but this disclosure is not limited to the examples described below. In the following description, specific numerical values ​​and materials may be given as examples, but other numerical values ​​and other materials may be applied as long as they allow the invention of this disclosure to be carried out. In this specification, the description "numerical value A to numerical value B" includes numerical value A and numerical value B, and can be read as "greater than or equal to numerical value A and less than or equal to numerical value B". In the following description, when lower and upper limits of numerical values ​​relating to specific physical properties or conditions are given as examples, either the given lower limit and either the given upper limit may be arbitrarily combined, as long as the lower limit does not exceed the upper limit. In the following description, when examples of components or methods are listed, unless otherwise specified, only one of the listed examples may be used, or multiple of the listed examples may be used in combination.

[0012] (Method of manufacturing a laminated structure) The manufacturing method according to this embodiment is a method for manufacturing a laminated structure. The manufacturing method according to this embodiment may be referred to as "manufacturing method (M)" below. Manufacturing method (M) includes steps (i), (ii), (iii), and (iv) in that order. These steps are described below.

[0013] (Step (i)) Step (i) is a step of preparing a first substrate including a first insulating layer and a first metal electrode arranged on one main surface (one main surface of the first substrate), and a second substrate including a second insulating layer and a second metal electrode arranged on one main surface (one main surface of the second substrate). The first insulating layer and the first metal electrode are exposed at the bonding surface of the first substrate. The second insulating layer and the second metal electrode are exposed at the bonding surface of the second substrate.

[0014] The preparation step may be the process of procuring the first and / or second substrates manufactured by a third party. Alternatively, the preparation step may be the process of manufacturing the first and / or second substrates. The method of manufacturing these substrates is not limited and may be done by known methods.

[0015] At least one of the first substrate and the second substrate includes semiconductor elements. The first substrate alone may include semiconductor elements. The second substrate alone may include semiconductor elements. Alternatively, the first substrate and the second substrate may each include semiconductor elements. In a typical example, the first substrate and the second substrate each include multiple semiconductor elements. In a typical example, the first substrate includes multiple first metal electrodes, and the second substrate includes multiple second metal electrodes. The first substrate and / or the second substrate may include elements other than semiconductor elements, and may include electrodes disposed within the substrate.

[0016] Each of the first and second substrates may contain multiple semiconductor chips that have not been individually packaged. For example, both the first and second substrates may contain semiconductor wafers, or only one of them may contain a semiconductor wafer. One of the first and second substrates may contain individually packaged semiconductor chips. In one example of manufacturing method (M), one of the first and second substrates contains a semiconductor wafer, and the other of the first and second substrates contains individually packaged semiconductor chips. This configuration makes it possible to improve the yield of semiconductor chips formed using a stacked structure. In this configuration, typically in step (iii), semiconductor chips are placed on a substrate containing a semiconductor wafer.

[0017] The first substrate may include a first base substrate. If the first substrate includes a first base substrate, the first insulating layer and the first metal electrode may be laminated directly or indirectly on the first base substrate. The second substrate may include a second base substrate. If the second substrate includes a second base substrate, the second insulating layer and the second metal electrode may be laminated directly or indirectly on the second base substrate. The first base substrate and the second base substrate can be semiconductor substrates, glass substrates, etc. Examples of semiconductor substrates include silicon substrates, etc. The first insulating layer and the second insulating layer may be inorganic insulating layers or organic insulating layers. Examples of inorganic insulating layers include silicon oxide layers and SiCN layers, etc. The insulating layer may be made of a compound containing the elements of the semiconductor that constitute the substrate.

[0018] The first and second metal electrodes may each be made of copper or a copper alloy. A first insulating layer is present around the first metal electrode, and a second insulating layer is present around the second metal electrode.

[0019] To ensure reliable bonding between the first and second metal electrodes, it is preferable that the bonding surfaces of the first and second substrates be generally flat. Therefore, the bonding surface of the first substrate may be polished, or the bonding surface of the second substrate may be polished. The difference in height between the surface of the first metal electrode and the surface of the first insulating layer is preferably 10 nm or less. The difference in height between the surface of the second metal electrode and the surface of the second insulating layer is also preferably 10 nm or less. Considering the difference in thermal expansion coefficients, in a preferred example, the surface of the first metal electrode is lower than the surface of the first insulating layer, and the surface of the second metal electrode is also lower than the surface of the second insulating layer.

[0020] If the first substrate is not polished in step (ii), step (i) may include polishing the bonding surface of the first substrate (the surface of the first metal electrode and the surface of the first insulating layer). Similarly, if the second substrate is not polished in step (ii), step (i) may include polishing the bonding surface of the second substrate (the surface of the second metal electrode and the surface of the second insulating layer). These polishing steps facilitate the bonding of the first metal electrode and the second metal electrode and increase their bonding strength. The polishing method is not limited. Examples of polishing methods include chemical mechanical polishing (CMP).

[0021] (Step (ii)) Step (ii) is a step of forming a recess in the adjacent portion of the first insulating layer by removing at least a portion of the adjacent portion of the first insulating layer adjacent to the first metal electrode. The portion of the first insulating layer adjacent to the first metal electrode may be referred to as "adjacent portion A1" below. Adjacent portion A1 means the portion of the first insulating layer whose distance from the first metal electrode is, for example, 1 μm or less. The surface of the first insulating layer in the region from which the first insulating layer is removed by step (ii) is lower than the surface of the first insulating layer in the other regions. In other words, in step (ii), at least a portion of adjacent portion A1 is removed such that the surface of the first insulating layer in adjacent portion A1 is lower than the surface of the first insulating layer in the region other than adjacent portion A1. By removing this portion, a gap is formed in the adjacent portion A1 when the first substrate and the second substrate are bonded together, as will be described later.

[0022] Examples of recessed forms include grooves. Other examples of recessed forms include forms in which the corners of adjacent areas of the first insulating layer are chamfered and lower than other areas of the first insulating layer.

[0023] The maximum height of the void (the void between adjacent portion A1 and the second insulating layer) (the maximum length of the void in the thickness direction of the first substrate) may be 1 nm or more, 5 nm or more, 10 nm or more, 50 nm or more, or 100 nm or more, and may be 1000 nm or less, 500 nm or less, 200 nm or less, or 100 nm or less. The maximum width of the void (the void between adjacent portion A1 and the second insulating layer) (the maximum length of the void in the direction parallel to the surface of the first substrate) may be 0.1 μm or more, or 0.5 μm or more, and may be 2 μm or less, or 1 μm or less.

[0024] Step (ii) may include a step of polishing the first metal electrode and the first insulating layer by a chemical mechanical polishing method so that the adjacent portions of the first insulating layer are chamfered. At this time, the polishing may be performed so that the surface of the first metal electrode is lower than the surface of the first insulating layer.

[0025] One example of process (ii) uses chemical mechanical polishing. In this case, one example of process (ii) includes process (iia) and process (iib) in this order. The method using chemical mechanical polishing is particularly effective when the insulating layer is more difficult to polish than the metal electrode. For example, it is particularly effective when the metal electrode is a copper electrode or a copper alloy electrode and the insulating layer is a silicon-containing insulating layer (silicon oxide, SiCN, etc.).

[0026] Step (iia) is a process of chemically mechanically polishing the first metal electrode and the first insulating layer by pressing the first substrate against a polishing pad at a first pressure such that the surface of the first metal electrode and the surface of the first insulating layer are planarized. Step (iib) is a process of chamfering the adjacent portions of the first insulating layer by chemically mechanically polishing the first metal electrode and the first insulating layer by pressing the first substrate against a polishing pad at a second pressure which is higher than the first pressure.

[0027] The pressure for chemical mechanical polishing is selected according to the materials of the metal electrode and insulating layer, the type of abrasive, etc. The first pressure may be 8 Pa or more and 18 Pa or less. The second pressure may be 15 Pa or more and 25 Pa or less. The ratio of the second pressure P2 (Pa) to the first pressure P1 (Pa), P2 / P1, may be 1.1 or more and 2.0 or less. The pressures described herein are particularly preferable when the metal electrode is a copper electrode or a copper alloy electrode and the insulating layer is a silicon-containing insulating layer (silicon oxide, SiCN, etc.).

[0028] Process (iia) is performed with the purpose of planarizing the surface of the first metal electrode and the surface of the first insulating layer. Therefore, the polishing in process (iia) is performed at a relatively low pressure. On the other hand, process (iia) is performed with the purpose of removing material from the first metal electrode and the adjacent part A1. Therefore, the polishing in process (iib) is performed at a higher pressure than the polishing in process (iia).

[0029] Another example step (ii) involves removing at least a portion of the adjacent portion A1 using a resist mask. This step (ii) includes steps (iiA) and (iiB) in that order. Step (iiA) is the step of forming a resist mask having an opening in the adjacent portion of the first insulating layer on the first insulating layer and the first metal electrode. Step (iiB) is the step (removal step) of forming a recess in the adjacent portion A1 of the first insulating layer by removing at least a portion of the adjacent portion A1 exposed at the opening. After step (iiB), the resist mask is removed.

[0030] The method for forming the resist mask is not limited, and known methods may be used. Removal of at least a portion of the adjacent areas may be performed by etching. The etching method is not limited and can be selected according to the material of the insulating layer. Etching may be plasma etching or etching using an etching solution.

[0031] Step (ii) may further include the step of forming a recess in the adjacent portion of the second insulating layer by removing at least a portion of the adjacent portion of the second insulating layer adjacent to the second metal electrode. This adjacent portion may be referred to as "adjacent portion A2" below. The method for removing adjacent portion A2 is not limited. Adjacent portion A2 may be removed using the method described for removing adjacent portion A1. By removing adjacent portion A2, the gap formed in the adjacent portion can be made larger. Therefore, a more reliable joint can be formed. The size of adjacent portion A2 may be the size described for adjacent portion A1.

[0032] (Step (iii)) This is a step of bonding the first substrate and the second substrate together such that the first insulating layer and the second insulating layer are in contact. Step (iii) can be performed by adjusting the relative positions of the first substrate and the second substrate and bringing the bonding surface of the first substrate into contact with the bonding surface of the second substrate. The first insulating layer and the second insulating layer are bonded together by contact.

[0033] Prior to step (iii), the bonding surfaces of the first substrate and the second substrate may be plasma-treated to bond hydroxyl groups to the surfaces of the first and second insulating layers. For example, the surfaces of the insulating layers may be hydrophilized (or activated) by plasma treatment. If the first and second insulating layers are silicon oxide films, hydroxyl groups can be bonded to the surface of the silicon oxide films by performing plasma treatment (hydrophilization treatment). In that case, the first and second insulating layers can be bonded more strongly via hydrogen bonds in step (iii). The conditions for plasma treatment are not particularly limited, and known conditions may be applied.

[0034] (Step (iv)) Step (iv) is a step in which the first metal electrode and the second metal electrode are joined together while the first substrate and the second substrate are bonded together. Step (iv) electrically connects the first metal electrode of the first substrate and the second metal electrode of the second substrate. Step (iv) can be performed by heating the first substrate and the second substrate while they are bonded together. For example, both substrates may be heated while applying pressure to them so that the bonding surface of the first substrate and the second substrate are in contact.

[0035] The heating method is not limited; the bonded first and second substrates may be heated in a heating chamber. The heating conditions can be selected according to the material of the metal electrodes, etc. The heating temperature may be between 180°C and 500°C. The heating time may be 60 minutes or more.

[0036] Generally, the thermal expansion coefficient (volume expansion coefficient) of a metal electrode (e.g., a copper electrode) is greater than that of an insulating layer (e.g., silicon oxide). Therefore, if the surface height of the metal electrode and the surface height of the insulating layer are the same, the expansion of the metal electrode generates a force that separates the first substrate from the second substrate. If all metal electrodes are at the same height, uniform bonding is possible, but it is difficult to make all metal electrodes the same height. If some metal electrodes are higher than others, the bonding of the other metal electrodes will be hindered. In step (ii) of manufacturing method (M), at least a portion of the insulating layer adjacent to the metal electrode is removed, so that a void can be created in that portion. Even if there is a metal electrode that is higher than other metal electrodes, the expanded metal electrode moves into the void, suppressing defects in the bonding of the metal electrodes. Therefore, according to manufacturing method (M), a laminated structure in which metal electrodes are stably bonded to each other can be obtained.

[0037] According to manufacturing method (M), a substrate containing multiple semiconductor chips can be manufactured. By dividing the substrate manufactured by manufacturing method (M), multiple semiconductor chips can be obtained. Furthermore, manufacturing method (M) can be applied to chiplet technology.

[0038] (Laminated structure) The stacked structure according to this embodiment may be referred to as "stacked structure (S)" below. The stacked structure (S) can be manufactured by the manufacturing method (M). Matters described regarding the manufacturing method (M) can be applied to the stacked structure (S), so redundant explanations may be omitted. Matters described regarding the stacked structure (S) may also be applied to the manufacturing method (M). From one perspective, the stacked structure (S) includes multiple semiconductor chips. Multiple semiconductor chips can be obtained by dividing the stacked structure (S). From one perspective, the stacked structure (S) can be considered to include at least one semiconductor device. Therefore, from one perspective, the manufacturing method (M) is a method for manufacturing a semiconductor device.

[0039] The laminated structure (S) includes a first substrate having a first insulating layer and a first metal electrode arranged on one main surface (one main surface of the first substrate), and a second substrate having a second insulating layer and a second metal electrode arranged on one main surface (one main surface of the second substrate). At least one of the first substrate and the second substrate includes a semiconductor element. At least a portion of the first insulating layer and at least a portion of the second insulating layer are in close contact. The adjacent portion A1 of the first insulating layer adjacent to the first metal electrode is thinner than the portion other than adjacent portion A1. There is a void between adjacent portion A1 and the second insulating layer. At least one portion of the first metal electrode and the second metal electrode extends into the void.

[0040] There is a gap between the adjacent portion A1 and the second insulating layer. In other words, the adjacent portion A1 and the second insulating layer are separated. As described above, even if there is an excess of metal electrode at the junction between the first metal electrode and the second metal electrode, the excess metal electrode will enter the gap, thus preventing the first substrate and the second substrate from separating.

[0041] Furthermore, when a large number of laminated structures are manufactured by manufacturing method (M), some laminated structures that are not laminated structures (S) may be manufactured. That is, when a large number of laminated structures are manufactured by manufacturing method (M), some laminated structures in which metal electrodes do not enter the gap between the adjacent portion A1 and the second insulating layer may be manufactured. When a large number of laminated structures are manufactured by manufacturing method (M), some of the laminated structures become laminated structures (S).

[0042] The surface of the adjacent portion A2 of the second insulating layer adjacent to the second metal electrode may be lower than the surface of the other portions of the second insulating layer. In this configuration, the volume of the void in the adjacent portion is particularly large, resulting in particularly high reliability of the joint. This configuration can be achieved by forming a recess in the adjacent portion A2 of the second insulating layer in step (ii).

[0043] Each of the first and second substrates may contain multiple semiconductor chips that have not been individually packaged. For example, both the first and second substrates may contain semiconductor wafers, or only one of them may contain a semiconductor wafer. One of the first and second substrates may contain individually packaged semiconductor chips. In one example of a stacked structure (S), one of the first and second substrates contains a semiconductor wafer, and the other of the first and second substrates contains individually packaged semiconductor chips.

[0044] Examples of embodiments relating to this disclosure will be specifically described below with reference to the drawings. The above description can be applied to the examples described below. Furthermore, the examples described below can be modified based on the above description. In addition, the matters described below may be applied to the embodiments described above. Furthermore, in the embodiments described below, matters that are not essential to the laminated structure and manufacturing method relating to this disclosure may be omitted. Note that the following figures are schematic and may differ from the actual configuration. In the following figures, only the surface portion of the substrate may be shown. Semiconductor elements are formed inside the actual substrate. A native oxide layer is formed on the surface of the metal electrode, but since it is a very thin layer, it is omitted from the following figures.

[0045] (Embodiment 1) Embodiment 1 describes an example of a manufacturing method (M) and an example of a laminated structure. First, a first substrate 10 and a second substrate 20 are prepared. A part of the first substrate 10 is shown in Figure 1(a). The first substrate 10 includes a first base substrate (not shown), a first insulating layer 11 laminated on one surface of the first base substrate, and a plurality of first metal electrodes 12. The first insulating layer 11 and the plurality of first metal electrodes 12 are exposed at the bonding surface 10a of the first substrate 10.

[0046] Next, a portion of the first insulating layer 11 of the first substrate 10 adjacent to the first metal electrode 12 is removed. An example of a method for removing a portion of the first insulating layer 11 adjacent to the first metal electrode 12 by chemical mechanical polishing is described below. Figure 2 shows a side view of an example of a chemical mechanical polishing apparatus. The apparatus 300 in Figure 2 includes a rotating stage 301, a polishing pad 302, a substrate holding head 303, a conditioner 304, and a slurry supply unit 305. The polishing pad 302 is fixed on the rotating stage 301 and rotates with the rotating stage 301. The substrate (first substrate 10 in Figure 3) is fixed to the substrate holding head 303. The substrate holding head 303 rotates while applying pressure to the substrate toward the polishing pad 302. That is, the substrate is pressed against the polishing pad 302 by the substrate holding head 303 at a predetermined pressure. The conditioner 304 is a component for refreshing the surface of the polishing pad 302. The slurry supply unit 305 supplies a slurry containing abrasive material onto the polishing pad 302. By rotating the polishing pad 302 and the substrate and pressing the substrate against the polishing pad, the surface of the substrate is flattened.

[0047] In one example of a method using chemical mechanical polishing, first, the bonding surface 10a (first insulating layer 11 and first metal electrode 12) of the first substrate 10 is chemically polished. At this time, as shown in Figure 3(a), chemical mechanical polishing is performed while applying pressure to the substrate holding head 303 with a first pressure so that the surface of the first insulating layer 11 and the surface of the first metal electrode 12 are flattened. That is, the first substrate 10 is pressed against the polishing pad with a first pressure to chemically polish the first metal electrode 12 and the first insulating layer 11.

[0048] It is preferable that the heights of the multiple first metal electrodes 12 are the same. However, in actual polishing, it is difficult to make their heights the same. Therefore, the heights of the multiple first metal electrodes 12 are not constant. Also, the surface of the first insulating layer 11 and the surface of the first metal electrodes 12 are not at exactly the same height.

[0049] Next, the substrate holding head 303 is pressurized with a second pressure higher than the first pressure to chemically mechanically polish the bonding surface 10a (the first insulating layer 11 and the first metal electrode 12). That is, the first substrate 10 is pressed against the polishing pad with the second pressure to chemically mechanically polish the first metal electrode 12 and the first insulating layer 11. As a result, as shown in Figure 3(b), the adjacent portion A1 of the first insulating layer 11 (the adjacent portion A1 adjacent to the first metal electrode 12) is chamfered. In this way, a part of the adjacent portion A1 is removed, and as a result, a recess 11c is formed in the adjacent portion A1. Note that a part of the adjacent portion A2 of the second insulating layer 21 of the second substrate 20 can also be removed by the method described above.

[0050] Next, as shown in Figure 1(b), the first substrate 10 (the first substrate 10 in Figure 3(b)) and the second substrate 20 are bonded together so that the first insulating layer 11 and the second insulating layer 21 are in contact. With the first insulating layer 11 and the second insulating layer 21 in contact, the second substrate 20 is pressed toward the first substrate 10, thereby bonding the first insulating layer 11 and the second insulating layer 21 together.

[0051] The second substrate 20 includes a second base substrate (not shown), a second insulating layer 21 laminated on one surface of the second base substrate, and a plurality of second metal electrodes 22. The second insulating layer 21 and the plurality of second metal electrodes 22 are exposed at the junction surface of the second substrate 20. The surface of the second insulating layer 21 and the surface of the second metal electrodes 22 are at approximately the same height, but their heights vary. As shown in Figure 1(b), a gap 100s exists between the first insulating layer 11 (more specifically, the adjacent portion A1 of the first insulating layer 11) and the second insulating layer 21.

[0052] In one example shown in Figure 1(b), the adjacent portion of the second insulating layer 21 of the second substrate 20 (adjacent portion A2 adjacent to the second metal electrode 22) is also chamfered. As described above, the second substrate 20 may be an unseparated semiconductor chip, or it may include a semiconductor wafer.

[0053] Next, the first metal electrode 12 and the second metal electrode 22 are joined together by heating the first substrate 10 and the second substrate 20 while they are bonded together. In this way, a laminated structure 100 is obtained in which the insulating layers and metal electrodes are joined together, as shown in Figure 1(c). The obtained laminated structure 100 may be divided as needed. As described above, in manufacturing method (M), even if the surface of the metal electrode is higher than expected, the excess metal electrode fills the gap 100s, which can alleviate the stress generated between the first metal electrode 12 and the second metal electrode 22 (the stress that separates the first substrate 10 and the second substrate 20). Therefore, according to manufacturing method (M), a laminated structure in which the metal electrodes are stably joined together can be obtained.

[0054] An example of removing a portion of the adjacent portion A1 by forming a resist mask and etching is shown in Figures 4(a) and 4(b). First, as shown in Figure 4(a), a resist mask 201 is formed on the first insulating layer 11 and the first metal electrode 12. The resist mask 201 has an opening 201a above the adjacent portion A1. Next, as shown in Figure 4(b), at least a portion of the first insulating layer 11 exposed at the opening 201a is removed. This forms a recess 11c in the adjacent portion A1 of the first insulating layer 11. After removing a portion of the adjacent portion A1 of the first insulating layer 11, the resist mask 201 is removed.

[0055] Figure 5 shows a partial example of a laminated structure manufactured by the above manufacturing method. The laminated structure 100 in Figure 5 includes a first substrate 10 and a second substrate 20. The first substrate 10 includes a first insulating layer 11, a first metal electrode 12, a first base substrate 13, and an internal electrode 14. The second substrate 20 includes a second insulating layer 21, a second metal electrode 22, a second base substrate 23, and an internal electrode 24. At least one of the first substrate 10 and the second substrate 20 includes a semiconductor element (not shown). The first insulating layer 11 and the second insulating layer 21 are joined together. The first metal electrode 12 and the second metal electrode 22 are joined together.

[0056] An example of the manufacturing process flow for producing a stacked structure (S) will be explained with reference to Figure 6. Figure 6 shows an example of an embodiment in which a fragmented semiconductor chip is used as the second substrate. However, an unfragmented first substrate and an unfragmented second substrate may be bonded together. Alternatively, a fragmented semiconductor chip may be used as the first substrate, and a substrate containing a semiconductor wafer may be used as the second substrate. In that case, the fragmented first substrate is bonded to the second substrate placed on the substrate stage.

[0057] First, prepare the first substrate and the second substrate (more precisely, the substrate that will become the second substrate). Next, as described above, remove at least a portion of the adjacent portion A1 of the first insulating layer and at least a portion of the adjacent portion A2 of the second insulating layer. Note that only at least a portion of the adjacent portion A1 may be removed.

[0058] Next, the bonding surfaces of the first substrate and the second substrate are treated to make them hydrophilic. Next, the second substrate is separated into individual pieces. Next, the bonding surfaces of the first substrate and the second substrate are brought into contact and the first insulating layer and the second insulating layer are bonded (temporary bonding step). Next, the first metal electrode and the second metal electrode are bonded (final bonding step). In this way, a laminated structure is obtained.

[0059] Examples of the temporary bonding process and the permanent bonding process are shown in Figures 7 and 8. In the temporary bonding process, as shown in Figure 7, a plurality of individualized second substrates 20 are sequentially placed at predetermined positions on the first substrate 10, which is placed on the substrate stage 401. Specifically, the second substrates 20 are attracted to the bonding head 402, transported, and pressed onto the predetermined positions on the first substrate 10. Temporary bonding is performed by this pressing. This transport and alignment can be carried out by known methods. For example, alignment can be performed using an alignment optical unit 403. Note that the parts shown in Figures 1(b), 1(c), and 5 are part of region A in Figure 7.

[0060] Next, as shown in Figure 8, the first substrate 10, to which multiple second substrates 20 are temporarily bonded, is heated in a heating chamber 410. This heating bonds the first metal electrode and the second metal electrode (main bonding step). In this way, a laminated structure (S) is obtained. The obtained laminated structure (S) is divided as needed.

[0061] (Note) The following technologies are disclosed based on the above description. (Technology 1) A method for manufacturing a laminated structure, Step (i) of preparing a first substrate including a first insulating layer and a first metal electrode arranged on one main surface, and a second substrate including a second insulating layer and a second metal electrode arranged on one main surface, (ii) A step of forming a recess in the adjacent portion of the first insulating layer by removing at least a portion of the adjacent portion of the first insulating layer adjacent to the first metal electrode, (iii) A step of bonding the first substrate and the second substrate together such that the first insulating layer and the second insulating layer are in contact, The process includes (iv) a step of bonding the first metal electrode and the second metal electrode while the first substrate and the second substrate are bonded together, A method for manufacturing a stacked structure, wherein at least one of the first substrate and the second substrate includes a semiconductor element. (Technology 2) The manufacturing method according to Art 1, wherein step (ii) includes polishing the first metal electrode and the first insulating layer by a chemical mechanical polishing method so that the adjacent portions of the first insulating layer are chamfered. (Technology 3) The above step (ii) is, A step (iia) of chemically mechanically polishing the first metal electrode and the first insulating layer by pressing the first substrate against a polishing pad with a first pressure such that the surface of the first metal electrode and the surface of the first insulating layer are flattened, The manufacturing method according to Art 2, comprising the step (iib) of chamfering the adjacent portions of the first insulating layer by chemically mechanically polishing the first metal electrode and the first insulating layer by pressing the first substrate against the polishing pad at a second pressure higher than the first pressure. (Technology 4) The above step (ii) is, (iiA) A step of forming a resist mask having an opening in the adjacent portion of the first insulating layer on the first insulating layer and the first metal electrode, The manufacturing method according to Technical Reference 2, comprising the step (iiB) of forming the recess in the adjacent portion of the first insulating layer by removing at least a portion of the adjacent portion exposed in the opening. (Technology 5) The manufacturing method according to any one of the technologies 1 to 4, further comprising step (ii) of forming a recess in the adjacent portion of the second insulating layer by removing at least a portion of the adjacent portion of the second insulating layer adjacent to the second metal electrode. (Technology 6) A manufacturing method according to any one of the technologies 1 to 5, wherein one of the first substrate and the second substrate comprises a semiconductor wafer, and the other of the first substrate and the second substrate comprises a flaked semiconductor chip. (Technology 7) A manufacturing method according to any one of the technologies 1 to 6, wherein the first metal electrode and the second metal electrode are each made of copper or a copper alloy. (Technology 8) A laminated structure, A first substrate including a first insulating layer and a first metal electrode arranged on one main surface, It includes a second substrate having a second insulating layer and a second metal electrode arranged on one main surface, At least one of the first substrate and the second substrate includes a semiconductor element. At least a portion of the first insulating layer and at least a portion of the second insulating layer are in close contact. The portion of the first insulating layer adjacent to the first metal electrode is thinner than the portion other than the adjacent portion. There is a gap between the adjacent portion and the second insulating layer. A laminated structure in which at least one of the first metal electrode and the second metal electrode is inserted into the void. (Technology 9) The laminated structure according to Art 8, wherein the surface of the adjacent portion of the second insulating layer adjacent to the second metal electrode is lower than the surface of the portion of the second insulating layer other than the adjacent portion. (Technology 10) The stacked structure according to Art 8 or 9, wherein one of the first substrate and the second substrate comprises a semiconductor wafer, and the other of the first substrate and the second substrate comprises a flaked semiconductor chip. [Industrial applicability]

[0062] This disclosure can be used for multilayer structures (such as semiconductor devices or semiconductor device precursors) and methods for manufacturing multilayer structures. [Explanation of symbols]

[0063] 10: First board 11: First insulating layer 11c: recess 12:First metal electrode 13: First base board 20: Second board 21: Second insulating layer 22:Second metal electrode 23: Second base board 100: Laminated structure 201: Resist Mask 201a: Opening 302: Polishing pad

Claims

1. A method for manufacturing a laminated structure, Step (i) of preparing a first substrate including a first insulating layer and a first metal electrode arranged on one main surface, and a second substrate including a second insulating layer and a second metal electrode arranged on one main surface, (ii) A step of forming a recess in the adjacent portion of the first insulating layer by removing at least a portion of the adjacent portion of the first insulating layer adjacent to the first metal electrode, (iii) A step of bonding the first substrate and the second substrate together such that the first insulating layer and the second insulating layer are in contact, The process includes (iv) a step of bonding the first metal electrode and the second metal electrode while the first substrate and the second substrate are bonded together, A method for manufacturing a stacked structure, wherein at least one of the first substrate and the second substrate includes a semiconductor element.

2. The manufacturing method according to claim 1, wherein step (ii) includes polishing the first metal electrode and the first insulating layer by a chemical mechanical polishing method so that the adjacent portions of the first insulating layer are chamfered.

3. The above step (ii) is, (iia) A step of chemically mechanically polishing the first metal electrode and the first insulating layer by pressing the first substrate against a polishing pad with a first pressure such that the surface of the first metal electrode and the surface of the first insulating layer are flattened, The manufacturing method according to claim 2, comprising the step (iib) of chamfering the adjacent portions of the first insulating layer by chemically and mechanically polishing the first metal electrode and the first insulating layer by pressing the first substrate against the polishing pad at a second pressure higher than the first pressure.

4. The above step (ii) is, (iiA) A step of forming a resist mask having an opening in the adjacent portion of the first insulating layer on the first insulating layer and the first metal electrode, The manufacturing method according to claim 2, further comprising the step (iiB) of forming the recess in the adjacent portion of the first insulating layer by removing at least a portion of the adjacent portion exposed in the opening.

5. The manufacturing method according to any one of claims 1 to 4, wherein step (ii) further comprises the step of forming a recess in the adjacent portion of the second insulating layer by removing at least a portion of the adjacent portion of the second insulating layer adjacent to the second metal electrode.

6. The manufacturing method according to any one of claims 1 to 4, wherein one of the first substrate and the second substrate includes a semiconductor wafer, and the other of the first substrate and the second substrate is a flammable semiconductor chip.

7. The manufacturing method according to any one of claims 1 to 4, wherein the first metal electrode and the second metal electrode are each made of copper or a copper alloy.

8. A laminated structure, A first substrate including a first insulating layer and a first metal electrode arranged on one main surface, It includes a second substrate having a second insulating layer and a second metal electrode arranged on one main surface, At least one of the first substrate and the second substrate includes a semiconductor element. At least a portion of the first insulating layer and at least a portion of the second insulating layer are in close contact. The portion of the first insulating layer adjacent to the first metal electrode is thinner than the portion other than the adjacent portion. There is a gap between the adjacent portion and the second insulating layer. A laminated structure in which at least one part of the first metal electrode and the second metal electrode is inserted into the void.

9. The laminated structure according to claim 8, wherein the surface of the adjacent portion of the second insulating layer adjacent to the second metal electrode is lower than the surface of the portion of the second insulating layer other than the adjacent portion.

10. The laminated structure according to claim 8 or 9, wherein one of the first substrate and the second substrate includes a semiconductor wafer, and the other of the first substrate and the second substrate is a flammable semiconductor chip.

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