Signal processing circuit and semiconductor device

Abstract

This provides a signal processing circuit that can prevent malfunctions even when the external power supply is degraded. [Solution] The signal processing circuit includes a power supply circuit that generates a second power supply voltage in a capacitor based on a first power supply voltage applied to a power supply line, a discharge circuit that discharges the capacitor when the first power supply voltage falls below a predetermined voltage level, a first detection circuit that operates based on the second power supply voltage and detects the falling edge of an input signal input via a signal line, and a first diode having an anode connected to the signal line and a cathode connected to the power supply line.

Description

Technical Field

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[0001] The present invention relates to a signal processing circuit and a semiconductor device.

Background Art

[0002] For example, some integrated circuits include a power supply circuit that generates an internal power supply from an external power supply of the integrated circuit, and a signal processing circuit that operates based on the internal power supply (for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

[0007] The semiconductor device of the present invention, which solves the aforementioned problems, is a semiconductor device comprising: a first switching element on the power supply side; a second switching element on the ground side that drives a load together with the first switching element; and a switching control circuit that controls the switching of the first and second switching elements, wherein the switching control circuit comprises: a power supply circuit that generates a second power supply voltage in a capacitor based on a first power supply voltage applied to a power supply line; a discharge circuit that discharges the capacitor when the first power supply voltage falls below a predetermined voltage level; a first detection circuit that operates based on the second power supply voltage and detects the falling edge of an input signal input via a signal line; a second detection circuit that operates based on the second power supply voltage and detects the rising edge of the input signal input via the signal line; a first drive circuit that drives the first switching element based on the first detection result of the first detection circuit and the second detection result of the second detection circuit; a second drive circuit that drives the second switching element based on the input signal; and a first diode having an anode connected to the signal line and a cathode connected to the power supply line. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a signal processing circuit that can prevent malfunctions even when the external power supply is degraded. [Brief explanation of the drawing]

[0009] [Figure 1]This figure shows an example of a power module 10. [Figure 2] This figure shows an example of the configuration of the power supply circuit 40. [Figure 3] This figure shows an example of the configuration of the pulse generation circuit 48. [Figure 4] This figure shows an example of the configuration of the pulse generation circuit 49. [Figure 5] This figure shows an example of a typical switching control IC500 configuration. [Figure 6] This figure shows an example of the operation of a typical switching control IC500. [Figure 7] This figure shows an example of the operation of the switching control IC20. [Modes for carrying out the invention]

[0010] The following matters become clear from this specification and the accompanying drawings:

[0011] =====Execution===== Figure 1 shows the configuration of a power module 10, which is one embodiment of the present invention. The power module 10 is a semiconductor device for driving a load 11 based on instructions from a microcontroller (not shown), and comprises a switching control IC (Integrated Circuit) 20, a half-bridge circuit 21, and a capacitor 22.

[0012] The switching control IC 20 is a high-voltage integrated circuit (HVIC) that controls the operation of the half-bridge circuit 21 based on the input signal Sin from the microcontroller (not shown). Details of the switching control IC 20 will be described later, but the switching control IC 20 has terminals VCC, IN, GND, B, S, HO, and LO.

[0013] The half-bridge circuit 21 is, for example, a circuit that drives the motor coil of an air conditioner which is the load 11, and includes an IGBT (Insulated Gate Bipolar Transistor) 30 and an IGBT 31.

[0014] The IGBT 30 is a switching element on the high side (power supply side). Its gate electrode is connected to the terminal HO, and its emitter electrode is connected to the terminal S. Also, a predetermined voltage Vdc (for example, "400V") is applied to the collector electrode of the IGBT 30.

[0015] The IGBT 31 is a switching element on the low side (ground side). Its gate electrode is connected to the terminal LO, and its collector electrode is connected to the terminal S. Also, the emitter electrode of the IGBT 31 is grounded.

[0016] In this embodiment, IGBTs are used as the switching elements. However, for example, MOS transistors or bipolar transistors may also be used. Also, the IGBT 30 corresponds to the "first switching element", and the IGBT 31 corresponds to the "second switching element".

[0017] One end of the capacitor 22 is connected to the terminal B, and the other end is connected to the terminal S. The capacitor 22 is charged when the bootstrap voltage Vb from a charge pump circuit 43 described later is applied to the terminal B. As a result, the bootstrap voltage Vb occurs across both ends of the capacitor 22. Note that the bootstrap voltage Vb is the voltage used to turn on the high-side IGBT 30.

[0018] For example, when the voltage Vs of terminal S is "0V", if the voltage of the gate electrode of IGBT30 becomes higher than the threshold voltage of IGBT30, IGBT30 turns on. However, when IGBT30 turns on, the voltage Vs of terminal S approaches the voltage Vdc (for example, "400V"). Therefore, in order to keep IGBT30 on, it is necessary to drive IGBT30 based on the voltage Vs of terminal S to which the emitter electrode of IGBT30 is connected.

[0019] In this embodiment, a voltage that is higher than the voltage Vs by the boost voltage Vb is generated at terminal B with respect to the voltage Vs of terminal S. Therefore, although details will be described later, the switching control IC20 can turn on IGBT30 by using the boost voltage Vb. Note that the power module 10 corresponds to a "semiconductor device".

[0020] <<<Configuration of Switching Control IC20>>> The switching control IC20 includes a power supply circuit 40, a capacitor 41, diodes 42, 45, 46, a charge pump circuit 43, a resistor 44, a comparator 47, pulse generation circuits 48, 49, and drive circuits 50, 51. Note that the switching control IC20 corresponds to a "signal processing circuit" and a "switching control circuit".

[0021] Based on the power supply voltage Vcc (for example, "20V") applied to the power supply line L1 connected to terminal VCC, the power supply circuit 40 generates the power supply voltage Vreg used inside the switching control IC20 in the capacitor 41 (described later). Although details will be described later, the power supply circuit 40 of this embodiment is configured to be able to generate a stable power supply voltage Vreg even when IGBT31 is on. Note that the power supply voltage Vcc corresponds to a "first power supply voltage", and the power supply voltage Vreg corresponds to a "second power supply voltage".

[0022] <<<An Example of Power Supply Circuit 40>>> Figure 2 shows an example of the configuration of the power supply circuit 40. The power supply circuit 40 is a circuit that generates a temperature-compensated power supply voltage Vreg (e.g., "5V") based on the power supply voltage Vcc. The power supply circuit 40 is composed of a bias circuit 100 and an output circuit 101.

[0023] The bias circuit 100 is a circuit that generates a bias voltage V3 for operating Darlington-connected transistors (described later). The bias circuit 100 is composed of voltage generation circuits 110 and 111.

[0024] The voltage generation circuit 110 is a circuit that generates a voltage V1 of a predetermined level, and is composed of a resistor 120, five diodes D1 to D5, and a Zener diode 121.

[0025] Resistor 120, diodes D1 to D5, and Zener diode 121 are each connected in series. Therefore, when power supply Vcc is applied to one end of resistor 120, the voltage V1 at the node where the other end of resistor 120 and the anode of diode D1 are connected is expressed by the following equation (1).

[0026] V1 = Vz + 5 × Vf ... (1) Here, "Vz" is the breakdown voltage of Zener diode 121, and "Vf" is the forward voltage of diodes D1 to D5.

[0027] The voltage generation circuit 111 is a circuit that generates a bias voltage V3 based on a voltage V1, and consists of an NPN transistor 130, resistors 131 and 132, and three diodes D6 to D8.

[0028] A voltage V1 is applied to the base electrode of the NPN transistor 130, and diodes D6 to D8 are connected to the emitter electrode via resistors 131 and 132. Therefore, a voltage V2, as shown in equation (2) below, is output from the emitter electrode of the NPN transistor 130.

[0029] V2=V1-Vbe=Vz+5×Vf-Vbe...(2) Here, "Vbe" is the base-emitter voltage of the NPN transistor 130. In the voltage generation circuit 111, the voltage difference between the forward voltages "3 × Vf" of the three diodes D6 to D8 and voltage V2 is divided by a voltage divider circuit composed of resistors 131 and 132. Therefore, the bias voltage V3 from the node to which resistors 131 and 132 are connected is expressed by the following equation (3).

[0030] V3=3×Vf+(V2-3×Vf)×(R2 / (R1+R2)) =3×Vf+(Vz+2×Vf-Vbe)×(R2 / (R1+R2))...(3) Here, "R1" is the resistance value of resistor 131, and "R2" is the resistance value of resistor 132.

[0031] The output circuit 101 is a circuit that outputs a predetermined power supply voltage Vreg based on a bias voltage V3, and is composed of a voltage-resistant circuit 140, NPN transistors 141 and 142, and a resistor 143.

[0032] The voltage-resistant circuit 140 is a circuit for protecting the NPN transistors 141 and 142 from overvoltage and includes four diodes D9 to D12 connected in series.

[0033] The emitter electrode of NPN transistor 141 is connected to the base electrode of NPN transistor 142, and the collector electrode of NPN transistor 141 is connected to the collector electrode of NPN transistor 142. Therefore, since the NPN transistors 141 and 142 in this embodiment are connected in a Darlington configuration, they can drive larger loads.

[0034] Furthermore, as described above, since a voltage V3 is applied to the base electrode of the first-stage NPN transistor 141, the power supply voltage Vreg shown in equation (4) below is output from the emitter electrode of the NPN transistor 142.

[0035] Vreg = V3 - 2 × Vbe =(3×Vf+(Vz+2×Vf-Vbe)×(R2 / (R1+R2))-2×Vbe...(4) Resistor 143 is an element for continuously generating the power supply voltage Vreg. Specifically, if resistor 143 is not provided, when the load state of the power supply circuit 40 becomes unloaded, the current flowing through NPN transistors 141 and 142 becomes zero. As a result, the generation of the power supply voltage Vreg stops.

[0036] In such cases, when current flows to the load of the power supply circuit 40, it takes time for the power supply circuit 40 to generate the power supply voltage Vreg.

[0037] In this embodiment, current continues to flow through the resistor 143 even when the power supply circuit 40 is unloaded. Therefore, the power supply circuit 40 can steadily generate a predetermined power supply voltage Vreg regardless of the load state of the power supply circuit 40.

[0038] Furthermore, the temperature coefficient of the breakdown voltage "Vz" of Zener diode 121 is positive, while the temperature coefficient of the forward voltage "Vf" of diodes D1 to D12 is negative. Also, the temperature coefficient of the base-emitter voltage "Vbe" is negative.

[0039] Furthermore, in this embodiment, resistors 131 and 132 are of the same type (e.g., polysilicon) with equal temperature coefficients. Therefore, the temperature coefficient of the “R2 / (R1+R2)” term in equation (4) can be almost ignored.

[0040] In this embodiment, the number of diodes D1 to D12 is adjusted based on equation (4) so ​​that the power supply voltage Vreg is temperature-compensated. As a result, the level of the power supply voltage Vreg remains constant regardless of temperature. In addition, in this embodiment, the power supply voltage Vreg can be set to a desired level by changing the resistance ratio of resistors 131 and 132.

[0041] Thus, the power supply circuit 40 has high output current capability because it includes Darlington-connected NPN transistors 141 and 142. In addition, the power supply circuit 40 can output a temperature-compensated predetermined level of power supply voltage Vreg (e.g., "5V").

[0042] The capacitor 41 in Figure 1 is an element for stabilizing the power supply voltage Vreg. The power supply voltage Vreg is applied to one end, and the other end is grounded.

[0043] Diode 42, as will be described in detail later, turns on when the power supply voltage Vcc falls below a predetermined voltage level (for example, the charging voltage of capacitor 41) and discharges capacitor 41. The anode of diode 42 is connected to capacitor 41, and the cathode is connected to the power supply line L1. Note that diode 42 corresponds to the "discharge circuit" and the "second diode".

[0044] The charge pump circuit 43 generates a bootstrap voltage Vb to charge the capacitor 22, for example, based on the power supply voltage Vcc.

[0045] Resistor 44 is an element that limits the current flowing through diodes 45 and 46 (described later), and is placed between the signal line L2 connected to terminal IN and the non-inverting input of comparator 47 (described later).

[0046] Diodes 45 and 46 are elements that protect the integrated circuit from static electricity input from terminal IN. Diode 45 turns on, for example, when a positive static voltage higher than the power supply voltage Vcc is input from terminal IN, raising the voltage level of signal Sina to a level higher than the power supply voltage Vcc by the forward voltage of diode 45. On the other hand, diode 46 turns on, for example, when a negative static voltage lower than the ground voltage is input from terminal IN, lowering the voltage level of signal Sina to a level lower than the ground voltage by the forward voltage of diode 46.

[0047] Diode 45 has its anode connected to the non-inverting input of comparator 47 (described later) and resistor 44, and its cathode connected to power line L1. Diode 46 has its anode grounded and its cathode connected to the non-inverting input of comparator 47 (described later) and resistor 44. Diode 45 corresponds to the "first diode," and diode 46 corresponds to the "third diode."

[0048] Comparator 47 is a circuit that detects the level of the input signal Sin input via signal line L2 and outputs a signal S0 with the same logic level as the input signal Sin. Specifically, when the input signal Sin is at a high level (hereinafter referred to as "H" level), comparator 47 outputs a "H" level signal S0, and when the input signal Sin is at a low level (hereinafter referred to as "L" level), comparator 47 outputs a "L" level signal S0. In addition, the non-inverting input of comparator 47 is input to a signal Sina based on the input signal Sin, and the inverting input is applied to a reference voltage Vref. Comparator 47 operates based on the power supply voltage Vreg.

[0049] The pulse generation circuit 48 outputs a pulse signal to control the switching of the IGBT 30 based on the signal S0. Specifically, the pulse generation circuit 48 detects the rising edge of the input signal Sin based on the signal S0 and outputs a set pulse signal S1 to turn on the high-side IGBT 30. The pulse generation circuit 48 operates based on the power supply voltage Vreg.

[0050] As shown in Figure 3, the pulse generation circuit 48 is composed of an SR flip-flop 200, inverter circuits 201 and 202, a PMOS transistor 203, a current source 204, a capacitor 205, and an NMOS transistor 206.

[0051] The SR flip-flop 200 is a circuit that generates a set pulse S1. When a high-level signal S0 is input to the set input, it sets the Q output to a high level. It then outputs the high-level set pulse signal S1 via inverter circuits 201 and 202.

[0052] In this case, the Q-bar output of the SR flip-flop 200 becomes "L" level, so the PMOS transistor 203 is turned on. Then, the capacitor 205 is charged by the current from the current source 204.

[0053] When the charging voltage of capacitor 205 exceeds the threshold voltage of the reset input of SR flip-flop 200, SR flip-flop 200 sets its Q output to "L" level. Then, it outputs a "L" level set pulse signal S1 via inverter circuits 201 and 202.

[0054] In this case, the Q-bar output of the SR flip-flop 200 becomes "H" level, so the PMOS transistor 203 is turned off. On the other hand, the NMOS transistor 206 is turned on, so the capacitor 205 is discharged. In this way, when the pulse generation circuit 48 receives an "H" level signal S0, it outputs a set pulse signal S1 with a predetermined pulse width. The SR flip-flop 200, inverter circuits 201 and 202, and current source 204 operate based on the power supply voltage Vreg. The pulse generation circuit 48 corresponds to the "second detection circuit," and the set pulse signal S1 corresponds to the "second detection result."

[0055] The pulse generation circuit 49 outputs a pulse signal to control the switching of the IGBT 30 based on signal S0. Specifically, the pulse generation circuit 49 detects the falling edge of the input signal Sin based on signal S0 and outputs a reset pulse signal S2 to turn off the high-side IGBT 30. The pulse generation circuit 49 operates based on the power supply voltage Vreg.

[0056] As shown in Figure 4, the pulse generation circuit 49 is composed of an SR flip-flop 200, inverter circuits 201, 202, 207, a PMOS transistor 203, a current source 204, a capacitor 205, and an NMOS transistor 206.

[0057] The pulse generation circuit 49 has the same configuration as the pulse generation circuit 48, except for the inverter circuit 207. Therefore, when the pulse generation circuit 49 receives an "L" level signal S0, it outputs a reset pulse signal S2 with a predetermined pulse width. The inverter circuit 207 operates based on the power supply voltage Vreg. In this embodiment, the set pulse signal S1 and the reset pulse signal S2 are pulse signals whose amplitude level changes from 0V to the level of the power supply voltage Vreg (for example, 5V). The pulse generation circuit 49 corresponds to the "first detection circuit," and the reset pulse signal S2 corresponds to the "first detection result."

[0058] The drive circuit 50 is a circuit that drives the low-side IGBT 31 based on the control signal S0. Specifically, the drive circuit 50 outputs an "H" level drive signal Vdr1 to the gate electrode of the IGBT 31 via terminal LO based on the "L" level control signal S0. As a result, the IGBT 31 turns on. On the other hand, the drive circuit 50 also outputs an "L" level drive signal Vdr1 to the gate electrode of the IGBT 31 via terminal LO based on the "H" level control signal S0. As a result, the IGBT 31 turns off. The drive circuit 50 operates based on the power supply voltage Vcc. The drive circuit 50 also corresponds to the "second drive circuit".

[0059] The drive circuit 51 is a circuit that turns on the high-side IGBT 30 based on the set pulse signal S1 and turns off the IGBT 30 based on the reset pulse signal S2. Specifically, when the set pulse signal S1 is input to the drive circuit 51, it outputs a drive signal Vdr2 of the "H" level to the gate electrode of the IGBT 30 via terminal HO. On the other hand, when the reset pulse signal S2 is input to the drive circuit 51, it outputs a drive signal Vdr2 of the "L" level to the gate electrode of the IGBT 30 via terminal HO.

[0060] Here, the drive signal Vdr2 is a signal whose logic level changes with respect to the voltage Vs at terminal S. Therefore, the IGBT 30 turns on based on the "H" level drive signal Vdr2 and turns off based on the "L" level drive signal Vdr2. Note that the drive circuit 51 corresponds to the "first drive circuit".

[0061] <<<General Configuration and Operation of Switching Control IC500>>> Figure 5 shows an example of the configuration of a typical switching control IC 500, and Figure 6 is a diagram illustrating the operation of the switching control IC 500. Here, as shown in Figure 5, the switching control IC 500 is included in the power module 400 and is a switching control IC that is the same as the switching control IC 20 but without the diode 42.

[0062] First, when the input signal Sin reaches a high level at time t0, the signal Sina also reaches a high level, and the comparator 47 in Figure 1 outputs a high-level signal S0. Furthermore, when the control signal S0 reaches a high level, the pulse generation circuit 48 outputs a high-level set pulse signal S1. As a result, the high-side drive circuit 51 outputs a high-level drive signal Vdr2.

[0063] Then, the low-side drive circuit 50 sets the drive signal Vdr1 to the "L" level based on the "H" level control signal S0. As a result, IGBT 30 turns on and IGBT 31 turns off.

[0064] Furthermore, when the input signal Sin becomes "L" level at time t1, the signal Sina also becomes "L" level, and the comparator 47 outputs a "L" level signal S0. Also, when the control signal S0 becomes "L" level, the pulse generation circuit 49 outputs a "H" level reset pulse signal S2. As a result, the drive circuit 51 outputs a "L" level drive signal Vdr2.

[0065] Then, the drive circuit 50 sets the drive signal Vdr1 to an "H" level based on the "L" level control signal S0. As a result, IGBT 30 is turned off and IGBT 31 is turned on.

[0066] Furthermore, when the input signal Sin reaches a "H" level at time t2, the switching control IC 500 operates in the same way as at time t0.

[0067] Furthermore, as the power supply voltage Vcc decreases at time t3, the power supply voltage Vreg also begins to decrease. As the power supply voltage Vcc decreases, the voltage at the connection point of diodes 45 and 46 in Figure 1 discharges towards the power supply voltage Vcc through diode 45, causing the signal Sina to decrease. Also, as the power supply voltage Vreg decreases, the level of the signal S0 output by comparator 47 also begins to decrease.

[0068] Furthermore, if the voltage level of the power supply voltage Vcc falls below a predetermined level at time t4 (for example, to 0V), the signal Sina will be lower than the reference voltage Vref, and the comparator 47 will output a "L" level signal S0.

[0069] Furthermore, in this case, the capacitor 41 in Figure 5 is not discharged. Therefore, as the signal S0 falls, the pulse generation circuit 49 attempts to output a high-level signal S2 because the inverter circuit 207 outputs a high-level signal and the SR flip-flop sets its Q output to high level. However, since the power supply voltage Vreg is, for example, below 5V, the reset pulse signal S2 is not recognized by the drive circuit 51. Therefore, the drive circuit 51 continues to output a high-level drive signal Vdr2.

[0070] Then, as the power supply voltage Vcc begins to recover at time t5, when the power supply voltage Vreg becomes, for example, 5V, the pulse generation circuit 49 outputs a reset pulse S2 corresponding to the voltage level of the power supply voltage Vreg in response to the recovery of the power supply voltage Vreg.

[0071] As a result, the drive circuit 51 recognizes the reset pulse signal S2 and outputs a drive signal Vdr2 at the "L" level. Therefore, although the drive circuit 51 should output a drive signal Vdr2 at the "H" level because a "H" level signal Sin is input, a malfunction occurs where it outputs a drive signal Vdr2 at the "L" level due to the drop in the power supply voltage Vcc.

[0072] Subsequently, when the power supply voltage Vcc is restored at time t6, the signal Sina changes along with the change in the voltage level of the power supply voltage Vcc and becomes higher than the reference voltage Vref, so the comparator 47 outputs a "H" level signal S0. Then, the pulse generation circuit 48 detects the rising edge of signal S0 and outputs a "H" level set pulse signal S1. In addition, the drive circuit 51 outputs a "H" level drive signal Vdr2 based on the "H" level set pulse signal S1.

[0073] Furthermore, when an "L" level signal Sin is input at time t7, the switching control IC 500 operates in the same way as at time t1. This operation is repeated thereafter. Note that even if an "L" level signal S0 is input during a period when the power supply voltage Vcc is low, the drive circuit 50 will not turn on the IGBT 31 because the power supply voltage Vcc is low.

[0074] <<<Operation of Switching Control IC20>>> Figure 7 is a diagram illustrating the operation of the switching control IC 20. Note that the operations at times t10-t13 and t17 are the same as those at times t0-t3 and t7 in Figure 6, so their explanation is omitted.

[0075] Furthermore, if the power supply voltage Vcc level falls below a predetermined level at time t14 (for example, to 0V), the signal Sina will be lower than the reference voltage Vref, similar to time t4 in Figure 6, and the comparator 47 will output a "L" level signal S0.

[0076] Furthermore, at this time, the capacitor 41 in Figure 1 is discharged to the power supply voltage Vcc (for example, 0V) by the diode 42, and the power supply voltage Vreg is, for example, 0V. Therefore, even if the signal S0 falls, the inverter circuit 202 outputs a "L" level signal. Consequently, the pulse generation circuit 49 cannot output a "H" level signal S2. As a result, the drive circuit 51 continues to output a "H" level drive signal Vdr2.

[0077] Then, as the power supply voltage Vcc begins to recover at time t15, even if the power supply voltage Vreg becomes, for example, 5V, the inverter circuit 207 in Figure 4 does not output a "H" level signal, and therefore the SR flip-flop does not set its Q output to "H" level. Consequently, as the power supply voltage Vreg recovers, the pulse generation circuit 49 does not output a reset pulse S2 corresponding to the voltage level of the power supply voltage Vreg.

[0078] Subsequently, when the power supply voltage Vcc is restored at time t16, the signal Sina changes along with the change in the voltage level of the power supply voltage Vcc and becomes higher than the reference voltage Vref, so the comparator 47 outputs a "H" level signal S0. The pulse generation circuit 48 then detects the rising edge of signal S0 and outputs a "H" level set pulse signal S1. On the other hand, the drive circuit 51 continues to output a "H" level drive signal Vdr2 even when a "H" level set pulse signal S1 is input. Therefore, the switching control IC 20 does not malfunction by outputting a "L" level drive signal Vdr2 due to a drop in the power supply voltage Vcc.

[0079] This makes it possible to provide a signal processing circuit that can prevent malfunctions even when the external power supply is depleted.

[0080] ===Summary=== The power module 10 of this embodiment has been described above. The switching control IC 20 includes a power supply circuit 40, a diode 42, a pulse generation circuit 49, and a diode 45. Since the diode 42 is connected to a capacitor 41 that stabilizes the power supply voltage Vreg output by the power supply circuit 40, the capacitor 41 discharges when the power supply voltage Vcc drops to, for example, 0V. Therefore, the pulse generation circuit 49 does not output a "H" level reset pulse signal S2 even if the power supply voltage Vcc drops. This makes it possible to provide a signal processing circuit that can prevent malfunctions even when the external power supply is depleted.

[0081] Furthermore, the switching control IC 20 includes a pulse generation circuit 48 and a drive circuit 51. This allows the IGBT 30 to be turned on and off.

[0082] Furthermore, the discharge circuit for discharging capacitor 41 is diode 42. This allows for a simple circuit configuration while preventing malfunction of the switching control IC 20.

[0083] Furthermore, the switching control IC 20 is provided with a diode 46 in addition to the diode 45 on the signal line L2. This reduces the influence of static electricity input via the signal line L2 on the switching control IC 20.

[0084] Furthermore, the power module 10 includes IGBTs 30 and 31, and a switching control IC 20. The switching control IC 20 comprises a power supply circuit 40, diodes 42 and 45, pulse generation circuits 48 and 49, and drive circuits 50 and 51. Since diode 42 is connected to capacitor 41, which stabilizes the power supply voltage Vreg output by power supply circuit 40, capacitor 41 discharges when the power supply voltage Vcc drops to, for example, 0V. Therefore, even if the power supply voltage Vcc drops, the pulse generation circuit 49 does not output a "H" level reset pulse signal S2. As a result, the IGBT 30 is not accidentally turned off when the power supply voltage Vcc drops.

[0085] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. Furthermore, the present invention may be modified or improved without departing from its spirit, and it goes without saying that equivalents thereof are included. [Explanation of Symbols]

[0086] 10,400 Power Modules 11 Load 20,500 Switching Control ICs 21 Half-bridge circuit 22,41,205 Capacitors 40 Power circuit 42, 45, 46 diodes 43 Charge pump circuit 44, 120, 131, 132, 143 resistors 47 Comparator 48,49 Pulse generation circuit 50, 51 Drive Circuit 100 bias circuit 101 Output Circuit 110,111 Voltage Generation Circuit 121 Zener diode 130, 141, 142 NPN transistors 140 rated voltage circuit 200 SR Flip-Flop 201, 202, 207 Inverter Circuit 203 PMOS transistors 204 Current source 206 NMOS transistors

Claims

1. A power supply circuit that generates a second power supply voltage in a capacitor based on a first power supply voltage applied to the power line, When the first power supply voltage falls below a predetermined voltage level, a discharge circuit discharges the capacitor, A first detection circuit that operates based on the second power supply voltage and detects the falling edge of an input signal input via a signal line, A first diode having an anode connected to the signal line and a cathode connected to the power line, A signal processing circuit equipped with the following features.

2. A signal processing circuit according to claim 1, A second detection circuit that operates based on the second power supply voltage and detects the rising edge of the input signal input via the signal line, A drive circuit that drives the first switching element based on the first detection result of the first detection circuit and the second detection result of the second detection circuit, A signal processing circuit equipped with the following features.

3. A signal processing circuit according to claim 1 or claim 2, The aforementioned discharge circuit is The second diode includes an anode connected to the capacitor and a cathode connected to the power line, Signal processing circuit.

4. A signal processing circuit according to claim 3, The third diode comprises a cathode connected to the signal line and a grounded anode. Signal processing circuit.

5. A semiconductor device comprising: a first switching element on the power supply side; a second switching element on the ground side that drives a load together with the first switching element; and a switching control circuit that controls the switching of the first and second switching elements, The aforementioned switching control circuit is A power supply circuit that generates a second power supply voltage in a capacitor based on a first power supply voltage applied to the power line, When the first power supply voltage falls below a predetermined voltage level, a discharge circuit discharges the capacitor, A first detection circuit that operates based on the second power supply voltage and detects the falling edge of an input signal input via a signal line, A second detection circuit that operates based on the second power supply voltage and detects the rising edge of the input signal input via the signal line, A first drive circuit drives the first switching element based on the first detection result of the first detection circuit and the second detection result of the second detection circuit. A second drive circuit drives the second switching element based on the input signal, A first diode having an anode connected to the signal line and a cathode connected to the power line, A semiconductor device equipped with a semiconductor device.

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