Semiconductor packages, camera modules

Abstract

To improve solder connection reliability in response to temperature changes during package mounting, reduce the module size of the camera module on which the package is mounted, and obtain good electrical characteristics with passive components mounted on the camera module. [Solution] The semiconductor package 1 includes a first semiconductor chip 20 having an electrode 23 formed on the first surface 21a of a chip substrate 21 having a first surface 20a and a second surface 21b, a through hole 24 from the second surface 21b side of the chip substrate 21 to the electrode 23, a first redistribution layer 30 formed on the second surface 21b side of the chip substrate 21, one or more first passive components 210 electrically connected to the first redistribution layer 30, a columnar electrode 60 electrically connected to the first redistribution layer 30, and a sealing resin layer 70 covering the second surface 21b side of the chip substrate 21, wherein the first passive components 210 are positioned lower than the height of the columnar electrode 60 with respect to the second surface 30b of the first redistribution layer 30 and are covered by the sealing resin layer 70.

Description

Technical Field

[0001] The present invention relates to a semiconductor package and a camera module.

Background Art

[0002] In recent years, in order to cope with the miniaturization and high integration of semiconductor chips, flip-chip mounting with a semiconductor package as a CSP (Chip Scale Package) has been actively adopted.

[0003] Since the package size of CSP is about the same as that of the semiconductor chip, it can be miniaturized and the productivity of the wafer-level process is good. However, on the other hand, the solder connection reliability of the package mounting is low. In the package mounting of CSP, the reason for the low solder connection reliability is that the difference between the linear expansion coefficient of silicon (~3 ppm / °C) constituting the chip substrate in the semiconductor chip that is the mother body of CSP and the linear expansion coefficient of the mounting substrate such as the motherboard on which CSP is mounted (15 - 20 ppm / °C) is large. Therefore, due to the thermal expansion difference with respect to temperature changes such as temperature cycles, the stress applied to the connection terminal portion and its periphery becomes large.

[0004] Patent Document 1 discloses a device including a stress relaxation layer for relaxing the stress applied to the semiconductor device between the redistribution layer and the coating layer laminated on the insulating layer covering the wiring layer formed on the semiconductor chip, and a post for relaxing the stress related to the solder (connection terminal portion).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The apparatus disclosed in Patent Document 1 includes a stress relaxation layer beneath the redistribution layer, but this stress relaxation layer alone has a very small stress relaxation effect. Furthermore, in the apparatus of Patent Document 1, since the posts on which the connection terminal portion is formed are directly provided to the redistribution layer formed on the device surface side, stress applied to the solder is directly transmitted to the redistribution layer, etc., which may lead to damage to the redistribution layer. Therefore, the apparatus of Patent Document 1 has room for improvement in terms of solder connection reliability.

[0007] Furthermore, conventional semiconductor packages are sometimes mounted on camera modules. Camera modules have numerous peripheral components mounted on them, including passive components such as power supply capacitors, in addition to the semiconductor package. Due to the structure of the module, these peripheral components are often placed around the semiconductor package. Therefore, conventional camera modules had the problem of becoming large because they had to secure space for mounting peripheral components. In addition, if peripheral components are placed far away from the semiconductor package, their characteristics can deteriorate due to parasitic capacitance of the wiring laid between the semiconductor package and the peripheral components.

[0008] The present invention has been made in view of the above circumstances, and specifically aims to provide a semiconductor package that can improve the reliability of solder connections with respect to temperature changes during package mounting, reduce the module size of the camera module on which the package is mounted, and obtain good electrical characteristics with passive components mounted on the camera module, and a camera module on which the semiconductor package is mounted. [Means for solving the problem]

[0009] The above problem can be solved by any of the following means (1) to (16).

[0010] (1) A semiconductor package comprising: a first semiconductor chip having an electrode formed on the first surface of a chip substrate having a first surface that is the surface to which light is incident and a second surface opposite to the first surface; a through hole from the second surface side of the chip substrate to the electrode; a first redistribution layer formed on the second surface side of the chip substrate and electrically connected to the electrode through the through hole; one or more first passive components electrically connected to the first redistribution layer; a columnar electrode electrically connected to the first redistribution layer; and a sealing resin layer covering the second surface side of the chip substrate, wherein the first redistribution layer has a first surface that is the side of the first semiconductor chip and a second surface opposite to the first surface; the columnar electrode is arranged on the second surface of the first redistribution layer; and the first passive component is arranged on the second surface of the first redistribution layer at a position lower than the height of the columnar electrode and is covered by the sealing resin layer.

[0011] (2) When the first passive component constitutes a first group of passive components that includes multiple types of passive components of different heights, the first passive component with the lowest height among the first group of passive components is arranged on the outer periphery of the first semiconductor chip, as described in (1) above, in the semiconductor package.

[0012] (3) The semiconductor package according to (1) or (2) above, wherein a second semiconductor chip is disposed on the second surface of the first redistribution layer.

[0013] (4) Having a second rewiring layer formed on the outer surface of the sealing resin layer so as to be electrically connected to the columnar electrode, The semiconductor package according to any one of (1) to (3) above, wherein the second redistribution layer has multiple connection terminals laid out on the second surface opposite to the first surface which is the first semiconductor chip side.

[0014] (5) A semiconductor package according to any one of (1) to (3) above, having a package substrate electrically connectable to the columnar electrode, wherein the package substrate comprises an insulating portion and an internal wiring portion formed inside the insulating portion, the internal wiring portion having a first connection portion formed exposed on a first surface of the package substrate and a second connection portion formed exposed on a second surface of the package substrate opposite to the first surface, the internal wiring portion being electrically connected to the columnar electrode through the first connection portion and electrically connected to a connection terminal portion laid out on the second surface of the package substrate through the second connection portion.

[0015] (6) The semiconductor package according to (5) above, wherein one or more second passive components connected to the wiring layer are arranged on the first surface of the package substrate.

[0016] (7) The semiconductor package as described in (6) above, wherein the second passive component constitutes a second group of passive components that include multiple types of passive components of different heights, and the second passive component with the lowest height is arranged on the outer periphery side of the first semiconductor chip.

[0017] (8) A semiconductor package according to any one of (5) to (7) above, wherein a third semiconductor chip is arranged on the first surface of the package substrate.

[0018] (9) The semiconductor package according to any one of (1) to (8) above, wherein the columnar electrode is bonded to the first redistribution layer via the first conductive portion.

[0019] (10) The semiconductor package according to (9) above, wherein the elastic modulus of the first conductive part is lower than the elastic modulus of the columnar electrode.

[0020] (11) The semiconductor package according to any one of (1) to (10) above, wherein the columnar electrode is formed of a metal pin or metal plating.

[0021] (12) The semiconductor package according to any one of (1) to (11) above, wherein the sealing resin layer contains a non-conductive filler.

[0022] (13) The semiconductor package according to any one of (1) to (12) above, wherein the linear expansion coefficient of the sealing resin layer is not less than the linear expansion coefficient of the chip substrate of the first semiconductor chip.

[0023] (14) The semiconductor package according to (9) or (10) above, wherein the first conductive portion is formed of a conductive paste or solder.

[0024] (15) The semiconductor package according to any one of (1) to (14) above, wherein the semiconductor chip is an image sensor.

[0025] (16) A camera module including the semiconductor package according to any one of (1) to (15) above, and an optical unit having at least a lens unit disposed on the side where light of the semiconductor package is incident.

Advantages of the Invention

[0026] The semiconductor package according to an embodiment of the present invention can reduce the solder stress associated with temperature changes during package mounting and improve the solder connection reliability. Further, the semiconductor package can reduce the module size of the mounted camera module. Further, the semiconductor package can obtain good electrical characteristics with passive components and the like mounted on the camera module.

[0027] The camera module according to an embodiment of the present invention can reduce the module size by mounting the semiconductor package according to the present invention, and can obtain good electrical characteristics with passive components and the like mounted thereon.

Brief Description of the Drawings

[0028] [Figure 1] It is a cross-sectional schematic view showing a state where the semiconductor package according to the first embodiment of the present invention is mounted on a mounting substrate. [Figure 2] This is a schematic cross-sectional view of the semiconductor package according to the first embodiment. [Figure 3] This is a flowchart of the manufacturing method for a semiconductor package according to the first embodiment. [Figure 4A] This is a schematic cross-sectional view showing step 1 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4B] This is a schematic cross-sectional view showing step 2 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4C] This is a schematic cross-sectional view showing step 3 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4D] This is a schematic cross-sectional view showing step 4 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4E] This is a schematic cross-sectional view showing step 5 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4F] This is a schematic cross-sectional view showing step 6 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4G] This is a schematic cross-sectional view showing step 7 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4H] This is a schematic cross-sectional view showing step 8 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4I] This is a schematic cross-sectional view showing step 9 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4J] This is a schematic cross-sectional view showing step 10 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4K] This is a schematic cross-sectional view showing step 11 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4L] This is a schematic cross-sectional view showing step 12 of the semiconductor package manufacturing method according to the first embodiment. [Figure 4M] This is a schematic cross-sectional view showing step 12 of the semiconductor package manufacturing method according to the first embodiment. [Figure 5] This is a schematic cross-sectional view showing an example of a modification of the semiconductor package of the first embodiment. [Figure 6]This is a schematic cross-sectional view showing another modification example of the semiconductor package of the first embodiment. [Figure 7A] This is a schematic cross-sectional view of a semiconductor package according to a second embodiment of the present invention. [Figure 7B] This figure shows an example of wiring of a first passive component mounted on the first redistribution layer of a semiconductor package according to the second embodiment. [Figure 8] This is a flowchart of the method for manufacturing a semiconductor package according to the second embodiment. [Figure 9A] This is a schematic cross-sectional view showing step 1 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9B] This is a schematic cross-sectional view showing step 2 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9C] This is a schematic cross-sectional view showing step 3 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9D] This is a schematic cross-sectional view showing step 4 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9E] This is a schematic cross-sectional view showing step 5 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9F] This is a schematic cross-sectional view showing step 6 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9G] This is a schematic cross-sectional view showing step 7 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9H] This is a schematic cross-sectional view showing step 8 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9I] This is a schematic cross-sectional view showing step 9 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9J] This is a schematic cross-sectional view showing step 10 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9K] This is a schematic cross-sectional view showing step 11 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9L] This is a schematic cross-sectional view showing step 12 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9M]This is a schematic cross-sectional view showing step 13 of the semiconductor package manufacturing method according to the second embodiment. [Figure 9N] This is a schematic cross-sectional view showing step 14 of the semiconductor package manufacturing method according to the second embodiment. [Figure 10] This is a schematic cross-sectional view showing an example of a modification of the semiconductor package according to the second embodiment. [Figure 11] This is a schematic cross-sectional view showing another modification example of the semiconductor package of the second embodiment. [Figure 12] This is a schematic cross-sectional view of a semiconductor package according to a third embodiment of the present invention. [Figure 13] This is a flowchart of the manufacturing method for a semiconductor package according to the third embodiment. [Figure 14A] This is a schematic cross-sectional view showing step 1 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14B] This is a schematic cross-sectional view showing step 2 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14C] This is a schematic cross-sectional view showing step 3 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14D] This is a schematic cross-sectional view showing step 4 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14E] This is a schematic cross-sectional view showing step 5 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14F] This is a schematic cross-sectional view showing step 6 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14G] This is a schematic cross-sectional view showing step 7 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14H] This is a schematic cross-sectional view showing step 8 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14I] This is a schematic cross-sectional view showing step 9 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14J] This is a schematic cross-sectional view showing step 10 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14K]This is a schematic cross-sectional view showing step 11 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14L] This is a schematic cross-sectional view showing step 12 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14M] This is a schematic cross-sectional view showing step 13 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14N] This is a schematic cross-sectional view showing step 14 of the semiconductor package manufacturing method according to the third embodiment. [Figure 14O] This is a schematic cross-sectional view showing step 15 of the semiconductor package manufacturing method according to the third embodiment. [Figure 15] This is a schematic cross-sectional view showing one form of a semiconductor package according to a modified example of the third embodiment. [Figure 16] This is a schematic cross-sectional view showing one form of a semiconductor package of another modification example of the third embodiment. [Figure 17] This is a schematic cross-sectional view showing another form of the semiconductor package of another modification example of the third embodiment. [Figure 18] This is a schematic cross-sectional view showing an example of a camera module equipped with the semiconductor package of the present invention. [Modes for carrying out the invention]

[0029] Embodiments of the present invention will be described in detail below with reference to the attached drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings is exaggerated for clarity and convenience of explanation. On the other hand, the embodiments described below are merely illustrative, and various modifications are possible from such embodiments.

[0030] In the following, "upper part" or "top" may include not only things that are directly above and in contact, but also things that are above but not in contact. Similarly, "lower part" or "bottom" may include not only things that are directly below and in contact, but also things that are below but not in contact.

[0031] A singular expression includes plural expressions unless the context clearly indicates that it is singular. Furthermore, when a part is said to "include," "possess," or "have" a component, it does not exclude other components, but rather may include other components, unless otherwise specified.

[0032] Unless explicitly stated otherwise, the steps constituting the method shall be performed in the appropriate order. This order is not necessarily limited to the order in which the steps are described. All examples or illustrative terms are used solely to illustrate the technical idea and are not limited in scope to the claims.

[0033] In the following explanations, when ordinal numbers such as "1st" and "2nd" are used, they are for convenience only and do not prescribe any particular order unless otherwise specified.

[0034] The semiconductor packages 1, 1A, 1B, 2, 2A, 2B, 3, 3A, 3B, and 3C shown in each embodiment of the present invention are wafer-level packages (CSPs) in which the first semiconductor chip 20 is composed of a solid-state image sensor (COMS image sensor).

[0035] [First Embodiment] The semiconductor package 1 according to the first embodiment will be described with reference to Figures 1 to 6 as appropriate.

[0036] As shown in Figures 1 and 2, the semiconductor package 1 comprises a transparent substrate 10, a first semiconductor chip 20, a first redistribution layer 30, a first insulating layer 40, a first conductive portion 50, a columnar electrode 60, a sealing resin layer 70, a second insulating layer 80, and a connection terminal portion 90. As shown in Figure 1, the semiconductor package 1 can be mounted on a mounting substrate 500 via the connection terminal portion 90.

[0037] Furthermore, the semiconductor package 1 has one or more first passive components 210. As shown in Figure 2, the first passive components 210 are positioned lower than the height of the columnar electrodes 60 on the second surface 30b of the first redistribution layer 30 and are mounted covered with a sealing resin layer 70.

[0038] The transparent substrate 10 is formed from a transparent material that has light transmittance, such as glass or a resin material such as polyimide. The planar size of the transparent substrate 10 is larger than or equal to the planar size of the chip substrate 21 of the first semiconductor chip 20. As shown in Figure 2, the transparent substrate 10 has a first surface 10a that is the incident surface of light and a second surface 10b that faces the first surface 10a. The transparent substrate 10 is joined to the first surface 21a of the chip substrate 21 of the first semiconductor chip 20 via a joint B made of a encapsulating material S (DAM agent) or the like, with the second surface 10b facing the first surface 21a of the chip substrate 21 of the first semiconductor chip 20. In Figure 1, the first surface 10a of the transparent substrate 10 is the top surface of the transparent substrate 10, and the second surface 10b of the transparent substrate 10 is the bottom surface of the transparent substrate 10.

[0039] The first semiconductor chip 20 has a chip substrate 21 made of silicon or the like. The chip substrate 21 of the first semiconductor chip 20 has a first surface 21a and a second surface 21b opposite to the first surface 21a. IC circuit patterns and the like are formed on the first surface 21a. In Figure 2, the first surface 21a of the chip substrate 21 is the upper surface which is the incident surface of light, and the second surface 21b of the chip substrate 21 is the lower surface of the chip substrate 21.

[0040] The first semiconductor chip 20 has a light-receiving area in which multiple pixels that convert incident light into electrical signals are arranged in rows vertically and horizontally, and can be configured as a CMOS image sensor with an on-chip lens (microlens) 22, as well as a color filter, photodiode, pixel circuit, etc. (not shown) mounted on it.

[0041] An electrode 23 is formed on the first surface 21a of the chip substrate 21, and through holes (vias) 24 are formed from the second surface 21b to the electrode 23 so that electrical contact with the electrode 23 is possible. The through holes 24 can be formed by known processing methods such as deep reactive ion etching (DRIE).

[0042] A second insulating layer 80 is formed on the second surface 21b, the side surface, and the side surface of the through-hole 24 of the chip substrate 21. The second insulating layer 80 is formed by known thin-film formation methods such as vapor deposition, sputtering, and CVD, and at least the portion formed on the surface facing the electrode 23 at the bottom of the through-hole 24 is removed.

[0043] The first redistribution layer 30 is formed by laminating the second insulating layer 80. The first redistribution layer 30 has a first surface 30a facing the first semiconductor chip 20 and a second surface 30b opposite to the first surface 30a.

[0044] The first redistribution layer 30 is formed with a predetermined conductive pattern. The conductive pattern of the first redistribution layer 30 can be formed from metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or alloys thereof. The first redistribution layer 30 can be formed by known formation methods. Electronic components such as the first passive component 210 can be mounted on the second surface 30b of the first redistribution layer 30.

[0045] The first redistribution layer 30 can be formed by laminating a first insulating layer 40 onto it. The first insulating layer 40 can be formed in advance in areas other than the formation areas of each conductive part in order to provide electrical conductivity between the first conductive part 50, the second conductive part 100 and the first redistribution layer 30. The first insulating layer 40 can be formed from an insulating resin such as a thermosetting resin like epoxy resin or a thermoplastic resin like polyimide.

[0046] A columnar electrode 60 is formed on the first redistribution layer 30 by lamination onto the first conductive part 50. The first conductive part 50 is interposed between the columnar electrode 60 and the first redistribution layer 30, electrically connecting the columnar electrode 60 and the first redistribution layer 30. The first conductive part 50 can be formed from a conductive paste such as a conductive adhesive containing copper particles, or from a conductive material such as solder. The first conductive part 50 can be formed by known printing methods such as screen printing or inkjet printing.

[0047] The elastic modulus of the first conductive part 50 is preferably lower than that of the columnar electrode 60. That is, the relationship between the elastic moduli of the first conductive part 50 and the columnar electrode 60 is preferably such that "elastic modulus of the first conductive part < elastic modulus of the columnar electrode". By forming the first conductive part 50, which has an elastic modulus lower than that of the columnar electrode 60, between the first redistribution layer 30 and the columnar electrode 60, the semiconductor package 1 can effectively reduce the stress on the connection terminal 90 due to the difference in thermal expansion.

[0048] The columnar electrode 60 is formed by laminating it onto the first conductive portion 50. As shown in Figure 2, the columnar electrode 60 is an electrode member having a first end portion 61 connected to the first conductive portion 50, a second end portion 62 on the axially opposite end to the first end portion 61 where a connection terminal portion 90 etc. is formed, and a side surface connecting the first end portion 61 and the second end portion 62. The columnar electrode 60 can be made of a metal pin (copper pin) mainly composed of copper, or a member formed by copper plating using known plating methods such as electroplating or chemical plating, in a columnar shape. By using copper pins, the columnar electrode 60 can be assembled during manufacturing because it is only necessary to place the metal pins that function as electrodes at the formation position of the first conductive portion 50.

[0049] The sealing resin layer 70 is formed to cover at least the side surface of the first conductive portion 50, the side surface of the columnar electrode 60, and the first passive component 210. The sealing resin layer 70 is formed by filling the space to be sealed (sealing space) of the semiconductor package 1 with sealing resin. As shown in Figure 2, the sealing resin layer 70 is formed to cover the first redistribution layer 30 and the first passive component 210, etc., while exposing the second end portion 62 of the columnar electrode 60. A connection terminal portion 90, etc., can be formed on the second end portion 62.

[0050] The sealing resin layer 70 is composed of an insulating resin such as epoxy resin, which can be used as a potting resin. Preferably, the sealing resin layer 70 contains non-conductive fillers such as spherical or flattened inorganic fillers such as silica. The content of the non-conductive fillers in the sealing resin layer 70 can be adjusted to achieve the best solder connection reliability of the semiconductor package 1. By adjusting the filler content, the linear expansion coefficient and elastic modulus of the sealing resin layer 70 itself can be adjusted. Therefore, the semiconductor package 1, by having a sealing resin layer 70 with a filler content adjusted to achieve the best solder connection reliability, becomes a package with excellent solder connection reliability.

[0051] The sealing resin layer 70 has a coefficient of linear expansion greater than or equal to the coefficient of linear expansion of the chip substrate 21 of the first semiconductor chip 20. The coefficient of linear expansion of the sealing resin layer 70 is 5 to 15 ppm / °C, which is higher than the coefficient of linear expansion of the chip substrate 21 of the first semiconductor chip 20 (~3 ppm / °C) and close to the coefficient of linear expansion of the mounting substrate 500 (15 to 20 ppm / °C). By being formed between the first semiconductor chip 20 and the mounting substrate 500, the sealing resin layer 70 can function as a stress-relieving layer that significantly reduces stress on the connection terminal portion 90 due to temperature changes that may occur between the first semiconductor chip 20 and the mounting substrate 500.

[0052] When the first semiconductor chip 20 is configured as an image sensor, the sealing resin layer 70 preferably has a light-shielding portion that blocks light of the sensitivity wavelength of the image sensor. The sealing resin layer 70 may contain light-shielding materials such as carbon or fillers to achieve the above light-shielding properties, so that the entire layer functions as a light-shielding portion. Alternatively, the sealing resin layer 70 may have a film material or layer formed to cover part or all of the sealing resin layer 70 to achieve the above light-shielding properties. By forming a light-shielding portion in the sealing resin layer 70, the semiconductor package 1 equipped with the image sensor can reduce adverse effects on the sensor due to stray light such as reflected light and scattered light.

[0053] The connection terminal portion 90 is formed of a conductive material such as solder and is connected to the second end portion 62 of the columnar electrode 60. The semiconductor package 1 can also be configured without forming the connection terminal portion 90 on the second end portion 62 of the columnar electrode 60.

[0054] The first passive component 210 is composed of passive components such as a power capacitor and matching elements. The first passive component 210 is placed on the second surface 30b of the first redistribution layer 30. Therefore, the first passive component 210 is mounted inside the semiconductor package 1. The first passive component 210 is positioned lower than the height of the columnar electrode 60 with respect to the second surface 30b of the first redistribution layer 30 and is covered with a sealing resin layer 70. The first passive component 210 is placed on the second conductive portion 100 formed on the second surface 30b of the first redistribution layer 30. The second conductive portion 100, like the first conductive portion 50, can be formed from a conductive paste such as a conductive adhesive containing copper particles or a conductive material such as solder.

[0055] When the semiconductor package 1 is mounted on, for example, the camera module 700 shown in Figure 18, passive components that can be mounted inside the camera module 700 can be mounted inside the semiconductor package 1 as first passive components 210. As a result, the camera module 700 can be made smaller in size, and good electrical characteristics can be obtained by reducing the distance between the semiconductor package 1 and the first passive components 210.

[0056] The first passive component 210 can form a first passive component group 220 composed of multiple passive components, as shown in Figure 5, for example. The first passive component group 220 may consist of components of substantially uniform height, or it may include components of different heights. Naturally, the first passive component group 220 may include components with different functions.

[0057] Next, we will explain the manufacturing method of the semiconductor package 1.

[0058] As shown in Figure 3, the manufacturing method for the semiconductor package 1 includes a sealing material coating step S1 (step 1), a bonding step S2 (step 2), a first grinding step S3 (step 3), a through-hole formation step S4 (step 4), an insulating layer formation step S5 (step 5), an exposure step S6 (step 6), a first redistribution layer formation step S7 (step 7), a conductive material coating step S8 (step 8), a placement step S9 (step 9), a sealing resin layer formation step S10 (step 10), a second grinding step S11 (step 11), a terminal formation step S12 (step 12), and a cutting step S13 (step 13). Figures 4A to 4M show diagrams of the configuration of each step (steps 1 to 13) included in the manufacturing process of the semiconductor package 1.

[0059] (Process 1) Step 1 involves performing a sealing material application step S1, as shown in Figure 4A, in which a sealing material S, which functions as a bonding portion B, is applied to the second surface Gb of the glass substrate G that will become the transparent substrate 10, opposite the first surface Ga. The sealing material S is applied so as to include the periphery of each package and the boundary portion to be separated.

[0060] (Process 2) Step 2 involves a bonding process S2, as shown in Figure 4B, in which the second surface Gb of the glass substrate G coated with the encapsulating material S is joined to the first surface Wa of the semiconductor wafer W which will become the chip substrate 21 of the first semiconductor chip 20, with the two surfaces facing each other. The semiconductor wafer W has on-chip lenses 22, electrodes 23, and other components that constitute the image sensor mounted on the light-receiving area of ​​each package on the first surface Wa. In step 2, the encapsulating material S is cured to form the bonded portion B.

[0061] (Step 3) Step 3 involves performing a first grinding step S3, as shown in Figure 4C, in which the second surface Wb of the semiconductor wafer W is back-ground to a predetermined chip size thickness.

[0062] (Step 4) Step 4 is a through-hole formation step S4 in which through-holes 24 are formed by etching from the second surface Wb side of the semiconductor wafer W, as shown in Figure 4D. The through-holes 24 can be formed by deep reactive ion etching (DRIE). The through-holes 24 are formed at the electrode formation locations 23 and at the package boundary locations. Due to the formation of the through-holes 24, a portion of the electrode 23 and a portion of the junction B at the boundary are exposed.

[0063] (Step 5) Step 5 is an insulating layer formation step S5 in which a second insulating layer 80 is formed on the entire surface of the second surface Wb of the semiconductor wafer W, as shown in Figure 4E. The formation process of the second insulating layer 80 can be carried out by vapor deposition, sputtering, CVD, etc.

[0064] (Step 6) Step 6, as shown in Figure 4F, involves performing an exposure step S6 to expose a portion of the electrode 23 by removing the second insulating layer 80 located at the bottom of the through hole 24, so that the electrode 23 can conduct electricity. The removal of the second insulating layer 80 can be carried out by etching or the like.

[0065] (Step 7) Step 7 is a first redistribution layer formation step S7 in which a first redistribution layer 30 is formed on the second insulating layer 80, as shown in Figure 4G. The first redistribution layer 30 is formed to be electrically conductive with the electrode 23 using photolithography and plating methods. In step 7, the first insulating layer 40 can be formed in advance in areas other than the formation areas of each conductive part in order to make the first redistribution layer 30 electrically conductive with the first conductive part 50 and the second conductive part 100 which will be formed in the next step. Alternatively, in step 7, after forming the first insulating layer 40, a process may be performed to remove the first insulating layer 40 corresponding to the formation areas of each conductive part.

[0066] (Step 8) Step 8 is a conductive material coating step S8 in which a conductive paste is applied as a conductive material to form the first conductive part 50 and the second conductive part 100, as shown in Figure 4H. The first conductive part 50 is formed on the first redistribution layer 30 corresponding to the placement position of the columnar electrode 60. The second conductive part 100 is formed on the first redistribution layer 30 corresponding to the placement position of the first passive component 210. The formation process of the first conductive part 50 and the second conductive part 100 can be carried out by screen printing, inkjet printing, etc., with a mask applied to areas other than the formation positions. In step 8, the conductive material is a conductive paste, but solder may also be used, and different materials may be used for the first conductive part 50 and the second conductive part 100.

[0067] (Step 9) Step 9 is a placement step S9 in which the columnar electrode 60 and the first passive component 210 are placed, as shown in Figure 4I. The placement process for the columnar electrode 60 is similar to the ball mounting method and can be carried out by a process of applying a mask to the area other than the first conductive part 50 so that the first conductive part 50 shown in Figure 4H is exposed, a process of transporting a plurality of copper pins that will become the columnar electrode 60 on the mask and placing the copper pins through the openings of the mask to make contact with each of the first conductive part 50, and a process of removing the mask and drying, firing, and hardening the first conductive part 50. The end of the columnar electrode 60 that contacts the first conductive part 50 is the first end 61. The first passive component 210 can be mounted on the first redistribution layer 30 by a known mounting process (such as mounting by a mounting device). Step 9 may also include a reflow process of the conductive material. The columnar electrode 60 and the first passive component 210 are fixed to the first redistribution layer 30 by the reflow process.

[0068] In step 9, the columnar electrode 60 and the first passive component 210 are mounted within the same step, but they may be mounted separately. Furthermore, the reflow process for the conductive material can be performed as a separate step from step 9.

[0069] (Step 10) Step 10 is a sealing resin layer forming step S10 in which a sealing resin layer 70 is formed, as shown in Figure 4J. The sealing resin layer 70 is formed by filling the sealing space with a resin containing a non-conductive filler, such as epoxy resin. The sealing resin layer 70 is applied so as to cover the first passive component 210. As a result, the sealing resin layer 70 is formed to cover the side surface of the first conductive part 50, the side surface of the columnar electrode 60, the first rewiring layer 30, and the first passive component 210, with the second end 62 of the columnar electrode 60 exposed.

[0070] (Step 11) Step 11 involves performing a second grinding step S11, as shown in Figure 4K, in which the sealing resin layer 70 is back-ground to expose the second end portion 62 of the columnar electrode 60.

[0071] (Step 12) Step 12 involves performing a terminal formation step S12, which involves forming a connection terminal portion 90 on the second end portion 62 of the columnar electrode 60, as shown in Figure 4L. The formation process for the connection terminal portion 90 can be carried out by a ball mounting method, a screen printing method, or the like. In step 12, from the viewpoint of ease of mounting, it is preferable that the height position of the contact surface of the connection terminal portion 90 with respect to the mounting substrate 500 be formed to be approximately the same as that in the thickness direction of the semiconductor package 1.

[0072] (Step 13) Step 13 involves performing a cutting step S13, as shown in Figure 4M, which involves cutting a predetermined location on the semiconductor wafer W to singulate the semiconductor package 1. Through these steps, the semiconductor package 1 shown in Figure 2 is manufactured.

[0073] Furthermore, the above-described method for manufacturing the semiconductor package 1 may include steps other than steps 1 to 13 (such as a cleaning step) as needed. In addition, in the method for manufacturing the semiconductor package 1, the order of each step may be appropriately rearranged as long as the configuration and function of the manufactured semiconductor package 1 do not depart from the gist of the present invention.

[0074] Furthermore, in the manufacturing method described above, the semiconductor package 1 may be configured in which no connection terminal portion 90 is formed on the second end portion 62 of the columnar electrode 60. In that case, the processing in step 12 is omitted.

[0075] The semiconductor package 1 can adopt the following configuration.

[0076] Figure 5 shows a semiconductor package 1A, which is a modified example of the first embodiment. As shown in Figure 5, semiconductor package 1A is a configuration in which first passive components 210 of different heights are mounted. In semiconductor package 1A, the first passive components 210 with lower heights are placed on the outer periphery side of the first semiconductor chip 20 in a cross-sectional view. In addition, semiconductor package 1A places the first passive components 210 with higher heights towards the center side of the first semiconductor chip 20 in a cross-sectional view.

[0077] By arranging the first passive component 210 in the semiconductor package 1A as shown in Figure 5, the flow of the sealing resin filling the sealing space during the formation of the sealing resin layer 70 can be prevented from being obstructed by the tall first passive component 210. Therefore, the semiconductor package 1A can reduce the generation of voids and the like after the formation of the sealing resin layer 70.

[0078] Figure 6 shows semiconductor package 1B, which is another modification of the first embodiment. As shown in Figure 6, semiconductor package 1B has a configuration in which the first passive component 210 and the second semiconductor chip 300 are mounted on the second surface 30b of the first redistribution layer 30. In addition to one or more first passive components 210, semiconductor package 1B can also mount other electronic components such as the second semiconductor chip 300 on the second surface 30b of the first redistribution layer 30. With this configuration, semiconductor package 1B can be made more functional.

[0079] [Second Embodiment] The semiconductor package 2 according to the second embodiment will be described with reference to Figures 7A to 11 as appropriate. Note that components of the semiconductor package 2 that are the same as those in the previously described embodiment are denoted by the same reference numerals, and their descriptions are omitted. Furthermore, components not specifically mentioned can be configured in the same way as in the previously described embodiment.

[0080] As shown in Figure 7A, the semiconductor package 2 comprises a transparent substrate 10, a first semiconductor chip 20, a first redistribution layer 30, a first conductive portion 50, a columnar electrode 60, a sealing resin layer 70, a second insulating layer 80, a connection terminal portion 90, and a second redistribution layer 110. The semiconductor package 2 can be mounted on a mounting substrate 500 or the like via the connection terminal portion 90. The semiconductor package 2 differs from the semiconductor package 1 of the first embodiment in that it includes a second redistribution layer 110 laminated on the sealing resin layer 70.

[0081] The second redistribution layer 110 is formed by laminating it onto the sealing resin layer 70. The second redistribution layer 110 is connected to the second end 62 of the columnar electrode 60.

[0082] The second redistribution layer 110 is formed with a predetermined conductive pattern. The conductive pattern of the second redistribution layer 110 can be formed from the same material as the first redistribution layer 30. The second redistribution layer 110 can be formed by a known formation method. The second redistribution layer 110 has a first surface 110a on the first semiconductor chip 20 side and a second surface 110b on the opposite side of the first surface 110a.

[0083] The second rewiring layer 110 can be formed by laminating a third insulating layer 120 onto it. The third insulating layer 120 can be formed such that the second rewiring layer 110 in the area where the connection terminal portion 90 is formed is exposed. The third insulating layer 120 can be formed from the same insulating resin as the first insulating layer 40.

[0084] A connection terminal portion 90 is positioned on the second surface 110b of the second redistribution layer 110. The connection terminal portion 90 is electrically connected to the first passive component 210 and the first semiconductor chip 20 through the columnar electrode 60 and the second redistribution layer 110.

[0085] In the semiconductor package 1 of the first embodiment, the arrangement of the columnar electrodes 60 is determined according to the arrangement of the first passive component 210 to be mounted. Furthermore, since the diameter of the columnar electrodes 60 of the semiconductor package 1 must match the size of the connection terminal portion 90, the size of the semiconductor package 1 is generally large. Thus, in the semiconductor package 1, the arrangement and size of the columnar electrodes 60 may be limited.

[0086] In contrast, as shown in Figure 7B, the semiconductor package 2 of the second embodiment allows the columnar electrodes 60 to be placed in the empty space of the first redistribution layer 30 (for example, on the outer periphery side of the second surface 30b of the first redistribution layer 30). Therefore, the semiconductor package 2 can place the connection terminal portion 90 regardless of the arrangement of the first passive component 210 to be mounted. Furthermore, since the semiconductor package 2 does not need to consider the size of the connection terminal portion 90, the size of the columnar electrodes 60 can be reduced. Moreover, the semiconductor package 2 does not need to form the connection terminal portion 90 on the second end 62 of the columnar electrodes 60. Therefore, the semiconductor package 2 can place the connection terminal portion 90 formed on the second surface 110b of the second redistribution layer 110 at a desired position. In addition, the semiconductor package 2, like the semiconductor package 1 of the first embodiment, has a sealing resin layer 70 that functions as a stress relaxation layer, covering the first redistribution layer 30 and a part of the columnar electrodes 60. Therefore, semiconductor package 3 significantly reduces solder stress caused by temperature changes during package mounting, resulting in a package with excellent solder connection reliability during package mounting.

[0087] Next, we will explain the manufacturing method for the semiconductor package 2.

[0088] As shown in Figure 8, the manufacturing method for the semiconductor package 2 includes a sealing material coating step S21 (step 1), a bonding step S22 (step 2), a first grinding step S23 (step 3), a through-hole formation step S24 (step 4), an insulating layer formation step S25 (step 5), an exposure step S26 (step 6), a first redistribution layer formation step S27 (step 7), a conductive material coating step S28 (step 8), a placement step S29 (step 9), a sealing resin layer formation step S30 (step 10), a second grinding step S31 (step 11), a second redistribution layer formation step S32 (step 12), a terminal formation step S33 (step 13), and a cutting step S34 (step 14). Figures 9A to 9N show diagrams of the configuration of each step (steps 1 to 14) included in the manufacturing process of the semiconductor package 2.

[0089] (Process 1) Step 1 involves performing a sealing material application step S21, as shown in Figure 9A, in which a sealing material S, which functions as a bonding portion B, is applied to the second surface Gb of the glass substrate G that will become the transparent substrate 10, opposite the first surface Ga. The sealing material S is applied so as to include the perimeter of each package and the boundary portion to be separated.

[0090] (Process 2) Step 2 involves a bonding process S22, as shown in Figure 9B, in which the second surface Gb of the glass substrate G coated with the encapsulating material S is joined to the first surface Wa of the semiconductor wafer W, which will become the chip substrate 21 of the first semiconductor chip 20, while they are facing each other. The semiconductor wafer W has on-chip lenses 22, electrodes 23, and other components that constitute the image sensor mounted on the light-receiving area of ​​each package on the first surface Wa. In Step 2, the encapsulating material S is subjected to a hardening treatment to form the bonded portion B.

[0091] (Step 3) Step 3 involves performing a first grinding step S23, as shown in Figure 9C, in which the second surface Wb of the semiconductor wafer W is back-ground to a predetermined chip size thickness.

[0092] (Step 4) Step 4 is a through-hole formation step S24 in which through-holes 24 are formed by etching from the second surface Wb side of the semiconductor wafer W, as shown in Figure 9D. The through-holes 24 can be formed by deep reactive ion etching (DRIE). The through-holes 24 are formed at the electrode formation locations 23 and at the package boundary locations. Due to the formation of the through-holes 24, a portion of the electrode 23 and a portion of the junction B at the boundary are exposed.

[0093] (Step 5) Step 5 involves performing an insulating layer formation step S25, in which a second insulating layer 80 is formed on the entire second surface Wb of the semiconductor wafer W, as shown in Figure 9E. The formation of the second insulating layer 80 can be carried out by methods such as vapor deposition, sputtering, or CVD.

[0094] (Step 6) Step 6, as shown in Figure 9F, involves performing an exposure step S26 to remove the second insulating layer 80 located at the bottom of the through hole 24, thereby exposing a portion of the electrode 23, so that the electrode 23 can conduct electricity. The removal of the second insulating layer 80 can be carried out by etching or the like.

[0095] (Step 7) Step 7 involves performing a first redistribution layer formation step S27, in which the first redistribution layer 30 is formed on the second insulating layer 80, as shown in Figure 9G. The first redistribution layer 30 is formed to be electrically connected to the electrode 23 using photolithography and plating methods.

[0096] (Step 8) Step 8 is a conductive material coating step S28 in which a conductive paste is applied as a conductive material to form the first conductive part 50 and the second conductive part 100, as shown in Figure 9H. The first conductive part 50 is formed on the first redistribution layer 30 corresponding to the placement position of the columnar electrode 60. The second conductive part 100 is formed on the first redistribution layer 30 corresponding to the placement position of the first passive component 210. The formation process of the first conductive part 50 and the second conductive part 100 can be carried out by screen printing, inkjet printing, etc., with a mask applied to areas other than the formation positions. In step 8, the conductive material is a conductive paste, but solder may also be used, and different materials may be used for the first conductive part 50 and the second conductive part 100.

[0097] (Step 9) Step 9 is a placement step S29 in which the columnar electrode 60 and the first passive component 210 are placed, as shown in Figure 9I. The placement process for the columnar electrode 60 is similar to the ball mounting method and can be carried out by a process of applying a mask to the area other than the first conductive part 50 so that the first conductive part 50 shown in Figure 9H is exposed, a process of transporting a plurality of copper pins that will become the columnar electrode 60 on the mask and placing the copper pins through the openings of the mask to make contact with each of the first conductive part 50, and a process of removing the mask and drying, firing, and hardening the first conductive part 50. The end of the columnar electrode 60 that contacts the first conductive part 50 is the first end 61. The first passive component 210 can be mounted on the first redistribution layer 30 by a known mounting process (such as mounting by a mounting device). Step 9 may also include a reflow process of the conductive material. The columnar electrode 60 and the first passive component 210 are fixed to the first redistribution layer 30 by the reflow process.

[0098] In step 9, the columnar electrode 60 and the first passive component 210 are mounted within the same step, but they may be mounted separately. Furthermore, the reflow process for the conductive material can be performed as a separate step from step 9.

[0099] (Step 10) Step 10 involves performing a sealing resin layer forming step S30 to form a sealing resin layer 70, as shown in Figure 9J. The sealing resin layer 70 is formed by filling the sealing space with a sealing resin containing a non-conductive filler, such as epoxy resin. The sealing resin layer 70 is applied so as to cover the first passive component 210. As a result, the sealing resin layer 70 is formed to cover the first conductive part 50, the side surface of the columnar electrode 60, the first rewiring layer 30, and the first passive component 210, with the second end 62 of the columnar electrode 60 exposed.

[0100] (Step 11) Step 11 involves performing a second grinding step S31, as shown in Figure 9K, which involves back grinding the sealing resin layer 70 to expose the second end 62 of the columnar electrode 60. As a result, the second end 62 of the columnar electrode 60 is exposed from the sealing resin layer 70.

[0101] (Step 12) Step 12 is a second redistribution layer formation step S32 in which a second redistribution layer 110 is formed on the sealing resin layer 70, as shown in Figure 9L. The second redistribution layer 110 is formed to be electrically connected to the second end 62 of the columnar electrode 60 using photolithography and plating methods, similar to the first redistribution layer formation step S27. Furthermore, the third insulating layer 120 can be formed so that the second redistribution layer 110 in the formation area of ​​the connection terminal portion 90 is exposed.

[0102] (Step 13) Step 13 is a terminal formation step S33 in which a connection terminal portion 90 is formed on the second end portion 62 of the columnar electrode 60, as shown in Figure 9M. The formation process of the connection terminal portion 90 can be carried out by a ball mounting method, a screen printing method, or the like. In step 12, from the viewpoint of ease of mounting, it is preferable that the height position of the contact surface of the connection terminal portion 90 with respect to the mounting substrate 500 be formed to be approximately the same as that in the thickness direction of the semiconductor package 2.

[0103] (Step 14) Step 14 involves performing a cutting step S34, as shown in Figure 9N, which involves cutting a predetermined location on the semiconductor wafer W to singulate the semiconductor package 2. Through these steps, the semiconductor package 2 shown in Figure 7A is manufactured.

[0104] Furthermore, the above-described method for manufacturing the semiconductor package 2 may include steps other than steps 1 to 14 (such as a cleaning step) as needed. In addition, in the method for manufacturing the semiconductor package 2, the order of each step may be appropriately rearranged as long as the configuration and function of the manufactured semiconductor package 2 do not depart from the gist of the present invention.

[0105] Furthermore, in the manufacturing method described above, the semiconductor package 2 may be configured in which no connection terminal portion 90 is formed on the second end portion 62 of the columnar electrode 60. In that case, the process in step 13 is omitted.

[0106] The semiconductor package 2 can adopt the following configuration.

[0107] Figure 10 shows a semiconductor package 2A, which is a modified example of the second embodiment. As shown in Figure 10, semiconductor package 2A is a configuration in which first passive components 210 of different heights are mounted in the sealing space between the first redistribution layer 30 and the second redistribution layer 110. In semiconductor package 2A, the first passive components 210 with lower heights are placed on the outer periphery side of the first semiconductor chip 20 in a cross-sectional view. Also, in semiconductor package 2A, the first passive components 210 with higher heights are placed on the central side of the first semiconductor chip 20 in a cross-sectional view.

[0108] By arranging the first passive component 210 in the semiconductor package 2A as shown in Figure 10, the flow of the sealing resin filling the sealing space during the formation of the sealing resin layer 70 can be prevented from being obstructed by the tall first passive component 210. Therefore, the semiconductor package 2A can reduce the generation of voids and the like after the formation of the sealing resin layer 70.

[0109] Figure 11 shows semiconductor package 2B, which is another modified example of the second embodiment. As shown in Figure 11, semiconductor package 2B has a configuration in which the first passive component 210 and the second semiconductor chip 300 are mounted on the second surface 30b of the first redistribution layer 30. In addition to one or more first passive components 210, semiconductor package 2B can also mount other electronic components such as the second semiconductor chip 300 on the second surface 30b of the first redistribution layer 30. With this configuration, semiconductor package 2B can be made more functional.

[0110] [Third Embodiment] The semiconductor package 3 according to the third embodiment will be described with reference to Figures 12 to 17 as appropriate. Note that components of the semiconductor package 3 that are the same as those in the previously described embodiments are denoted by the same reference numerals, and their descriptions are omitted. Furthermore, components not specifically mentioned can be configured in the same way as in the previously described embodiments.

[0111] As shown in Figure 12, the semiconductor package 3 comprises a transparent substrate 10, a first semiconductor chip 20, a first redistribution layer 30, a first conductive portion 50, a columnar electrode 60, a sealing resin layer 70, a second insulating layer 80, a connection terminal portion 90, and a package substrate 130. The semiconductor package 2 can be mounted on a mounting substrate 500 or the like via the connection terminal portion 90. The semiconductor package 3 differs from the semiconductor package 2 of the second embodiment in that it includes a package substrate 130 instead of a second redistribution layer 110.

[0112] The package substrate 130 can be made of, for example, a printed circuit board (PCB). The package substrate 130 is composed of an insulating portion 131 and an internal wiring portion 132.

[0113] The internal wiring section 132 has a first connection section 132a and a second connection section 132b. The package substrate 130 has a first surface 130a formed on the side facing the first semiconductor chip 20, where the first connection section 132a is exposed, and a second surface 130b formed on the opposite side of the first surface 130a, where the second connection section 132b is exposed. The first connection section 132a only needs to have the connection point with the connection section of the component to be connected (for example, the second end 62 of the columnar electrode 60) exposed. The second connection section 132b only needs to have the connection point with the connection section of the component to be connected (for example, the end of the connection terminal section 90 on the package substrate 130 side) exposed.

[0114] The first connection portion 132a is electrically connected to the second end portion 62 of the columnar electrode 60. The second connection portion 132b is electrically connected to one or more connection terminal portions 90 laid out on the second surface 130b of the package substrate 130. That is, the internal wiring portion 132 is electrically connected to the columnar electrode 60 through the first connection portion 132a and electrically connected to the connection terminal portions 90 laid out on the second surface 130b of the package substrate 130 through the second connection portion 132b. The second connection portion 132b can be formed according to the arrangement position of the connection terminal portions 90. Therefore, the connection terminal portions 90 can be laid out at a desired position on the second surface 130b of the package substrate 130. The connection terminal portions 90 are electrically connected to the first passive component 210 and the first semiconductor chip 20 through the package substrate 130 and the columnar electrode 60.

[0115] The insulating portion 131 can be formed from an insulating resin such as phenolic resin, epoxy resin, or polyimide. The internal wiring portion 132 can be formed with a wiring structure that allows connection between a first connection portion 132a, such as a through-silicon via (TSV), and a second connection portion 132b. The first connection portion 132a and the second connection portion 132b can be formed from metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru), or alloys thereof.

[0116] The semiconductor package 3 of the third embodiment, like the semiconductor package 2 of the second embodiment, allows the columnar electrodes 60 to be placed in the empty space of the first redistribution layer 30 (for example, on the outer periphery side of the second surface 30b of the first redistribution layer 30). Therefore, the semiconductor package 2 can place the connection terminal portion 90 regardless of the arrangement of the first passive component 210 to be mounted. Furthermore, since the semiconductor package 3 does not need to consider the size of the connection terminal portion 90, the size of the columnar electrodes 60 can be reduced. Moreover, the semiconductor package 3 does not need to form the connection terminal portion 90 on the second end 62 of the columnar electrodes 60. Therefore, the semiconductor package 3 can place the connection terminal portion 90 formed on the second surface 130b of the package substrate 130 at a desired position. In addition, the semiconductor package 3, like the semiconductor package 1 of the first embodiment, has a sealing resin layer 70 that functions as a stress relaxation layer, covering the first redistribution layer 30 and a part of the columnar electrodes 60. Therefore, semiconductor package 3 significantly reduces solder stress caused by temperature changes during package mounting, resulting in a package with excellent solder connection reliability during package mounting.

[0117] Next, we will explain the manufacturing method of the semiconductor package 3.

[0118] As shown in Figure 13, the manufacturing method for the semiconductor package 3 includes a sealing material coating step S41 (step 1), a bonding step S42 (step 2), a grinding step S43 (step 3), a through-hole formation step S44 (step 4), an insulating layer formation step S45 (step 5), an exposure step S46 (step 6), a first redistribution layer formation step S47 (step 7), a conductive material coating step S48 (step 8), a placement step S49 (step 9), a first cutting step S50 (step 10), a substrate preparation step S51 (step 11), a substrate mounting step S52 (step 12), a sealing resin layer formation step S53 (step 13), a terminal formation step S54 (step 14), and a second cutting step S55 (step 15). Figures 14A to 14O show diagrams of the configuration of each step (steps 1 to 15) included in the manufacturing process of the semiconductor package 2.

[0119] (Process 1) Step 1 involves performing a sealing material application step S41, as shown in Figure 14A, in which a sealing material S, which functions as a bonding portion B, is applied to the second surface Gb of the glass substrate G that will become the transparent substrate 10, opposite the first surface Ga. The sealing material S is applied so as to include the perimeter of each package and the boundary portion to be separated.

[0120] (Process 2) Step 2 involves a bonding process S42, as shown in Figure 14B, in which the second surface Gb of the glass substrate G coated with the encapsulating material S is joined to the first surface Wa of the semiconductor wafer W which will become the chip substrate 21 of the first semiconductor chip 20, with the two surfaces facing each other. The semiconductor wafer W has on-chip lenses 22, electrodes 23, and other components that constitute the image sensor mounted on the light-receiving area of ​​each package on the first surface Wa. In Step 2, the encapsulating material S is cured to form the bonded portion B.

[0121] (Step 3) Step 3 involves a grinding process S43, in which the second surface Wb of the semiconductor wafer W is back-ground to a predetermined chip size thickness, as shown in Figure 14C.

[0122] (Step 4) Step 4 is a through-hole formation step S44 in which through-holes 24 are formed by etching from the second surface Wb side of the semiconductor wafer W, as shown in Figure 14D. The through-holes 24 can be formed by deep reactive ion etching (DRIE). The through-holes 24 are formed at the electrode formation locations 23 and at the package boundary locations. Due to the formation of the through-holes 24, a portion of the electrode 23 and a portion of the junction B at the boundary are exposed.

[0123] (Step 5) Step 5 is an insulating layer formation step S45 in which a second insulating layer 80 is formed on the entire second surface Wb of the semiconductor wafer W, as shown in Figure 14E. The formation process of the second insulating layer 80 can be carried out by vapor deposition, sputtering, CVD, etc.

[0124] (Step 6) Step 6, as shown in Figure 14F, involves performing an exposure step S46 to remove the second insulating layer 80 located at the bottom of the through hole 24, thereby exposing a portion of the electrode 23 so that the electrode 23 can conduct electricity. The removal of the second insulating layer 80 can be carried out by etching or the like.

[0125] (Step 7) Step 7 involves performing a first redistribution layer formation step S47, in which the first redistribution layer 30 is formed on the second insulating layer 80, as shown in Figure 14G. The first redistribution layer 30 is formed to be electrically connected to the electrode 23 using photolithography and plating methods.

[0126] (Step 8) Step 8 is a conductive material coating step S48 in which a conductive paste is applied as a conductive material to form the first conductive part 50 and the second conductive part 100, as shown in Figure 14H. The first conductive part 50 is formed on the first redistribution layer 30 corresponding to the placement position of the columnar electrode 60. The second conductive part 100 is formed on the first redistribution layer 30 corresponding to the placement position of the first passive component 210. The formation process of the first conductive part 50 and the second conductive part 100 can be carried out by screen printing, inkjet printing, etc., with a mask applied to areas other than the formation positions. In step 8, the conductive material is a conductive paste, but solder may also be used, and different materials may be used for the first conductive part 50 and the second conductive part 100.

[0127] (Step 9) Step 9 is a placement step S49 in which the columnar electrode 60 and the first passive component 210 are placed, as shown in Figure 14I. The placement process for the columnar electrode 60 is similar to the ball mounting method and can be carried out by a process of applying a mask to the area other than the first conductive part 50 so that the first conductive part 50 shown in Figure 14H is exposed, a process of transporting a plurality of copper pins that will become the columnar electrode 60 on the mask and placing the copper pins through the openings of the mask to make contact with each of the first conductive parts 50, and a process of removing the mask and drying, firing, and hardening the first conductive part 50. The end of the columnar electrode 60 that contacts the first conductive part 50 is the first end 61. The first passive component 210 can be mounted on the first redistribution layer 30 by a known mounting process (such as mounting by a mounting device). Step 9 may also include a reflow process of the conductive material. Through reflow processing, the columnar electrode 60 and the first passive component 210 are fixed to the first redistribution layer 30.

[0128] In step 9, the columnar electrode 60 and the first passive component 210 are mounted within the same step, but they may be mounted separately. Furthermore, the reflow process for the conductive material can be performed as a separate step from step 9.

[0129] (Step 10) Step 10, as shown in Figure 14J, performs a first cutting step S50 in which a predetermined location on the semiconductor wafer W is cut to singulate the first semiconductor chip 20 of the semiconductor package 3. This forms individual semiconductor packages 3 before encapsulation.

[0130] (Step 11) Step 11, as shown in Figure 14K, involves preparing the package substrate 130 and performing a substrate preparation step S51 in which a conductive material is applied to the first connection portion 132a corresponding to the mounting position of the semiconductor package 3 before encapsulation. The conductive material can be applied by screen printing, inkjet printing, or the like, with a mask applied to areas other than the formation position. In step 11, the conductive material can be solder or conductive paste, similar to the material used to form the first conductive portion 50.

[0131] (Step 12) Step 12 is a substrate mounting step S52 in which the unsealed semiconductor package 3, which was diced in step 10, is mounted on the first surface 130a of the package substrate 130, as shown in Figure 14L. The unsealed semiconductor package 3 is mounted so that the second end 62 of the columnar electrode 60 is electrically connected to the first connection portion 132a formed on the first surface 130a of the package substrate 130. The unsealed semiconductor package 3 can be mounted on the package substrate 130 by known mounting processes (such as mounting by a mounting device). Step 12 may also include a reflow process of the conductive material. The unsealed semiconductor package 3 is fixed to the package substrate 130 by the reflow process. Note that in step 12, the reflow process of the conductive material can be a separate process.

[0132] (Step 13) Step 13 involves performing a sealing resin layer forming step S53, as shown in Figure 14M, to form a sealing resin layer 70. The sealing resin layer 70 is formed by filling the sealing space with a sealing resin containing a non-conductive filler in epoxy resin or the like. The sealing resin layer 70 is applied so as to cover the first passive component 210. As a result, the sealing resin layer 70 is formed to cover the side surface of the first conductive part 50, the side surface of the columnar electrode 60, the first rewiring layer 30, and the first passive component 210.

[0133] (Step 14) Step 14 is a terminal formation step S54 in which a connection terminal portion 90 is formed on the second connection portion 132b of the package substrate 130, as shown in Figure 14N. The formation process of the connection terminal portion 90 can be carried out by a ball mounting method, a screen printing method, or the like. In step 14, from the viewpoint of ease of mounting, it is preferable that the height position of the contact surface of the connection terminal portion 90 with respect to the mounting substrate 500 be formed to be approximately the same in the thickness direction of the semiconductor package 3.

[0134] (Step 15) Step 15 involves performing a second cutting step S55, which involves cutting a predetermined location in the sealing resin layer 70 to singulate the semiconductor package 2, as shown in Figure 14O. Through these steps, the semiconductor package 3 shown in Figure 12 is manufactured.

[0135] Furthermore, the above-described method for manufacturing the semiconductor package 3 may include steps other than steps 1 to 15 (such as a cleaning step) as needed. In addition, in the method for manufacturing the semiconductor package 3, the order of each step may be appropriately rearranged as long as the configuration and function of the manufactured semiconductor package 2 do not depart from the spirit of the present invention.

[0136] Furthermore, in the manufacturing method described above, the semiconductor package 3 may be configured such that the connection terminal portion 90 is not formed on the second connection portion 132b of the package substrate 130. In that case, the processing in step 14 is omitted.

[0137] The semiconductor package 3 can adopt the following configuration.

[0138] As shown in Figure 15, semiconductor package 3A is a configuration in which a group of first passive components 220, consisting of multiple first passive components 210 of different heights, is mounted on the first redistribution layer 30 in the sealing space between the first redistribution layer 30 and the package substrate 130. In semiconductor package 3A, the first passive components 210 with the lowest height are placed on the outer periphery side of the first semiconductor chip 20 in a cross-sectional view. In addition, semiconductor package 3A places the first passive components 210 with the highest height on the central side of the first semiconductor chip 20 in a cross-sectional view.

[0139] As shown in Figure 16, semiconductor package 3B can mount electronic components on the package substrate 130 in addition to the first redistribution layer 30. Semiconductor package 3 is a configuration in which a second passive component group 240, consisting of multiple second passive components 230 of different heights, is mounted on the package substrate 130, in addition to the configuration shown in Figure 16. In semiconductor package 3B, the first passive component 210 with a low height is placed on the outer periphery side of the first semiconductor chip 20 in a cross-sectional view, and the first passive component 210 with a high height is placed on the central side of the first semiconductor chip 20 in a cross-sectional view. In semiconductor package 3B, the second passive component 230 with a low height is placed on the outer periphery side of the first semiconductor chip 20 in a cross-sectional view, and the second passive component 230 with a high height is placed on the central side of the first semiconductor chip 20 in a cross-sectional view.

[0140] As shown in Figures 15 and 16, the semiconductor packages 3A and 3B have the first passive component 210 and the second passive component 230 arranged as shown, which prevents the flow of the sealing resin filling the sealing space from being obstructed by the tall first passive component 210 during the formation of the sealing resin layer 70. Therefore, the semiconductor packages 3A and 3B can reduce the generation of voids and the like after the sealing resin layer 70 is formed.

[0141] Another modified example of semiconductor package 3C, as shown in Figure 17, has a configuration in which the first passive component 210 and the second semiconductor chip 300 are mounted on the second surface 30b of the first redistribution layer 30, and the second passive component 230 and the third semiconductor chip 400 are mounted on the first surface 130a of the package substrate 130. Semiconductor package 3C can mount one or more first passive components 210, as well as other electronic components such as the second semiconductor chip 300, on the second surface 30b of the first redistribution layer 30. Semiconductor package 3C can mount one or more second passive components 230, as well as other electronic components such as the third semiconductor chip 400, on the second surface 130b of the package substrate 130. With such a configuration, semiconductor package 3B can be made more functional. In this example, the semiconductor package 3C is configured with the second semiconductor chip 300 mounted on the first redistribution layer 30 and the third semiconductor chip 400 mounted on the package substrate 130, but the semiconductor chip may be present in only one form.

[0142] [Turf Module] A camera module equipped with a semiconductor package according to this embodiment will be described.

[0143] Figure 18 shows a camera module 700 equipped with the semiconductor package according to the embodiment of the present invention described above. The camera module 700 shown in Figure 18 is equipped with the semiconductor package 1 of the first embodiment. The camera module 700 is not limited to the semiconductor package 1, but can also be similarly implemented with the semiconductor package 2 of the second embodiment, the semiconductor package 3 of the third embodiment, and modified versions of each embodiment described above.

[0144] The camera module 700 is configured to include an optical unit 610 having at least a lens unit 620. The camera module 700 can be mounted on electronic devices such as cameras and mobile terminals (not shown). The camera module 700 may have other electronic components and mechanical structures besides the optical unit 610.

[0145] The optical unit 610 collects light from the subject and guides it to the first semiconductor chip 20, which is a solid-state image sensor. The optical unit 610 has at least a lens unit 620 consisting of multiple lenses. In addition to the lens unit 620, the optical unit 610 may be configured to include actuators, etc., that can implement at least one of the following functions: autofocus or image stabilization. However, the optical unit 610 may be a simple lens holder that does not have either autofocus or image stabilization functions. In this case, autofocus and image stabilization functions can be implemented by image processing, etc.

[0146] The camera module 700 incorporates semiconductor packages 1, 1A, 1B, 2, 2A, 2B, 3, 3A, 3B, and 3C, which are manufactured at the wafer level. This reduces the mounting area for passive components (such as the first passive component 210) and electronic components such as semiconductor chips that are mounted inside the module. Therefore, if the lens section 620 of the camera module 700 is manufactured at the wafer level, the entire module can be manufactured at the wafer level.

[0147] As described above, the semiconductor package 1 according to the present invention comprises a first semiconductor chip 20 having an electrode 23 formed on the first surface 21a of a chip substrate 21 having a first surface 21a that is the surface to which light is incident and a second surface 21b opposite to the first surface 20a; a through hole 24 extending from the second surface 21b side of the chip substrate 21 to the electrode 23; a first redistribution layer 30 formed on the second surface 21b side of the chip substrate 21 and electrically connected to the electrode 23 via the through hole 24; and one or more first components electrically connected to the first redistribution layer 30. The first redistribution layer 30 includes a passive component 210, a columnar electrode 60 electrically connected to the first redistribution layer 30, and a sealing resin layer 70 covering the second surface 21b of the chip substrate 21. The first redistribution layer 30 has a first surface 30a facing the first semiconductor chip 20 and a second surface 30b opposite to the first surface 30a. The columnar electrode 60 is positioned on the second surface 30b of the first redistribution layer 30. The first passive component 210 is positioned lower than the height of the columnar electrode 60 relative to the second surface 30b of the first redistribution layer 30 and is covered by the sealing resin layer 70.

[0148] The camera module 700 according to the present invention includes the semiconductor package 1 and an optical unit 610 having at least a lens unit 620 positioned on the side of the semiconductor package 1 into which light is incident.

[0149] The semiconductor package 1 has a sealing resin layer 70 that functions as a stress-relieving layer, covering a portion of the first redistribution layer 30 and the columnar electrodes 60. As a result, the semiconductor package 1 experiences significantly reduced solder stress due to temperature changes during package mounting, resulting in a package with excellent solder connection reliability during package mounting. Furthermore, the semiconductor package 1 allows for the mounting of passive components, such as a camera module 700, as first passive components 210 inside the semiconductor package 1. Therefore, the camera module 700 can be made smaller in size, and good electrical characteristics can be obtained by reducing the distance between the semiconductor package 1 and the first passive components 210. [Explanation of symbols]

[0150] 1, 1A, 1B, 2, 2A, 2B, 3, 3A, 3B, 3C semiconductor package, 10 transparent substrates, 20 First semiconductor chip, 21 Chip board, 21a First surface of the chip substrate, 21b Second surface of the chip substrate, 22 on-chip lenses, 23 electrodes, 24 through holes, 30 first redistribution layer, 30a First surface of the first redistribution layer, 30b Second surface of the first redistribution layer, 40 First insulating layer, 50 First conductive part, 60 columnar electrodes, 61 first end; 62 second end; 70 Sealing resin layer, 80 Second insulating layer, 90 Connection terminal section, 100 Second conductive part, 110 second redistribution layer, 110a First surface of the second redistribution layer, 110b Second surface of the second redistribution layer, 120 Third insulating layer, 130 package substrates, 130a Package substrate, first surface, 130b Second side of the package substrate, 131 Insulation part, 132 Internal wiring section, 132a First connection section, 132b Second connection section, 210 First passive component, 220 First passive component group, 230 Second passive component, 240 Second passive component group, 300 second semiconductor chips, 400 third semiconductor chips, 500 mounted circuit boards, 700 camera module, 610 Optical Department, 620 Lens section, B joint, S: Sealing material.

Claims

1. A first semiconductor chip having an electrode formed on the first surface of a chip substrate having a first surface that is the surface on which light is incident and a second surface opposite to the first surface, The through hole extending from the second surface side of the chip substrate to the electrode, A first redistribution layer formed on the second surface side of the chip substrate and electrically connected to the electrode through the through hole, One or more first passive components electrically connected to the first redistribution layer, A columnar electrode electrically connected to the first rewiring layer, The chip substrate includes a sealing resin layer covering the second side, The first redistribution layer has a first surface facing the first semiconductor chip and a second surface opposite to the first surface. The columnar electrode is arranged on the second surface of the first redistribution layer, A semiconductor package in which the first passive component is positioned lower than the height of the columnar electrode with respect to the second surface of the first redistribution layer and is covered with the sealing resin layer.

2. The semiconductor package according to claim 1, wherein the first passive component constitutes a group of first passive components that include multiple types of passive components of different heights, and the first passive component with the lowest height among the group of first passive components is arranged on the outer periphery side of the first semiconductor chip.

3. The semiconductor package according to claim 1, wherein a second semiconductor chip is disposed on the second surface of the first redistribution layer.

4. The columnar electrode has a second rewiring layer formed on the outer surface of the sealing resin layer so as to be electrically connected to the columnar electrode, The semiconductor package according to claim 1, wherein the second redistribution layer has a plurality of connection terminals laid out on the second surface opposite to the first surface which is the first semiconductor chip side.

5. The package substrate has an electrical connection to the columnar electrode, The package substrate is composed of an insulating portion and an internal wiring portion formed inside the insulating portion. The internal wiring portion has a first connection portion formed exposed on the first surface of the package substrate and a second connection portion formed exposed on the second surface of the package substrate opposite to the first surface. The semiconductor package according to claim 1, wherein the internal wiring portion is electrically connected to the columnar electrode through the first connection portion and electrically connected to the connection terminal portion laid out on the second surface of the package substrate through the second connection portion.

6. The semiconductor package according to claim 5, wherein one or more second passive components connected to the internal wiring portion are arranged on the first surface of the package substrate.

7. The second passive component constitutes a second group of passive components that includes multiple types of passive components of different heights. The semiconductor package according to claim 6, wherein, among the second group of passive components, the second passive component with the lowest height is arranged on the outer periphery side of the first semiconductor chip.

8. The semiconductor package according to claim 5, wherein a third semiconductor chip is arranged on the first surface of the package substrate.

9. The semiconductor package according to claim 1, wherein the columnar electrode is bonded to the first redistribution layer via the first conductive portion.

10. The semiconductor package according to claim 9, wherein the elastic modulus of the first conductive portion is lower than the elastic modulus of the columnar electrode.

11. The semiconductor package according to claim 1, wherein the columnar electrode is formed of a metal pin or metal plating.

12. The semiconductor package according to claim 1, wherein the sealing resin layer contains a non-conductive filler.

13. The semiconductor package according to claim 1, wherein the coefficient of linear expansion of the sealing resin layer is greater than or equal to the coefficient of linear expansion of the chip substrate of the first semiconductor chip.

14. The semiconductor package according to claim 9, wherein the first conductive portion is formed of a conductive paste or solder.

15. The semiconductor package according to claim 1, wherein the first semiconductor chip is an image sensor.

16. The semiconductor package according to any one of claims 1 to 15, A camera module comprising an optical section having at least a lens section positioned on the side of the semiconductor package into which light enters.

Images