Semiconductor equipment

Abstract

We provide technology to miniaturize protection circuits. [Solution] The semiconductor device has a semiconductor substrate having an element region and an outer peripheral region arranged around the element region, an upper electrode and a lower electrode. The semiconductor device has an insulating film covering the upper surface of the semiconductor substrate in the outer peripheral region, a semiconductor layer disposed above the insulating film and on which a diode is provided, and an anode electrode. The semiconductor substrate has a first n-type layer disposed within the outer peripheral region and in a range including the corner between the upper surface and the side surface of the semiconductor substrate, a second n-type layer disposed within the outer peripheral region and in contact with the lower electrode, and an n-type drift layer distributed across the element region and the outer peripheral region and disposed between the first n-type layer and the second n-type layer. The anode of the diode of the semiconductor device is electrically connected to the anode electrode, and the cathode of the diode of the semiconductor device is electrically connected to the first n-type layer.

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor devices.

Background Art

[0002] Patent Document 1 discloses a protection circuit for protecting a switching element from a short circuit. This type of protection function may be called DESAT (Desaturation). This protection circuit has a gate drive circuit and a diode for DESAT. The anode of the diode is connected to the gate drive circuit, and the cathode of the diode is connected to the high-potential terminal (for example, collector or drain) of the switching element. The diode prevents a high voltage from being input from the high-potential terminal to the gate drive circuit. The gate drive circuit detects the potential of the high-potential terminal via the diode. The gate drive circuit determines whether an overcurrent is flowing through the switching element from the potential of the high-potential terminal, and turns off the switching element when it is determined that an overcurrent is flowing through the switching element.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, since the diode for DESAT is externally attached to the switching element, the protection circuit becomes large. This specification provides a technology for miniaturizing the protection circuit.

Means for Solving the Problems

[0005] A semiconductor device disclosed herein includes a semiconductor substrate having an element region and an outer peripheral region disposed around the element region; an upper electrode covering the upper surface of the semiconductor substrate within the element region; and a lower electrode covering the lower surface of the semiconductor substrate in a range spanning the element region and the outer peripheral region. The semiconductor device also includes an insulating film covering the upper surface of the semiconductor substrate within the outer peripheral region; a semiconductor layer disposed above the insulating film and having a diode provided on it; and an anode electrode provided on the upper part of the semiconductor substrate. A switching element capable of conducting current between the upper electrode and the lower electrode is provided in the element region. The semiconductor substrate has a first n-type layer disposed within the outer peripheral region and in a range including the corner between the upper surface and the side surface of the semiconductor substrate. The semiconductor substrate also has a second n-type layer disposed within the outer peripheral region, below the first n-type layer, and in contact with the lower electrode. Furthermore, the semiconductor substrate is distributed across the element region and the outer peripheral region, has a lower n-type impurity concentration than the first n-type layer and the second n-type layer, and is arranged between the first n-type layer and the second n-type layer, and in contact with both. The anode of the diode of the semiconductor device is electrically connected to the anode electrode, and the cathode of the diode of the semiconductor device is electrically connected to the first n-type layer.

[0006] In the semiconductor device described above, the diode provided in the semiconductor layer can be used as a diode for DESAT. Since the semiconductor layer on which the diode is provided is integrated with the semiconductor substrate on which the switching element is provided, the protection circuit can be miniaturized. [Brief explanation of the drawing]

[0007] [Figure 1] This is a circuit diagram showing a semiconductor device. [Figure 2] This is a top view of the semiconductor device of Example 1. [Figure 3] This is a cross-sectional view of line III-III in Figure 2, which is a schematic diagram of the semiconductor device of Example 1. [Figure 4] This is an explanatory diagram of the diode structure in Example 1. [Figure 5] This is an explanatory diagram of the diode structure in Example 1. [Figure 6] This is a schematic diagram of the semiconductor device of Example 2. [Figure 7] This is a schematic diagram of the semiconductor device of Example 3. [Figure 8] This is a schematic diagram of a modified semiconductor device. [Modes for carrying out the invention]

[0008] An example semiconductor device disclosed herein may further include a semi-insulating film disposed between the insulating film and the semiconductor layer. The semi-insulating film may also be electrically connected to the upper electrode and the first n-type layer.

[0009] In this configuration, equipotential lines are dispersed within the semi-insulating film. Therefore, mutual influence of electric fields between the semiconductor layer above the semi-insulating film and the semiconductor substrate below the semi-insulating film can be suppressed.

[0010] In one example semiconductor device disclosed herein, the diode may have a p-type first anode layer, an n-type first cathode layer disposed laterally from the first anode layer, and a laminated portion disposed between the first anode layer and the first cathode layer. The laminated portion may have a structure in which a p-type second anode layer and an n-type second cathode layer are stacked vertically. The second anode layer may have a lower p-type impurity concentration than the first anode layer, and the second cathode layer may have a lower n-type impurity concentration than the first cathode layer. The second anode layer may be in contact with the first anode layer on the side surface of the laminated portion, and the second cathode layer may be in contact with the first cathode layer on the side surface of the laminated portion.

[0011] With this configuration, the laminated layers are prone to depletion. In depleted laminated layers, equipotential lines are easily dispersed, which can suppress electric field concentration within the semiconductor layer.

[0012] An example semiconductor device disclosed herein may further include a p-type p-voltage layer disposed within the outer peripheral region and in a range including the upper surface of the semiconductor substrate, and provided between the element region and the first n-type layer. The p-type voltage layer may also be provided at a distance from the element region and at a distance from the first n-type layer. A drift layer may be present between the p-type voltage layer and the element region, and between the p-type voltage layer and the first n-type layer.

[0013] In one example semiconductor device disclosed herein, the semiconductor layer may be provided within a range that overlaps with the p-type breakdown layer when viewed along the thickness direction of the semiconductor substrate.

[0014] This configuration makes it possible to suppress the mutual influence of electric fields between the semiconductor layer above the p-type breakdown layer and the semiconductor substrate below the p-type breakdown layer.

[0015] In one example semiconductor device disclosed herein, a plurality of the p-type breakdown layers may be provided. The semiconductor layer may also have a first semiconductor layer positioned on top of a first p-type breakdown layer among the plurality of p-type breakdown layers, and a second semiconductor layer positioned on top of a second p-type breakdown layer among the plurality of p-type breakdown layers. A first diode provided in the first semiconductor layer and a second diode provided in the second semiconductor layer may be connected in series between the anode electrode and the first n-type layer with the anode facing the anode electrode side.

[0016] This configuration improves the voltage rating of the diode.

[0017] In a semiconductor device according to an example disclosed in this specification, the p-type pressure-resistant layer may have a ring shape surrounding the element region. The diode may include a p-type anode layer provided in the semiconductor layer and an n-type cathode layer provided in the semiconductor layer. The anode layer and the cathode layer may be arranged along the longitudinal direction of the p-type pressure-resistant layer.

[0018] According to this configuration, the breakdown voltage of the diode can be increased.

[0019] In a semiconductor device according to an example disclosed in this specification, the p-type pressure-resistant layer may have a ring shape surrounding the element region. The diode may include a p-type anode layer provided in the semiconductor layer and an n-type cathode layer provided in the semiconductor layer. Further, the pn junction at the boundary between the anode layer and the cathode layer may have a ring shape extending along the p-type pressure-resistant layer.

[0020] The "lateral direction" described in the semiconductor device above refers to a direction parallel to the upper surface of the semiconductor device.

[0021] Figure 1 shows a circuit 101 including a semiconductor device 100 of an embodiment. The semiconductor device 100 has a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 10. Circuit 101 controls the operation of the MOSFET 10. Circuit 101 also functions as a protection circuit that turns off the MOSFET 10 when an overcurrent flows through it. The MOSFET 10 has a source electrode 12, a drain electrode 14, and a gate electrode 16. The drain electrode 14 is connected to a high-potential wiring. The source electrode 12 is connected to a low-potential wiring. The gate electrode 16 is electrically connected to the output terminal of a logic circuit 99 via a resistor 98. The logic circuit 99 controls the potential of the gate electrode 16. The semiconductor device 100 has a diode 52 and an anode electrode 70. The cathode of the diode 52 is electrically connected to the drain electrode 14. The anode of the diode 52 is electrically connected to the anode electrode 70. The anode electrode 70 is also connected to one end of a resistor 95. The other end of resistor 95 is connected to the potential detection terminal of logic circuit 99 via wiring 96. Circuit 101 has a constant current source 97. The power supply terminal of constant current source 97 is connected to the potential Vcc. The output terminal of constant current source 97 is connected to wiring 96.

[0022] Next, the operation of circuit 101 will be explained. Logic circuit 99 switches MOSFET 10 by changing the potential of gate electrode 16. When logic circuit 99 controls the potential of gate electrode 16 to a potential above the gate threshold (hereinafter referred to as the gate-on potential), MOSFET 10 turns on. When MOSFET 10 is on, current flows from the drain electrode 14 to the source electrode 12 through MOSFET 10, and the potentials of the drain electrode 14 and source electrode 12 become approximately equal. In this case, diode 52 turns on, and current flows from constant current source 97 to source electrode 12 through resistor 95, anode electrode 70, diode 52, and MOSFET 10. Therefore, the potential of wiring 96 becomes a low potential, approximately equal to that of source electrode 12. In this case, logic circuit 99 detects this low potential as the potential of wiring 96.

[0023] When the logic circuit 99 controls the potential of the gate electrode 16 to a potential below the gate threshold (hereinafter referred to as the gate-off potential), the MOSFET 10 turns off. When the MOSFET 10 is off, the drain electrode 14 becomes high potential, and the diode 52 turns off. As a result, the wiring 96 is charged by the current supplied from the constant current source 97, and the potential of the wiring 96 rises to potential Vcc. In this case, the logic circuit 99 detects potential Vcc as the potential of the wiring 96.

[0024] When MOSFET 10 is ON, a short circuit may occur in the load to which MOSFET 10 is connected, causing a saturation current to flow through MOSFET 10. When a saturation current flows through MOSFET 10, the potential of the drain electrode 14 becomes high, even though MOSFET 10 is ON. Therefore, when a saturation current is flowing, diode 52 turns OFF, and the potential of wiring 96 becomes potential Vcc. In this case, logic circuit 99 detects potential Vcc as the potential of wiring 96. Thus, logic circuit 99 determines that a saturation current is flowing through MOSFET 10 when the potential of wiring 96 rises to potential Vcc while MOSFET 10 is ON. When logic circuit 99 determines that a saturation current is flowing, it turns OFF MOSFET 10. This protects MOSFET 10 from overcurrent.

[0025] (Example 1) The semiconductor device 100 of Embodiment 1 shown in Figure 2 has a semiconductor substrate 20. Hereinafter, the thickness direction of the semiconductor substrate 20 will be referred to as the z direction, the direction parallel to the upper surface 20a of the semiconductor substrate 20 will be referred to as the x direction, and the direction parallel to the upper surface 20a of the semiconductor substrate 20 and perpendicular to the x direction will be referred to as the y direction. The semiconductor substrate 20 is a SiC substrate. The semiconductor substrate 20 may be made of other semiconductor materials such as silicon or gallium nitride. The semiconductor substrate 20 has an element region 110 and an outer peripheral region 120. When the semiconductor device 100 is viewed from above, the element region 110 is located in the center of the semiconductor substrate 20. Also, when the semiconductor device 100 is viewed from above, the outer peripheral region 120 is located around the element region 110.

[0026] As described above, the semiconductor device 100 has a source electrode 12 and a drain electrode 14. As shown in Figure 3, the source electrode 12 covers the upper surface 20a of the semiconductor substrate 20 within the element region 110. The drain electrode 14 covers the lower surface 20b of the semiconductor substrate 20 in an area that spans both the element region 110 and the outer peripheral region 120. In other words, the drain electrode 14 covers the entire lower surface 20b of the semiconductor substrate 20.

[0027] A MOSFET 10 is provided in the element region 110. The MOSFET 10 can pass current from the drain electrode 14 to the source electrode 12 along the thickness direction (z direction) of the semiconductor substrate 20.

[0028] Multiple trenches 22 are provided on the upper surface 20a of the semiconductor substrate 20 within the element region 110. The semiconductor device 100 has a gate insulating film 24, a gate electrode 16, and an interlayer insulating film 26. The gate insulating film 24 and the gate electrode 16 are arranged within the trenches 22. The gate insulating film 24 covers the inner surface of the trenches 22. The gate electrode 16 is provided inside the gate insulating film 24. The gate electrode 16 is insulated from the semiconductor substrate 20 by the gate insulating film 24. The interlayer insulating film 26 covers the upper surface of the gate electrode 16. The gate electrode 16 is insulated from the source electrode 12 by the interlayer insulating film 26.

[0029] The semiconductor substrate 20 has a source layer 28 and a body layer 30 within the device region 110. The source layer 28 is an n-type layer. The source layer 28 is located in a region including the upper surface 20a. The source layer 28 is in contact with the source electrode 12. The source layer 28 is also in contact with the gate insulating film 24 on the side surface of the corresponding trench 22.

[0030] The body layer 30 is a p-type layer. The body layer 30 is located in a region that includes the upper surface 20a. The body layer 30 is in contact with the source electrode 12. The body layer 30 is also distributed from the side to the bottom of the source layer 28 and is in contact with the source layer 28. Furthermore, the body layer 30 is in contact with the gate insulating film 24 on the side surface of the trench 22 below the source layer 28.

[0031] The semiconductor substrate 20 has a drift layer 32 and a drain layer 34. The drift layer 32 is an n-type layer having a lower n-type impurity concentration than the source layer 28. The drift layer 32 is distributed across the device region 110 and the outer peripheral region 120. Within the device region 110, the drift layer 32 is in contact with the body layer 30. Within the device region 110, the drift layer 32 is in contact with the gate insulating film 24 at the side surface and bottom surface of the trench 22 below the body layer 30. Furthermore, within the outer peripheral region 120, the drift layer 32 is positioned in a range that includes the upper surface 20a.

[0032] The drain layer 34 is an n-type layer having a higher n-type impurity concentration than the drift layer 32. The drain layer 34 is distributed across the device region 110 and the outer peripheral region 120. The drain layer 34 is in contact with the lower surface of the drift layer 32. The drain layer 34 is also located in a region that includes the lower surface 20b of the semiconductor substrate 20. The drain layer 34 is in contact with the drain electrode 14 over the entire area of ​​the lower surface 20b.

[0033] The semiconductor substrate 20 has an outer peripheral n-type layer 40 and a plurality of guard rings 42 within its outer peripheral region 120. The outer peripheral n-type layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 32. The outer peripheral n-type layer 40 is located in a region including the corner 21 between the top surface 20a and the side surface 20c of the semiconductor substrate 20. The side and bottom surfaces of the outer peripheral n-type layer 40 are in contact with the drift layer 32. A drain layer 34 is located below the outer peripheral n-type layer 40. That is, the drift layer 32 is located between the outer peripheral n-type layer 40 and the drain layer 34. The drift layer 32 separates the outer peripheral n-type layer 40 from the drain layer 34.

[0034] Multiple guard rings 42 are p-type layers and are arranged in a region including the upper surface 20a of the semiconductor substrate 20. Multiple guard rings 42 are provided between the device region 110 and the outer n-type layer 40. Multiple guard rings 42 are provided at intervals in the direction from the device region 110 toward the outer n-type layer 40 (i.e., the side surface 20c of the semiconductor substrate 20). The side and bottom surfaces of each guard ring 42 (i.e., around the guard ring 42) are in contact with the drift layer 32. Guard rings 42a to 42c are separated from each other by the drift layer 32. A gap is provided between the guard ring 42a closest to the device region 110 and the body layer 30. Guard ring 42a and the body layer 30 are separated by the drift layer 32. A gap is provided between the guard ring 42c closest to the outer n-type layer 40 and the outer n-type layer 40. Guard ring 42c and the outer n-type layer 40 are separated by the drift layer 32. Each guard ring 42 has a ring shape that surrounds the element region 110 when the semiconductor device 100 is viewed from above.

[0035] The semiconductor device 100 has an insulating film 44 within its outer peripheral region 120. Within the outer peripheral region 120, the insulating film 44 covers an area including the upper surface 20a of the semiconductor substrate 20. Within the outer peripheral region 120, the insulating film 44 covers the body layer 30, the drift layer 32, and the guard ring 42. The insulating film 44 does not cover the outer peripheral n-type layer 40.

[0036] The semiconductor device 100 has a plurality of semiconductor layers 50 within its outer peripheral region 120. Each semiconductor layer 50 is made of polycrystalline Si. Each semiconductor layer 50 may be made of a material such as single-crystal Si or SiC. Each semiconductor layer 50 is placed on an insulating film 44. Each semiconductor layer 50 is insulated from the semiconductor substrate 20 by the insulating film 44. Furthermore, each semiconductor layer 50 is provided within a range that overlaps with the corresponding guard ring 42 when viewed along the z direction. That is, semiconductor layer 50a is provided at a position overlapping with guard ring 42a, semiconductor layer 50b is provided at a position overlapping with guard ring 42b, and semiconductor layer 50c is provided at a position overlapping with guard ring 42c. Each semiconductor layer 50 has a width smaller in the x direction than the corresponding guard ring 42. Each semiconductor layer 50 is provided within the width range of the corresponding guard ring 42 in the x direction.

[0037] Each semiconductor layer 50 is provided with a p-type anode layer 54 and an n-type cathode layer 56. The anode layer 54 and the cathode layer 56 constitute a diode 52. The anode layer 54 is located closer to the element region 110 in the x-direction (hereinafter referred to as the inner circumference side). The cathode layer 56 is located closer to the side surface 20c of the semiconductor substrate 20 in the x-direction (hereinafter referred to as the outer circumference side). The side surface of the anode layer 54 is in contact with the side surface of the cathode layer 56. In the following, the diodes 52 provided in semiconductor layers 50a, 50b, and 50c will be referred to as diodes 52a, 52b, and 52c. The anode layers 54 of diodes 52a, 52b, and 52c will be referred to as anode layers 54a, 54b, and 54c, and the cathode layers 56 of diodes 52a, 52b, and 52c will be referred to as 56a, 56b, and 56c.

[0038] The semiconductor device 100 has an insulating film 46 within its outer peripheral region 120. The insulating film 46 is provided on an insulating film 44. The insulating film 46 covers the semiconductor layers 50a to 50c and the outer peripheral n-type layer 40.

[0039] The semiconductor device 100 has an anode electrode 70. The anode electrode 70 is provided on an insulating film 46. The anode electrode 70 is isolated from the source electrode 12, the drain electrode 14, and the gate electrode 16.

[0040] The semiconductor device 100 has wiring layers 71, 72, 73, and 74 provided on the insulating film 46. Wiring layer 71 connects the anode electrode 70 and the anode layer 54a. Wiring layer 72 connects the cathode layer 56a and the anode layer 54b. Wiring layer 73 connects the cathode layer 56b and the anode layer 54c. Wiring layer 74 connects the cathode layer 56c and the outer n-type layer 40. Therefore, diodes 52a, 52b, and 52c are connected in series between the anode electrode 70 and the outer n-type layer 40 with the anode layer 54 facing the anode electrode 70.

[0041] When MOSFET 10 is turned off, the depletion layer spreads from the body layer 30 to the drift layer 32. The depletion layer extends to the position shown by the dashed line 130 in Figure 3. As shown in Figure 3, the drift layer 32 is not depleted below the outer n-type layer 40. Therefore, regardless of whether MOSFET 10 is on or off, the outer n-type layer 40 is electrically connected to the drain electrode 14 by the drift layer 32 and drain layer 34 below it. For this reason, diodes 52a, 52b, and 52c are connected in series between the anode electrode 70 and the drain electrode 14 with the anode layer 54 facing the anode electrode 70. In Figure 1, the three diodes 52a, 52b, and 52c are shown as diode 52. As described above, diode 52 is connected between the anode electrode 70 and the drain electrode 14 with the anode facing the anode electrode 70. In this way, by configuring diode 52 with three diodes 52a, 52b, and 52c connected in series, the voltage withstand capability of diode 52 is improved.

[0042] In the semiconductor device 100 of Example 1, the MOSFET 10 and the diode 52 are provided within the same semiconductor device 100. Therefore, the circuit can be made smaller than when the diode for DESAT is externally connected to the MOSFET.

[0043] As described above, when MOSFET 10 is turned off, the depletion layer extends from the body layer 30 into the drift layer 32 to the position indicated by the dashed line 130. The guard ring 42 promotes the extension of the depletion layer within the drift layer 32, so the depletion layer extends beyond the outermost guard ring 42c. An electric field is generated within the depleted drift layer 32. Since the guard ring 42 has a high p-type impurity concentration, guard rings 42a, 42b, and 42c are not depleted. Also, when MOSFET 10 is turned off, a reverse voltage is applied to the diode 52, so the semiconductor layers 50a, 50b, and 50c are depleted. As a result, an electric field is generated within the semiconductor layers 50a, 50b, and 50c. Since the depleted semiconductor layers 50a, 50b, and 50c are positioned above the undepleted guard rings 42a, 42b, and 42c, the mutual influence between the electric fields inside the semiconductor layers 50a, 50b, and 50c and the electric fields inside the drift layer 32 can be suppressed. This suppresses electric field concentration within the drift layer 32. In addition, the operation of the diodes 52a, 52b, and 52c becomes more stable.

[0044] In the above-described embodiment 1, when the semiconductor device 100 is viewed from above, the anode layer 54 and the cathode layer 56 were adjacent in the width direction of the guard ring 42 (i.e., the direction from the element region 110 toward the side surface 20c). However, as shown in Figure 4, when the semiconductor device 100 is viewed from above, the anode layer 54 and the cathode layer 56 may be adjacent in the longitudinal direction of the guard ring 42 (i.e., the direction parallel to the side surface 20c). With this configuration, the width of the anode layer 54 and the cathode layer 56 can be increased in the direction perpendicular to the pn junction. Therefore, the breakdown voltage of the diode 52 can be increased.

[0045] In the above-described embodiment 1, as shown in Figure 5, each diode 52 may have a ring shape surrounding the element region 110 when the semiconductor device 100 is viewed from above. That is, the pn junction at the boundary between the anode layer 54 and the cathode layer 56 may have a ring shape extending along the corresponding guard ring 42. With this configuration, the characteristics of the diode 52 are stabilized.

[0046] (Example 2) In the semiconductor device 200 of Example 2 shown in Figure 6, the structure of the upper part of the insulating film 44 differs from that of Example 1. The other configurations of the semiconductor device 200 of Example 2 are the same as those of Example 1. In Figure 6, the same symbols are used for parts that are common with Figure 3.

[0047] In Example 2, the semiconductor layer 50 is placed on the insulating film 44 and is distributed so as to span the top of a plurality of guard rings 42. The semiconductor layer 50 is covered by the insulating film 46. When viewed along the z-direction, the semiconductor layer 50 extends from a position overlapping with the body layer 30 to a position overlapping with the guard ring 42c. A diode 52 is provided in the semiconductor layer 50. The diode 52 has a first anode layer 58, a first cathode layer 60, and a laminated portion 62. The first anode layer 58 is a p-type layer. When viewed along the z-direction, the first anode layer 58 is positioned to overlap with the body layer 30.

[0048] The first cathode layer 60 is an n-type layer. The first cathode layer 60 is positioned so as to overlap with the guard ring 42c when viewed along the z-direction. In the x-direction, the first cathode layer 60 is spaced apart from the first anode layer 58.

[0049] The laminated portion 62 is positioned between the first anode layer 58 and the first cathode layer 60. One side of the laminated portion 62 is in contact with the first anode layer 58, and the other side of the laminated portion 62 is in contact with the first cathode layer 60. The laminated portion 62 has a second anode layer 64 and a second cathode layer 66.

[0050] The second cathode layer 66 is an n-type layer having a lower n-type impurity concentration than the first cathode layer 60. The second cathode layer 66 is in contact with the upper surface of the insulating film 44. In the x-direction, the second cathode layer 66 extends from the first anode layer 58 to the first cathode layer 60. One side of the second cathode layer 66 is in contact with the first anode layer 58, and the other side of the second cathode layer 66 is in contact with the first cathode layer 60.

[0051] The second anode layer 64 is a p-type layer having a lower p-type impurity concentration than the first anode layer 58. The second anode layer 64 is in contact with the upper surface of the second cathode layer 66. In the x-direction, the second anode layer 64 extends from the first anode layer 58 to the first cathode layer 60. One side of the second anode layer 64 is in contact with the first anode layer 58, and the other side of the second anode layer 64 is in contact with the first cathode layer 60.

[0052] The semiconductor device 200 has a wiring layer 76 and a wiring layer 77 provided on an insulating film 46. The wiring layer 76 connects the anode electrode 70 and the first anode layer 58. The wiring layer 77 connects the first cathode layer 60 and the outer n-type layer 40. The diode 52 is connected between the anode electrode 70 and the outer n-type layer 40 with the first anode layer 58 facing the anode electrode 70.

[0053] In Example 2, the MOSFET and the diode for DESAT are also provided within a common semiconductor device 200, allowing for miniaturization of the circuit.

[0054] Furthermore, as explained above, the laminated portion 62 has a structure in which the second anode layer 64 and the second cathode layer 66 are stacked vertically. With this structure, a depletion layer extends from the pn junction in the thickness direction of the second anode layer 64 and the second cathode layer 66. Because the thickness of the second anode layer 64 and the second cathode layer 66 is thin, the entire second anode layer 64 and the second cathode layer 66 (i.e., the laminated portion 62) becomes depleted. In the depleted laminated portion 62, equipotential lines are easily dispersed in the x direction. As a result, electric field concentration is less likely to occur within the semiconductor layer 50. This also makes it less likely for electric field concentration to occur within the drift layer 32.

[0055] (Example 3) In the semiconductor device 300 of Example 3 shown in Figure 7, the structure of the upper part of the insulating film 44 differs from that of Example 2. Otherwise, the semiconductor device 300 of Example 3 is the same as that of Example 2. The semiconductor device 300 has a semi-insulating film 80, an insulating film 82, a semiconductor layer 50, and an insulating film 46 on top of the insulating film 44.

[0056] The semi-insulating film 80 is positioned on the insulating film 44 and is distributed so as to span over the top of the multiple guard rings 42. When viewed along the z-direction, the semi-insulating film 80 extends from a position overlapping with the body layer 30 to the outside of the guard rings 42c. Examples of materials for the semi-insulating film 80 include semi-insulating silicon nitride. The semi-insulating film 80 may also be composed of other materials such as high-resistance polysilicon. The end of the semi-insulating film 80 closer to the element region 110 is connected to the source electrode 12 by a wiring layer 78. The outer end of the semi-insulating film 80 is connected to the outer n-type layer 40 by a wiring layer 77.

[0057] The insulating film 82 is placed on the semi-insulating film 80.

[0058] The semiconductor layer 50 is placed on the insulating film 82 and is distributed so as to span over the top of multiple guard rings 42. The semiconductor layer 50 is covered by the insulating film 46. A diode 52 is provided within the semiconductor layer 50. The structure of the diode 52 is the same as that of Example 2.

[0059] In Example 3, the MOSFET and the diode for DESAT are provided within a common semiconductor device 300, allowing for miniaturization of the circuit.

[0060] Furthermore, in Example 3, the laminated portion 62 becomes depleted, making it less likely for electric field concentration to occur within the semiconductor layer 50. This suppresses electric field concentration within the drift layer 32.

[0061] Furthermore, in Example 3, a small current flows through the semi-insulating film 80 from the drain electrode 14 towards the source electrode 12. As a result, the potential is dispersed within the semi-insulating film 80 in the direction from the element region 110 toward the side surface 20c. Therefore, mutual influence of electric fields between the semiconductor layer 50 located above the semi-insulating film 80 and the drift layer 32 located below the semi-insulating film 80 can be suppressed. This suppresses electric field concentration within the drift layer 32.

[0062] In the above-described embodiments 1 to 3, a MOSFET 10 was provided in the element region 110. However, an IGBT (Insulated Gate Bipolar Transistor) may also be provided in the element region 110. In this case, as shown in Figure 8, the semiconductor substrate 20 has a p-type collector layer 36 in place of the drain layer 34 within the element region 110. The collector layer 36 is in contact with the lower surface of the drift layer 32. The collector layer 36 is located in the area of ​​the semiconductor substrate 20 within the element region 110 that includes the lower surface 20b of the semiconductor substrate 20. Furthermore, when an IGBT is provided in the element region 110, the drain electrode 14 functions as the collector electrode, and the source electrode 12 functions as the emitter electrode.

[0063] In the above-described embodiment 1, the semiconductor device 100 only needs to have at least one set of a guard ring 42 and a semiconductor layer 50 disposed on the guard ring 42.

[0064] In the above-described examples 2 and 3, the semiconductor substrate 20 had multiple guard rings 42. However, the semiconductor substrate 20 only needs to have at least one guard ring 42. Furthermore, in examples 2 and 3, the semiconductor substrate 20 does not need to have any guard rings 42.

[0065] In the above-described embodiments 1 to 3, the guard ring 42 had a ring shape surrounding the element region 110. However, the guard ring 42 does not necessarily have to have a ring shape surrounding the element region 110.

[0066] The structure of the diode 52 in Example 3 described above was the same as that of Example 2. However, the structure of the diode 52 in Example 3 may also be the same as that of Example 1.

[0067] In the above-described embodiments 1 to 3, the semiconductor layer 50 was provided with a diode 52 having a p-type anode layer and an n-type cathode layer. However, the semiconductor layer 50 may also be provided with a Schottky diode or the like.

[0068] In the above-described examples 1 to 3, the source electrode 12 is an example of an "upper electrode". The drain electrode 14 is an example of a "lower electrode". The outer n-type layer 40 is an example of a "first n-type layer". The drain layer 34 is an example of a "second n-type layer". The guard ring 42 is an example of a "p-type pressure-resistant layer".

[0069] The configuration of the semiconductor device disclosed in this specification is described below. (Composition 1) A semiconductor device, A semiconductor substrate having an element region and an outer peripheral region arranged around the element region, An upper electrode covering the upper surface of the semiconductor substrate within the element region, An insulating film covering the upper surface of the semiconductor substrate within the outer peripheral region, A lower electrode that covers the lower surface of the semiconductor substrate in a range spanning the element region and the outer peripheral region, A semiconductor layer is disposed on top of the insulating film and has a diode provided on it, an anode electrode provided on the upper part of the semiconductor substrate, It has, A switching element capable of passing current between the upper electrode and the lower electrode is provided in the element region. The aforementioned semiconductor substrate is A first n-type layer is disposed within the aforementioned outer peripheral region and is located in a range that includes the corner between the upper surface and the side surface of the semiconductor substrate, A second n-type layer is located within the outer peripheral region, below the first n-type layer, and in contact with the lower electrode, An n-type drift layer is distributed across the element region and the outer peripheral region, has a lower n-type impurity concentration than the first n-type layer and the second n-type layer, and is positioned between the first n-type layer and the second n-type layer, and in contact with both. It has, The anode of the diode is electrically connected to the anode electrode. The cathode of the diode is electrically connected to the first n-type layer. Semiconductor equipment. (Configuration 2) The present invention further comprises a semi-insulating film disposed between the insulating film and the semiconductor layer, The semi-insulating film is electrically connected to the upper electrode and the first n-type layer. The semiconductor device described in Configuration 1. (Composition 3) The aforementioned diode, The first anode layer of the p-type, An n-type first cathode layer is arranged with a lateral gap between it and the first anode layer, A laminated portion disposed between the first anode layer and the first cathode layer, It has, The aforementioned laminated portion has a structure in which a p-type second anode layer and an n-type second cathode layer are stacked vertically. The second anode layer has a lower p-type impurity concentration than the first anode layer. The second cathode layer has a lower n-type impurity concentration than the first cathode layer. The second anode layer is in contact with the first anode layer on the side surface of the laminated portion. The second cathode layer is in contact with the first cathode layer on the side surface of the laminated portion. A semiconductor device as described in configuration 1 or 2. (Composition 4) The device further comprises a p-type p-type breakdown voltage layer, which is located within the outer peripheral region, including the upper surface of the semiconductor substrate, and is provided between the element region and the first n-type layer. The p-type breakdown layer is provided at a distance from the element region and at a distance from the first n-type layer. The drift layer exists between the p-type breakdown layer and the element region, and between the p-type breakdown layer and the first n-type layer. A semiconductor device as described in any one of configurations 1 to 3. (Composition 5) The semiconductor device according to configuration 4, wherein the semiconductor layer is provided within a range that overlaps with the p-type breakdown layer when viewed along the thickness direction of the semiconductor substrate. (Composition 6) Multiple p-type pressure-resistant layers are provided, The semiconductor layer comprises a first semiconductor layer positioned on top of a first p-type breakdown layer among the plurality of p-type breakdown layers, and a second semiconductor layer positioned on top of a second p-type breakdown layer among the plurality of p-type breakdown layers. A first diode provided in the first semiconductor layer and a second diode provided in the second semiconductor layer are connected in series between the anode electrode and the first n-type layer, with the anode facing the anode electrode side. The semiconductor device described in Configuration 5. (Composition 7) The p-type breakdown layer has a ring shape surrounding the element region. The diode has a p-type anode layer provided within the semiconductor layer and an n-type cathode layer provided within the semiconductor layer. The anode layer and the cathode layer are arranged along the longitudinal direction of the p-type breakdown layer. The semiconductor device described in Configuration 5. (Composition 8) The p-type breakdown layer has a ring shape surrounding the element region. The diode has a p-type anode layer provided within the semiconductor layer and an n-type cathode layer provided within the semiconductor layer. The pn junction at the boundary between the anode layer and the cathode layer has a ring shape that extends along the p-type pressure-resistant layer. The semiconductor device described in Configuration 5.

[0070] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0071] 12: Source electrode, 14: Drain electrode, 16: Gate electrode, 20: Semiconductor substrate, 20a: Top surface, 20b: Bottom surface, 20c: Side surface, 21: Corner, 32: Drift layer, 34: Drain layer, 40: Outer periphery n-type layer, 42, 42a, 42b, 42c: Guard ring, 44: Insulating film, 50, 50a, 50b, 50c: Semiconductor layer, 52, 52a, 52b, 52 c: diode, 54, 54a, 54b, 54c: anode layer, 56, 56a, 56b, 56c: cathode layer, 58: first anode layer, 60: first cathode layer, 62: laminated portion, 64: second anode layer, 66: second cathode layer, 70: anode electrode, 80: semi-insulating film, 100, 200, 300: semiconductor device, 110: device region, 120: outer periphery region

Claims

1. A semiconductor device, A semiconductor substrate (20) having an element region (110) and an outer peripheral region (120) arranged around the element region, An upper electrode (12) covering the upper surface of the semiconductor substrate within the element region, An insulating film (44) covering the upper surface of the semiconductor substrate within the outer peripheral region, A lower electrode (14) that covers the lower surface of the semiconductor substrate in a range spanning the element region and the outer peripheral region, A semiconductor layer (50) is provided on top of the insulating film and has a diode (52) on it, an anode electrode (70) provided on the upper part of the semiconductor substrate, It has, A switching element (10) capable of passing current between the upper electrode and the lower electrode is provided in the element region. The aforementioned semiconductor substrate is A first n-type layer (40) is disposed within the outer peripheral region and is located in a range that includes the corner between the top surface and the side surface of the semiconductor substrate, A second n-type layer (34) is located within the outer peripheral region, below the first n-type layer, and in contact with the lower electrode, An n-type drift layer (32) is distributed across the element region and the outer peripheral region, has a lower n-type impurity concentration than the first n-type layer and the second n-type layer, and is arranged between the first n-type layer and the second n-type layer, in contact with both. It has, The anode of the diode is electrically connected to the anode electrode. The cathode of the diode is electrically connected to the first n-type layer. Semiconductor equipment.

2. The present invention further comprises a semi-insulating film (80) disposed between the insulating film and the semiconductor layer, The semi-insulating film is electrically connected to the upper electrode and the first n-type layer. The semiconductor device according to claim 1.

3. The aforementioned diode, The first anode layer (58) of the p-type, An n-type first cathode layer (60) is arranged with a lateral gap between it and the first anode layer, A laminated portion (62) disposed between the first anode layer and the first cathode layer, It has, The laminated portion has a structure in which a p-type second anode layer (64) and an n-type second cathode layer (66) are stacked vertically. The second anode layer has a lower p-type impurity concentration than the first anode layer. The second cathode layer has a lower n-type impurity concentration than the first cathode layer. The second anode layer is in contact with the first anode layer on the side surface of the laminated portion. The second cathode layer is in contact with the first cathode layer on the side surface of the laminated portion. The semiconductor device according to claim 1 or 2.

4. The device further comprises a p-type p-type breakdown voltage layer (42) located within the outer peripheral region, including the upper surface of the semiconductor substrate, and provided between the element region and the first n-type layer. The p-type breakdown layer is provided at a distance from the element region and at a distance from the first n-type layer. The drift layer exists between the p-type breakdown layer and the element region, and between the p-type breakdown layer and the first n-type layer. The semiconductor device according to claim 1 or 2.

5. The semiconductor device according to claim 4, wherein the semiconductor layer is provided within a range that overlaps with the p-type breakdown layer when viewed along the thickness direction of the semiconductor substrate.

6. Multiple p-type pressure-resistant layers are provided, The semiconductor layer comprises a first semiconductor layer positioned on top of a first p-type breakdown layer among the plurality of p-type breakdown layers, and a second semiconductor layer positioned on top of a second p-type breakdown layer among the plurality of p-type breakdown layers. A first diode provided in the first semiconductor layer and a second diode provided in the second semiconductor layer are connected in series between the anode electrode and the first n-type layer, with the anode facing the anode electrode side. The semiconductor device according to claim 5.

7. The p-type breakdown layer has a ring shape surrounding the element region, The diode has a p-type anode layer (54) provided within the semiconductor layer and an n-type cathode layer (56) provided within the semiconductor layer. The anode layer and the cathode layer are arranged along the longitudinal direction of the p-type pressure-resistant layer. The semiconductor device according to claim 5.

8. The p-type breakdown layer has a ring shape surrounding the element region, The diode has a p-type anode layer (54) provided within the semiconductor layer and an n-type cathode layer (56) provided within the semiconductor layer. The pn junction at the boundary between the anode layer and the cathode layer has a ring shape that extends along the p-type pressure-resistant layer. The semiconductor device according to claim 5.

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