Semiconductor package with bumps

JP2026089028APending Publication Date: 2026-05-29SK HYNIX INC

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
SK HYNIX INC
Filing Date
2025-11-05
Publication Date
2026-05-29

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  • Figure 2026089028000001_ABST
    Figure 2026089028000001_ABST
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Abstract

To provide a semiconductor package with improved reliability and a method for forming the same. [Solution] The semiconductor package includes a wiring structure 21 having a first surface 21S1 forming a flat surface, a second surface 21S2 facing the first surface, and a first electrode 31 on the first surface. The second surface includes a recessed area superimposed on the first electrode. A first bump 63 is provided on the first surface of the wiring structure and in contact with the first electrode, the first bump including a first conductive pillar 65 on the first electrode and a first solder 64 on the first conductive pillar. The horizontal width W3 of the first conductive pillar may be smaller than the first electrode. A semiconductor chip 91 is placed on the second surface.
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