Semiconductor elements including transistors

Abstract

To improve the integration density and performance of semiconductor devices. [Solution] In the semiconductor device 1, the first and second NMOS transistor structures include NMOS source / drain regions 45 and 30, NMOS channel layers 9a and 9b stacked vertically spaced apart from each other and connected to the NMOS source / drain regions in the first horizontal direction, NMOS gate electrodes 69n and 72n surrounding the NMOS channel layers in the second horizontal direction, NMOS gate dielectric layers 63n and 66n between the NMOS gate electrodes and the NMOS channel layers and between the NMOS source / drain regions, and an NMOS insulating spacer structure disposed between the NMOS gate dielectric layer and the NMOS source / drain region. The NMOS insulating spacer structure of the first NMOS transistor includes an insulating spacer pattern 42, and the second NMOS transistor includes an insulating oxide layer 57.

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a transistor, and more particularly to a semiconductor device capable of increasing integration and improving performance.

Background Art

[0002] While the requirements for high performance, high speed, and / or multifunctionality of semiconductor devices are increasing, the integration of semiconductor devices is also increasing. In manufacturing a semiconductor device with a fine pattern corresponding to the trend of high integration of semiconductor devices, it is required to realize a pattern having a fine width or a fine separation distance.

[0003] In addition, in order to overcome the limitations of operating characteristics due to the size reduction of planar MOSFETs (metal oxide semiconductor FETs), efforts have been made to develop semiconductor devices including transistors having a three-dimensional channel structure, which has become a daily challenge.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device capable of increasing integration and improving performance.

Means for Solving the Problems

[0005] To achieve the objective, the semiconductor device according to the present invention comprises a first NMOS transistor structure and a second NMOS transistor structure, wherein the first NMOS transistor structure includes a first NMOS source / drain region, a plurality of first NMOS channel layers stacked vertically spaced apart from each other and connected to the first NMOS source / drain region in a first horizontal direction orthogonal to the vertical direction, first NMOS gate electrodes surrounding the first NMOS channel layers in the first horizontal direction and a second horizontal direction orthogonal to the vertical direction, a first NMOS gate dielectric layer disposed between the first NMOS gate electrodes and the first NMOS channel layers and between the first NMOS gate electrodes and the first NMOS source / drain region, and a first NMOS insulating spacer structure disposed between the first NMOS gate dielectric layer and the first NMOS source / drain region, and the second NMOS transistor The structure includes a second NMOS source / drain region, a plurality of second NMOS channel layers stacked spaced apart from each other in the vertical direction and connected to the second NMOS source / drain region in the first horizontal direction, second NMOS gate electrodes extending in the second horizontal direction and surrounding the second NMOS channel layers in the second horizontal direction, a second NMOS gate dielectric layer disposed between the second NMOS gate electrodes and the second NMOS channel layers and between the second NMOS gate electrodes and the second NMOS source / drain region, and a second NMOS insulating spacer structure disposed between the second NMOS gate dielectric layer and the second NMOS source / drain region, wherein the first NMOS insulating spacer structure includes an insulating spacer pattern, and the second NMOS insulating spacer structure includes an insulating oxide layer but does not include the same insulating spacer pattern as the insulating spacer pattern.

[0006] Furthermore, the semiconductor device according to the present invention made to achieve the objective comprises a first NMOS transistor structure and a second NMOS transistor structure, the first NMOS transistor structure comprising a first NMOS source / drain region, a plurality of first NMOS channel layers stacked spaced apart from each other in the vertical direction and connected to the first NMOS source / drain region in a first horizontal direction orthogonal to the vertical direction, a first NMOS gate electrode extending in the first horizontal direction and a second horizontal direction orthogonal to the vertical direction and surrounding the first NMOS channel layer in the second horizontal direction, a first NMOS gate dielectric layer disposed between the first NMOS gate electrode and the first NMOS channel layer and between the first NMOS gate electrode and the first NMOS source / drain region, and a first NMOS insulating spacer structure disposed between the first NMOS gate dielectric layer and the first NMOS source / drain region, the second NMOS transistor structure comprising a second NMOS source / drain region, a plurality of first NMOS channel layers stacked spaced apart from each other in the vertical direction and in the first horizontal direction The first NMOS channel layer includes a plurality of second NMOS channel layers connected to the second NMOS source / drain region, a second NMOS gate electrode extending in the second horizontal direction and surrounding each of the second NMOS channel layers in the second horizontal direction, a second NMOS gate dielectric layer disposed between the second NMOS gate electrode and the second NMOS channel layer and between the second NMOS gate electrode and the second NMOS source / drain region, and a second NMOS insulating spacer structure disposed between the second NMOS gate dielectric layer and the second NMOS source / drain region, wherein the first NMOS channel layer includes a first NMOS lower channel layer, a first NMOS intermediate channel layer disposed on the first NMOS lower channel layer, and a first NMOS upper channel layer disposed on the first NMOS intermediate channel layer, and the second NMOS channel layer includes a second NMOS lower channel layer, a second NMOS intermediate channel layer disposed on the second NMOS intermediate channel layer, and the first NMOS gate electrode isThe first NMOS gate electrode includes a first NMOS lower gate portion located directly beneath the first NMOS lower channel layer, a first NMOS intermediate gate portion located directly beneath the first NMOS intermediate channel layer, and a first NMOS upper gate portion located directly beneath the first NMOS upper channel layer, and the second NMOS gate electrode includes a second NMOS lower gate portion located directly beneath the second NMOS lower channel layer, a second NMOS intermediate gate portion located directly beneath the second NMOS intermediate channel layer, and a second NMOS upper gate portion located directly beneath the second NMOS upper channel layer, and the first NMOS insulating spacer structure is located between the first NMOS source / drain region and the first NMOS intermediate gate portion The second NMOS insulating spacer structure includes an intermediate spacer portion, and the second NMOS intermediate spacer portion is positioned between the second NMOS source / drain region and the second NMOS intermediate gate portion. The thickness of the first NMOS intermediate spacer portion is greater than the thickness of the second NMOS intermediate spacer portion, and the thickness of the second NMOS intermediate spacer portion is perpendicular to the surface of the second NMOS gate dielectric layer that contacts the second NMOS intermediate spacer portion within the second NMOS gate dielectric layer, while the thickness of the first NMOS intermediate spacer portion is perpendicular to the surface of the first NMOS gate dielectric layer that contacts or faces the first NMOS intermediate spacer portion within the first NMOS gate dielectric layer.

[0007] Furthermore, the semiconductor device according to the present invention made to achieve the objective comprises a first NMOS transistor structure and a second NMOS transistor structure, wherein the first NMOS transistor structure includes a plurality of first NMOS channel layers spaced apart from each other in the vertical direction, a first NMOS source / drain region connected to the first NMOS channel layers in a first horizontal direction orthogonal to the vertical direction, a first NMOS gate electrode including a first NMOS intermediate electrode portion disposed between the first NMOS channel layers, a first NMOS gate dielectric layer disposed between the first NMOS gate electrode and the first NMOS channel layers, and a first NMOS insulating spacer structure disposed between the first NMOS intermediate electrode portion and the first NMOS source / drain region, and the second NMOS transistor structure The invention comprises a plurality of second NMOS channel layers spaced apart from each other in the vertical direction, a second NMOS source / drain region connected to the second NMOS channel layers in the first horizontal direction, a second NMOS gate electrode including a second NMOS intermediate electrode portion disposed between the second NMOS channel layers, a second NMOS gate dielectric layer disposed between the second NMOS gate electrode and the second NMOS channel layers, and a second NMOS insulating spacer structure disposed between the second NMOS intermediate electrode portion and the second NMOS source / drain region, wherein the first NMOS insulating spacer structure includes an insulating spacer pattern, and the second NMOS insulating spacer structure includes a second NMOS insulating oxide layer without including the same insulating spacer pattern as the insulating spacer pattern. [Effects of the Invention]

[0008] The semiconductor device according to the present invention provides first and second NMOS transistor structures that include source / drain regions having different widths and different insulating spacer structures. Therefore, it is possible to provide a first NMOS transistor that can prevent or minimize leakage current caused by the GIDL (Gate-Induced Drain Leakage) phenomenon, and a second NMOS transistor that includes a source / drain region that can be reliably formed. [Brief explanation of the drawing]

[0009] [Figure 1a] This is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 1b] This is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 3a] This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 3b] This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 5] This is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 6a] This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 6b] This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 8] This is an exemplary partially enlarged cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 9] This is an exemplary partially enlarged cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 10] This is an exemplary partially enlarged cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 11] This is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 12] This is a cross-sectional view for explaining a semiconductor device according to an embodiment of the present invention. [Figure 13] This is a cross-sectional view for explaining a semiconductor device according to an embodiment of the present invention. [Figure 14] This is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 15] This is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 16a] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 16b] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 17a] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 17b] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 18] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 19] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 20] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 21] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 22] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 23] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 24a] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 24b] This is a cross-sectional view for explaining a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 25a]This is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 25b] This is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 25c] This is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 25d] This is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 26a] This is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 26b] This is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0010] Next, specific examples of embodiments for implementing the semiconductor device according to the present invention will be described with reference to the drawings.

[0011] In the following, terms such as “upper,” “middle,” and “lower” may be replaced with other terms, such as “first,” “second,” and “third,” and used to describe the components of the specification. Terms such as "first," "second," and "third" may be used to describe various components, but the components are not limited by these terms, and "first component" may be named "second component." In the specification, terms such as "bottom," "top," "upper end," and "lower end" may be terms that are explained based on the drawings.

[0012] In this specification, "NMOS transistor" means N-channel MOSFET (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor), and "PMOS transistor" means P-channel MOSFET (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor). In this specification, in order to clearly distinguish and explain the components of an NMOS transistor and a PMOS transistor, the gate, channel layer, and source / drain, which are components of an "NMOS transistor," will be referred to as the NMOS gate, NMOS channel layer, and NMOS source / drain, respectively, and the gate, channel layer, and source / drain, which are components of a "PMOS transistor," will be referred to as the PMOS gate, PMOS channel layer, and PMOS source / drain, respectively. In this specification, "transistor structure" means a structure that includes a "transistor".

[0013] In this specification, in order to distinguish between the components of the "first NMOS transistor structure," the "second NMOS transistor structure," the "first PMOS transistor structure," and the "first PMOS transistor structure," the components of the "first NMOS transistor structure" are referred to as the first NMOS components, the components of the "second NMOS transistor structure" are referred to as the second NMOS components, the components of the "first PMOS transistor structure" are referred to as the first PMOS components, and the components of the "second PMOS transistor structure" are referred to as the second PMOS components.

[0014] A semiconductor device according to an embodiment of the present invention will be described with reference to Figures 1a, 1b, 2, 3a, 3b, 4, 5, 6a, 6b, and 7. In Figures 1a, 1b, 2, 3a, 3b, 4, 5, 6a, 6b, and 7, Figure 1a is a plan view showing a first region C1 of a semiconductor device according to an embodiment of the present invention, Figure 1b is a plan view showing a second region C2 of a semiconductor device according to an embodiment of the present invention, Figure 2 is a cross-sectional view showing a region cut along the line I-I' in Figure 1a and the line II-II' in Figure 1b, Figure 3a is an enlarged portion of the part represented by "A" in Figure 2, and Figure 3b is an enlarged portion of the part represented by "B" in Figure 2. These are enlarged views. Figure 4 is a cross-sectional view showing the region cut along the line III-III' in Figure 1a and the line IV-IV' in Figure 1b. Figure 5 is a cross-sectional view showing the region cut along the line V-V' in Figure 1a and the line VI-VI' in Figure 1b. Figure 6a is a partially enlarged view of the portion indicated by "C" in Figure 5. Figure 6b is a partially enlarged view of the portion indicated by "D" in Figure 5. Figure 7 is a cross-sectional view showing the region cut along the line VII-VII' in Figure 1a and the line VIII-VIII' in Figure 1b.

[0015] Referring to Figures 1a, 1b, 2, 3a, 3b, 4, 5, 6a, 6b, and 7, the semiconductor element 1 according to an embodiment of the present invention includes a first region C1 and a second region C2. The first region C1 includes the first NMOS transistor region N1, and the second region C2 includes the second NMOS transistor region N2. The first region C1 further includes the first PMOS transistor region P1, and the second region C2 further includes the second PMOS transistor region P2.

[0016] The first NMOS transistor region N1 includes the first NMOS transistor structure nTR1S, and the second NMOS transistor region N2 includes the second NMOS transistor structure nTR2S. The first PMOS transistor region P1 includes the first PMOS transistor structure pTR1S, and the second PMOS transistor region P2 includes the second PMOS transistor structure pTR2S. The first NMOS transistor region N1, the second NMOS transistor region N2, the first PMOS transistor region P1, and the second PMOS transistor region P2 further include a substrate 3, active regions (3a, 3b, 3c, 3d) on the substrate 3, and element isolation regions 15 arranged on the side surfaces of the active regions (3a, 3b, 3c, 3d) on the substrate 3.

[0017] Substrate 3 is a semiconductor substrate, for example, a single-crystal silicon substrate. Each of the active regions (3a, 3b, 3c, 3d) has a shape that protrudes perpendicularly from the substrate 3. The active regions (3a, 3b, 3c, 3d) include semiconductor materials, such as single-crystal silicon. The element isolation region 15 contains an insulating material such as silicon oxide.

[0018] The first NMOS transistor region N1 includes the first active region 3a of the active regions (3a, 3b, 3c, 3d), the second NMOS transistor region N2 includes the second active region 3b of the active regions (3a, 3b, 3c, 3d), the first PMOS transistor region P1 includes the third active region 3c of the active regions (3a, 3b, 3c, 3d), and the second PMOS transistor region P1 includes the fourth active region 3d of the active regions (3a, 3b, 3c, 3d). The first NMOS transistor structure (indicated as nTR1S in Figure 3a) includes a first NMOS source / drain region 45, a first NMOS channel layer 9a, a first NMOS gate electrode 69n, a first NMOS gate dielectric layer 63n, and a first NMOS insulating spacer structure 41.

[0019] The first NMOS source / drain regions 45 are separated from each other in the first horizontal direction X. Each of the first NMOS source / drain regions 45 has an N-type conductivity. Each of the first NMOS source / drain regions 45 contains an epitaxially grown semiconductor material. For example, each of the first NMOS source / drain regions 45 contains silicon.

[0020] The first NMOS channel layer 9a is located between the first NMOS source / drain regions 45. The first NMOS channel layer 9a is located on the first active region 3a. The first NMOS channel layers 9a are stacked spaced apart from each other in the vertical direction Z, which is orthogonal to the first horizontal direction X. The first NMOS channel layer 9a is connected to the first NMOS source / drain region 45. The first NMOS channel layer 9a contains a semiconductor material, such as single-crystal silicon. The first NMOS channel layer 9a includes a first NMOS lower channel layer 9a1 located on the first active region 3a, a first NMOS intermediate channel layer 9a2 located on the first NMOS lower channel layer 9a1, and a first NMOS upper channel layer 9a3 located on the first NMOS intermediate channel layer 9a2. In Figures 2 and 3a, the first NMOS channel layer 9a is shown as three, but the embodiment is not limited to this. For example, the first NMOS channel layer 9a may include four or more channel layers stacked spaced apart from each other in the vertical direction Z.

[0021] The first NMOS gate electrode 69n extends in the second horizontal direction Y, which is orthogonal to the first horizontal direction X and the vertical direction Z, and surrounds the first NMOS channel layer 9a, respectively. The first NMOS gate electrode 69n surrounds the first NMOS channel layer 9a, extends in the second horizontal direction Y, and is positioned on the first active region 3a and the element isolation region 15. The first NMOS gate electrode 69n includes the first NMOS lower gate portion (69n_1) directly beneath the first NMOS lower channel layer 9a1, the first NMOS intermediate gate portion (69n_2) directly beneath the first NMOS intermediate channel layer 9a2, the first NMOS upper gate portion (69n_3) directly beneath the first NMOS upper channel layer 9a3, and the first NMOS uppermost gate portion (69n_4) on the first NMOS upper channel layer 9a3. The first NMOS lower gate portion (69n_1) is located between the first active region 3a and the first NMOS lower channel layer 9a1, the first NMOS intermediate gate portion (69n_2) is located between the first NMOS lower channel layer 9a1 and the first NMOS intermediate channel layer 9a2, and the first NMOS upper gate portion (69n_3) is located between the first NMOS intermediate channel layer 9a2 and the first NMOS upper channel layer 9a3.

[0022] The first NMOS gate dielectric layer 63n is positioned between the first NMOS source / drain region 45 and the first NMOS gate electrode 69n, and extends between the first NMOS gate electrode 69n and the first NMOS channel layer 9a. The first NMOS gate dielectric layer 63n contains a high dielectric material. High dielectric materials are dielectrics that have a dielectric constant higher than that of silicon oxide.

[0023] The first NMOS insulating spacer structure 41 is placed between the first NMOS gate dielectric layer 63n and the first NMOS source / drain region 45. The first NMOS insulating spacer structure 41 is superimposed perpendicularly with the first NMOS channel layer 9a. The first NMOS insulating spacer structure 41 includes an insulating spacer pattern 42. The insulating spacer pattern 42 is positioned between the first NMOS source / drain regions 45. The insulating spacer pattern 42 is superimposed perpendicularly with the first NMOS channel layer 9a. The insulating spacer pattern 42 includes an insulating nitride. For example, the insulating spacer pattern 42 includes silicon nitride.

[0024] The first NMOS source / drain region 45 includes the (1-1) NMOS source / drain region (45_1) and the (1-2) NMOS source / drain region (45_2), which are separated from each other in the first horizontal direction X. The insulating spacer pattern 42 includes the (1-1) insulating spacer pattern 42, which is positioned between the (1-1) NMOS source / drain region (45_1) and the first NMOS gate dielectric layer 63n, and the (1-2) insulating spacer pattern (42_2), which is positioned between the (1-2) NMOS source / drain region (45_2) and the first NMOS gate dielectric layer 63n, within the first NMOS source / drain region 45. The (1-1) insulating spacer pattern (42_1) is in contact with the (1-1) NMOS source / drain region (45_1), and the (1-2) insulating spacer pattern (42_2) is in contact with the (1-2) NMOS source / drain region (45_2).

[0025] In at least one of the first NMOS channel layers 9a, the maximum thickness in the vertical Z direction of the portion that overlaps perpendicularly with the first NMOS gate electrode 69n is smaller than the maximum thickness in the vertical Z direction of the portion that overlaps perpendicularly with the insulating spacer pattern 42. In at least one of the first NMOS channel layers 9a, the maximum thickness in the vertical Z direction of the portion that overlaps perpendicularly with the first NMOS gate electrode 69n is smaller than the maximum thickness in the vertical Z direction of the portion that does not overlap perpendicularly with the first NMOS gate electrode 69n. For example, the first NMOS intermediate channel layer 9a2 has a first maximum thickness in the portion that overlaps perpendicularly with the first NMOS intermediate gate portion (69n_2), and a second maximum thickness that is greater than the first maximum thickness in the portion that does not overlap perpendicularly with the first NMOS intermediate gate portion (69n_2). The structure of the first NMOS channel layer 9a in this form increases the thickness of the first NMOS lower gate portion (69n_1), the first NMOS intermediate gate portion (69n_2), and the first NMOS upper gate portion (69n_3), thereby improving the electrical characteristics of the first NMOS gate electrode 69n. Therefore, the performance of semiconductor device 1 can be improved. In the first NMOS channel layer 9a, the thickness refers to the thickness in the vertical direction Z.

[0026] The first NMOS transistor structure nTR1S further includes a first NMOS insulating oxide layer 60. The first NMOS insulating oxide layer 60 contains silicon oxide. The minimum thickness of the insulating spacer pattern 42 is greater than the minimum thickness of the first NMOS insulating oxide layer 60. Here, the thickness of the insulating spacer pattern 42 is the thickness in the first horizontal direction X, and the thickness of the first NMOS insulating oxide layer 60 is the thickness in the direction perpendicular to the surface of the first NMOS gate dielectric layer 63n that is in contact with the first NMOS insulating oxide layer 60.

[0027] The first NMOS insulating oxide layer 60 includes a first NMOS lower insulating oxide layer (60_1) and a first NMOS upper insulating oxide layer (60_2). The first NMOS upper insulating oxide layer (60_2) is in contact with the outer surface of the first NMOS gate dielectric layer 63n located on the side surface of the first NMOS uppermost gate portion (69n_4), and with the lower surface of the first NMOS gate layer 63n located below the lower surface of the first NMOS uppermost gate portion (69n_4). The portion of the first NMOS lower insulating oxide layer (60_1) located beneath each of the first NMOS channel layers 9a includes a spacer portion (60_1a) and an interface portion (60_1b). The interface portion (60_1b) is an interface oxide layer.

[0028] The spacer portion (60_1a) is placed between the insulating spacer pattern 42 and the first NMOS gate dielectric layer 63n. The interface portion (60_1b) extends from the spacer portion (60_1a), is superimposed perpendicularly on the first NMOS gate electrode 69n, and contacts the first NMOS gate dielectric layer 63n. For example, the spacer portion (60_1a) includes a portion positioned between the (1-1) insulating spacer pattern (42_1) and the first NMOS gate dielectric layer 63n, and a portion positioned between the (1-2) insulating spacer pattern (42_2) and the first NMOS gate dielectric layer 63n, and the interface portion (60_1b) includes a portion that contacts the lower surface of the first NMOS gate dielectric layer 63n located below the lower surfaces of the first NMOS lower gate portion (69n_1), the first NMOS intermediate gate portion (69n_2), and the first NMOS upper gate portion (69n_3), and a portion that contacts the upper surface of the first NMOS gate dielectric layer 63n located on the upper surfaces of the first NMOS lower gate portion (69n_1), the first NMOS intermediate gate portion (69n_2), and the first NMOS upper gate portion (69n_3).

[0029] For example, as shown in Figure 3a, when viewed with respect to the first NMOS intermediate gate portion (69n_2), the spacer portion (60_1a) includes the portion located between the (1-1) insulating spacer pattern (42_1) and the first NMOS gate dielectric layer 63n, and the portion located between the (1-2) insulating spacer pattern (42_2) and the first NMOS gate dielectric layer 63n. The interface portion (60_1b) extends from the spacer portion (60_1a) and includes the portion located between the first NMOS lower channel layer 9a1 and the first NMOS gate dielectric layer 63n, and the portion located between the first NMOS intermediate channel layer 9a2 and the first NMOS gate dielectric layer 63n.

[0030] As shown in Figure 3a, when viewed with respect to the (1-1) insulating spacer pattern (42_1) and one spacer portion (60_1a) in contact with the (1-1) insulating spacer pattern (42_1), one spacer portion (60_1a) includes an intermediate portion (60_1a_M) located midway between the (1-1) insulating spacer pattern (42_1) and the first NMOS gate dielectric layer 63n, a lower portion (60_1a_L) extending downward from the intermediate portion (60_1a_M) and having a maximum thickness greater than the thickness of the intermediate portion (60_1a_M), and an upper portion (60_1a_U) extending upward from the intermediate portion (60_1a_M) and having a maximum thickness greater than the thickness of the first intermediate portion (60_1a_M).

[0031] In the first NMOS lower insulating oxide layer (60_1), the thickness of each spacer portion (60_1a) is greater than the thickness of each interface portion (60_1b). In the first NMOS lower insulating oxide layer (60_1), the thickness of each portion of the first NMOS lower insulating oxide layer (60_1) refers to the thickness in the direction perpendicular to the surface of the first NMOS gate dielectric layer 63n that is in contact with the first NMOS lower insulating oxide layer (60_1). The first NMOS insulating spacer structure 41 includes an insulating spacer pattern 42 and a spacer portion (60_1a) of the first NMOS lower insulating oxide layer (60_1).

[0032] The first NMOS source / drain region 45, the first NMOS channel layer 9a, the first NMOS gate electrode 69n, and the first NMOS gate dielectric layer 63n constitute the first NMOS transistor (reference numerals 45, 9a, 69n, and 63n in Figure 3a), and the first NMOS insulating spacer structure 41 can improve the performance of the first NMOS transistor (reference numerals 45, 9a, 69n, and 63n in Figure 3a). The first NMOS insulating spacer structure 41 can increase the separation distance between the drain region of the first NMOS source / drain region 45 and the first NMOS gate electrode 69n, thereby preventing or minimizing the leakage current of the first NMOS transistor (reference numerals 45, 9a, 69n, and 63n in Figure 3a) caused by the GIDL (Gate-Induced Drain Leakage) phenomenon.

[0033] The interface portion (60_1b) of the first NMOS lower insulating oxide layer (60_1) is positioned between the first NMOS channel layer 9a and the first NMOS gate dielectric layer 63n formed of high dielectric material, thereby preventing interface defects that may occur due to contact between the first NMOS channel layer 9a and the first NMOS gate dielectric layer 63n. Therefore, the interface portion (60_1b) of the lower insulating oxide layer (60_1) of the first NMOS can improve the performance and reliability of the first NMOS transistor (reference numerals 45, 9a, 69n, and 63n in Figure 3a).

[0034] The second NMOS transistor structure (indicated as nTR2S in Figure 3b) includes a second NMOS source / drain region 30, a second NMOS channel layer 9b, a second NMOS gate electrode 72n, and a second NMOS gate dielectric layer 66n. The second NMOS source / drain regions 30 are separated from each other in the first horizontal direction X. Each of the second NMOS source / drain regions 30 has an N-type conductivity. The second NMOS source / drain region 30 is formed from the same material as the first NMOS source / drain region 45. In the first horizontal direction X, the width of each of the second NMOS source / drain regions 30 is greater than the width of each of the first NMOS source / drain regions 45. The maximum width of the second NMOS source / drain region 30 in the first horizontal direction X is greater than the maximum width of the first NMOS source / drain region 45 in the first horizontal direction X.

[0035] The second NMOS channel layer 9b is located between the second NMOS source / drain regions 30. The second NMOS channel layer 9b is located on the second active region 3b. The second NMOS channel layers 9b are stacked spaced apart from each other in the vertical Z direction. The second NMOS channel layer 9b is connected to the second NMOS source / drain region 30. The second NMOS channel layer 9b contains a semiconductor material, such as single-crystal silicon. The second NMOS channel layer 9b is located at the same level as the first NMOS channel layer 9a. The second NMOS channel layer 9b includes a second NMOS lower channel layer 9b1 on the second active region 3b, a second NMOS intermediate channel layer 9b2 on the second NMOS lower channel layer 9b1, and a second NMOS upper channel layer 9b3 on the second NMOS intermediate channel layer 9b2. In Figures 2 and 3b, the second NMOS channel layer 9b is shown as three, but the embodiment is not limited to this. For example, the second NMOS channel layer 9b may include four or more channel layers stacked spaced apart from each other in the vertical direction Z.

[0036] The width of the first horizontal X of the second NMOS channel layer located at the first level of the second NMOS channel layer 9b is greater than the width of the first horizontal X of the first NMOS channel layer located at the first level of the first NMOS channel layer 9a. For example, in the first horizontal direction X, the width of the second NMOS intermediate channel layer 9b2 is greater than the width of the first NMOS intermediate channel layer 9a2, which is located at the same level as the second NMOS intermediate channel layer 9b2. The second NMOS gate electrode 72n is extended in the second horizontal direction Y, surrounding the second NMOS channel layer 9b. The second NMOS gate electrode 72n surrounds the second NMOS channel layer 9b and is extended in the second horizontal direction Y, positioned on the second active region 3b and the element isolation region 15.

[0037] The second NMOS gate electrode 72n includes the second NMOS lower gate portion (72n_1) directly below the second NMOS lower channel layer 9b1, the second NMOS intermediate gate portion (72n_2) directly below the second NMOS intermediate channel layer 9b2, the second NMOS upper gate portion (72n_3) directly below the second NMOS upper channel layer 9b3, and the second NMOS uppermost gate portion (74n_4) on the second NMOS upper channel layer 9b3. The second NMOS lower gate portion (72n_1) is located between the second active region 3b and the second NMOS lower channel layer 9b1, the second NMOS intermediate gate portion (72n_2) is located between the second NMOS lower channel layer 9b1 and the second NMOS intermediate channel layer 9b2, and the second NMOS upper gate portion (72n_3) is located between the second NMOS intermediate channel layer 9b2 and the second NMOS upper channel layer 9b3.

[0038] The second NMOS gate dielectric layer 66n is positioned between the second NMOS source / drain region 30 and the second NMOS gate electrode 72n, and extends between the second NMOS gate electrode 72n and the second NMOS channel layer 9b. The second NMOS gate dielectric layer 66n contains a high dielectric material. In at least one of the second NMOS channel layers 9b, the maximum thickness in the vertical Z direction of the portion that overlaps perpendicularly with the second NMOS gate electrode 72n is smaller than the maximum thickness in the vertical Z direction of the portion that does not overlap perpendicularly with the second NMOS gate electrode 72n. In the second NMOS channel layer 9b, the thickness refers to the thickness in the vertical direction Z.

[0039] The second NMOS transistor structure nTR2S further includes a second NMOS insulating oxide layer 57. The second NMOS insulating oxide layer 57 contains silicon oxide. The second NMOS insulating oxide layer 57 includes a second NMOS lower insulating oxide layer (57_1) and a second NMOS upper insulating oxide layer (57_2). The second NMOS upper insulating oxide layer (57_2) is in contact with the outer surface of the second NMOS gate dielectric layer 66n located on the side surface of the second NMOS uppermost gate portion (72n_4) and with the lower surface of the second NMOS gate dielectric layer 66n located below the lower surface of the second NMOS uppermost gate portion (72n_4). The portion of the second NMOS lower insulating oxide layer (57_1) located beneath each of the second NMOS channel layers 9b includes a spacer portion (57_1a) and an interface portion (57_1b). The interface portion (57_1b) is an interface oxide layer.

[0040] The spacer portion (57_1a) is placed between the second NMOS source / drain region 30 and the second NMOS gate dielectric layer 66n. The spacer portion (57_1a) is in contact with the second NMOS source / drain region 30 and the second NMOS gate dielectric layer 66n. The spacer portion (57_1a) is defined as the second NMOS insulating spacer structure (57_1a). The interface portion (57_1b) extends from the spacer portion (57_1a) and contacts the second NMOS gate dielectric layer 66n, which is superimposed perpendicularly on the second NMOS gate electrode 72n. The interface portion (57_1b) includes a portion that contacts the lower surface of the second NMOS gate dielectric layer 66n located below the lower surfaces of the second NMOS lower gate portion (72n_1), the second NMOS intermediate gate portion (72n_2), and the second NMOS upper gate portion (72n_3), and a portion that contacts the upper surface of the second NMOS gate dielectric layer 66n located on the upper surfaces of the second NMOS lower gate portion (72n_1), the second NMOS intermediate gate portion (72n_2), and the second NMOS upper gate portion (72n_3). The interface portion (57_1b) extends from the spacer portion (57_1a).

[0041] As shown in Figure 3b, when viewed with respect to the second NMOS intermediate gate portion (72n_2), the interface portion (57_1b) includes the portion located between the second NMOS lower channel layer 9b1 and the second NMOS gate dielectric layer 66n, and the portion located between the second NMOS intermediate channel layer 9b2 and the second NMOS gate dielectric layer 66n. As shown in Figure 3b, when viewed with respect to any one of the spacer portions (57_1a) as the center, the spacer portion (57_1a) includes an intermediate portion (57_1a_M) located in the middle, a lower portion (57_1a_L) extending downward from the intermediate portion (57_1a_M) and having a maximum thickness greater than the thickness of the intermediate portion (57_1a_M), and an upper portion (57_1a_U) extending upward from the intermediate portion (57_1a_M) and having a maximum thickness greater than the thickness of the first intermediate portion (57_1a_M).

[0042] In the second NMOS lower insulating oxide layer (57_1), the thickness of each spacer portion (57_1a) is greater than the thickness of each interface portion (57_1b). In the second NMOS lower insulating oxide layer (57_1), the thickness of each portion of the second NMOS lower insulating oxide layer (57_1) refers to the thickness in the direction perpendicular to the surface of the second NMOS gate dielectric layer 66n that is in contact with the second NMOS lower insulating oxide layer (57_1).

[0043] The second NMOS source / drain region 30, the second NMOS channel layer 9b, the second NMOS gate electrode 72n, and the second NMOS gate dielectric layer 66n constitute the second NMOS transistor (reference numerals 30, 9b, 72n, and 66n in Figure 3b), and the spacer portion (57_1a), i.e., the second NMOS insulating spacer structure (57_1a), can improve the performance of the second NMOS transistor (reference numerals 30, 9b, 72n, and 66n in Figure 3b). The second NMOS insulating spacer structure (57_1a) can increase the separation distance between the drain region of the second NMOS source / drain region 30 and the second NMOS gate electrode 72n, thereby preventing or minimizing the leakage current of the second NMOS transistor (indicated by 30, 9b, 72n, and 66n in Figure 3b) caused by the GIDL (Gate-Induced Drain Leakage) phenomenon.

[0044] By ensuring that the second NMOS transistor structure nTR2S does not include the insulating spacer pattern 42 of the first NMOS insulating spacer structure 41, it is possible to reliably form a second NMOS source / drain region 30 that has a wider width than the first NMOS source / drain region 45. Therefore, the reliability of the second NMOS source / drain region 30, which has a width greater than the first NMOS source / drain region 45, can be increased. The interface portion (57_1b) of the second NMOS lower insulating oxide layer (57_1) is positioned between the second NMOS channel layer 9b and the second NMOS gate dielectric layer 66n formed of high dielectric material, thereby preventing interface defects that occur when the second NMOS channel layer 9b and the second NMOS gate dielectric layer 66n are in contact. Therefore, the interface portion (57_1b) of the second NMOS lower insulating oxide layer (57_1) can improve the performance and reliability of the second NMOS transistors (indicated by 30, 9b, 72n, and 66n in Figure b).

[0045] The first PMOS transistor structure (indicated as pTR1S in Figure 6a) includes a first PMOS source / drain region 128, a first PMOS channel layer 9c, a first PMOS gate electrode 69p, and a first PMOS gate dielectric layer 63p. The first PMOS source / drain regions 128 are separated from each other in the first horizontal direction X. Each of the first PMOS source / drain regions 128 has a P-type conductivity. Each of the first PMOS source / drain regions 128 contains an epitaxially grown semiconductor material. For example, each of the first PMOS source / drain regions 128 may contain at least one of germanium (Ge) and silicon-germanium (SiGe).

[0046] The first PMOS channel layer 9c is located between the first PMOS source / drain regions 128. The first PMOS channel layer 9c is located on the third active region 3c. The first PMOS channel layers 9c are stacked spaced apart from each other in the second vertical direction Z. The first PMOS channel layer 9c is connected to the first PMOS source / drain region 128. The first PMOS channel layer 9c contains a semiconductor material, such as single-crystal silicon. The first PMOS channel layer 9c includes a first PMOS lower channel layer 9c1 on the third active region 3c, a first PMOS intermediate channel layer 9c2 on the first PMOS lower channel layer 9c1, and a first PMOS upper channel layer 9c3 on the first PMOS intermediate channel layer 9c2. In Figures 5 and 6a, the first PMOS channel layer 9c is shown as three, but the embodiments are not limited to this. For example, the first PMOS channel layer 9c may include four or more channel layers stacked spaced apart from each other in the vertical Z direction.

[0047] The first PMOS gate electrode 69p is extended in the second horizontal direction Y, surrounding the first PMOS channel layer 9c. The first PMOS gate electrode 69p surrounds the first PMOS channel layer 9c and is extended in the second horizontal direction Y, positioned on the third active region 3c and the element isolation region 15. The first PMOS gate electrode 69p includes the first PMOS lower gate portion (69p_1) directly beneath the first PMOS lower channel layer 9c1, the first PMOS intermediate gate portion (69p_2) directly beneath the first PMOS intermediate channel layer 9c2, the first PMOS upper channel layer (69p_3) directly beneath the first PMOS upper channel layer 9c3, and the first PMOS uppermost gate portion (69p_4) on the first PMOS upper channel layer 9c3. The first PMOS lower gate portion (69p_1) is located between the third active region 3c and the first PMOS lower channel layer 9c1, the first PMOS intermediate gate portion (69p_2) is located between the first PMOS lower channel layer 9c1 and the first PMOS intermediate channel layer 9c2, and the first PMOS upper gate portion (69p_3) is located between the first PMOS intermediate channel layer 9c2 and the first PMOS upper channel layer 9c3.

[0048] The first PMOS gate dielectric layer 63p is positioned between the first PMOS source / drain region 128 and the first PMOS gate electrode 69p, and extends between the first PMOS gate electrode 69p and the first PMOS channel layer 9c. The first PMOS gate dielectric layer 63p contains a high dielectric material. In at least one of the first PMOS channel layers 9c, the maximum thickness in the vertical Z direction of the portion that overlaps perpendicularly with the first PMOS gate electrode 69p is smaller than the maximum thickness in the vertical Z direction of the portion that does not overlap perpendicularly with the first PMOS gate electrode 69p. In the first PMOS channel layer 9c, the thickness refers to the thickness in the vertical direction Z.

[0049] The first PMOS transistor structure pTR1S further includes a first PMOS insulating oxide layer 158. The first PMOS insulating oxide layer 158 contains silicon oxide. The first PMOS insulating oxide layer 158 includes a first PMOS lower insulating oxide layer (158_1) and a first PMOS upper insulating oxide layer (158_2). The first PMOS upper insulating oxide layer (158_2) is in contact with the outer surface of the first PMOS gate dielectric layer 63p located on the side surface of the first PMOS uppermost gate portion (69p_4), and with the lower surface of the first PMOS gate dielectric layer 63p located below the lower surface of the first PMOS uppermost gate portion (69p_4). The portion of the first PMOS lower insulating oxide layer (158_1) located beneath each of the first PMOS channel layers 9c includes a spacer portion (158_1a) and an interface portion (158_1b).

[0050] The spacer portion (158_1a) is placed between the first PMOS source / drain region 128 and the first PMOS gate dielectric layer 63p. The spacer portion (158_1a) is in contact with the first PMOS source / drain region 128 and the first PMOS gate dielectric layer 63p. The spacer portion (158_1a) is defined as the first PMOS insulating spacer structure (158_1a). The interface portion (158_1b) extends from the spacer portion (158_1a) and contacts the first PMOS gate dielectric layer 63p, which is superimposed perpendicularly to the first PMOS gate electrode 69p. The interface portion (158_1b) includes a portion that contacts the lower surface of the first PMOS gate dielectric layer 63p located below the lower surfaces of the first PMOS lower gate portion (69p_1), the first PMOS intermediate gate portion (69p_2), and the first PMOS upper gate portion (69p_3), and a portion that contacts the upper surface of the first PMOS gate dielectric layer 63p located on the upper surfaces of the first PMOS lower gate portion (69p_1), the first PMOS intermediate gate portion (69p_2), and the first PMOS upper gate portion (69p_3). The interface portion (158_1b) extends from the spacer portion (158_1a).

[0051] As shown in Figure 6a, when viewed with respect to the first PMOS intermediate gate portion (69p_2), the interface portion (158_1b) includes the portion located between the first PMOS lower channel layer 9c1 and the first PMOS gate dielectric layer 63p, and the portion located between the first PMOS intermediate channel layer 9c2 and the first PMOS gate dielectric layer 63p. As shown in Figure 6a, when viewed with respect to any one of the spacer portions (158_1a) as the center, the spacer portion (158_1a) includes an intermediate portion (158_1a_M) located in the middle, a lower portion (158_1a_L) extending downward from the intermediate portion (158_1a_M) and having a maximum thickness greater than the thickness of the intermediate portion (158_1a_M), and an upper portion (158_1a_U) extending upward from the intermediate portion (158_1a_M) and having a maximum thickness greater than the thickness of the first intermediate portion (158_1a_M).

[0052] In the first PMOS lower insulating oxide layer (158_1), the thickness of each spacer portion (158_1a) is greater than the thickness of each interface portion (158_1b). In the first PMOS lower insulating oxide layer (158_1), the thickness of each portion of the first PMOS lower insulating oxide layer (158_1) refers to the thickness in the direction perpendicular to the surface of the first PMOS gate dielectric layer 63p that is in contact with the first PMOS lower insulating oxide layer (158_1).

[0053] The first PMOS source / drain region 128, the first PMOS channel layer 9c, the first PMOS gate electrode 69p, and the first PMOS gate dielectric layer 63p constitute the first PMOS transistor (reference numerals 128, 9c, 69p, and 63p in Figure 6a), and the spacer portion (158_1a), i.e., the first PMOS insulating spacer structure (158_1a), can improve the performance of the first PMOS transistor (reference numerals 128, 9c, 69p, and 63p in Figure 6a). The first PMOS insulating spacer structure (158_1a) can increase the separation distance between the drain region of the first PMOS source / drain region 128 and the first PMOS gate electrode 69p, thereby preventing or minimizing the leakage current of the first PMOS transistor (indicated by 128, 9c, 69p, and 63p in Figure 6a) caused by the GIDL (Gate-Induced Drain Leakage) phenomenon.

[0054] The interface portion (158_1b) of the first PMOS lower insulating oxide layer (158_1) is positioned between the first PMOS channel layer 9c and the first PMOS gate dielectric layer 63p, which may be formed of a high dielectric material, thereby preventing interface defects that occur when the first PMOS channel layer 9c and the first PMOS gate dielectric layer 63p are in contact. Therefore, the interface portion (158_1b) of the lower insulating oxide layer (158_1) of the first PMOS can improve the performance and reliability of the first PMOS transistor (128, 9c, 69p, 63p in Figure 6a).

[0055] The second PMOS transistor structure (indicated as pTR2S in Figure 6b) includes a second PMOS source / drain region 129, a second PMOS channel layer 9d, a second PMOS gate electrode 72p, and a second PMOS gate dielectric layer 66p. The second PMOS source / drain regions 129 are separated from each other in the first horizontal direction X. Each of the second PMOS source / drain regions 129 has a P-type conductivity. Each of the second PMOS source / drain regions 129 contains an epitaxially grown semiconductor material. For example, each of the second PMOS source / drain regions 129 may contain at least one of germanium (Ge) and silicon-germanium (SiGe). In the first horizontal direction X, the width of each of the second PMOS source / drain regions 129 is greater than the width of each of the first PMOS source / drain regions 128.

[0056] The second PMOS channel layer 9d is located between the second PMOS source / drain regions 129. The second PMOS channel layer 9d is located on the fourth active region 3d. The second PMOS channel layers 9d are stacked spaced apart from each other in the second vertical direction Z. The second PMOS channel layer 9d is connected to the second PMOS source / drain region 129. The second PMOS channel layer 9d contains a semiconductor material, such as single-crystal silicon. The second PMOS channel layer 9d includes a second PMOS lower channel layer 9d1 on the fourth active region 3d, a second PMOS intermediate channel layer 9d2 on the second PMOS lower channel layer 9d1, and a second PMOS upper channel layer 9d3 on the second PMOS intermediate channel layer 9d2. In Figures 5 and 6b, the second PMOS channel layer 9d is shown as three, but the embodiments are not limited to this. For example, the second PMOS channel layer 9d may include four or more channel layers stacked spaced apart from each other in the vertical Z direction.

[0057] The second PMOS gate electrode 72p is extended in the second horizontal direction Y, surrounding the second PMOS channel layer 9d. The second PMOS gate electrode 72p surrounds the second PMOS channel layer 9d and is extended in the second horizontal direction Y, positioned on the fourth active region 3d and the element isolation region 15. The second PMOS gate electrode 72p includes the second PMOS lower gate portion (72p_1) directly below the second PMOS lower channel layer 9d1, the second PMOS intermediate gate portion (72p_2) directly below the second PMOS intermediate channel layer 9d2, the second PMOS upper gate portion (72p_3) directly below the second PMOS upper channel layer 9d3, and the second PMOS uppermost gate portion (72p_4) on the second PMOS upper channel layer 9d3. The second PMOS lower gate portion (72p_1) is located between the fourth active region 3d and the second PMOS lower channel layer 9d1, the second PMOS intermediate gate portion (72p_2) is located between the second PMOS lower channel layer 9d1 and the second PMOS intermediate channel layer 9d2, and the second PMOS upper gate portion (72p_3) is located between the second PMOS intermediate channel layer 9d2 and the second PMOS upper channel layer 9d3.

[0058] The second PMOS gate dielectric layer 66p is positioned between the second PMOS source / drain region 129 and the second PMOS gate electrode 72p, and extends between the second PMOS gate electrode 72p and the second PMOS channel layer 9d. The second PMOS gate dielectric layer 66p contains a high dielectric material. In at least one of the second PMOS channel layers 9d, the maximum thickness in the vertical Z direction of the portion that overlaps perpendicularly with the second PMOS gate electrode 72p is smaller than the maximum thickness in the vertical Z direction of the portion that does not overlap perpendicularly with the second PMOS gate electrode 72p. In the second PMOS channel layer 9d, the thickness refers to the thickness in the vertical direction Z.

[0059] The second PMOS transistor structure pTR2S further includes a second PMOS insulating oxide layer 159. The second PMOS insulating oxide layer 159 contains silicon oxide. The second PMOS insulating oxide layer 159 includes a second PMOS lower insulating oxide layer (159_1) and a second PMOS upper insulating oxide layer (159_2). The second PMOS upper insulating oxide layer (159_2) is in contact with the outer surface of the second PMOS gate dielectric layer 66p located on the side surface of the second PMOS uppermost gate portion (72p_4) and with the lower surface of the second PMOS gate dielectric layer 66p located below the lower surface of the second PMOS uppermost gate portion (72p_4). The portion of the second PMOS lower insulating oxide layer (159_1) located beneath each of the second PMOS channel layers 9d includes a spacer portion (159_1a) and an interface portion (159_1b).

[0060] The spacer portion (159_1a) is placed between the second PMOS source / drain region 129 and the second PMOS gate dielectric layer 66p. The spacer portion (159_1a) is in contact with the second PMOS source / drain region 129 and the second PMOS gate dielectric layer 66p. The spacer portion (159_1a) is defined as the second PMOS insulating spacer structure (159_1a). The interface portion (159_1b) extends from the spacer portion (159_1a) and contacts the second PMOS gate dielectric layer 66p, which is superimposed perpendicularly to the second PMOS gate electrode 72p. The interface portion (159_1b) includes a portion that contacts the lower surface of the second PMOS gate dielectric layer 66p located below the lower surfaces of the second PMOS lower gate portion (72p_1), the second PMOS intermediate gate portion (72p_2), and the second PMOS upper gate portion (72p_3), and a portion that contacts the upper surface of the second PMOS gate dielectric layer 66p located on the upper surfaces of the second PMOS lower gate portion (72p_1), the second PMOS intermediate gate portion (72p_2), and the second PMOS upper gate portion (72p_3). The interface portion (159_1b) extends from the spacer portion (159_1a).

[0061] As shown in Figure 6b, when viewed with respect to the second PMOS intermediate gate portion (72p_2), the interface portion (159_1b) includes the portion located between the second PMOS lower channel layer 9d1 and the second PMOS gate dielectric layer 66p, and the portion located between the second PMOS intermediate channel layer 9d2 and the second PMOS gate dielectric layer 66p. As shown in Figure 6b, when viewed with respect to any one of the spacer portions (159_1a) as the center, the spacer portion (159_1a) includes an intermediate portion (159_1a_M) located in the middle, a lower portion (159_1a_L) extending downward from the intermediate portion (159_1a_M) and having a maximum thickness greater than the thickness of the intermediate portion (159_1a_M), and an upper portion (159_1a_U) extending upward from the intermediate portion (159_1a_M) and having a maximum thickness greater than the thickness of the first intermediate portion (159_1a_M).

[0062] In the second PMOS lower insulating oxide layer (159_1), the thickness of each spacer portion (159_1a) is greater than the thickness of each interface portion (159_1b). In the second PMOS lower insulating oxide layer (159_1), the thickness of each portion of the second PMOS lower insulating oxide layer (159_1) refers to the thickness in the direction perpendicular to the surface of the second PMOS gate dielectric layer 66p that is in contact with the second PMOS lower insulating oxide layer (159_1).

[0063] The second PMOS source / drain region 129, the second PMOS channel layer 9d, the second PMOS gate electrode 72p, and the second PMOS gate dielectric layer 66p constitute the second PMOS transistor (reference numerals 129, 9d, 72p, and 66p in Figure 6b), and the spacer portion (159_1a), i.e., the second PMOS insulating spacer structure (159_1a), can improve the performance of the second PMOS transistor (reference numerals 129, 9d, 72p, and 66p in Figure 6b). The second PMOS insulating spacer structure (159_1a) can increase the separation distance between the drain region of the second PMOS source / drain region 129 and the second PMOS gate electrode 72p, thereby preventing or minimizing the leakage current of the second PMOS transistor (indicated by 129, 9d, 72p, and 66p in Figure 6b) caused by the GIDL (Gate-Induced Drain Leakage) phenomenon.

[0064] The interface portion (159_1b) of the second PMOS lower insulating oxide layer (159_1) is positioned between the second PMOS channel layer 9d and the second PMOS gate dielectric layer 66p formed of high dielectric material, thereby preventing interface defects that occur when the second PMOS channel layer 9d and the second PMOS gate dielectric layer 66p are in contact. Therefore, the interface portion (159_1b) of the second PMOS lower insulating oxide layer (159_1) can improve the performance and reliability of the second PMOS transistor (indicated by 129, 9d, 72p, and 66p in Figure 6b).

[0065] The semiconductor device 1 further includes a first insulating liner 21, a second insulating liner 33, a third insulating liner 48, and an interlayer insulating layer 51. Within the first NMOS region N1, the interlayer insulating layer 51 is positioned on the first NMOS source / drain region 45, the third insulating liner 48 covers the side and bottom surfaces of the interlayer insulating layer 51, the second insulating liner 33 is positioned between the third insulating liner 48 and the first NMOS upper insulating oxide layer (60_2), the first insulating liner 21 is positioned between the second insulating liner 33 and the first NMOS upper insulating oxide layer (60_2), and between the second insulating liner 33 and the first NMOS upper channel layer 9a3. Within the first NMOS region N1, the first and second insulating liners (21, 33) are arranged on the first NMOS upper channel layer 9a3, and the third insulating liner 33 is arranged on the first NMOS source / drain region 45.

[0066] Within the second NMOS region N2, the interlayer insulating layer 51 is positioned on the second NMOS source / drain region 30, the third insulating liner 48 covers the side and bottom surfaces of the interlayer insulating layer 51, the second insulating liner 33 is positioned between the third insulating liner 48 and the second NMOS upper insulating oxide layer (57_2), and between the second NMOS source / drain region 30 and the third insulating liner 48, and the first insulating liner 21 is positioned between the second insulating liner 33 and the second NMOS upper insulating oxide layer (57_2).

[0067] Within the first PMOS region P1, the interlayer insulating layer 51 is positioned on the first PMOS source / drain region 128, the third insulating liner 48 covers the side and bottom surfaces of the interlayer insulating layer 51, the second insulating liner 33 is positioned between the third insulating liner 48 and the first PMOS upper insulating oxide layer (158_2), and between the first PMOS source / drain region 128 and the third insulating liner 48, and the first insulating liner 21 is positioned between the second insulating liner 33 and the first PMOS upper insulating oxide layer (158_2).

[0068] Within the second PMOS region P2, the interlayer insulating layer 51 is positioned on the second PMOS source / drain region 129, the third insulating liner 48 covers the side and bottom surfaces of the interlayer insulating layer 51, the second insulating liner 33 is positioned between the third insulating liner 48 and the second PMOS upper insulating oxide layer (159_2), and between the second PMOS source / drain region 129 and the third insulating liner 48, and the first insulating liner 21 is positioned between the second insulating liner 33 and the second PMOS upper insulating oxide layer (159_2).

[0069] The upper surfaces of the first NMOS gate electrode 69n, the second NMOS gate electrode 72n, the first PMOS gate electrode 69p, the second PMOS gate electrode 72p, the first NMOS gate dielectric layer 63n, the second NMOS gate dielectric layer 66n, the first PMOS gate dielectric layer 63p, the second PMOS gate dielectric layer 66p, the first NMOS insulating oxide layer 60, the second NMOS insulating oxide layer 57, the first PMOS insulating oxide layer 158, the second PMOS insulating oxide layer 159, the first insulating liner 21, the second insulating liner 33, the third insulating liner 48, and the interlayer insulating layer 51 are coplane.

[0070] The semiconductor element 1 may further include sequentially stacked first capping insulating layer 75, first intermetallic insulating layer 78, second capping insulating layer 88, second intermetallic insulating layer 90, and third intermetallic insulating layer 98. The thickness of each of the first to third intermetallic insulating layers (78, 90, 98) is greater than the thickness of each of the first and second capping insulating layers (75, 88). The first capping insulating layer 75 covers the first NMOS gate electrode 69n, the second NMOS gate electrode 72n, the first PMOS gate electrode 69p, the second PMOS gate electrode 72p, the first NMOS gate dielectric layer 63n, the second NMOS gate dielectric layer 66n, the first PMOS gate dielectric layer 63p, the second PMOS gate dielectric layer 66p, the first NMOS insulating oxide layer 60, the second NMOS insulating oxide layer 57, the first PMOS insulating oxide layer 158, the second PMOS insulating oxide layer 159, the first insulating liner, the second insulating liner 33, the third insulating liner 48, and the interlayer insulating layer 51.

[0071] The first and second capping insulating layers (75, 88) contain materials different from the first to third intermetallic insulating layers (78, 90, 98) and the interlayer insulating layer 51. For example, the first and second capping insulating layers (75, 88) may contain silicon nitride or a metal oxide, and the first to third intermetallic insulating layers (78, 90, 98) and the interlayer insulating layer 51 may contain silicon oxide or a low-k dielectric having a dielectric constant lower than that of silicon oxide.

[0072] The semiconductor device 1 further includes source / drain contact structures (81n1, 81n2, 81p1, 81p2). Each of the source / drain contact structures (81n1, 81n2, 81p1, 81p2) is electrically connected by contact with the corresponding source / drain region within the source / drain regions (45, 30, 128, 129). For example, each of the source / drain contact structures (81n1, 81n2, 81p1, 81p2) includes a metal-semiconductor compound layer 83 and a source / drain contact plug 85 on the metal-semiconductor compound layer 83.

[0073] The source / drain contact plug 85 includes a plug conductive pattern 85b, and a conductive barrier layer 85a that covers the side and bottom surfaces of the plug conductive pattern 85b. In each source / drain contact structure (81n1, 81n2, 81p1, 81p2), the metal-semiconductor compound layer 83 is in contact with the corresponding source / drain region among the source / drain regions (45, 30, 128, 129). In each source / drain contact structure (81n1, 81n2, 81p1, 81p2), the metal-semiconductor compound layer 83 is positioned between the corresponding source / drain region (45, 30, 128, 129) and the source / drain contact plug 85. The second capping insulating layer 88 is positioned on the upper surfaces of the source / drain contact structures (81n1, 81n2, 81p1, 81p2) and the upper surface of the first intermetallic insulating layer 78.

[0074] The semiconductor device 1 further includes gate contact structures (93n1, 93n2, 93p1, 93p2). The gate contact structures (93n1, 93n2, 93p1, 93p2) penetrate the second intermetallic insulating layer 90, the second capping insulating layer 88, the first intermetallic insulating layer 78, and the first capping insulating layer 75, and are electrically connected to the gate electrodes (69n, 72n, 69p, 72p). Each of the gate contact structures (93n1, 93n2, 93p1, 93p2) is electrically connected to the corresponding gate electrode among the gate electrodes (69n, 72n, 69p, 72p). The gate contact structures (93n1, 93n2, 93p1, 93p2) include a first NMOS gate contact structure 93n1 connected to a first NMOS gate electrode 69n, a second NMOS gate contact structure 93n2 connected to a second NMOS gate electrode 72n, a first PMOS gate contact structure 93p1 connected to a first PMOS gate contact structure 69p, and a second PMOS gate contact structure 93p2 connected to a second PMOS gate electrode 72p.

[0075] The semiconductor device 1 further includes gate contact structures (93n1, 93n2, 93p1, 93p2) and source / drain contact structures (81n1, 81n2, 81p1, 81p2), and wiring structures (95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1, 96p2) that are electrically connected to these structures. The wiring structures (95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1, 96p2) are placed on the second intermetallic insulating layer 90, the gate contact structures (93n1, 93n2, 93p1, 93p2), and the source / drain contact structures (81n1, 81n2, 81p1, 81p2). Each of the wiring structures (95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1, 96p2) is connected to the corresponding contact structure among the gate contact structures (93n1, 93n2, 93p1, 93p2) and source / drain contact structures (81n1, 81n2, 81p1, 81p2). The second intermetallic insulating layer 98 is placed on the second intermetallic insulating layer 90 and the wiring structure (95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1, 96p2).

[0076] Next, various modifications of the components of the embodiments of the present invention described above will be explained. The various modifications of the components of the above-described embodiment, as described below, will focus on the components that are modified or replaced. Here, the aforementioned components are either directly cited without further detailed explanation, or their explanation is omitted. Furthermore, the deformable or replaceable components described below will be explained with reference to the following drawings, and the deformable or replaceable components can be combined with each other or with the aforementioned components to constitute the semiconductor element 1 according to the embodiment of the present invention.

[0077] Figure 8 is a partially enlarged cross-sectional view showing a modified portion in a partially enlarged view of Figure 3a, illustrating an exemplary example of a semiconductor device according to an embodiment of the present invention. Referring to Figure 8, in one embodiment of the present invention, the aforementioned first NMOS insulating oxide layer (reference numeral 60 in Figure 3a) is replaced by a first NMOS insulating oxide layer 160 formed in a manner in which the spacer portion (reference numeral 60_1a in Figure 3a) is omitted and the interface portion (reference numeral 60_1b in Figure 3a) remains. The first NMOS insulating oxide layer 160 is positioned between the first NMOS gate dielectric layer 63n and the first NMOS channel layer 9a, and between the first NMOS gate dielectric layer 63n and the first active region 3a. By replacing the aforementioned first NMOS insulating oxide layer (reference numeral 60 in Figure 3a) with the first NMOS insulating oxide layer 160, the aforementioned first NMOS insulating spacer structure (reference numeral 41 in Figure 3a) is replaced with an insulating spacer pattern 42 that contacts the first NMOS gate dielectric layer 63n.

[0078] Figure 9 is a partially enlarged cross-sectional view showing a modified portion in a partially enlarged view of Figure 6a, illustrating an exemplary example of a semiconductor device according to an embodiment of the present invention. Referring to Figure 9, in one embodiment, the aforementioned first PMOS insulating oxide layer (reference numeral 158 in Figure 6a) is replaced by a first PMOS insulating oxide layer 258 formed in a manner in which the spacer portion (reference numeral 158_1a in Figure 6a) is omitted and the interface portion (reference numeral 158_1b in Figure 6a) remains. By omitting the spacer portion (reference numeral 158_1a in Figure 6a), the size of the first PMOS gate electrode 69p is increased, and the electrical characteristics of the gate electrode of the PMOS transistor including the first PMOS gate electrode 69p can be improved. The first PMOS insulating oxide layer 258 is positioned between the first PMOS gate dielectric layer 63p and the first PMOS channel layer 9c, and between the first PMOS gate dielectric layer 63p and the third active region 3c. Therefore, the first PMOS gate dielectric layer 63p is in contact with the first PMOS source / drain region 128.

[0079] Figure 10 is a partially enlarged cross-sectional view showing a modified portion in a partially enlarged view of Figure 6b, illustrating an exemplary example of a semiconductor device according to an embodiment of the present invention. Referring to Figure 10, in one embodiment, the aforementioned second PMOS insulating oxide layer (reference numeral 159 in Figure 6b) is replaced by a second PMOS insulating oxide layer 259 formed in a manner in which the spacer portion (reference numeral 159_1a in Figure 6b) is omitted and the interface portion (reference numeral 159_1b in Figure 6b) remains. By omitting the spacer portion (reference numeral 159_1a in Figure 6b), the size of the second PMOS gate electrode 72p is increased, and the electrical characteristics of the gate electrode of the PMOS transistor including the second PMOS gate electrode 72p can be improved. The second PMOS insulating oxide layer 259 is positioned between the second PMOS gate dielectric layer 66p and the second PMOS channel layer 9d, and between the first PMOS gate dielectric layer 63p and the third active region 3c. Therefore, the first PMOS gate dielectric layer 63p is in contact with the first PMOS source / drain region 128.

[0080] Figure 11 shows a schematic configuration of a semiconductor device according to an embodiment of the present invention, and is a cross-sectional view showing a region cut along the line I-I' in Figure 1a and the line II-II' in Figure 1b, representing the deformed portion in the cross-sectional view of Figure 2. Figure 12 is a magnified partial view of the region represented by "Aa" in Figure 11, and Figure 13 is a magnified partial view of the region represented by "Ba" in Figure 11. Referring to Figures 11, 12, and 13, in the first NMOS gate electrode 69n, the aforementioned first NMOS intermediate gate portion (indicated as 69n_2 in Figure 3a) is transformed into a first NMOS intermediate gate portion (69n_2') with an increased width in the first horizontal direction X, and the aforementioned first NMOS lower gate portion (indicated as (69n_1) in Figure 3a) is transformed into a first NMOS lower gate portion (69n_1') with an increased width in the first horizontal direction X.

[0081] In the first horizontal direction X, the first NMOS intermediate gate portion (69n_2') has a width greater than the width of the first NMOS upper gate portion (69n_3) described above, and the first NMOS lower gate portion (69n_1') has a width greater than the width of the first NMOS intermediate gate portion (69n_2'). Therefore, by increasing the overall size of the first NMOS gate electrode 69n, the electrical characteristics of the gate electrode of the NMOS transistor, including the first NMOS gate electrode 69n, can be improved.

[0082] In the second NMOS gate electrode 72n, the aforementioned second NMOS intermediate gate portion (indicated as 72n_2 in Figure 3b) is transformed into a second NMOS intermediate gate portion (72n_2') with an increased width in the first horizontal direction X, and the aforementioned second NMOS lower gate portion (indicated as 72n_1 in Figure 3b) is transformed into a second NMOS lower gate portion (72n_1') with an increased width in the first horizontal direction X. In the first horizontal direction X, the second NMOS intermediate gate portion (72n_2') has a width greater than the width of the second NMOS upper gate portion (72n_3) mentioned above, and the second NMOS lower gate portion (72n_1') has a width greater than the width of the second NMOS intermediate gate portion (72n_2'). Therefore, by increasing the overall size of the second NMOS gate electrode 72n, the electrical characteristics of the gate electrode of the NMOS transistor, including the second NMOS gate electrode 72n, can be improved.

[0083] Figure 14 is a cross-sectional view showing a region cut along the line I-I' in Figure 1a to illustrate the schematic configuration of a semiconductor device according to an embodiment of the present invention, and shows a deformed portion in the cross-sectional area along the line I-I' in Figure 2. Figure 15 is a cross-sectional view showing a region cut along the line II-II' in Figure 1b to illustrate the schematic configuration of a semiconductor device according to an embodiment of the present invention, and shows a deformed portion in the cross-sectional area along the line II-II' in Figure 2.

[0084] Referring to Figures 14 and 15, the aforementioned first NMOS source / drain region (reference numeral 30 in Figures 2 and 3a) is replaced by the (1-1) NMOS source / drain region 345a and the (1-2) NMOS source / drain region 345b, which are separated from each other in the first horizontal direction X. The aforementioned second NMOS source / drain region (reference numeral 30 in Figures 2 and 3b) is replaced by the (2-1) NMOS source / drain region 330a and the 2-2 NMOS source / drain region 330b, which are separated from each other in the first horizontal direction X. In Figures 2, 3a, and 3b, the substrate 3, the first active region 3a, and the second active region 3b described above are replaced with a semiconductor substrate 303a with reduced thickness. The semiconductor substrate 303a is located beneath the first and second NMOS channel layers (9a, 9b), the first and second NMOS gate electrodes (69n, 72n), the (1-1) NMOS source / drain region 345a, the (1-2) NMOS source / drain region 345b, the (2-1) NMOS source / drain region 330a, and the (2-2) NMOS source / drain region 330b.

[0085] The semiconductor element 1 further includes a first back surface insulating layer 305 beneath the semiconductor substrate 303a, back surface wiring structures (395n1, 395n2) disposed beneath the first back surface insulating layer 305, and a second back surface insulating layer 398 covering the back surface wiring structures (395n1, 395n2) beneath the first back surface insulating layer 305. The semiconductor element 1 further includes an insulating separation structure 310 that penetrates the first back surface insulating layer 305 and the semiconductor substrate 303a. The insulating isolation structure 310 separates the portion of the semiconductor substrate 303a connected to the (1-1) NMOS source / drain region 345a from the portion of the semiconductor substrate 303a connected to the (1-2) NMOS source / drain region 345b, and separates the portion of the semiconductor substrate 303a connected to the (2-1) NMOS source / drain region 330a from the portion of the semiconductor substrate 303a connected to the (2-2) NMOS source / drain region 330b.

[0086] At least one of the source / drain contact structures (reference numeral 81n1 in Figures 2 and 3a) connected to the aforementioned first NMOS source / drain region (reference numeral 45 in Figures 2 and 3a), or at least one of the source / drain contact structures (reference numeral 81n2 in Figures 2 and 3b) connected to the aforementioned second NMOS source / drain region (reference numeral 30 in Figures 2 and 3b), is replaced by a back-side contact structure (381n1, 381n2) that penetrates the first back-side insulating layer 305 and the semiconductor substrate 303a. For example, at least one of the source / drain contact structures (reference numeral 81n1 in Figures 2 and 3a) connected to the first NMOS source / drain region (reference numeral 45 in Figures 2 and 3a) is replaced by a back-side source / drain contact structure connected to at least one corresponding source / drain region from the (1-1) NMOS source / drain region 345a and the (1-2) NMOS source / drain region 345b.

[0087] For example, one of the source / drain contact structures (reference numeral 81n1 in Figures 2 and 3a) is electrically connected to the (1-1) NMOS source / drain region 345a in the form shown in Figures 2 and 3a, while the other is replaced by a first back-surface source / drain contact structure 381n1 that penetrates the first back-surface insulating layer 305 and the semiconductor substrate 303a and extends into the (1-2) NMOS source / drain region 345b through the lower surface of the (1-2) NMOS source / drain region 345b. One of the source / drain contact structures (reference numeral 81n2 in Figures 2 and 3b) is electrically connected to the (2-1) NMOS source / drain region 330a in the configuration shown in Figures 2 and 3b, while the other is replaced by a second back-surface source / drain contact structure 381n2 that penetrates the first back-surface insulating layer 305 and the semiconductor substrate 303a and extends into the (2-2) NMOS source / drain region 330b through the lower surface of the (2-2) NMOS source / drain region 330b.

[0088] Each of the backside source / drain contact structures (381n1, 381n2) includes a metal-semiconductor compound layer 383 and a source / drain contact plug 385 beneath the metal-semiconductor compound layer 383. The source / drain contact plug 385 includes a plug conductive pattern 385b and a conductive barrier layer 385a that covers the side and top surfaces of the plug conductive pattern 385b. In each of the back surface source / drain contact structures (381n1, 381n2), the metal-semiconductor compound layer 383 is in contact with the corresponding source / drain region within the source / drain region (345b, 330b) and the corresponding semiconductor substrate within the semiconductor substrate 303a. The rear source / drain contact structures (381n1, 381n2) are electrically connected to the rear wiring structures (395n1, 395n2).

[0089] Next, a method for forming a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 16a, 16b, 17a, 17b, 18-23, 24a, 24b, 25a, 25b, 25c, 25d, 26a, and 26b. For example, this explanation will focus on a method for forming a first insulating spacer structure (reference numeral 41 in Figures 2 and 3a) and a second NMOS insulating spacer structure (reference numeral 57_1a in Figures 2 and 3b), which have different shapes and structures from each other. In Figures 16a, 16b, 17a, 17b, 18-23, 24a, 24b, 25a, 25b, 25c, 25d, 26a, and 26b, Figures 16a, 17a, 18-23, 24a, 25a, and 26a are cross-sectional views showing the region cut along the line I-I' in Figure 1a and the line II-II' in Figure 1b; Figures 16b, 17b, 24b, 25d, and 26b are cross-sectional views showing the region cut along the line III-III' in Figure 1a and the line IV-IV' in Figure 1b; Figure 25b is a magnified partial view of the region represented as "A1" in Figure 25a; and Figure 25c is a magnified partial view of the region represented as "B1" in Figure 25a.

[0090] Referring to Figures 1a, 1b, 16a, and 16b, a substrate 3, an element isolation region 15 that limits the active region 3a, and a structure including a stacked structure (12a, 12b) on the active region 3a are prepared. The laminated structure (12a, 12b) includes a first laminated structure 12a formed within a first NMOS region N1 and a second laminated structure 12b formed within a second NMOS region N2. The first stacked structure 12a includes alternately stacked first sacrificial semiconductor layers 6a and first channel layers 9a. The second stacked structure 12b includes alternately stacked second sacrificial semiconductor layers 6b and second channel layers 9b. The first sacrificial semiconductor layer 6a includes a first lower sacrificial semiconductor layer 6a1, a first intermediate sacrificial semiconductor layer 6a2, and a first upper sacrificial semiconductor layer 6a3, which are stacked spaced apart from each other in the vertical direction Z. The second sacrificial semiconductor layer 6b includes a second lower sacrificial semiconductor layer 6b1, a second intermediate sacrificial semiconductor layer 6b2, and a second upper sacrificial semiconductor layer 6b3, which are stacked spaced apart from each other in the vertical direction Z. The first channel layer 9a includes a first lower channel layer 9a1, a first intermediate channel layer 9a2, and a first upper channel layer 9a3, which are stacked spaced apart from each other in the vertical direction Z. The second channel layer 9b includes a second lower channel layer 9b1, a second intermediate channel layer 9b2, and a second upper channel layer 9b3, which are stacked spaced apart from each other in the vertical direction Z. The first and second channel layers (9a, 9b) are formed from a first semiconductor material such as silicon. The first and second sacrificial semiconductor layers (6a, 6b) are formed from a different material from the first and second channel layers (9a, 9b), such as a second semiconductor material like silicon-germanium.

[0091] A gate mask pattern (18a, 18b) is formed, which extends in the second horizontal direction Y. The gate mask patterns (18a, 18b) are formed on the laminated structures (12a, 12b) and the element isolation region 15. The gate mask patterns (18a, 18b) include a first NMOS mask pattern 18a formed in the first NMOS region N1, and a second NMOS mask pattern 18b formed in the second NMOS region N2. The first NMOS mask pattern 18a extends across the first stacked structure 12a in the second horizontal direction Y, and the second NMOS mask pattern 18b extends across the second stacked structure 12b in the second horizontal direction Y. The first NMOS mask pattern 18a includes a first lower mask layer 18a1 and a first upper mask layer 18a2 stacked sequentially, and the second NMOS mask pattern 18b includes a second lower mask layer 18b1 and a second upper mask layer 18b2 stacked sequentially. A first insulating liner 21 is formed that conformally covers the laminated structures (12a, 12b) and the gate mask patterns (18a, 18b).

[0092] Referring to Figures 1a, 1b, 17a, and 17b, a first protective mask 24 is formed on the first NMOS region N1, covering the first insulating liner 21. With the first NMOS region N1 protected by the first protective mask 24, the first insulating liner 21 of the second NMOS region N2 is anisotropically etched, and then the second laminated structure 12b is etched to form a recess 27 that penetrates the second laminated structure 12b.

[0093] Referring to Figures 1a, 1b, and 18, with the first NMOS region N1 protected by the first protective mask 24, the second NMOS source / drain epitaxial growth process is performed to form the second NMOS source / drain region 30, which is formed by epitaxial growth from the active region 3b exposed by the recess 27, the side surface of the second sacrificial semiconductor layer 6b, and the side surface of the second channel layer 9b. Each of the second NMOS source / drain regions 30 has an upper surface with a recessed central portion.

[0094] Referring to Figures 1a, 1b, and 19, the first protective mask (reference numeral 24 in Figure 18) is removed. Next, a second insulating liner 33 is formed that conformally covers the first insulating liner 21 and the second NMOS source / drain region 30. A second protective mask 36 is formed on the second NMOS region N2, covering the second insulating liner 33.

[0095] Referring to Figures 1a, 1b, and 20, with the second NMOS region N2 protected by the second protective mask 36, the first and second insulating liners (21, 33) of the first NMOS region N1 are anisotropically etched, and then the first laminated structure 12a is etched to form a recess 39 that penetrates the first laminated structure 12a. The side of the first sacrificial semiconductor layer 6a exposed by recess 39 is recessed more than the side of the first channel layer 9a exposed by recess 39. Next, insulating spacer patterns 42 are formed beneath each first channel layer 9a that is in contact with the side surface of the first sacrificial semiconductor layer 6a. The insulating spacer pattern 42 is formed from silicon nitride.

[0096] Referring to Figures 1a, 1b, and 21, with the second NMOS region N2 protected by the second protective mask 36, the first NMOS source / drain epitaxial growth process is performed to form the first NMOS source / drain region 45, which is formed by epitaxial growth from the active region 3a exposed by the recess 39 and the first channel layer 9a. Since the first NMOS source / drain region 45 has a relatively small width, it can be formed without defects even when epitaxially grown from the active region 3a and the first channel layer 9a exposed by the recess 39. As described in Figure 18 above, the second NMOS source / drain region 30 has a wider width than the first NMOS source / drain region 45. However, since the second NMOS source / drain region 30 is formed by epitaxial growth from the active region 3b exposed by the recess 27, the side surface of the second sacrificial semiconductor layer 6b, and the side surface of the second channel layer 9b, it can be formed without defects. According to this embodiment, the first NMOS source / drain region 45 and the second NMOS source / drain region 30 can be reliably formed without defects.

[0097] Referring to Figures 1a, 1b, and 22, the second protective mask (reference numeral 36 in Figure 21) is removed. Next, a third insulating liner 48 is formed that conformally covers the first NMOS source / drain region 45 and the second insulating liner 33.

[0098] Referring to Figures 1a, 1b, and 23, an interlayer insulating layer 51 is formed on the third insulating liner 48. The planarization process is carried out until the first and second lower mask layers (18a1, 18b1) are exposed. The planarization process removes the first and second upper mask layers (reference numerals 18a2 and 18b2 in Figure 22), and the interlayer insulating layer 51 remains on the third insulating liner 48 on the sides of the first and second lower mask layers (18a1 and 18b1).

[0099] Referring to Figures 1a, 1b, 24a, and 24b, the first and second lower mask layers (reference numerals 18a1 and 18b1 in Figure 23) and the first and second sacrificial semiconductor layers (reference numerals 6a and 6b in Figure 23) are removed to simultaneously form the first opening 54a and the second opening 54b. The first opening 54a includes a first upper opening (54a_2) formed by removing the first lower mask layer 18a1 and a first lower opening (54a_1) formed by removing the first sacrificial semiconductor layer 6a. The second opening 54b includes a second upper opening (54b_2) formed by removing the second lower mask layer 18b1 and a second lower opening (54b_1) formed by removing the second sacrificial semiconductor layer 6b. The first lower opening (54a_1) exposes the insulating spacer pattern 42, and the second lower opening (54b_1) exposes the second NMOS source / drain region 30.

[0100] Referring to Figures 1a, 1b, 25a, 25b, 25c, and 25d, an insulating oxide layer (57, 60) is formed. Forming insulating oxide layers (57, 60) includes forming a pre-oxide layer conformally covering the inner walls of the first and second openings (54a, 54b), densifying at least a portion of the pre-oxide layer, and etching the densified pre-oxide layer so that it remains thicker at the corners of the openings (54, 54b) and the side walls of the lower openings (54a_1, 54b_1). The insulating oxide layers (57, 60) include a first insulating oxide layer 60 formed on the inner wall of the first opening 54a and a second insulating oxide layer 57 formed on the inner wall of the first opening 54a.

[0101] Referring to Figures 1a, 1b, 26a, and 26b, gate dielectric layers (63n, 66n) are formed conformally over the first and second openings (54a, 54b) on which insulating oxide layers (57, 60) are formed on the inner walls. A conductive material is formed to fill the first and second openings (54a, 54b) covered by gate dielectric layers (63n, 66n), and the conductive material is planarized to form gate electrodes (69n, 72n). In order to form the gate electrodes (69n, 72n), the interlayer insulating layer 51 and the insulating liners (21, 33, 48) are formed by a process of planarizing the conductive material so that they have upper surfaces that are coplane with the upper surfaces of the gate electrodes (69n, 72n).

[0102] Next, contact and wiring processes are performed to form source / drain contact structures (81n1, 81n2, 81p1, 81p2), gate contact structures (93n1, 93n2, 93p1, 93p2), and wiring structures (95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1, 96p2) as shown in Figures 2, 3a, 3b, 4, 5, 6a, and 6b.

[0103] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0104] 1. Semiconductor element 3 circuit boards 3a, 3b, 3c, 3d active area 9a, 9b (1st, 2nd) NMOS channel layers 9a1 First NMOS lower channel layer 9a2 First NMOS Intermediate Channel Layer 9a3 First NMOS upper channel layer 9b1 Second lower channel layer 9b2 Second Intermediate Channel Layer 9b3 Second Upper Channel Layer 9c First PMOS channel layer 21. First insulating liner 30. Second NMOS source / drain region 33. Second insulating liner 41. First NMOS insulating spacer structure 42 Insulating Spacer Patterns 45. First NMOS Source / Drain Region 48 Third insulating liner 51 Interlayer insulating layer 60, 57 (1st, 2nd) NMOS insulating oxide layer 158, 159 (1st, 2nd) PMOS insulating oxide layer 63n 1st NMOS gate dielectric layer 63p First PMOS gate dielectric layer 66n 2nd NMOS Gate Dielectric Layer 66p Second PMOS Gate Dielectric Layer 69n 1st NMOS gate electrode 69p 1st PMOS Token 72n 2nd NMOS Electron Shutdown Circuit 72pF 2nd PMOS Grid Socket 75 First capping insulating layer 78 First intermetallic insulating layer 81n1, 81n2, 81p1, 81p2 Source / Drain Contact Structures 88 Second capping insulating layer 90 Second intermetallic insulating layer 93n1, 93n2, 93p1, 93p2 Gate Contact Structures 95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1, 96p2 Wiring Structures 98 Third intermetallic insulating layer 128 First PMOS Source / Drain Region 129 Second PMOS Source / Drain Region C1 1st area C2 2nd area N1 1st NMOS region N2 2nd NMOS area nTR1S First NMOS Transistor Structure nTR2S Second NMOS Transistor Structure P1 1st PMOS area P2 2nd PMOS area pTR1S First PMOS Transistor Structure pTR2S Second PMOS Transistor Structure

Claims

1. First NMOS transistor structure, It has a second NMOS transistor structure, The first NMOS transistor structure is The first NMOS source / drain region, A plurality of first NMOS channel layers are stacked vertically apart from each other and connected to the first NMOS source / drain region in a first horizontal direction perpendicular to the vertical direction, In the first horizontal direction and the second horizontal direction perpendicular to the vertical direction, the first NMOS gate electrode surrounds the first NMOS channel layer, A first NMOS gate dielectric layer is disposed between the first NMOS gate electrode and the first NMOS channel layer, and between the first NMOS gate electrode and the first NMOS source / drain region, The present invention includes a first NMOS insulating spacer structure disposed between the first NMOS gate dielectric layer and the first NMOS source / drain region, The aforementioned second NMOS transistor structure is The second NMOS source / drain region, A plurality of second NMOS channel layers stacked apart from each other in the vertical direction and connected to the second NMOS source / drain region in the first horizontal direction, A second NMOS gate electrode extending in the second horizontal direction and surrounding the second NMOS channel layer in the second horizontal direction, A second NMOS gate dielectric layer is disposed between the second NMOS gate electrode and the second NMOS channel layer, and between the second NMOS gate electrode and the second NMOS source / drain region, The present invention includes a second NMOS insulating spacer structure disposed between the second NMOS gate dielectric layer and the second NMOS source / drain region, The first NMOS insulating spacer structure includes an insulating spacer pattern, The semiconductor device is characterized in that the second NMOS insulating spacer structure includes an insulating oxide layer without including the same insulating spacer pattern as the insulating spacer pattern.

2. The semiconductor device according to claim 1, characterized in that the first horizontal width of the second NMOS channel layer located at the first level of the second NMOS channel layer is greater than the first horizontal width of the first NMOS channel layer located at the first level of the first channel layer.

3. The semiconductor device according to claim 1, characterized in that the maximum width in the first horizontal direction of the second NMOS source / drain region is greater than the maximum width in the first horizontal direction of the first NMOS source / drain region.

4. Each of the first and second NMOS gate dielectric layers includes a high dielectric layer. The aforementioned high dielectric layer has a dielectric constant higher than that of silicon oxide. The insulating spacer pattern comprises silicon nitride, The semiconductor device according to claim 1, characterized in that the insulating oxide layer contains silicon oxide.

5. The semiconductor device according to claim 1, characterized in that the second NMOS transistor structure further includes an interface oxide layer that extends from the insulating oxide layer of the second NMOS insulating spacer structure and is disposed between the second NMOS channel layer and the second NMOS gate dielectric layer.

6. First NMOS transistor structure, It has a second NMOS transistor structure, The first NMOS transistor structure is The first NMOS source / drain region, A plurality of first NMOS channel layers are stacked vertically apart from each other and connected to the first NMOS source / drain region in a first horizontal direction perpendicular to the vertical direction, Extending in the first horizontal direction and a second horizontal direction perpendicular to the vertical direction, the first NMOS gate electrode surrounds the first NMOS channel layer in the second horizontal direction, A first NMOS gate dielectric layer is disposed between the first NMOS gate electrode and the first NMOS channel layer, and between the first NMOS gate electrode and the first NMOS source / drain region, The present invention includes a first NMOS insulating spacer structure disposed between the first NMOS gate dielectric layer and the first NMOS source / drain region, The aforementioned second NMOS transistor structure is The second NMOS source / drain region, A plurality of second NMOS channel layers stacked apart from each other in the vertical direction and connected to the second NMOS source / drain region in the first horizontal direction, A second NMOS gate electrode extending in the second horizontal direction and surrounding the second NMOS channel layer in the second horizontal direction, A second NMOS gate dielectric layer is disposed between the second NMOS gate electrode and the second NMOS channel layer, and between the second NMOS gate electrode and the second NMOS source / drain region, The present invention includes a second NMOS insulating spacer structure disposed between the second NMOS gate dielectric layer and the second NMOS source / drain region, The first NMOS channel layer is The first NMOS lower channel layer, A first NMOS intermediate channel layer is disposed on the first NMOS lower channel layer, The first NMOS upper channel layer is disposed on the first NMOS intermediate channel layer, The second NMOS channel layer is The second NMOS lower channel layer, A second NMOS intermediate channel layer is placed on the second NMOS lower channel layer, The system includes a second NMOS upper channel layer disposed on the second NMOS intermediate channel layer, The first NMOS gate electrode is The first NMOS lower gate portion is located directly below the first NMOS lower channel layer, A first NMOS intermediate gate portion is located directly beneath the first NMOS intermediate channel layer, The first NMOS upper gate portion is located directly below the first NMOS upper channel layer, The second NMOS gate electrode is The second NMOS lower gate portion is located directly below the second NMOS lower channel layer, A second NMOS intermediate gate portion located directly beneath the second NMOS intermediate channel layer, The second NMOS upper gate portion is located directly below the second NMOS upper channel layer, The first NMOS insulating spacer structure includes a first NMOS intermediate spacer portion disposed between the first NMOS source / drain region and the first NMOS intermediate gate portion, The second NMOS insulating spacer structure includes a second NMOS intermediate spacer portion positioned between the second NMOS source / drain region and the second NMOS intermediate gate portion. The thickness of the first NMOS intermediate spacer portion is greater than the thickness of the second NMOS intermediate spacer portion. The thickness of the second NMOS intermediate spacer portion is perpendicular to the surface of the second NMOS gate dielectric layer that is in contact with the second NMOS intermediate spacer portion within the second NMOS gate dielectric layer. The semiconductor device is characterized in that the thickness of the first NMOS intermediate spacer portion is perpendicular to the surface of the first NMOS gate dielectric layer that is in contact with or facing the first NMOS intermediate spacer portion within the first NMOS gate dielectric layer.

7. The semiconductor device according to claim 6, characterized in that the second NMOS insulating spacer structure extends from a portion disposed between the second NMOS gate dielectric layer and the second NMOS source / drain region to a portion between the second NMOS gate dielectric layer and the second NMOS channel layer.

8. The semiconductor device according to claim 6, characterized in that the first horizontal width of the second NMOS lower channel layer is greater than the first horizontal width of the first NMOS lower channel layer.

9. First NMOS transistor structure, It has a second NMOS transistor structure, The first NMOS transistor structure is Multiple first NMOS channel layers separated from each other in the vertical direction, A first NMOS source / drain region connected to the first NMOS channel layer in a first horizontal direction perpendicular to the vertical direction, A first NMOS gate electrode including a first NMOS intermediate electrode portion disposed between the first NMOS channel layers, A first NMOS gate dielectric layer is disposed between the first NMOS gate electrode and the first NMOS channel layer, The system includes a first NMOS insulating spacer structure disposed between the first NMOS intermediate electrode portion and the first NMOS source / drain region, The aforementioned second NMOS transistor structure is The plurality of second NMOS channel layers separated from each other in the vertical direction, A second NMOS source / drain region connected to the second NMOS channel layer in the first horizontal direction, A second NMOS gate electrode including a second NMOS intermediate electrode portion disposed between the second NMOS channel layers, A second NMOS gate dielectric layer is disposed between the second NMOS gate electrode and the second NMOS channel layer, The present invention includes a second NMOS insulating spacer structure disposed between the second NMOS intermediate electrode portion and the second NMOS source / drain region, The first NMOS insulating spacer structure includes an insulating spacer pattern, The semiconductor device is characterized in that the second NMOS insulating spacer structure includes a second NMOS insulating oxide layer without including the same insulating spacer pattern as the insulating spacer pattern.

10. In the first horizontal direction, the width of the second NMOS source / drain region is greater than the width of the first NMOS source / drain region. The first NMOS gate dielectric layer extends between the first NMOS intermediate electrode portion and the first NMOS insulating spacer structure. The semiconductor device according to claim 9, characterized in that the second NMOS gate dielectric layer is extended between the second NMOS intermediate electrode portion and the second NMOS insulating spacer structure.

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