Semiconductor device and method for manufacturing the same

Abstract

Miniaturization and increased integration density of semiconductor devices. [Solution] The semiconductor device includes a first channel structure 160, a first air layer 130 surrounding the side of the first channel structure 160, a first bit line 150 in contact with the side of the first channel structure 160, a first word line 110 in contact with the bottom of the first channel structure 160, a storage node 170 with one end in contact with the top of the first channel structure 160, a second channel structure 250 in contact with the top of the storage node 170, a second air layer 220 surrounding the side of the second channel structure 250, a second bit line 240 in contact with the side of the second channel structure 250, and a second word line 260 in contact with the top of the second channel structure 250, wherein the first bit line 150 extends in a direction perpendicular to the direction in which the first channel structure 160 extends, and the second word line 260 can extend in a direction perpendicular to the direction in which the second channel structure 250 extends.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a memory cell.

Background Art

[0002] Miniaturization and improvement of the integration degree of semiconductor devices have been the main issues. Along with this, memory cells included in semiconductor devices are formed so as to have a three-dimensional pattern. A memory cell having a three-dimensional pattern can be provided with a configuration for improving its operation characteristics.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The technical idea of the present disclosure aims to provide a semiconductor memory device including two transistors and having an improved integration degree.

[0004] Also, an embodiment of the present disclosure aims to provide a semiconductor memory device in which the influence of parasitic capacitance is reduced.

[0005] The technical problems of the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0006] A semiconductor device according to one embodiment of the present invention includes a first channel structure, a first air layer surrounding the side surface of the first channel structure, a first bit line in contact with the side surface of the first channel structure, a first word line in contact with the lower part of the first channel structure, a storage node with one end in contact with the upper part of the first channel structure, a second channel structure in contact with the upper part of the storage node, a second air layer surrounding the side surface of the second channel structure, a second bit line in contact with the side surface of the second channel structure, and a second word line in contact with the upper part of the second channel structure, wherein the first bit line extends in a direction perpendicular to the direction in which the first channel structure extends, and the second word line can extend in a direction perpendicular to the direction in which the second channel structure extends.

[0007] According to one embodiment, the first bit line can extend in a direction perpendicular to the direction in which the second word line extends.

[0008] According to one embodiment, the first air layer may include a first vertical extension located between two adjacent first bit lines.

[0009] According to one embodiment, the second air layer may include a second vertical extension located between two adjacent second bit lines.

[0010] According to one embodiment, the first channel structure includes a vertically extending columnar first gate, a first gate insulating layer surrounding the side and bottom surfaces of the first gate, and a first channel region surrounding the first gate insulating layer, and the second channel structure may include a vertically extending columnar second gate, a second gate insulating layer surrounding the side and bottom surfaces of the second gate, and a second channel region surrounding the second gate insulating layer.

[0011] According to one embodiment, the semiconductor device may further include a peri region located below the first word line.

[0012] According to one embodiment, the first air layer may include a first gap fill region located within the first vertical extension.

[0013] According to one embodiment, the second air layer may include a second gap fill region located within the second vertical extension.

[0014] According to one embodiment, the first air layer may include a first residual sacrificial layer in contact with the side wall of the first channel structure.

[0015] According to one embodiment, the second air layer may include a second residual sacrificial layer in contact with the side wall of the second channel structure.

[0016] According to one embodiment, the first air layer is located between the first bit line and the first word line and can surround a portion of the side surface of the first channel structure.

[0017] According to one embodiment, the second air layer is located between the second bit line and the second word line and can surround a portion of the side surface of the second channel structure.

[0018] Another embodiment of the present invention includes a semiconductor device comprising: a plurality of first word lines, each extending in a first direction; a plurality of first channel structures, touching the upper parts of the plurality of first word lines and extending in a second direction perpendicular to the first direction; a plurality of first bit lines, among the plurality of first channel structures, commonly touching the sides of first channel structures located in a third direction; a first air layer located between the plurality of first channel structures; a plurality of storage nodes, each touching the upper parts of the plurality of first channel structures; a plurality of second channel structures, each touching the plurality of storage nodes and extending in a second direction; a plurality of second bit lines, among the plurality of second channel structures, commonly touching the sides of second channel structures located in a third direction; a second air layer located between the plurality of second channel structures; and a plurality of second word lines, among the plurality of second channel structures, touching the upper parts of second channel structures located in a first direction.

[0019] According to other embodiments, the first air layer may surround a portion of the sides of the plurality of first channel structures, and the second air layer may surround a portion of the sides of the plurality of second channel structures. The plurality of first word lines may be arranged repeatedly in the third direction, and the plurality of second word lines may be arranged repeatedly in the third direction.

[0020] According to another embodiment, each of the plurality of first channel structures includes a columnar first gate extending in the second direction, a first gate insulating layer surrounding the side and bottom surfaces of the first gate, and a first channel region surrounding the first gate insulating layer, and each of the plurality of second channel structures may include a columnar second gate extending in the second direction, a second gate insulating layer surrounding the side and bottom surfaces of the second gate, and a second channel region surrounding the second gate insulating layer.

[0021] According to another embodiment, at least a partial region of the first air layer can be located below the plurality of first bit lines, and at least a partial region of the second air layer can be located below the plurality of second bit lines.

[0022] According to another embodiment, the first air layer is located between two adjacent first bit lines and includes a plurality of first vertical extensions extending in the third direction, and the second air layer can be located between two adjacent second bit lines and include a plurality of second vertical extensions extending in the third direction.

[0023] A method for manufacturing a semiconductor device according to yet another embodiment forms a first word line on a substrate, forms a first bit line on top of the first word line, forms a first channel structure whose bottom surface contacts the first word line and whose side surface contacts the first bit line, forms a first air layer surrounding the side surface of the first channel structure, forms a storage node contacting the top surface of the first channel structure, forms a second bit line on top of the storage node, forms a second channel structure whose bottom surface contacts the storage node and whose side surface contacts the second bit line, and can form a second air layer surrounding the side surface of the second channel structure.

Advantages of the Invention

[0024] The semiconductor device of the present disclosure can provide a semiconductor device with improved integration by having a three-dimensional channel.

[0025] The semiconductor device of the present disclosure can provide a semiconductor device with a simplified manufacturing process by including a transistor that operates as a storage element.

[0026] Also, the semiconductor device of the present disclosure can improve signal distortion caused by parasitic capacitance by including an air layer.

[0027] In addition, various effects directly or indirectly grasped by this document can be provided.

Brief Description of the Drawings

[0028] [Figure 1] It shows a part of the memory cell array of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] It shows an equivalent circuit diagram of a memory cell according to an embodiment of the present disclosure. [Figure 3a] It is a plan view of a part of the memory cell array according to an embodiment of the present disclosure viewed from the second direction. [Figure 3b] It is a cross-sectional view taken along the first cutting line of FIG. 3a. [Figure 3c] It is a cross-sectional view taken along the second cutting line of FIG. 3a. [Figure 4a] It is a plan view of a part of the memory cell array according to another embodiment of the present disclosure viewed from the second direction. [Figure 4b] It is a cross-sectional view taken along the third cutting line of FIG. 4a. [Figure 4c] It is a cross-sectional view taken along the fourth cutting line of FIG. 4a. [Figure 5a] It is for explaining a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. [Figure 5b] It is for explaining a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. [Figure 5c] It is for explaining a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. [Figure 6a] It is for explaining a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. [Figure 6b] It is for explaining a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. [Figure 6c] It is for explaining a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. [Figure 7a] It is for explaining a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. [Figure 7b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 7c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 8a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 8b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 8c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 9a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 9b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 9c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 10a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 10b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 10c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 11a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 11b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 11c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 12a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 12b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 12c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 13a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 13b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 13c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 14a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 14b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 14c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 15a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 15b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 15c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 16a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 16b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 16c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 17a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 17b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 17c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 18a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 18b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 18c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 19a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 19b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 19c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 20a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 20b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 20c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 21a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 21b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 21c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 22a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 22b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 22c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 23a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 23b]This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 23c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 24a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 24b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 24c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 25a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 25b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 25c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 26a] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 26b] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Figure 26c] This disclosure is intended to describe a method for manufacturing a semiconductor device according to one embodiment of this disclosure. [Modes for carrying out the invention]

[0029] Various embodiments of this disclosure are described below with reference to the accompanying drawings. The advantages and features of this disclosure, as well as how to achieve them, will become clear with reference to the detailed embodiments, along with the accompanying drawings. However, this is not intended to limit the invention to any particular embodiment.

[0030] The present invention is not limited by its embodiments and can be realized in a variety of different forms, and should be understood to include a variety of modifications, equivalents, and / or alternatives to the embodiments of the present disclosure.

[0031] Furthermore, when assigning reference numerals to the components of each drawing, it should be noted that, as far as possible, the same component should have the same reference numeral, even if it is shown on different drawings.

[0032] In describing embodiments of this disclosure, if a specific description of a relevant known configuration or function is deemed to interfere with understanding the embodiments of this disclosure, such detailed description will be omitted.

[0033] In this specification, singular types include plural types unless otherwise specified in the text. The terms "comprises" and / or "comprising" used in this specification do not exclude the presence or addition of one or more other components, steps, operations, and / or elements that are mentioned.

[0034] Hereinafter, a semiconductor device and a method for manufacturing the same according to an embodiment of this disclosure will be described with reference to the drawings.

[0035] Figure 1 shows a part of the memory cell array 1 of a semiconductor device according to one embodiment of the present disclosure.

[0036] Referring to Figure 1, the memory cell array includes memory cells MC, and each memory cell MC may include a first transistor TR1, a storage node SN, and a second transistor TR2.

[0037] The first transistor TR1 and the second transistor TR2 can be arranged vertically, and the first transistor TR1 and the second transistor TR2 can be connected to the storage node SN.

[0038] The first transistor TR1 may include a first channel structure CS1, a first bit line BL1, and a first word line WL1.

[0039] The first word line WL1 can extend in the first direction (D1). Multiple first channel structures CS1 can be arranged above the first word line WL1, repeating in the first direction (D1).

[0040] Multiple first channel structures CS1, arranged repeatedly in the first direction (D1), can be connected to a single first word line WL1.

[0041] The first channel structure CS1 can extend in a second direction (D2) and may include multiple layers. Exemplary, the first channel structure CS1 may include a first gate, a first gate insulating layer, and a first channel region.

[0042] The first channel structure CS1 can be connected to the first word line WL1 via the first channel region.

[0043] The first bit line BL1 can extend in a third direction (D3). The first bit line BL1 can be adjacent to the side of the first channel region contained in the first channel structure CS1.

[0044] A first bit line BL1 extending in the third direction (D3) can be in common contact with the sides of multiple first channel structures CS1 that are repeatedly arranged in the third direction (D3).

[0045] Storage node SN can be an area connected to the first channel structure CS1 and the second channel structure CS2. Storage node SN can be adjacent to the bottom of the second channel area contained in the second channel structure CS2 and adjacent to the top of the first gate contained in the first channel structure CS1.

[0046] A second channel structure CS2 can be connected to the top of the storage node SN.

[0047] The second channel structure CS2 can extend in a second direction (D2) and may include multiple layers. Exemplaryly, the second channel structure CS2 may include a second gate, a second gate insulating layer, and a second channel region.

[0048] The second bit line BL2 can be connected to the side of the second channel structure CS2.

[0049] The second bit line BL2 can extend in a third direction (D3). The second bit line BL2 can be adjacent to the side of the second channel region contained in the second channel structure CS2.

[0050] A second bit line BL2 extending in the third direction (D3) can be in common contact with the sides of multiple second channel structures CS2 that are repeatedly arranged in the third direction (D3).

[0051] The second word line WL2 can touch the top of the second channel structure CS2. The second word line WL2 can touch the top of the second gate contained within the second channel structure CS2.

[0052] Multiple second channel structures CS2, arranged repeatedly in the first direction (D1), can be connected to a single second word line WL2.

[0053] Figure 2 shows an equivalent circuit diagram of a memory cell according to one embodiment of the present disclosure.

[0054] Figure 2 shows the connection relationship between the first transistor TR1, the storage node SN, and the second transistor TR2.

[0055] Based on Figures 1 and 2, the structure and operation method of a memory cell according to one embodiment of this disclosure will be described in detail.

[0056] The second transistor TR2 may include a second word line WL2 and a second bit line BL2. Furthermore, the second transistor TR2 may include a second gate, a second gate insulating layer, and a second channel region.

[0057] According to this embodiment, the second gate can be connected to the second word line WL2, and one side of the second channel region can be connected to the second bit line BL2.

[0058] The other side of the second channel region can be connected to a storage node SN. The storage node SN is located between the first transistor TR1 and the second transistor TR2, and can be the region connecting the second channel region containing the second transistor TR2 and the first gate containing the first transistor TR1.

[0059] The first transistor TR1 may include a first word line WL1 and a first bit line BL1. The first transistor TR1 may also include a first gate, a first gate insulating layer, and a first channel region.

[0060] According to this embodiment, the first gate can be in contact with the storage node SN. In addition, the first word line WL1 can be in contact with one side of the first channel area, and the first bit line BL1 can be in contact with the other side of the first channel area.

[0061] A semiconductor device including a first transistor TR1 and a second transistor TR2 can operate as a memory device.

[0062] When a signal with an activation level is supplied to the second gate via the second word line WL2, the second transistor TR2 can be turned on. When the second transistor TR2 is turned on, the voltage supplied to the second bit line BL2 can cause a change in the amount of charge stored in the storage node SN. At this time, the type of data stored in the storage node SN can be determined according to the voltage supplied to the second bit line BL2. This operation is called a write operation.

[0063] The voltage output from the first transistor TR1 can be changed depending on the charge accumulated in the storage node SN.

[0064] When an arbitrary voltage is supplied to the first word line WL1 and the first bit line BL1 is in a pre-charged state, if a charge with an active-level voltage is accumulated in the storage node SN, the pre-charge voltage of the first bit line BL1 can be changed by the voltage supplied by the first word line WL1.

[0065] In contrast, if no charge with an active voltage is accumulated in the storage node SN, the precharge voltage of the first bit line BL1 may not be changed by the voltage provided by the first word line WL1.

[0066] Therefore, by detecting the voltage change of the first bit line BL1, the type of data stored in the storage node SN can be confirmed. This operation is called a read operation.

[0067] A single storage node SN can correspond to a single memory cell. By the selective operation of the first transistor TR1 and the second transistor TR2, different data can be stored in or read from each memory cell.

[0068] Parasitic capacitance may occur between storage node SN and the adjacent first word line WL1, and between storage node SN and the adjacent first bit line BL1. Furthermore, parasitic capacitance may occur between storage node SN and the adjacent second word line WL2, and between storage node SN and the adjacent second bit line BL2.

[0069] Parasitic capacitance can cause voltage drops in storage node SN. For example, a voltage change in the first word line WL1 or the second word line WL2 can cause a voltage change in storage node SN, and the higher the parasitic capacitance, the larger the voltage change will be.

[0070] If a voltage drop occurs in the storage node's signal-to-noise ratio (SN), the sensing margin of the semiconductor device may decrease, potentially degrading the operating characteristics of the memory elements.

[0071] Therefore, a structure is needed to reduce the parasitic capacitance between storage node SN and the adjacent first word line WL1, the parasitic capacitance between storage node SN and the adjacent first bit line BL1, the parasitic capacitance between storage node SN and the second word line WL2, and the parasitic capacitance between storage node SN and the second bit line BL2.

[0072] Figure 3a is a plan view of a portion of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction.

[0073] Figure 3b is a cross-sectional view taken along the first cutting line A1-A1' in Figure 3a.

[0074] Figure 3c is a cross-sectional view taken along the second cutting line B1-B1' in Figure 3a.

[0075] According to this embodiment, the first cutting line A1-A1' can be a cutting line extending in the third direction (D3). The second cutting line B1-B1' can be a cutting line extending in the first direction (D1).

[0076] The structure of a semiconductor device according to one embodiment of this disclosure will be described below with reference to Figures 3a, 3b, and 3c.

[0077] A semiconductor device according to one embodiment of the present disclosure may include a first word line 110 located at the top of the peri region PERI.

[0078] The peri region (PERI) can be a region containing multiple transistors and control circuits. These transistors and control circuits within the peri region (PERI) can be connected to the memory cell located above it by vertical contacts.

[0079] A structure in which the periphery region (PERI) is located at the bottom of a memory cell is called a PUC (Peripheral Under Cell) structure.

[0080] The first word line 110 can extend in a first direction (D1). The first word line 110 can contain multiple layers. For example, the first word line 110 can contain metal, metal nitride, polysilicon, a combination thereof, or multiple layers thereof.

[0081] A first word line 110 can be surrounded by a first insulating layer 120, and multiple adjacent first word lines 110 can be electrically isolated by the first insulating layer 120. The first insulating layer 120 may contain an insulating material such as silicon nitride.

[0082] A first air layer 130 can be placed on top of the first insulating layer 120. The first air layer 130 can be a region containing air.

[0083] The first air layer 130 can open up at least a portion of the side surface of the first channel structure 160.

[0084] Referring to Figure 3c, the first air layer 130 is located between two adjacent first bit lines 150 and may include a first vertical extension V1 extending in a third direction (D3).

[0085] Furthermore, the first air layer 130 may include a first gap fill region 131 located within the first vertical extension V1. The first gap fill region 131 may extend in a third direction (D3).

[0086] The first gap fill region 131 may contain silicon oxide produced by the SOD (Spin on Dielectric) process.

[0087] The formation of a first air layer 130 containing air reduces parasitic capacitance that may occur between the storage node 170 and the first word line 110.

[0088] Furthermore, the first vertical extension V1 included in the first air layer 130 can reduce parasitic capacitance that may occur between the first bit lines 150.

[0089] A second insulating layer 140 can be placed on top of the first air layer 130. The second insulating layer 140 can surround the sides of the first bit line 150, the first channel structure 160, and the storage node 170.

[0090] According to the embodiment, the second insulating layer 140 may contain an insulating material such as silicon nitride.

[0091] The second insulating layer 140 may, by example, include a lower layer 140a, a middle layer 140b, and an upper layer 140c.

[0092] The lower 140a, middle 140b, and upper 140c of the second insulating layer may contain the same insulating material or different insulating materials. The presence of the second insulating layer 140 allows adjacent first bit lines 150, first channel structures 160, and storage nodes 170 to be electrically isolated from each other.

[0093] The first bit line 150 can be located within the second insulating layer 140 and can extend in a third direction (D3). The first bit line 150 can include multiple layers. For example, the first bit line 150 can include metal, metal nitride, polysilicon, a combination thereof, or a multilayer thereof.

[0094] The first bit line 150 can be in contact with the side surface of the first channel structure 160. The first bit line 150 can be shaped to surround at least a portion of the side surface of the first channel structure 160. The first bit line 150 can be in contact with the first channel region 163 contained within the first channel structure 160.

[0095] The first channel structure 160 may include a columnar first gate 161 extending in a second direction (D2), a first gate insulating layer 162 surrounding the side and bottom surfaces of the first gate 161, and a first channel region 163 surrounding the first gate insulating layer 162.

[0096] The first gate 161 may include metal, metal nitride, polysilicon, a combination thereof, or multilayers thereof. The first gate 161 may have a shape that includes sides extending along the second direction (D2). Exemplarily, the first gate 161 may have a cylindrical or polygonal columnar shape.

[0097] The first gate insulating layer 162 may contain an insulating material such as silicon oxide.

[0098] The first channel region 163 can be located on the side and bottom surfaces of the first gate insulating layer 162. The first channel region 163 may, exemplary, include an oxide semiconductor material.

[0099] Oxide semiconductor materials can, for example, include indium gallium zinc oxide (IGZO).

[0100] According to other embodiments, the first channel region 163 may include doped polysilicon, undoped polysilicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), and indium oxide (InO3), among others.

[0101] The first channel region 163 containing an oxide semiconductor material can have low leakage current characteristics.

[0102] The storage node 170 can be surrounded by a second insulating layer 140.

[0103] The storage node 170 may, for example, include metal, metal nitride, polysilicon, a combination thereof, or multilayers thereof. The storage node 170 can electrically connect one first channel structure 160 and one second channel structure 250.

[0104] A third insulating layer 210 can be placed on top of the storage node 170. The third insulating layer 210 may contain an insulating material such as silicon nitride.

[0105] A second air layer 220 can be placed on top of the third insulating layer 210. The second air layer 220 may be an area containing air.

[0106] The second air layer 220 can open up at least a portion of the side surface of the second channel structure 250.

[0107] Referring to Figure 3c, the second air layer 220 is located between two adjacent second bit lines 240 and may include a second vertical extension V2 extending in a third direction (D3).

[0108] Furthermore, the second air layer 220 may include a second gap fill region 221 located within the second vertical extension V2. The second gap fill region 221 may extend in a third direction (D3).

[0109] The second gap fill region 221 may contain silicon oxide produced by the SOD (Spin on Dielectric) process.

[0110] The formation of a second air layer 220 containing air can reduce parasitic capacitance that may occur between the storage node 170 and the second bit line 240, or between the storage node 170 and the second word line 260.

[0111] Furthermore, the second vertical extension V2 included in the second air layer 220 can reduce parasitic capacitance that may occur between the second bit lines 240.

[0112] A fourth insulating layer 230 can be placed on top of the second air layer 220. The fourth insulating layer 230 can surround the sides of the second bit line 240, the second channel structure 250, and the second word line 260.

[0113] According to one embodiment, the fourth insulating layer 230 may contain an insulating material such as silicon nitride.

[0114] The fourth insulating layer 230 may, by example, include a lower fourth insulating layer 230a, a middle fourth insulating layer 230b, and an upper fourth insulating layer 230c.

[0115] The lower 230a, middle 230b, and upper 230c of the fourth insulating layer may contain the same insulating material or different insulating materials.

[0116] The provision of the fourth insulating layer 230 allows the adjacent second bit line 240, second channel structure 250, and second word line 260 to be electrically isolated from each other.

[0117] The second bit line 240 can be located within the fourth insulating layer 230 and can extend in a third direction. The second bit line 240 can include multiple layers. For example, the second bit line 240 can include metal, metal nitride, polysilicon, a combination thereof, or a multilayer thereof.

[0118] The second bit line 240 can be in contact with the side surface of the second channel structure 250. The second bit line 240 can be shaped to surround at least a portion of the side surface of the second channel structure 250. The second bit line 240 can be in contact with the second channel region 253 contained within the second channel structure 240.

[0119] The second channel structure 250 may include a columnar second gate 251 extending in a second direction (D2), a second gate insulating layer 252 surrounding the side and bottom surfaces of the second gate 251, and a second channel region 253 surrounding the second gate insulating layer 252.

[0120] The second gate 251 may include metal, metal nitride, polysilicon, a combination thereof, or multilayers thereof. The second gate 251 may have a shape that includes sides extending along the second direction (D2). Exemplarily, the second gate 251 may have a cylindrical or polygonal columnar shape.

[0121] The second gate insulating layer 252 may contain an insulating material such as silicon oxide.

[0122] The second channel region 253 can be located on the side and bottom surfaces of the second gate insulating layer 252. The second channel region 253 may, exemplary, include an oxide semiconductor material.

[0123] Oxide semiconductor materials can, for example, include indium gallium zinc oxide (IGZO).

[0124] According to other embodiments, the second channel region 253 may include doped polysilicon, undoped polysilicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), and indium oxide (InO3), among others.

[0125] The second channel region 253 containing oxide semiconductor material can have low leakage current characteristics.

[0126] A second word line 260 can be positioned on top of the second channel structure 250. More specifically, the second word line 260 can be connected to a second gate 251 included in the second channel structure 250.

[0127] The second word line 260 can extend in the first direction (D1). The second word line 260 can include multiple layers. For example, the second word line 260 can include metal, metal nitride, polysilicon, a combination thereof, or multiple layers thereof. Multiple adjacent second word lines 260 can be electrically isolated by the fourth insulating layer 230.

[0128] Figure 4a is a plan view of a portion of a memory cell array according to another embodiment of the present disclosure, viewed from a second direction.

[0129] Figure 4b is a cross-sectional view taken along the third cutting line A2-A2' in Figure 4a.

[0130] Figure 4c is a cross-sectional view taken along the fourth cutting line B2-B2' in Figure 4a.

[0131] According to the embodiment, the third cutting line A2-A2' can be a cutting line extending in the third direction (D3). Also, the fourth cutting line B2-B2' can be a cutting line extending in the first direction (D1).

[0132] The structure of a semiconductor device according to one embodiment of this disclosure will be described below with reference to Figures 4a, 4b, and 4c.

[0133] The semiconductor device shown in Figures 4a to 4c has a structure that is substantially the same as the semiconductor device shown in Figures 3a to 3c, except for the first residual sacrificial layer 132 located within the first air layer 130 and the second residual sacrificial layer 222 located within the second air layer 220. Therefore, redundant explanations will be omitted, and the explanation will focus on the residual sacrificial layers 132 and 222.

[0134] The first residual sacrificial layer 132 is located within the first air layer 130 and can surround at least a portion of the side surface of the first channel structure 160.

[0135] The first residual sacrificial layer 132 can surround the side walls of the first channel region 163, which is contained within the first channel structure 160.

[0136] The first residual sacrificial layer 132 may contain carbon-containing materials such as spin-on carbon (SOC).

[0137] The first residual sacrificial layer 132 can be formed by selectively removing the spin-on carbon film when forming the first air layer 130 by a plasma process.

[0138] In this process, the plasma process can use a gas containing at least one of oxygen, nitrogen, or hydrogen, such as O2, N2, H2, CO, CO2, or CH4.

[0139] For example, when the O2 plasma process is performed, oxygen radicals combine with the carbon of the sacrificial film to produce CO or CO2, and the produced CO or CO2 passes through the first vertical extension V1 to remove the sacrificial film pattern and form the first air layer 130.

[0140] In this process, the presence or absence of a sacrificial film pattern can be controlled by adjusting the time, temperature, or gas used during the plasma process.

[0141] The second residual sacrificial layer 222 is located within the second air layer 220 and can surround at least a portion of the side surface of the second channel structure 250.

[0142] The second residual sacrificial layer 222 can surround the side walls of the second channel region 253, which is contained within the second channel structure 250.

[0143] The second residual sacrificial layer 222 may contain carbon-containing materials such as spin-on carbon (SOC).

[0144] The second residual sacrificial layer 222 can be formed by selectively removing the spin-on carbon film when forming the second air layer 220 by a plasma process. Since its manufacturing process is substantially the same as that of the first residual sacrificial layer 132 described above, a redundant explanation will be omitted.

[0145] Figures 5a to 26c illustrate a method for manufacturing a semiconductor device according to one embodiment of this disclosure.

[0146] Figures 5a to 5c illustrate a method for forming a first word line in a semiconductor device according to one embodiment of the present disclosure.

[0147] Figure 5a is a plan view from a second direction of the manufacturing steps of a memory cell array according to one embodiment of the present disclosure.

[0148] Figure 5b is a cross-sectional view taken along the fifth cutting line A3-A3' in Figure 5a.

[0149] Figure 5c is a cross-sectional view taken along the sixth cutting line B3-B3' in Figure 5a.

[0150] Figures 5a to 5c illustrate how the first sacrificial layer is formed above the first ward line.

[0151] Referring to Figures 5a to 5c, a first insulating layer 120 can be formed on top of the first word line 110, and a first sacrificial layer 130a can be formed on top of the first insulating layer 120.

[0152] Although not shown in the drawings, the first word line 110 can be formed on a substrate suitable for semiconductor processing.

[0153] Exemplary, the substrate may consist of a semiconductor material containing silicon. The substrate may include silicon, single-crystal silicon, polysilicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof.

[0154] The substrate may contain other semiconductor materials such as germanium. The substrate may also contain a III / V semiconductor substrate, such as a compound semiconductor substrate like GaAs.

[0155] The substrate may include an SOI (Silicon On Insulator) substrate.

[0156] In other embodiments, the substrate may include a peripheral circuit region (not shown) at its base.

[0157] The first word line 110 can extend in the first direction (D1).

[0158] The first word line 110 may include metals, metal nitrides, polysilicon, combinations thereof, or multilayers thereof.

[0159] The first insulating layer 120 can overlap with the first word line 110 formed on the substrate. The first insulating layer 120 may contain silicon nitride.

[0160] The first sacrificial layer 130a can be formed so as to overlap the entire upper part of the first insulating layer 120. The region in which the first sacrificial layer 130a is formed can be the region that will later become the first air layer 130 by a plasma process.

[0161] The first sacrificial layer 130a may contain carbon-containing material, and may, exemplarily, include spin-on carbon (SOC).

[0162] Figures 6a to 6c illustrate a method for forming the lower second insulating layer and the first pre-bit line on top of the first sacrificial layer 130a.

[0163] Figure 6a is a plan view from a second direction showing the manufacturing steps of a memory cell array according to one embodiment of the present disclosure.

[0164] Figure 6b is a cross-sectional view taken along the seventh cutting line A4-A4' in Figure 6a.

[0165] Figure 6c is a cross-sectional view taken along the eighth cutting line B4-B4' in Figure 6a.

[0166] Referring to Figures 6a to 6c, a second insulating layer lower section 140a can be formed on top of the first sacrificial layer 130a, and a first pre-bit line 150a can be formed inside the second insulating layer lower section 140a.

[0167] The lower part 140a of the second insulating layer may be a region containing silicon nitride, and may later be a region included in the second insulating layer 140.

[0168] The first pre-bit line 150a can be formed by etching a portion of the lower layer 140a of the second insulating layer and depositing a conductive material. The first pre-bit line 150a may include metal, metal nitride, polysilicon, a combination thereof, or a multilayer thereof.

[0169] Figures 7a to 7c illustrate the method for forming the first channel hole 160a.

[0170] Figure 7a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0171] Figure 7b is a cross-sectional view taken along the ninth cutting line A5-A5' in Figure 7a.

[0172] Figure 7c is a cross-sectional view taken along the 10th cutting line B5-B5' in Figure 7a.

[0173] Referring to Figures 7a to 7c, the first channel hole 160a can penetrate the first pre-bit line 150a, the lower second insulating layer 140a, the first sacrificial layer 130a, and at least a portion of the first insulating layer 120.

[0174] The first channel hole 160a can be columnar in shape and extend in the second direction (D2) such that the first channel region 163 contained within the first channel structure 160 has a CAA (Channel All Around) structure.

[0175] Referring to Figure 7a, the first channel hole 160a can be formed within the first bit line 150. Also, referring to Figures 7b and 7c, the first channel hole 160a can be formed such that at least a portion of the first word line 110 is open.

[0176] By opening up at least a portion of the first word line 110, the first channel region 163 can be connected to the first word line 110. The first channel hole 160a can be selectively formed by an etching process.

[0177] Figures 8a to 8c illustrate a method for forming a first pregate 161a, a first pregate insulating layer 162a, and a first prechannel region 163a within a first channel hole 160a.

[0178] Figure 8a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0179] Figure 8b is a cross-sectional view taken along the 11th cutting line A6-A6' in Figure 8a.

[0180] Figure 8c is a cross-sectional view taken along the 12th cutting line B6-B6' in Figure 8a.

[0181] Referring to Figures 8a to 8c, a first pre-channel region 163a, a first pre-gate insulating layer 162a, and a first pre-gate 161a can be formed sequentially within the first channel hole 160a.

[0182] The first prechannel region 163a may contain an oxide semiconductor material, which may, exemplary, include indium gallium zinc oxide.

[0183] The first pre-channel region 163a can be formed to surround the lower and side surfaces of the first channel hole 160a. The lower surface of the first pre-channel region 163a may be in contact with the first word line 110, and a portion of the side surface of the first pre-channel region 163a may be in contact with the first bit line 150.

[0184] A first pregate insulating layer 162a can be formed on top of the first prechannel region 163a. ​​The first pregate insulating layer 162a may contain an insulating material such as silicon oxide.

[0185] A first pregate 161a can be formed on top of the first pregate insulating layer 162a. The first pregate 161a may include metal, metal nitride, polysilicon, a combination thereof, or a multilayer thereof.

[0186] Figures 9a to 9c illustrate the method for forming the first channel structure 160.

[0187] Figure 9a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0188] Figure 9b is a cross-sectional view taken along the 13th cutting line A7-A7' in Figure 9a.

[0189] Figure 9c is a cross-sectional view taken along the 14th cutting line B7-B7' in Figure 9a.

[0190] Referring to Figures 9a to 9c, the first channel structure 160 can be formed by selectively removing a portion of the first pre-channel region 163a, the first pre-gate insulating layer 162a, and the first pre-gate 161a.

[0191] By selectively removing a portion of the first pre-channel region 163a, the first pre-gate insulating layer 162a, and the first pre-gate 161a, multiple first gates 161 can be electrically isolated. In addition, multiple first channel regions 163 that are adjacent to each other in the first direction (D1) can be electrically isolated.

[0192] On the other hand, multiple first channel regions 163 arranged adjacent to each other in the third direction (D3) can be electrically connected by the first bit line 150.

[0193] Figures 10a to 10c illustrate the method for forming the second insulating layer 140.

[0194] Figure 10a is a plan view of the manufacturing steps of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0195] Figure 10b is a cross-sectional view taken along the 15th cutting line A8-A8' in Figure 10a.

[0196] Figure 10c is a cross-sectional view taken along the 16th cutting line B8-B8' in Figure 10a.

[0197] Referring to Figures 10a to 10c, an insulating layer can be further deposited on top of the first channel structure 160 to form a second insulating layer middle section 140b. The second insulating layer middle section 140b may contain an insulating material such as silicon nitride.

[0198] The middle section 140b of the second insulating layer can be a region included in the second insulating layer 140 that is formed later.

[0199] Figures 11a to 11c illustrate the method for forming the first vertical hole V1a.

[0200] Figure 11a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0201] Figure 11b is a cross-sectional view taken along the 17th cutting line A9-A9' in Figure 11a.

[0202] Figure 11c is a cross-sectional view taken along the 18th cutting line B9-B9' in Figure 11a.

[0203] Referring to Figures 11a to 11c, the first vertical hole V1a can be an etched region of the middle 140b and lower 140a of the second insulating layer, and can be a region connected to the first sacrificial layer 130a. The first vertical hole V1a can be formed by selectively etching the region between adjacent first bit lines 150. The first vertical hole V1a can extend in a third direction (D3).

[0204] Figures 12a to 12c illustrate the method for forming the first air layer 130.

[0205] Figure 12a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0206] Figure 12b is a cross-sectional view taken along the 19th cutting line A10-A10' in Figure 12a.

[0207] Figure 12c is a cross-sectional view taken along the 20th cutting line B10-B10' in Figure 12a.

[0208] Referring to Figures 12a to 12c, the process of removing the first sacrificial layer 130a by a plasma process and forming the first air layer 130 is illustrated.

[0209] In the plasma process, gases containing at least one of oxygen, nitrogen, and hydrogen, such as O2, N2, H2, CO, CO2, and CH4, can be used.

[0210] The sacrificial film reacts with the plasma, and the gas generated by the reaction can pass through the first vertical extension V1. The first air layer 130 can be formed in the region where the first sacrificial layer 130a has been removed.

[0211] According to the embodiment, the shape of the residual sacrificial layer in contact with the side wall of the first channel region 163 can be adjusted by adjusting the time, temperature, or gas used in the plasma process.

[0212] For example, if the first sacrificial film 130a is completely removed by the plasma process, no residual sacrificial layer will remain in the first air layer 130, as shown in the embodiments of Figures 3a, 3b, and 3c.

[0213] In contrast, when the plasma process is performed such that a portion of the first sacrificial film 130a remains, the first residual sacrificial layer 132 will remain in the first air layer 130, as shown in the embodiments of Figures 4a, 4b, and 4c.

[0214] Figures 13a to 13c illustrate the method for forming the first pre-gap fill region 131a.

[0215] Figure 13a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0216] Figure 13b is a cross-sectional view taken along the 21st cutting line A11-A11' in Figure 13a.

[0217] Figure 13c is a cross-sectional view taken along the 22nd cutting line B11-B11' in Figure 13a.

[0218] Referring to Figures 13a to 13c, the first pre-gap fill region 131a is formed on the upper part of the second insulating layer 140 by the SOD (Spin on Dielectric) process.

[0219] The first pre-gap fill region 131a may contain an insulating material such as silicon oxide.

[0220] According to the embodiment, the first pre-gap fill region 131a can extend into the interior of the first vertical extension V1 from the upper part of the second insulating layer middle section 140b to the depth where the first bit line 150 is located.

[0221] If the first pregap fill region 131a extends to the depth where the first bit line 150 is located, it can function as an insulating film between adjacent first bit lines 150. The first pregap fill region 131a extending between adjacent first bit lines 150 can reduce the parasitic capacitance that occurs between the first bit lines 150.

[0222] Figures 14a to 14c illustrate the method for forming the first gap fill region 131.

[0223] Figure 14a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0224] Figure 14b is a cross-sectional view taken along the 23rd cutting line A12-A12' in Figure 14a.

[0225] Figure 14c is a cross-sectional view taken along the 24th cutting line B12-B12' in Figure 14a.

[0226] Referring to Figures 14a to 14c, the first gap fill region 131 can be formed by removing a portion of the first pre-gap fill region 131a and a portion of the second insulating layer middle section 140b.

[0227] Figures 15a to 15c illustrate how to form the storage node 170.

[0228] Figure 15a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0229] Figure 15b is a cross-sectional view taken along the 25th cutting line A13-A13' in Figure 15a.

[0230] Figure 15c is a cross-sectional view taken along the 26th cutting line B13-B13' in Figure 15a.

[0231] Referring to Figures 15a to 15c, a storage node 170 can be formed above the first gate 161 included in the first channel structure 160.

[0232] Storage node 170 may include metal, metal nitride, polysilicon, a combination of these, or multilayers of these.

[0233] According to one embodiment, a second insulating layer upper stage 140c can be further formed on top of the first channel structure 160, and a storage node 170 can be formed within the second insulating layer upper stage 140c.

[0234] The upper part 140c of the second insulating layer can be a region included in the second insulating layer 140.

[0235] By selectively etching a portion of the upper layer 140c of the second insulating layer, the region in which the storage node 170 is formed can be defined.

[0236] Figures 16a to 16c illustrate how to form a second sacrificial layer 220a on top of the storage node 170.

[0237] Figure 16a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0238] Figure 16b is a cross-sectional view taken along the 27th cutting line A14-A14' in Figure 16a.

[0239] Figure 16c is a cross-sectional view taken along the 28th cutting line B14-B14' in Figure 16a.

[0240] Referring to Figures 16a to 16c, a third insulating layer 210 can be formed on top of the storage node 170, and a second sacrificial layer 220a can be formed on top of the third insulating layer 210.

[0241] The third insulating layer 210 can include silicon nitride or the like, and the second sacrificial layer 220a can include a carbon-containing substance. Exemplarily, the second sacrificial layer 220a can include spin on carbon (SOC).

[0242] FIGS. 17A through 17C are for explaining a method of forming a lower portion 230a of a fourth insulating layer and a second pre-bit line 240a over the second sacrificial layer 220a.

[0243] FIG. 17A is a plan view of a manufacturing step of a memory cell array according to an embodiment of the present disclosure, viewed from a second direction (D2).

[0244] FIG. 17B is a cross-sectional view taken along a 29th cutting line A15-A15' of FIG. 17A.

[0245] FIG. 17C is a cross-sectional view taken along a 30th cutting line B15-B15' of FIG. 17A.

[0246] Referring to FIGS. 17A through 17C, a lower portion 230a of a fourth insulating layer can be formed over the second sacrificial layer layer 220a, and a second pre-bit line 240a can be formed inside the lower portion 230a of the fourth insulating layer.

[0247] The lower portion 230a of the fourth insulating layer can be a region including silicon nitride, and later can be a region included in the fourth insulating layer 230.

[0248] The second pre-bit line 240a can be formed by etching a partial region of the lower portion 230a of the fourth insulating layer and depositing a conductive material. The second pre-bit line 240a can include a metal, a metal nitride, polysilicon, a combination thereof, or a multilayer thereof.

[0249] FIGS. 18A through 18C are for explaining a method of forming a second channel hole 250a.

[0250] Figure 18a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0251] Figure 18b is a cross-sectional view taken along the 31st cutting line A16-A16' in Figure 18a.

[0252] Figure 18c is a cross-sectional view taken along the 32nd cutting line B16-B16' in Figure 18a.

[0253] Referring to Figures 18a to 18c, the second channel hole 250a can penetrate at least a portion of the second pre-bit line 240a, the second lower insulating layer 240a, the second sacrificial layer 220a, and the third insulating layer 210.

[0254] The second channel hole 250a can be columnar in shape and extend in the second direction (D2) such that the second channel region 253 contained within the second channel structure 250 has a CAA (Channel All Around) structure.

[0255] Referring to Figure 18a, the second channel hole 250a can be formed within the second bit line 240. Also, referring to Figures 18b and 18c, the second channel hole 250a can be formed such that at least a portion of the storage node 170 is open.

[0256] By freeing up at least a portion of the storage node 170, the second channel region 253 can be connected to the storage node 170. The second channel hole 250a can be selectively formed by an etching process.

[0257] Figures 19a to 19c illustrate a method for forming a second pregate 251a, a second pregate insulating layer 252a, and a second prechannel region 253a within a second channel hole 250a.

[0258] Figure 19a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0259] Figure 19b is a cross-sectional view taken along the 33rd cutting line A17-A17' in Figure 19a.

[0260] Figure 19c is a cross-sectional view taken along the 34th cutting line B17-B17' in Figure 19a.

[0261] Referring to Figures 19a to 19c, a second pre-channel region 253a, a second pre-gate insulating layer 252a, and a second pre-gate 251a can be formed sequentially within the second channel hole 250a.

[0262] The second prechannel region 253a may contain an oxide semiconductor material, which may, exemplarily, include indium gallium zinc oxide.

[0263] The second pre-channel area 253a can be formed to surround the bottom and sides of the second channel hole 250a. The bottom of the second pre-channel area 253a is in contact with the storage node 170, and a portion of the side of the second pre-channel area 253a can be in contact with the second bit line 240.

[0264] A second pregate insulating layer 252a can be formed on top of the second prechannel region 253a. The second pregate insulating layer 252a may contain an insulating material such as silicon oxide.

[0265] A second pregate 251a can be formed on top of the second pregate insulating layer 252a. The second pregate 251a may include metal, metal nitride, polysilicon, a combination thereof, or a multilayer thereof.

[0266] Figures 20a to 20c illustrate the method for forming the second channel structure 250.

[0267] FIG. 20a is a plan view of the manufacturing steps of a memory cell array according to an embodiment of the present disclosure, viewed from the second direction (D2).

[0268] FIG. 20b is a cross-sectional view taken along the 35th cutting line A18-A18' of FIG. 20a.

[0269] FIG. 20c is a cross-sectional view taken along the 36th cutting line B18-B18' of FIG. 20a.

[0270] Referring to FIGS. 20a to 20c, the second channel structure 250 can be formed by selectively removing a part of the second pre-channel region 253a, the second pre-gate insulating layer 252a, and the second pre-gate 251a.

[0271] By selectively removing a part of the second pre-channel region 253a, the second pre-gate insulating layer 252a, and the second pre-gate 251a, a plurality of second gates 251 can be electrically separated. Also, a plurality of second channel regions 253 arranged adjacent to each other in the first direction (D1) can be electrically separated.

[0272] On the other hand, a plurality of second channel regions 253 arranged adjacent to each other in the third direction (D3) can be electrically connected by the second bit line 240.

[0273] FIGS. 21a to 21c are for explaining a method of forming the fourth insulating layer 230.

[0274] FIG. 21a is a plan view of the manufacturing steps of a memory cell array according to an embodiment of the present disclosure, viewed from the second direction (D2).

[0275] FIG. 21b is a cross-sectional view taken along the 37th cutting line A19-A19' of FIG. 21a.

[0276] FIG. 21c is a cross-sectional view taken along the 38th cutting line B19-B19' of FIG. 21a.

[0277] Referring to Figures 21a to 21c, an insulating layer can be further deposited on top of the second channel structure 250 to form a fourth insulating layer intermediate 230b. The fourth insulating layer intermediate 230b may contain an insulating material such as silicon nitride. The fourth insulating layer intermediate 230b may later be a region included in the fourth insulating layer 230.

[0278] Figures 22a to 22c illustrate the method for forming the second vertical hole V2a.

[0279] Figure 22a is a plan view of the manufacturing steps of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0280] Figure 22b is a cross-sectional view taken along the 39th cutting line A20-A20' in Figure 22a.

[0281] Figure 22c is a cross-sectional view taken along the 40th cutting line B20-B20' ​​in Figure 22a.

[0282] Referring to Figures 22a to 22c, the second vertical hole V2a can be an etched region of the middle 230b and lower 230a of the fourth insulating layer, and can be a region connected to the second sacrificial layer 220a. The second vertical hole V2a can be formed by selectively etching the region between adjacent second bit lines 240. The second vertical hole V2a can extend in a third direction (D3).

[0283] Figures 23a to 23c illustrate the method for forming the second air layer 220.

[0284] Figure 23a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0285] Figure 23b is a cross-sectional view taken along the 41st cutting line A21-A21' in Figure 23a.

[0286] Figure 23c is a cross-sectional view taken along the 42nd cutting line B21-B21' in Figure 23a.

[0287] Referring to Figures 23a to 23c, the process of removing the second sacrificial layer 220a by a plasma process and forming the second air layer 220 is illustrated.

[0288] In the plasma process, gases containing at least one of oxygen, nitrogen, and hydrogen, such as O2, N2, H2, CO, CO2, and CH4, can be used.

[0289] The sacrificial film reacts with the plasma, and the gas generated by the reaction can pass through the second vertical extension V2. A second air layer 220 can be formed in the region where the second sacrificial film 220a has been removed.

[0290] According to the embodiment, the shape of the residual sacrificial layer in contact with the side wall of the second channel region 253 can be adjusted by adjusting the time, temperature, or gas used in the plasma process.

[0291] For example, if the second sacrificial film 220a is completely removed by the plasma process, no residual sacrificial layer will remain in the second air layer 220, as shown in the embodiments of Figures 3a, 3b, and 3c.

[0292] In contrast, when the plasma process is performed such that a portion of the second sacrificial film 220a remains, the second residual sacrificial layer 222 will remain within the second air layer 220, as shown in the embodiments of Figures 4a, 4b, and 4c.

[0293] Figures 24a to 24c illustrate the method for forming the second pregap fill region 221a.

[0294] Figure 24a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0295] Figure 24b is a cross-sectional view taken along the 43rd cutting line A22-A22' in Figure 24a.

[0296] Figure 24c is a cross-sectional view taken along the 44th cutting line B22-B22' in Figure 24a.

[0297] Referring to Figures 24a to 24c, the SOD (Spin on Dielectric) process forms a second pre-gap fill region 221a above the middle section 230b of the fourth insulating layer.

[0298] The second pre-gap fill region 221a may contain an insulating material such as silicon oxide.

[0299] According to the embodiment, the second pregap fill region 221a can extend into the interior of the second vertical extension V2 from the upper part of the fourth insulating layer middle section 230b to the depth where the second bit line 240 is located.

[0300] If the second pregap fill region 221a extends to the depth where the second bit line 240 is located, it can function as an insulating film between adjacent second bit lines 240. The second pregap fill region 221a extending between adjacent second bit lines 240 can reduce the parasitic capacitance that occurs between the second bit lines 240.

[0301] Figures 25a to 25c illustrate the method for forming the second gap fill region 221.

[0302] Figure 25a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0303] Figure 25b is a cross-sectional view taken along the 45th cutting line A23-A23' in Figure 25a.

[0304] Figure 25c is a cross-sectional view taken along the 46th cutting line B23-B23' in Figure 25a.

[0305] Referring to Figures 25a to 25c, the second gap fill region 221 can be formed by removing a portion of the second pre-gap fill region 221a and a portion of the middle section 230b of the fourth insulating layer.

[0306] Figures 26a to 26c illustrate the method for forming the second word line 260.

[0307] Figure 26a is a plan view of a manufacturing step of a memory cell array according to one embodiment of the present disclosure, viewed from a second direction (D2).

[0308] Figure 26b is a cross-sectional view taken along the 47th cutting line A24-A24' in Figure 26a.

[0309] Figure 26c is a cross-sectional view taken along the 48th cutting line B24-B24' in Figure 26a.

[0310] Referring to Figures 26a to 26c, a second word line 260 can be formed above the second gate 251, which is included in the second channel structure 250.

[0311] The second word line 260 may include metals, metal nitrides, polysilicon, combinations thereof, or multilayers thereof.

[0312] According to the embodiment, a fourth insulating layer upper stage 230c can be further formed on the upper part of the second channel structure 250, and a second word line 260 can be formed within the fourth insulating layer upper stage 230c.

[0313] By selectively etching a portion of the upper 230c of the fourth insulating layer, the region in which the second word line 260 is formed can be defined.

[0314] The fourth insulating layer 230 may be a region including the lower layer 230a, the middle layer 230b, and the upper layer 230c of the fourth insulating layer.

[0315] The second word line 260 can have a shape that extends in the first direction (D1).

[0316] The second word line 260 can be connected in common to multiple second channel structures 250 adjacent in the second direction.

[0317] Furthermore, according to the embodiment, a peri region PERI can be further formed below the first word line 110 and the first insulating layer 120. In this case, the peri region PERI may be a region that includes multiple transistors and control circuits.

[0318] While embodiments of this disclosure have been described above with reference to the attached drawings, any person with ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without altering its technical idea or essential features. Therefore, it should be understood that the embodiments described above are illustrative and not limiting in all respects. [Explanation of Symbols]

[0319] 110 First Wordline 120 First insulating layer 130 First air layer 130a First Sacrifice Layer 131 First Gap Fill Region 131a First pre-gap fill area 132. First remaining victim group (remaining victim group) 140 Second insulating layer 140a Lower part of the second insulating layer 140b Middle section of the second insulating layer 140c Upper part of the second insulating layer 150 1st bit line 160 First channel structure 160a First Channel Hall 161 Gate 1 161a First Pregate 162 First Gate Insulation Layer 162a First pregate insulating layer 163 First channel region 163a First prechannel region 170 storage nodes 210 Third insulating layer 220 Second air layer 220a Second Sacrifice Layer 221 Second Gap Fill Area 221a Second pre-gap fill area 222 Second remaining victim group (remaining victim group) 230 Fourth insulating layer 230a Lower part of the fourth insulating layer 230b Middle section of the fourth insulating layer 230c Upper part of the 4th insulating layer 240 Second bit line 240a Lower part of the second insulating layer 250 Second channel structure 250a Second Channel Hall 251 Gate 2 251a Second Pregate 252 Second gate insulating layer 252a Second pregate insulating layer 253 Second channel region 253a Second pre-channel region 260 Second Wordline BL1 1st bit line BL2 2nd bit line CS1 First Channel Structure CS2 Second Channel Structure D1 1st direction D2 2nd direction D3 Third direction MC Memory Cell PERI (Peripheral Region) SN Storage Node TR1 First Transistor TR2 Second transistor V1 1st vertical extension V1a First Vertical Hall V2 2nd vertical extension V2a Second Vertical Hall WL1 1st Wardline WL2 2nd Wardline

Claims

1. The first channel structure, A first air layer surrounding the side surface of the first channel structure, A first bit line adjacent to the side surface of the first channel structure, A first word line adjacent to the lower part of the first channel structure, A storage node having one end in contact with the upper part of the first channel structure, A second channel structure adjacent to the top of the aforementioned storage node, A second air layer surrounding the side surface of the second channel structure, A second bit line adjacent to the side surface of the second channel structure, The second channel structure includes a second word line adjacent to the upper part of the second channel structure, The first bit line extends in a direction perpendicular to the direction in which the first channel structure extends, The second word line extends in a direction perpendicular to the direction in which the second channel structure extends, and is a semiconductor device.

2. The semiconductor device according to claim 1, wherein the first bit line extends in a direction perpendicular to the direction in which the second word line extends.

3. The first air layer is The semiconductor device according to claim 1, comprising a first vertical extension located between two adjacent first bit lines.

4. The aforementioned second air layer is The semiconductor device according to claim 1, comprising a second vertical extension located between two adjacent second bit lines.

5. The first channel structure is, The columnar first gate extending in the vertical direction, A first gate insulating layer surrounding the side and bottom surfaces of the first gate, The first channel region surrounding the first gate insulating layer includes, The second channel structure described above is The columnar second gate extending in the vertical direction, A second gate insulating layer surrounding the side and bottom surfaces of the second gate, The semiconductor device according to claim 1, comprising a second channel region surrounding the second gate insulating layer.

6. The semiconductor device according to claim 1, further comprising a peri region located below the first word line.

7. The semiconductor device according to claim 3, wherein the first air layer includes a first gap fill region located within the first vertical extension.

8. The semiconductor device according to claim 4, wherein the second air layer includes a second gap fill region located within the second vertical extension.

9. The semiconductor device according to claim 1, wherein the first air layer includes a first residual sacrificial layer in contact with the side wall of the first channel structure.

10. The semiconductor device according to claim 1, wherein the second air layer includes a second residual sacrificial layer in contact with the side wall of the second channel structure.

11. The semiconductor device according to claim 1, wherein the first air layer is located between the first bit line and the first word line and surrounds a portion of the side surface of the first channel structure.

12. The semiconductor device according to claim 1, wherein the second air layer is located between the second bit line and the second word line and surrounds a portion of the side surface of the second channel structure.

13. Multiple first word lines, each extending in the first direction, A plurality of first channel structures are in contact with the upper part of the plurality of first word lines and extend in a second direction perpendicular to the first direction, Among the plurality of first channel structures, a plurality of first bit lines that are in common contact with the sides of the first channel structures located in a third direction, A first air layer located between the plurality of first channel structures, A plurality of storage nodes adjacent to the upper part of each of the plurality of first channel structures, A plurality of second channel structures are adjacent to each of the plurality of storage nodes and extend in the second direction, Among the plurality of second channel structures, a plurality of second bit lines that are in common contact with the side surfaces of the second channel structures located in the third direction, A second air layer located between the plurality of second channel structures, A semiconductor device comprising: a plurality of second word lines, among the plurality of second channel structures, that are in contact with the upper part of the second channel structures located in the first direction.

14. The first air layer surrounds a portion of the side surface of the plurality of first channel structures, The semiconductor device according to claim 13, wherein the second air layer surrounds a portion of the side surfaces of the plurality of second channel structures.

15. The plurality of first word lines are arranged repeatedly in the third direction, The semiconductor device according to claim 13, wherein the plurality of second word lines are arranged repeatedly in the third direction.

16. Each of the plurality of first channel structures is A columnar first gate extending in the second direction, A first gate insulating layer surrounding the side and bottom surfaces of the first gate, The first channel region surrounding the first gate insulating layer includes, Each of the aforementioned plurality of second channel structures is A columnar second gate extending in the second direction, A second gate insulating layer surrounding the side and bottom surfaces of the second gate, The semiconductor device according to claim 13, further comprising a second channel region surrounding the second gate insulating layer.

17. At least a portion of the first air layer is located below the plurality of first bit lines, The semiconductor device according to claim 13, wherein at least a portion of the second air layer is located below the plurality of second bit lines.

18. The first air layer is located between two adjacent first bit lines and includes a plurality of first vertical extensions extending in the third direction. The semiconductor device according to claim 13, wherein the second air layer is located between two adjacent second bit lines and includes a plurality of second vertical extensions extending in the third direction.

19. A first word line is formed on the substrate. A first bit line is formed above the first word line, A first channel structure is formed in which the lower surface is in contact with the first word line and the side surface is in contact with the first bit line. A first air layer is formed surrounding the side surface of the first channel structure. A storage node is formed in contact with the upper surface of the first channel structure, A second bit line is formed at the top of the aforementioned storage node. A second channel structure is formed in which the lower surface is in contact with the storage node and the side surface is in contact with the second bit line. A method for manufacturing a semiconductor device, comprising forming a second air layer surrounding the side surface of the second channel structure.

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