Wiring board, multilayer wiring board, semiconductor device, and method for manufacturing a wiring board

Abstract

To provide a wiring board that can improve the reliability of electrical connections. [Solution] The wiring board 10 has a first wiring structure 11 and a second wiring structure 12 formed on the upper surface of the first wiring structure 11 and having a higher wiring density than the first wiring structure 11. The first wiring structure 11 has a wiring layer 20, an insulating layer 21 covering the wiring layer 20, and a wiring layer 22 having an upper end surface exposed from the upper surface of the insulating layer 21, penetrating the insulating layer 21 in the thickness direction and electrically connected to the wiring layer 20. The second wiring structure 12 has an insulating layer 30 formed on the upper surface of the insulating layer 21, a plurality of via wirings 40 penetrating the insulating layer 30 in the thickness direction, and a wiring layer 31 formed on the upper surface of the insulating layer 21 and electrically connected to the wiring layer 22 via the plurality of via wirings 40. The filler content in the insulating layer 30 is lower than the filler content in the insulating layer 21.

Description

Technical Field

[0001] The present invention relates to a wiring board, a laminated wiring board, a semiconductor device, and a method for manufacturing a wiring board.

Background Art

[0002] Conventionally, as a wiring board on which electronic components such as semiconductor chips are mounted, a wiring board in which a plurality of wiring layers and insulating layers are alternately laminated by a build-up method is known. As this type of wiring board, a wiring board has been proposed in which a high-density wiring structure including an insulating layer made of a photosensitive resin is formed on a low-density wiring structure including an insulating layer made of a non-photosensitive thermosetting resin (for example, see Patent Document 1).

[0003] In the above wiring board, after being polished so that the upper surface of the uppermost insulating layer in the low-density wiring structure and the upper end surface of the uppermost wiring layer are flush, a wiring layer in the high-density wiring structure is formed on the upper surface of the uppermost insulating layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, in the above-described wiring board, improvement in the electrical connection reliability between the wiring layer in the low-density wiring structure and the wiring layer in the high-density wiring structure is desired.

Means for Solving the Problems

[0006] According to one aspect of the present invention, a first wiring structure and a second wiring structure formed on the upper surface of the first wiring structure and having a higher wiring density than the first wiring structure, wherein the first wiring structure comprises a first wiring layer, a first insulating layer covering the first wiring layer, and a second wiring layer having an upper end surface exposed from the upper surface of the first insulating layer and penetrating the first insulating layer in the thickness direction and electrically connected to the first wiring layer, wherein the second wiring structure comprises a second insulating layer formed on the upper surface of the first insulating layer, a plurality of through holes penetrating the second insulating layer in the thickness direction and exposing a part of the upper end surface of the second wiring layer, a plurality of via wirings each filled in the plurality of through holes, and a third wiring layer formed on the upper surface of the second insulating layer and electrically connected to the second wiring layer via the plurality of via wirings, wherein the filler content in the second insulating layer is lower than the filler content in the first insulating layer. [Effects of the Invention]

[0007] According to one aspect of the present invention, the electrical connection reliability can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic cross-sectional view showing a wiring board according to one embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view showing an enlarged portion of a wiring board according to one embodiment. [Figure 3] Figure 3 is a schematic plan view showing a part of a wiring board according to one embodiment. [Figure 4] Figure 4 is a schematic cross-sectional view showing a semiconductor device of one embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 6] Figure 6 is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 7] Figure 7 is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 8]FIG. 8 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to an embodiment. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a method of manufacturing a laminated wiring board according to an embodiment. [Figure 23] FIG. 23 is a schematic plan view showing a part of a wiring board of a modified example. [Figure 24] FIG. 24 is a schematic plan view showing a part of a wiring board of a modified example.

MODE FOR CARRYING OUT THE INVENTION

[0009] Hereinafter, an embodiment will be described with reference to the accompanying drawings. Note that, for convenience, the accompanying drawings may show enlarged portions that are characteristic in order to make the features easier to understand, and the dimensional ratios of each component may be different in each drawing. Also, in sectional views, in order to make the sectional structure of each member easier to understand, the hatching of some members is shown replaced with a satin pattern, and the hatching of some members is omitted. In plan views, in order to make the planar shape of each member easier to understand, some members are hatched. Note that, unless otherwise stated, in the description of the present disclosure, the numerical range of "X1 to X2" defined by the upper limit value X1 and the lower limit value X2 means that it is X1 or more and X2 or less.

[0010] (Overall Configuration of Wiring Substrate 10) As shown in FIG. 1, the wiring substrate 10 has a first wiring structure 11 and a second wiring structure 12. The first wiring structure 11 has a wiring layer 20, an insulating layer 21, and a wiring layer 22. The second wiring structure 12 is provided on one side of the first wiring structure 11. The second wiring structure 12 is a high-density wiring structure (fine wiring structure) in which a wiring layer having a higher wiring density than the first wiring structure 11 is formed. The second wiring structure 12 has an insulating layer 30, a wiring layer 31, an insulating layer 32, a wiring layer 33, an insulating layer 34, a wiring layer 35, an insulating layer 36, and a wiring layer 37.

[0011] In this embodiment, the side of the wiring substrate 10 on the wiring layer 37 side in FIG. 1 is referred to as the upper side or one side, and the side on the wiring layer 20 side is referred to as the lower side or the other side. Also, in this embodiment, for convenience, the surface on the wiring layer 37 side of each part is referred to as the upper surface or one surface, and the surface on the wiring layer 20 side of each part is referred to as the lower surface or the other surface. However, the wiring substrate 10 can be used in an upside-down state or arranged at an arbitrary angle. Also, in this specification, "plan view" means looking at an object from the normal direction of one surface of the wiring layer 37, and "planar shape" means the shape of an object when viewed from the normal direction of one surface of the wiring layer 37.

[0012] The planar shape of the wiring board 10 can be set to any shape and size. For example, the planar shape of the wiring board 10 is formed in a rectangular shape. The planar size of the wiring board 10 can be, for example, approximately 30mm x 30mm to 50mm x 50mm.

[0013] (Structure of the first wiring structure 11) The wiring layer 20 is the bottommost wiring layer in the first wiring structure 11, and also the bottommost wiring layer in the wiring board 10. The lower surface of the wiring layer 20 is exposed from the lower surface of the insulating layer 21. The lower surface of the wiring layer 20 is formed flush with, for example, the lower surface of the insulating layer 21. The wiring layer 20 functions, for example, as an external connection terminal for electrically connecting to other wiring boards. As the material of the wiring layer 20, for example, copper (Cu) or a copper alloy can be used. The thickness of the wiring layer 20 can be, for example, about 10 μm to 30 μm. The line / space (L / S) of the wiring layer 20 can be, for example, about 10 μm / 10 μm to 50 μm / 50 μm. Here, in line / space, line represents the wiring width, and space represents the distance between adjacent wirings (wiring spacing). For example, if the line / space is specified as 10μm / 10μm to 50μm / 50μm, it means that the wiring width is between 10μm and 50μm, and the spacing between adjacent wirings is between 10μm and 50μm. Note that the wiring width and wiring spacing do not necessarily have to be equal.

[0014] The planar shape of the wiring layer 20 can be set to any shape and size. For example, the planar shape of the wiring layer 20 is formed to be circular. The diameter of the wiring layer 20 can be, for example, about 90 μm to 110 μm.

[0015] The insulating layer 21 covers the upper and side surfaces of the wiring layer 20, while exposing the lower surface of the wiring layer 20. The insulating layer 21 is both the lowest insulating layer and the uppermost insulating layer in the first wiring structure 11. The insulating layer 21 is an insulating layer mainly composed of a non-photosensitive resin. The insulating layer 21 can be mainly composed of a thermosetting non-photosensitive resin such as epoxy resin, imide resin, phenolic resin, or cyanate resin. The insulating layer 21 is, for example, an insulating layer mainly composed of a thermosetting non-photosensitive resin and having a reinforcing member 21G. The insulating layer 21 has higher rigidity than the insulating layers 30, 32, 34, and 36 of the second wiring structure 12. The insulating layer 21 can be configured by impregnating the reinforcing member 21G with a thermosetting non-photosensitive resin. As the reinforcing member 21G, for example, woven or nonwoven fabrics such as glass fiber, carbon fiber, or aramid fiber can be used. The thickness of the insulating layer 21 can be, for example, about 30 μm to 80 μm.

[0016] As shown in Figure 2, the wiring layer 22 is a via wiring embedded in the insulating layer 21. More specifically, the wiring layer 22 is a via wiring filled in a through-hole 21X that penetrates the insulating layer 21 in the thickness direction and exposes a portion of the upper surface of the wiring layer 20. The wiring layer 22 is electrically connected to the wiring layer 20. The wiring layer 22 is the uppermost wiring layer in the first wiring structure 11. Note that in Figure 2, the insulating layers 34, 36 and the wiring layers 35, 37 are omitted from the illustration for the sake of simplicity.

[0017] As shown in Figure 3, the planar shape of the wiring layer 22 is formed, for example, in a circular shape. However, the planar shape of the wiring layer 20 is not limited to a circular shape and can be set to any shape. As shown in Figure 2, the wiring layer 22 is formed in a tapered shape, with its diameter decreasing from the top (second wiring structure 12 side) to the bottom (wiring layer 20 side) in Figure 2. For example, the wiring layer 22 is formed in an inverted frustoconical shape, with the upper end surface having a larger diameter than the lower end surface. The upper end surface of the wiring layer 22 is exposed from the insulating layer 21. The upper end surface of the wiring layer 22 is formed flush with the upper surface of the insulating layer 21, for example. The upper end surface of the wiring layer 22 and the upper surface of the insulating layer 21 are polished surfaces, for example. The diameter of the upper end surface of the wiring layer 22 can be, for example, about 60 μm to 80 μm. As the material for the wiring layer 22, for example, copper or a copper alloy can be used.

[0018] The wiring layer 22 has a seed layer 22A formed on the inner surface of the through hole 21X and a metal layer 22B formed inside the through hole 21X, which is further inside than the seed layer 22A. The seed layer 22A is formed to cover the entire inner surface of the through hole 21X, that is, the entire inner wall surface of the through hole 21X and the entire upper surface of the wiring layer 20 exposed at the bottom of the through hole 21X. The seed layer 22A is not formed on the upper surface of the insulating layer 21, for example. As the seed layer 22A, for example, an electroless plating film formed by an electroless plating method or a sputtered film formed by a sputtering method can be used.

[0019] The metal layer 22B is formed to fill the through-holes 21X located inside the seed layer 22A. The metal layer 22B is formed to cover the entire surface of the seed layer 22A. As the metal layer 22B, for example, an electroplated layer formed by an electroplating method can be used. As the material for the metal layer 22B, for example, copper or a copper alloy can be used.

[0020] (Structure of the second wiring structure 12) As shown in Figure 1, the second wiring structure 12 is laminated on the upper surface of the first wiring structure 11. The second wiring structure 12 is laminated on the upper surface of the insulating layer 21 and the upper surface of the wiring layer 22.

[0021] The insulating layers 30, 32, 34, and 36 of the second wiring structure 12 are, for example, insulating layers mainly composed of a photosensitive resin. As the material for the insulating layers 30, 32, 34, and 36, for example, a photosensitive insulating resin mainly composed of a phenolic resin or a polyimide resin can be used. The insulating layers 30, 32, 34, and 36 may contain fillers such as silica or alumina. The filler content in each of the insulating layers 30, 32, 34, and 36 is lower than the filler content in the insulating layer 21. The insulating layers 30, 32, 34, and 36 of this embodiment do not contain fillers. The thickness of each of the insulating layers 30, 32, 34, and 36 is thinner than the thickness of the insulating layer 21. The thickness of each of the insulating layers 30, 32, 34, and 36 can be, for example, about 5 μm to 10 μm.

[0022] Copper or a copper alloy can be used as the material for the wiring layers 31, 33, 35, and 37 of the second wiring structure 12. The thickness of each wiring layer 31, 33, 35, and 37 is thinner than the thickness of the wiring layer 20. The thickness of each wiring layer 31, 33, and 35 can be, for example, about 1 μm to 3 μm. The thickness of the wiring layer 37 can be, for example, about 5 μm to 15 μm. Each of the wiring layers 31, 33, 35, and 37 has a higher wiring density than the wiring layer 20, that is, a smaller line / space (L / S) than the wiring layer 20. The line / space of the wiring layers 31, 33, 35, and 37 can be about 1 μm / 1 μm to 3 μm / 3 μm.

[0023] (Configuration of the insulating layer 30) The insulating layer 30 is laminated on the upper surface of the insulating layer 21 so as to cover the upper end surface of the wiring layer 22. The insulating layer 30 is formed, for example, to cover the entire upper surface of the insulating layer 21. The insulating layer 30 is the bottom insulating layer in the second wiring structure 12.

[0024] As shown in Figure 2, the insulating layer 30 has through-holes 30X formed at required locations, penetrating the insulating layer 30 in the thickness direction and exposing a portion of the upper end surface of the wiring layer 22. Multiple through-holes 30X are formed for one wiring layer 22. As shown in Figure 3, in this embodiment, five through-holes 30X are formed for one wiring layer 22. The five through-holes 30X are, for example, spaced apart from each other on the wiring layer 22. The five through-holes 30X are, for example, arranged in a + shape in a plan view. Specifically, three of the five through-holes 30X are arranged side by side in the left-right direction in the figure, and three of the through-holes 30X are arranged side by side in the up-down direction in the figure. The planar shape of each through-hole 30X can be set to any shape and size. The planar shape of each through-hole 30X is, for example, circular.

[0025] As shown in Figure 2, the opening diameter of each through-hole 30X is formed to be smaller than the opening diameter of the through-hole 21X. Each through-hole 30X is formed in a tapered shape, with the diameter decreasing from the upper side (wiring layer 31 side) to the lower side (wiring layer 22 side) in Figure 2. For example, each through-hole 30X is formed in an inverted frustoconical shape, where the opening diameter of the lower opening end is smaller than the opening diameter of the upper opening end. The opening diameter of the upper opening end of each through-hole 30X can be, for example, about 10 μm to 15 μm.

[0026] (Configuration of wiring layer 31) The wiring layer 31 is laminated on the upper surface of the insulating layer 30. The wiring layer 31 is the bottommost wiring layer in the second wiring structure 12. The wiring layer 31 is electrically connected to the wiring layer 22 via via wiring 40 formed in through holes 30X. The wiring layer 31 is formed integrally with, for example, the via wiring 40 that are each filled in the through holes 30X. The wiring layer 31 is formed integrally with a plurality of via wiring 40 that are filled in a plurality of through holes 30X. One wiring layer 31 is electrically connected to one wiring layer 22 via a plurality of via wiring 40. In this way, a plurality (five in this embodiment) of via wiring 40 are connected to one wiring layer 22.

[0027] Each via wiring 40 is formed to fill the through hole 30X and therefore has the same structure as the through hole 30X. Each via wiring 40 is formed in an inverted truncated cone shape, where the diameter of the upper surface is larger than the diameter of the lower surface. Here, as shown in Figure 3, the planar size of each via wiring 40 is set to be smaller than the planar size of the wiring layer 22. The diameter of the upper surface of each via wiring 40 is set to be smaller than the diameter of the upper end surface of the wiring layer 22. The diameter of the upper surface of each via wiring 40 is set to be, for example, about 0.1 to 0.3 times the diameter of the upper end surface of each via wiring 40. The diameter of the upper surface of each via wiring 40 can be, for example, about 10 μm to 15 μm. The separation distance between adjacent via wirings 40 can be, for example, about 10 μm to 15 μm. Note that in Figure 3, other components are omitted from the illustration in order to show the relationship between the through hole 21X and the wiring layer 22 and the through hole 30X and the via wiring 40.

[0028] As shown in Figure 2, the via wiring 40 has a seed layer 41 that covers the inner surface of the through hole 30X and a metal layer 42 formed in the through hole 30X inside the seed layer 41. The seed layer 41 is formed to continuously cover the inner surface of the through-hole 30X and the upper surface of the insulating layer 30. The seed layer 41 is formed to continuously cover the entire upper end surface of the wiring layer 22 exposed at the bottom of the through-hole 30X, the entire inner wall surface of the through-hole 30X, and the upper surface of the insulating layer 30. For example, a sputtered film can be used as the seed layer 41. As a seed layer 41 formed by the sputtering method, for example, a two-layer metal film can be used, in which a Ti layer made of titanium (Ti) and a Cu layer made of copper (Cu) are sequentially laminated on the inner surface of the through-hole 30X. In this case, the thickness of the Ti layer can be, for example, about 20 nm to 50 nm, and the thickness of the Cu layer can be, for example, about 100 nm to 300 nm. The Ti layer functions as a metal barrier film that suppresses the diffusion of copper from the Cu layer or metal layer 42 (for example, the Cu layer) to the insulating layer 30. In addition to Ti, other materials that can be used for the metal film that functions as a metal barrier film include titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), and chromium (Cr).

[0029] The metal layer 42 is formed to fill the through-holes 30X located inside the seed layer 41. The metal layer 42 is formed to cover the entire surface of the seed layer 41. For example, an electroplated layer can be used as the metal layer 42. For example, copper or a copper alloy can be used as the material for the metal layer 42.

[0030] The wiring layer 31 has a seed layer 41 formed on the upper surface of the insulating layer 30 and a metal layer 43 formed on the upper surface of the seed layer 41. The seed layer 41 is formed to cover the upper surface of the insulating layer 30 located around the through hole 30X. The metal layer 43 is formed on the seed layer 41 and the metal layer 42 formed on the upper surface of the insulating layer 30. The metal layer 43 is formed continuously and integrally with the metal layer 42. As the material of the metal layer 43, for example, copper or a copper alloy can be used. As the metal layer 43, for example, an electroplated layer can be used.

[0031] (Configuration of the insulating layer 32) The insulating layer 32 is laminated on the upper surface of the insulating layer 30 so as to cover the wiring layer 31. Through holes 32X are formed in the insulating layer 32 at required locations, penetrating the insulating layer 32 in the thickness direction and exposing a portion of the upper surface of the wiring layer 31. The through holes 32X are provided, for example, in positions that do not overlap with through holes 21X in a plan view. The through holes 32X are provided, for example, in positions that do not overlap with a plurality of through holes 30X in a plan view.

[0032] (Configuration of wiring layer 33) The wiring layer 33 is laminated on the upper surface of the insulating layer 32. The wiring layer 33 is electrically connected to the wiring layer 31 via via wiring 33V formed in the through-hole 32X. The wiring layer 33 is formed continuously and integrally with the via wiring 33V. The via wiring 33V is formed, for example, to fill the through-hole 32X.

[0033] As shown in Figure 1, the insulating layer 34 is laminated on the upper surface of the insulating layer 32 so as to cover the wiring layer 33. Through holes 34X are formed in the insulating layer 34 at required locations, penetrating the insulating layer 34 in the thickness direction and exposing a portion of the upper surface of the wiring layer 33.

[0034] The wiring layer 35 is laminated on the upper surface of the insulating layer 34. The wiring layer 35 is electrically connected to the wiring layer 33 via via wiring 35V formed in the through-hole 34X. The wiring layer 35 is formed continuously and integrally with the via wiring 35V. The via wiring 35V is formed, for example, to fill the through-hole 34X.

[0035] The insulating layer 36 is laminated on the upper surface of the insulating layer 34 so as to cover the wiring layer 35. The insulating layer 36 has through holes 36X formed at required locations, which penetrate the insulating layer 36 in the thickness direction and expose a portion of the upper surface of the wiring layer 35.

[0036] The wiring layer 37 is laminated on the upper surface of the insulating layer 36. The wiring layer 37 is a wiring layer formed on the uppermost layer of the wiring substrate 10. The wiring layer 37 is electrically connected to the wiring layer 35 via via wiring 37V formed in through holes 36X. The wiring layer 37 is formed continuously and integrally with the via wiring 37V. The via wiring 37V is formed, for example, to fill the through holes 36X. The wiring layer 37 has pads P1. The pads P1 function as pads for mounting electronic components, such as semiconductor chips, for electrical connection to electronic components. The planar shape of the pads P1 can be, for example, a circular shape with a diameter of about 20 μm to 30 μm. The pitch of the pads P1 can be, for example, about 40 μm to 60 μm. The thickness of the pads P1 can be, for example, about 10 μm to 15 μm.

[0037] A surface treatment layer is formed on the surface of the pad P1 (top and side surfaces, or top surface only) as needed. Examples of surface treatment layers include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by stacking Ni and Au layers in that order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by stacking Ni, Pd, and Au layers in that order). Other examples of surface treatment layers include a Ni layer / Pd layer (a metal layer formed by stacking Ni and Pd layers in that order) and a Pd layer / Au layer (a metal layer formed by stacking Pd and Au layers in that order). Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. For these Au, Ni, and Pd layers, for example, electroless plated metal layers or electroplated metal layers can be used. Furthermore, as the surface treatment layer, an OSP (Organic Solderability Preservative) film can be formed by applying an anti-oxidation treatment such as OSP treatment to the surface of the pad P1. As the OSP film, an organic coating such as an azole compound or an imidazole compound can be used. When a surface treatment layer is formed on the surface of the pad P1, that surface treatment layer functions as a pad for mounting electronic components.

[0038] (Structure of semiconductor device 1) Next, the structure of the semiconductor device 1 will be described according to Figure 4. As shown in Figure 4, the semiconductor device 1 includes a multilayer wiring board 2, one or more (two in this embodiment) semiconductor chips 91 mounted on the multilayer wiring board 2, and an underfill resin 95.

[0039] (Structure of the multilayer wiring board 2) The laminated wiring board 2 includes a wiring board 50 and a wiring board 10 mounted on the wiring board 50. The laminated wiring board 2 has, for example, an underfill resin 85 formed in the gap between the wiring board 50 and the wiring board 10.

[0040] (Structure of the wiring board 50) The wiring board 50 has a core layer 51. The core layer 51 is provided, for example, in the center of the wiring board 50 in the thickness direction. For the core layer 51, for example, a so-called glass epoxy substrate can be used, which is made by impregnating a glass cloth, which is a reinforcing member, with a non-photosensitive thermosetting resin mainly composed of epoxy resin and curing it. The reinforcing member is not limited to glass cloth, but for example, glass nonwoven fabric, aramid woven fabric, or aramid nonwoven fabric can be used. As the thermosetting insulating resin, it is not limited to epoxy resin, but for example, resin materials such as imide resin, phenolic resin, or cyanate resin can be used. The thickness of the core layer 51 can be, for example, about 60 μm to 400 μm.

[0041] The core layer 51 is provided with through holes 51X at required locations (six locations in Figure 1). The through holes 51X are formed to penetrate the core layer 51 in the thickness direction. Through electrodes 52 are formed within the through holes 51X, penetrating the core layer 51 in the thickness direction. The through electrodes 52 are formed, for example, to fill the through holes 51X. For the material of the through electrodes 52, for example, copper or a copper alloy can be used.

[0042] The lower surface of the core layer 51 has a wiring structure in which a wiring layer 60, an insulating layer 61, a wiring layer 62, an insulating layer 63, a wiring layer 64, and a solder resist layer 65 are stacked in that order. The upper surface of the core layer 51 has a wiring structure (third wiring structure) in which a wiring layer 70, an insulating layer 71, a wiring layer 72, an insulating layer 73, a wiring layer 74, and a solder resist layer 75 are stacked in that order. Here, the wiring layers 60, 62, 64, 70, 72, and 74 of the wiring board 50 have a lower wiring density, that is, a larger line-and-space (L / S), compared to the wiring layers 31, 33, 35, and 37 of the second wiring structure 12 of the wiring board 10. The line-and-space (L / S) of the wiring layers 60, 62, 64, 70, 72, and 74 can be, for example, about 20 μm / 20 μm to 30 μm / 30 μm.

[0043] For the wiring layers 60, 62, 64, 70, 72, and 74, for example, copper or copper alloys can be used. The insulating layers 61, 63, 71, and 73 are insulating layers mainly composed of a non-photosensitive resin. For example, the insulating layers 61, 63, 71, and 73 can be mainly composed of thermosetting non-photosensitive resins such as epoxy resins, imide resins, phenolic resins, and cyanate resins. The insulating layers 61, 63, 71, and 73 may contain fillers such as silica or alumina. The solder resist layers 65 and 75 are insulating layers mainly composed of a photosensitive resin. For example, the solder resist layers 65 and 75 can be made of a photosensitive insulating resin mainly composed of phenolic resins or polyimide resins. The solder resist layers 65 and 75 may contain fillers such as silica or alumina.

[0044] The wiring layer 60 is laminated on the lower surface of the core layer 51. The wiring layer 60 is electrically connected to the wiring layer 70 via through electrodes 52. The insulating layer 61 is laminated on the lower surface of the core layer 51 so as to cover the wiring layer 60. The wiring layer 62 is laminated on the lower surface of the insulating layer 61. The wiring layer 62 is formed integrally with, for example, via wiring that penetrates the insulating layer 61 in the thickness direction, and is electrically connected to the wiring layer 60 via that via wiring. The insulating layer 63 is laminated on the lower surface of the insulating layer 61 so as to cover the wiring layer 62. The wiring layer 64 is laminated on the lower surface of the insulating layer 63. The wiring layer 64 is a wiring layer formed as the bottom layer of the wiring board 50. The wiring layer 64 is formed integrally with, for example, via wiring that penetrates the insulating layer 63 in the thickness direction, and is electrically connected to the wiring layer 62 via that via wiring.

[0045] The thickness of the wiring layers 60, 62, and 64 can be, for example, about 15 μm to 35 μm. The thickness of the insulating layers 61 and 63 can be, for example, about 20 μm to 45 μm. The solder resist layer 65 is the outermost insulating layer of the outermost layer (in this case, the bottom layer) of the wiring board 50. The solder resist layer 65 is formed on the underside of the insulating layer 63 so as to cover the bottom wiring layer 64. The solder resist layer 65 has openings 65X formed therein to expose a portion of the bottom wiring layer 64 as an external connection pad 64P. External connection terminals used when mounting the stacked wiring board 2 onto a mounting board such as a motherboard are connected to the external connection pad 64P.

[0046] The wiring layer 70 is laminated on the upper surface of the core layer 51. The wiring layer 70 is electrically connected to the wiring layer 60 via through electrodes 52. The insulating layer 71 is laminated on the upper surface of the core layer 51 so as to cover the wiring layer 70. The wiring layer 72 is laminated on the upper surface of the insulating layer 71. The wiring layer 72 is formed integrally with, for example, via wiring that penetrates the insulating layer 71 in the thickness direction, and is electrically connected to the wiring layer 70 via that via wiring. The insulating layer 73 is laminated on the upper surface of the insulating layer 71 so as to cover the wiring layer 72. The wiring layer 74 is laminated on the upper surface of the insulating layer 73. The wiring layer 74 is a wiring layer formed as the uppermost layer of the wiring board 50. The wiring layer 74 functions as an external connection terminal for electrically connecting to other wiring boards, in this case the wiring board 10. The wiring layer 74 is formed integrally with, for example, via wiring that penetrates the insulating layer 73 in the thickness direction, and is electrically connected to the wiring layer 72 via that via wiring. The multiple wiring layers 74 are arranged, for example, so as to face each of the multiple wiring layers 20 of the wiring board 10.

[0047] The planar shape of the wiring layer 74 can be set to any shape and size. For example, the planar shape of the wiring layer 74 is formed to be circular. The diameter of the wiring layer 74 can be, for example, about 70 μm to 85 μm.

[0048] The solder resist layer 75 is the outermost insulating layer of the outermost layer (in this case, the top layer) of the wiring board 50. The solder resist layer 75 is formed on the upper surface of the insulating layer 73. The solder resist layer 75 is laminated on the upper surface of the insulating layer 73 so as to expose the wiring layer 74. The solder resist layer 75 has an opening 75X that penetrates the solder resist layer 75 in the thickness direction and exposes the wiring layer 74 and a part of the upper surface of the insulating layer 73. The opening 75X is formed so as to overlap, for example, the mounting area on which the wiring board 10 is mounted in a plan view. The opening 75X is formed so as to expose the upper surface of the insulating layer 73 and the wiring layer 74 in the mounting area. In other words, the solder resist layer 75 is formed so as to surround the mounting area in a plan view.

[0049] The planar shape of the wiring board 50 described above can be any shape and any size. In plan view, the wiring board 50 is larger in size than the wiring board 10. The planar shape of the wiring board 50 can be, for example, a rectangular shape of about 60mm x 60mm to 80mm x 80mm.

[0050] The wiring board 10 is mounted on the upper surface of the wiring board 50. The wiring board 10 is mounted, for example, on the wiring layer 74 of the wiring board 50. More specifically, the wiring layer 74 of the wiring board 50 and the wiring layer 20 of the wiring board 10 are joined to each other by a solder layer 81. The solder layer 81 is joined to the upper and side surfaces of the wiring layer 74 and to the lower surface of the wiring layer 20. As the material for the solder layer 81, for example, an alloy containing lead (Pb), an alloy of tin (Sn) and gold (Au), an alloy of Sn and copper (Cu), an alloy of Sn and silver (Ag), an alloy of Sn, Ag and copper (Cu), etc. can be used.

[0051] (Composition of underfill resin 85) The underfill resin 85 is provided to fill the gap between the wiring board 50 and the wiring board 10. The underfill resin 85 is provided to fill the gap between the upper surface of the insulating layer 73 exposed at the opening 75X and the lower surface of the insulating layer 21 of the wiring board 10. As the material for the underfill resin 85, an insulating resin such as epoxy resin can be used, for example.

[0052] In this way, by mounting a wiring board 10 having a wiring structure with high wiring density on a wiring board 50 having a wiring structure with low wiring density, a stacked wiring board 2 capable of mounting electronic components such as semiconductor chips at high density can be easily manufactured.

[0053] (Configuration of semiconductor chip 91) Each semiconductor chip 91 has, for example, a plurality of electrode pads 92 formed on the circuit formation surface (in this case, the bottom surface) of the semiconductor chip 91. The semiconductor chips 91 are flip-chip mounted on the wiring substrate 10. More specifically, the electrode pads 92 of the semiconductor chip 91 are electrically connected to the pads P1 of the wiring substrate 10 via bumps 93. Thus, the semiconductor chip 91 is electrically connected to the wiring layer 37 via the electrode pads 92 and the bumps 93.

[0054] As the semiconductor chip 91, for example, logic chips such as CPU (Central Processing Unit) chips and GPU (Graphics Processing Unit) chips can be used. Alternatively, as the semiconductor chip 91, memory chips such as DRAM (Dynamic Random Access Memory) chips, SRAM (Static Random Access Memory) chips, and flash memory chips can be used. When mounting multiple semiconductor chips 91 on the wiring board 10, logic chips and memory chips may be combined and mounted on the wiring board 10. The multiple semiconductor chips 91 may be the same size or of different sizes.

[0055] For example, gold bumps or solder bumps can be used as bump 93. As for the material of the solder bump, for example, alloys containing Pb, alloys of Sn and Au, alloys of Sn and Cu, alloys of Sn and Ag, alloys of Sn, Ag and Cu, etc. can be used.

[0056] The underfill resin 95 is provided to fill the gap between the wiring board 10 and the semiconductor chip 91. As the material for the underfill resin 95, an insulating resin such as epoxy resin can be used, for example.

[0057] In semiconductor device 1, semiconductor chips 91 are mounted on a wiring substrate 10 having a wiring structure with high wiring density. Therefore, multiple semiconductor chips 91 can be easily signal-connected to each other by the wiring structure with high wiring density.

[0058] (Manufacturing method for wiring board 10) Next, the manufacturing method of the wiring board 10 will be described with reference to Figures 5 to 21. For the sake of clarity, parts that will ultimately become components of the wiring board 10 will be denoted by their final component reference numerals.

[0059] First, in the process shown in Figure 5, a support 100 is prepared. The support 100 has a structure in which a metal foil 102 and a metal film 103 are sequentially laminated on the upper surface of a substrate 101, for example. The substrate 101 is a prepreg made by impregnating a reinforcing member such as glass or aramid woven or nonwoven fabric with a thermosetting resin such as epoxy resin or polyimide resin. The metal foil 102 is, for example, copper foil. The metal film 103 is, for example, a Ni plating film. Note that the material of the metal foil 102 is not limited to copper, and may be a metal other than copper. Also, the material of the metal film 103 may be a metal other than Ni, as long as it is a conductive material that can be selectively etched away from the wiring layer 20 (see Figure 1) formed in a later process.

[0060] Next, in the process shown in Figure 6, a resist layer 105 having an opening pattern 105X is formed on the upper surface of the metal film 103 of the support 100. The opening pattern 105X is formed so as to expose the upper surface of the metal film 103 in the portion corresponding to the formation area of ​​the wiring layer 20. As the material of the resist layer 105, for example, a material that is resistant to plating in the next plating process can be used. As the material of the resist layer 105, for example, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or liquid resist such as a novolac resin or acrylic resin) can be used. When using a photosensitive dry film resist, the dry film is laminated to the upper surface of the metal film 103 by thermocompression bonding, and the dry film is patterned by photolithography to form a resist layer 105 having an opening pattern 105X. Note that when using a liquid photoresist, the resist layer 105 can also be formed by a similar process.

[0061] Next, using the resist layer 105 as a plating mask, an electrolytic plating method is applied to the metal film 103, utilizing the metal film 103 as the plating power supply layer. Specifically, an electrolytic plating method, in this case an electrolytic Cu plating method, is applied to the upper surface of the metal film 103 exposed through the opening pattern 105X of the resist layer 105. Through this process, a wiring layer 20 is formed on the upper surface of the metal film 103 exposed through the opening pattern 105X.

[0062] Next, in the step shown in Figure 7, the resist layer 105 shown in Figure 6 is removed using an alkaline stripping solution (for example, an organic amine-based stripping solution, caustic soda, acetone, or ethanol).

[0063] Next, in the process shown in Figure 8, an insulating layer 21 is formed on the upper surface of the metal film 103 to cover the wiring layer 20. When a resin film is used as the insulating layer 21, for example, the resin film is laminated onto the upper surface of the metal film 103. Then, the insulating layer 21 can be formed by heat-treating the resin film at a temperature above its curing temperature (for example, around 130°C to 200°C) while pressing it down to cure it. As the resin film, for example, a thermosetting resin film mainly composed of epoxy resin can be used.

[0064] Next, through-holes 21X are formed at predetermined locations in the insulating layer 21 so that a portion of the upper surface of the wiring layer 20 is exposed. The through-holes 21X can be formed, for example, by a laser processing method using a CO2 laser or a UV-YAG laser.

[0065] Next, if the through-hole 21X is formed by laser processing, desmear treatment is performed to remove the resin smear adhering to the exposed surface of the wiring layer 20 exposed at the bottom of the through-hole 21X.

[0066] Next, in the process shown in Figure 9, a seed layer 22A is formed that covers the entire upper surface of the insulating layer 21, the entire inner wall surface of the through hole 21X, and the entire upper surface of the wiring layer 20 exposed at the bottom of the through hole 21X. The seed layer 22A can be formed, for example, using a sputtering method or an electroless plating method.

[0067] Next, in the process shown in Figure 10, an electrolytic plating method, specifically an electrolytic Cu plating method, is applied to the seed layer 22A as the plating power supply layer. This fills the through-holes 21X inside the seed layer 22A and forms a metal layer 22B that covers the entire upper surface of the seed layer 22A formed on the upper surface of the insulating layer 21.

[0068] Next, in the process shown in Figure 11, the metal layer 22B protruding from the upper surface of the insulating layer 21 is polished, and a portion of the upper surface of the insulating layer 21 is polished, for example, by the CMP (Chemical Mechanical Polishing) method. As a result, a wiring layer 22 having a seed layer 22A and a metal layer 22B is formed within the through hole 21X, and the upper end surface of the wiring layer 22 and the upper surface of the insulating layer 21 are formed to be flush. In addition, by polishing a portion of the upper surface of the insulating layer 21, the upper surface of the insulating layer 21 is smoothed. For example, while the roughness of the upper surface of the insulating layer 21 before polishing is about 300 nm to 400 nm in surface roughness Ra value, polishing can reduce the roughness of the upper surface of the insulating layer 21 to about 15 nm to 40 nm in surface roughness Ra value. As a result of the polishing in this process, the upper surface of the insulating layer 21 and the upper end surface of the wiring layer 22 become polished surfaces.

[0069] Next, in the process shown in Figure 12, an insulating layer 30 is formed on the upper surface of the insulating layer 21, covering the entire upper surface of the insulating layer 21 and the entire upper end surface of the wiring layer 22. Subsequently, through holes 30X are formed at required locations in the insulating layer 30, penetrating the insulating layer 30 in the thickness direction and exposing a portion of the upper end surface of the wiring layer 22. Multiple through holes 30X are provided for each wiring layer 22. When a resin film is used as the insulating layer 30, the resin film is laminated to the upper surface of the insulating layer 21 by heat compression, and the resin film is patterned by photolithography to form the insulating layer 30. Alternatively, a liquid or paste-like insulating resin is applied to the upper surface of the insulating layer 21 by a spin coating method, and the insulating resin is patterned by photolithography to form the insulating layer 30.

[0070] Through the above manufacturing process, the first wiring structure 11 can be formed on the support 100. The surface roughness of the upper surface of the insulating layer 30, which is made of an insulating resin mainly composed of such a photosensitive resin, can be, for example, set to a surface roughness Ra value of about 2 nm to 10 nm. For example, the surface roughness of the upper surface of the insulating layer 30 is lower than that of the upper surface (polished surface) of the insulating layer 21.

[0071] Next, in the process shown in Figure 13, a seed layer 41 is formed that covers the entire upper surface of the insulating layer 30, the entire inner wall surface of the through hole 30X, and the entire upper end surface of the wiring layer 22 exposed at the bottom of the through hole 30X. The seed layer 41 can be formed, for example, by sputtering or electroless plating.

[0072] For example, when forming the seed layer 41 by sputtering, first, titanium is deposited by sputtering on the inner surfaces of the insulating layer 30 and the through-holes 30X to cover the upper surface of the insulating layer 30 and the inner surface of the through-holes 30X, thereby forming a Ti layer. Then, copper is deposited on the Ti layer by sputtering to form a Cu layer. This allows for the formation of a two-layer seed layer 41 (Ti layer / Cu layer). Alternatively, when forming the seed layer 41 by electroless plating, for example, a seed layer 41 consisting of a Cu layer (single-layer structure) can be formed by electroless copper plating.

[0073] Next, in the process shown in Figure 14, a resist layer 106 having an opening pattern 106X at a predetermined location is formed on the seed layer 41. The opening pattern 106X is formed so as to expose the portion of the seed layer 41 corresponding to the formation area of ​​the wiring layer 31 (see Figure 1). As the material for the resist layer 106, for example, a material that is resistant to plating in the next plating process can be used. As the material for the resist layer 106, for example, the same material as the resist layer 105 shown in Figure 6 can be used. Furthermore, the resist layer 106 can be formed by the same method as the resist layer 105 shown in Figure 6.

[0074] Next, in the process shown in Figure 15, the resist layer 106 is used as a plating mask, and an electrolytic plating method, in this case an electrolytic copper plating method, is applied to the seed layer 41 exposed from the opening pattern 106X of the resist layer 106, using the seed layer 41 as the plating power supply layer. As a result, a metal layer 42 is formed that fills the through holes 30X inside the seed layer 41, and a metal layer 43 is formed on the seed layer 41 formed on the upper surface of the insulating layer 30.

[0075] Next, in the step shown in Figure 16, the resist layer 106 shown in Figure 15 is removed with an alkaline stripping solution. Next, in the process shown in Figure 17, the metal layers 42 and 43 are used as etching masks to remove the unnecessary seed layer 41 by etching. For example, if the seed layer 41 consists of a Ti layer / Cu layer, first, the unnecessary Cu layer is removed by wet etching using a sulfuric acid-hydrogen peroxide-based etching solution. Then, the unnecessary Ti layer is removed by dry etching using an etching gas such as CF4, or by wet etching using a KOH-based etching solution. Through this process, via wiring 40 consisting of the seed layer 41 and the metal layer 42 formed within the through hole 30X is formed within the through hole 30X. In addition, wiring layer 31 consisting of the seed layer 41 and the metal layer 43 formed on the upper surface of the insulating layer 30 is formed on the upper surface of the insulating layer 30. In this way, the via wiring 40 and wiring layer 31 are formed by the semi-additive method. Note that in Figures 18 to 22 thereafter, the seed layer 41 and the metal layers 42 and 43 are omitted from the illustration and are shown as via wiring 40 and wiring layer 31.

[0076] Next, in the process shown in Figure 18, the insulating layer 32 and the wiring layer 33 are laminated on the upper surface of the insulating layer 30 by performing the same process as shown in Figures 12 to 17. Next, in the process shown in Figure 19, the insulating layer 34 and the wiring layer 35 are laminated on the upper surface of the insulating layer 32 by performing the same process as shown in Figures 12 to 17.

[0077] Next, in the process shown in Figure 20, the insulating layer 36 and the wiring layer 37 are laminated on the upper surface of the insulating layer 34 by performing the same process as shown in Figures 12 to 17. Next, the support 100 is removed. In detail, first, the substrate 101 of the support 100 is removed. For example, the substrate 101 is mechanically peeled off from the metal foil 102. Subsequently, the metal foil 102 is removed. For example, the metal foil 102 is mechanically peeled off from the metal film 103. For example, the metal foil 102 is selectively etched off from the metal film 103. Next, the metal film 103 is removed. For example, the metal film 103 is selectively etched off from the wiring layer 20. As a result, as shown in Figure 21, the lower surface of the wiring layer 20 and the lower surface of the insulating layer 21 are exposed to the outside. At this time, the lower surfaces of the wiring layer 20 and the insulating layer 21, which were in contact with the upper surface of the metal film 103 (see Figure 20), are formed in a shape that follows the upper surface of the metal film 103 (in this case, the flat surface). Therefore, the lower surface of the wiring layer 20 and the lower surface of the insulating layer 21 are formed flush.

[0078] The wiring board 10 of this embodiment can be manufactured through the above manufacturing process. (Manufacturing method for multilayer wiring board 2) Next, the manufacturing method of the laminated wiring board 2 will be described according to Figure 22.

[0079] First, in the process shown in Figure 22, the wiring board 50 is manufactured. Since the wiring board 50 can be manufactured by known manufacturing methods, a detailed explanation is omitted here. Next, the wiring board 10 is mounted onto the wiring board 50. More specifically, the wiring layer 20 of the wiring board 10 is joined to the wiring layer 74 of the wiring board 50 via a solder layer 81. After that, underfill resin 85 is filled into the gap between the joined wiring board 50 and the wiring board 10, and the underfill resin 85 is cured.

[0080] The multilayer wiring board 2 of this embodiment can be manufactured through the above manufacturing process. (Effects of this embodiment) Next, the effects and advantages of this embodiment will be explained.

[0081] (1) The wiring board 10 has a first wiring structure 11 and a second wiring structure 12 formed on the upper surface of the first wiring structure 11 and having a higher wiring density than the first wiring structure 11. The first wiring structure 11 has a wiring layer 20, an insulating layer 21 covering the wiring layer 20, and a wiring layer 22 having an upper end surface exposed from the upper surface of the insulating layer 21, penetrating the insulating layer 21 in the thickness direction and electrically connected to the wiring layer 20. The second wiring structure 12 has an insulating layer 30 formed on the upper surface of the insulating layer 21, a plurality of through holes 30X penetrating the insulating layer 30 in the thickness direction and exposing a part of the upper end surface of the wiring layer 22, and a plurality of via wirings 40 each filling the plurality of through holes 30X. The second wiring structure 12 has a wiring layer 31 formed on the upper surface of the insulating layer 21 and electrically connected to the wiring layer 22 via the plurality of via wirings 40. The filler content in the insulating layer 30 is lower than the filler content in the insulating layer 21.

[0082] In this configuration, the lowest insulating layer 30 of the second wiring structure 12, which is a high-density wiring structure, is formed on the upper surface of the insulating layer 21 of the first wiring structure 11, which is a low-density wiring structure, and the lowest wiring layer 31 of the second wiring structure 12 is formed on the upper surface of the insulating layer 30. The lowest wiring layer 31 is then electrically connected to the wiring layer 22 via via wiring 40 that penetrates the lowest insulating layer 30 in the thickness direction. As a result, the wiring layer 31, which is a fine wiring, is not formed on the upper surface of the insulating layer 21, which has a high filler content, but rather on the upper surface of the insulating layer 30, which has a lower filler content than the insulating layer 21. Therefore, problems such as wiring lifting and peeling caused by filler detachment can be effectively suppressed.

[0083] In detail, when forming the wiring layer 31, in the process of removing unnecessary seed layers, a portion of the insulating layer beneath the wiring layer 31 is also removed by etching in order to completely remove the unnecessary seed layers and improve insulation reliability. Here, if the wiring layer 31 is formed on the upper surface of the insulating layer 21, a portion of the upper surface of the insulating layer 21, which has a high filler content, will be removed by etching. In this case, if the upper surface of the insulating layer 21 is etched excessively, the filler of the insulating layer 21 will fall off, and the side surface of the insulating layer 21 located beneath the wiring layer 31 will be gouged out. As a result, the insulating layer 21 located beneath the wiring layer 31 will become thinner, and a gap will be created between the wiring layer 31 and the insulating layer 21, resulting in what is known as wiring lifting.

[0084] In contrast, in the wiring board 10 of this embodiment, the lowest wiring layer 31 in the second wiring structure 12 is formed on the upper surface of an insulating layer 30 having a lower filler content than the insulating layer 21. This effectively suppresses the thinning of the insulating layer 30 located below the wiring layer 31 due to filler shedding, thus effectively suppressing wiring lifting caused by filler shedding. As a result, the wiring layer 31, which is a fine wiring, can be stably formed. Consequently, the electrical connection reliability between the wiring layer 31 in the high-density wiring structure and the wiring layer 22 in the low-density wiring structure can be improved.

[0085] (2) The wiring layer 31 is electrically connected to the wiring layer 22 via a plurality of vias 40 that have a smaller planar size than the wiring layer 22. That is, a plurality of small-diameter vias 40 are connected to a single wiring layer 22. This makes it possible to reduce the aspect ratio of the through-hole 30X compared to the case where a single via having the same planar size as the wiring layer 22 is connected to a single wiring layer 22, thereby improving the filling of the through-hole 30X by the vias 40. This makes it possible to improve the flatness of the upper surface of the wiring layer 31 connected to the plurality of vias 40.

[0086] (3) Furthermore, compared to the case where one small-diameter via wiring 40 is connected to one wiring layer 22, the conductor cross-sectional area of ​​the via wiring 40 connecting the wiring layer 22 and the wiring layer 31 can be increased. This effectively suppresses the degradation of signal quality caused by the reduction in the conductor cross-sectional area of ​​the via wiring 40.

[0087] (4) The insulating layer 30 is an insulating layer mainly composed of a photosensitive resin. With this configuration, the surface roughness of the upper surface of the insulating layer 30 can be made smaller than the surface roughness of the upper surface (polished surface) of the insulating layer 21. For this reason, the wiring layer 31, which is a fine wiring, can be suitably formed on the upper surface of the insulating layer 21.

[0088] (Example of change) The above embodiment can be implemented with the following modifications. The above embodiment and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0089] In the above embodiment, five via connections 40 are connected to one wiring layer 22, but the number of via connections 40 to one wiring layer 22 is not particularly limited. For example, two to four via connections 40 may be connected to one wiring layer 22, or six or more via connections 40 may be connected to one wiring layer 22.

[0090] In the above embodiment, the multiple via connections 40 are arranged in a + shape in a plan view, but the arrangement of the multiple via connections 40 is not limited to this. For example, as shown in Figure 23, multiple via connections 40 may be arranged in a plan view along only one direction (in this case, the left-right direction in the figure). In this modified example, three via connections 40 are arranged in a line along the left-right direction in the figure when viewed from above.

[0091] For example, as shown in Figure 24, multiple via connections 40 may be arranged in a matrix in a plan view. In this modified example, nine via connections 40 are arranged in a 3x3 matrix in a plan view.

[0092] In the above embodiment, multiple vias 40 were formed so that they had the same planar size, but the invention is not limited to this. For example, as shown in Figure 24, the multiple via wirings 40 may have multiple types of via wirings 40 with different planar sizes. The multiple via wirings 40 in this modified example have a first via wiring 40A and a second via wiring 40B which has a smaller planar size than the first via wiring 40A. The multiple via wirings 40 in this modified example have five first via wirings 40A and four second via wirings 40B. Each first via wiring 40A is formed to fill a through hole 30X. Each second via wiring 40B is formed to fill a through hole 30Y. Here, the opening diameter of the through hole 30Y is formed to be smaller than the opening diameter of the through hole 30X.

[0093] With this configuration, by providing a second via wiring 40B with a smaller planar size than the first via wiring 40A, even in spaces where the first via wiring 40A cannot be formed, the small-diameter second via wiring 40B can be suitably formed in that space. As a result, the conductor cross-sectional area of ​​the multiple via wirings 40 can be suitably increased, and thus the degradation of signal quality can be more suitably suppressed.

[0094] The structure of the wiring board 10 in the above embodiment can be modified as appropriate. The number of wiring layers and insulating layers, as well as the routing of the wiring, in the first wiring structure 11 of the above embodiment can be modified and changed in various ways.

[0095] The insulating layer 21 in the above embodiment may be changed to an insulating layer that does not have a reinforcing member 21G. In the above embodiment, the upper end surface of the wiring layer 22 is formed to be flush with the upper surface of the insulating layer 21, but the embodiment is not limited to this. For example, the upper end surface of the wiring layer 22 may be formed to be recessed toward the wiring layer 20 side (in this case, downward) compared to the upper surface of the insulating layer 21. For example, the upper end surface of the wiring layer 22 may be formed to protrude toward the second wiring structure 12 side (in this case, upward) compared to the upper surface of the insulating layer 21.

[0096] In the above embodiment, the lower surface of the wiring layer 20 was formed to be flush with the lower surface of the insulating layer 21, but this is not the case. For example, the lower surface of the wiring layer 20 may be formed to be recessed toward the wiring layer 22 side (in this case, upward) than the lower surface of the insulating layer 21. For example, the lower surface of the wiring layer 20 may be formed to protrude downward from the lower surface of the insulating layer 21.

[0097] The number of wiring layers and insulating layers, as well as the routing of the wiring, in the second wiring structure 12 of the above embodiment can be modified and changed in various ways. In the above embodiment, the via wiring 33V is provided in a position that does not overlap with the multiple via wirings 40 in a plan view, but the embodiment is not limited to this. For example, the via wiring 33V may be provided in a position that overlaps with the multiple via wirings 40 in a plan view.

[0098] In the above embodiment, the insulating layers 30, 32, 34, and 36 in the second wiring structure 12 are insulating layers mainly composed of a photosensitive resin. However, the embodiment is not limited to this, and for example, the insulating layers 30, 32, 34, and 36 may be insulating layers mainly composed of a non-photosensitive resin. In this case, the through holes 30X, 32X, 34X, and 36X are formed, for example, by a laser processing method using an excimer laser suitable for microfabrication.

[0099] The structure of the laminated wiring board 2 in the above embodiment can be modified as appropriate. In the above embodiment, one wiring board 10 is mounted on one wiring board 50, but the invention is not limited to this. For example, multiple wiring boards 10 may be mounted on one wiring board 50.

[0100] The number of wiring layers and insulating layers, as well as the routing of the wiring, in the wiring board 50 of the above embodiment can be modified and changed in various ways. In the above embodiment, the upper and lower wiring layers 70 and 60 of the core layer 51 are electrically connected to each other via through electrodes 52 that fill the through holes 51X of the core layer 51. However, the embodiment is not limited to this, and for example, the upper and lower wiring layers 70 and 60 of the core layer 51 may be electrically connected to each other via a through-hole plating layer provided on the inner wall of the through holes 51X. In this case, the holes of the through holes 51X formed inside the through-hole plating layer may be filled with resin.

[0101] In the above embodiment, solder resist layers 65 and 75 were given as an example of a protective insulating layer that forms the outermost layer of the wiring board 50, but protective insulating layers can be formed from various photosensitive insulating resins.

[0102] The solder resist layers 65 and 75 in the above embodiment may be omitted. In the semiconductor device 1 of the above embodiment, a semiconductor chip 91 is mounted on a multilayer wiring board 2. However, this is not limited to this, and for example, instead of a semiconductor chip 91, chip components such as chip capacitors, chip resistors, and chip inductors, or electronic components other than semiconductor chips such as crystal oscillators, may be mounted on the multilayer wiring board 2.

[0103] Furthermore, the mounting configurations for semiconductor chips, chip components, and electronic components such as crystal oscillators can be modified and changed in various ways. Examples of electronic component mounting configurations include flip-chip mounting, wire bonding mounting, soldering mounting, or combinations thereof.

[0104] • In the above embodiment, the method for manufacturing a single piece is used, but it may also be used for manufacturing a multi-piece set. [Explanation of Symbols]

[0105] 1 Semiconductor device 2. Stacked wiring board 10 Wiring board (First wiring board) 11 1st wiring structure 12 Second wiring structure 20 Wiring layer (1st wiring layer) 21. Insulating layer (first insulating layer) 21X through hole 22 Wiring layer (2nd wiring layer) 30. Insulating layer (second insulating layer) 30X through hole 31 Wiring layer (3rd wiring layer) 40 via wiring 40A Via 1 Wiring 40B Second via wiring 41 Seed Layer 42 Metal layer 43 Metal layer 50 Wiring board (Second wiring board) 74 Wiring layer (4th wiring layer) 91 Semiconductor chips

Claims

1. First wiring structure and The first wiring structure is formed on the upper surface of the first wiring structure and has a second wiring structure with a higher wiring density than the first wiring structure. The first wiring structure is, The first wiring layer and A first insulating layer covering the first wiring layer, A second wiring layer having an upper end surface exposed from the upper surface of the first insulating layer, and electrically connected to the first wiring layer by penetrating the first insulating layer in the thickness direction, The second wiring structure is, A second insulating layer formed on the upper surface of the first insulating layer, Multiple through holes that penetrate the second insulating layer in the thickness direction and expose a portion of the upper end surface of the second wiring layer, Multiple via wirings filled in each of the aforementioned multiple through holes, A third wiring layer is formed on the upper surface of the second insulating layer and is electrically connected to the second wiring layer via the plurality of via wirings, A wiring board in which the filler content in the second insulating layer is lower than the filler content in the first insulating layer.

2. The planar size of each of the plurality of via connections is formed to be smaller than the planar size of the second wiring layer. Each of the above multiple via connections is A seed layer covering the inner wall surface of the through hole and the upper end surface of the second wiring layer exposed at the bottom of the through hole, The wiring board according to claim 1, further comprising a metal layer that fills the through-holes located inside the seed layer.

3. The planar shape of the second wiring layer is formed in a circular shape. The planar shape of each of the aforementioned multiple via connections is formed in a circular shape. The wiring board according to claim 1, wherein the plurality of via connections are arranged in a cross shape in a plan view.

4. The wiring board according to claim 1, wherein the plurality of via connections include a first via connection and a second via connection having a smaller planar size than the first via connection.

5. The first insulating layer is an insulating layer mainly composed of a non-photosensitive resin, The wiring board according to claim 1, wherein the second insulating layer is an insulating layer mainly composed of a photosensitive resin.

6. The first wiring structure comprises only the first wiring layer, the first insulating layer, and the second wiring layer. The wiring board according to claim 1, wherein the upper end surface of the second wiring layer is formed flush with the upper surface of the first insulating layer.

7. A first wiring board which is a wiring board according to any one of claims 1 to 6, It has a second wiring board on which the first wiring board is mounted on its upper surface, The aforementioned second wiring board is A third wiring structure having a lower wiring density than the second wiring structure, A laminated wiring substrate having a fourth wiring layer formed on the uppermost layer of the third wiring structure and connected to the first wiring layer.

8. A laminated wiring board according to claim 7, A semiconductor device comprising a semiconductor chip mounted on the first wiring board.

9. A step of forming the first wiring structure, The process includes the step of forming a second wiring structure with a higher wiring density than the first wiring structure on the upper surface of the first wiring structure, The step of forming the aforementioned first wiring structure is: The process of forming the first wiring layer, A step of forming a first insulating layer that covers the first wiring layer, The process includes forming a second wiring layer having an upper end surface exposed from the upper surface of the first insulating layer, and penetrating the first insulating layer in the thickness direction to be electrically connected to the first wiring layer, The process of forming the two-wire structure is as follows: A step of forming a second insulating layer that covers the upper surface of the first insulating layer and the upper end surface of the second wiring layer, A step of forming a plurality of through holes that penetrate the second insulating layer in the thickness direction and expose a portion of the upper end surface of the second wiring layer, The process includes forming a plurality of via wirings that are each filled in the plurality of through holes, and forming a third wiring layer on the upper surface of the second insulating layer that is electrically connected to the second wiring layer via the plurality of via wirings. A method for manufacturing a wiring board, wherein the filler content in the second insulating layer is lower than the filler content in the first insulating layer.

Images