Semiconductor and display devices

Abstract

To achieve high integration of semiconductor devices using oxide semiconductors. [Solution] The semiconductor device includes a first transistor comprising a first oxide semiconductor layer on a first insulating layer, a second insulating layer on the first oxide semiconductor layer, and a first gate electrode on the second insulating layer, and a second transistor comprising a second oxide semiconductor layer covering an opening provided in the first insulating layer, a second insulating layer on the second oxide semiconductor layer, and a second gate electrode on the second insulating layer, wherein the portion of the second oxide semiconductor layer along the side wall of the opening functions as a channel.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor and a display device including the same.

Background Art

[0002] In recent years, development of semiconductor devices using oxide semiconductors instead of silicon semiconductors using amorphous silicon, low-temperature polysilicon, single-crystalline silicon, etc. has been advanced (see, for example, Patent Documents 1 to 6). For example, a transistor using an oxide semiconductor layer as a channel can be manufactured with a simple structure and a low-temperature process, similar to a transistor including an amorphous silicon layer. A transistor including an oxide semiconductor layer is known to have a higher field-effect mobility than a transistor including an amorphous silicon layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0004] With the miniaturization of semiconductor devices, there is a growing demand for higher integration of transistors, including those containing oxide semiconductor layers. This demand is particularly strong for transistors used in the pixels of display devices. Furthermore, for example, the pixels of an organic EL display device utilize multiple transistors, and the required specifications may differ for each transistor. Therefore, in semiconductor devices using oxide semiconductors, there is a need for technology to adjust device characteristics to match the required specifications.

[0005] One embodiment of the present invention aims to achieve high integration of semiconductor devices using oxide semiconductors.

[0006] Furthermore, one of the challenges of one embodiment of the present invention is to make the characteristics of the individual transistors constituting a semiconductor device using an oxide semiconductor different. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention includes a first transistor comprising a first oxide semiconductor layer on a first insulating layer, a second insulating layer on the first oxide semiconductor layer, and a first gate electrode on the second insulating layer, and a second transistor comprising a second oxide semiconductor layer covering an opening provided in the first insulating layer, a second insulating layer on the second oxide semiconductor layer, and a second gate electrode on the second insulating layer, wherein the portion of the second oxide semiconductor layer along the side wall of the opening functions as a channel.

[0008] A semiconductor device according to one embodiment of the present invention includes a first transistor comprising a first gate electrode on an insulating surface, a first insulating layer on the first gate electrode, and a first oxide semiconductor layer on the first insulating layer, and a second transistor comprising a second oxide semiconductor layer covering an opening provided in the first insulating layer, a second insulating layer on the second oxide semiconductor layer, and a second gate electrode on the second insulating layer, wherein the portion of the second oxide semiconductor layer along the side wall of the opening functions as a channel. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic plan view showing the configuration of a display device including a semiconductor device according to one embodiment of the present invention. [Figure 2] This is a schematic circuit diagram showing the equivalent circuit of a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view showing the configuration of a semiconductor device relating to one embodiment of the present invention. [Figure 4] This is a schematic plan view showing the configuration of the first transistor of a semiconductor device relating to one embodiment of the present invention. [Figure 5] This is a schematic plan view showing the configuration of the second transistor of a semiconductor device according to one embodiment of the present invention. [Figure 6] This is a flowchart illustrating a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 7] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 8] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 9] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 10] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 11] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 12] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 13] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 14] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 15]It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 16] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 17] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 18] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 19] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 20] It is a schematic cross-sectional view showing the configuration including a semiconductor device according to an embodiment of the present invention. [Figure 21] It is a flowchart for explaining a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 22] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 23] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 24] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 25] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 26] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 27] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0010] Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, and shape of the components compared to the actual embodiments. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification, claims, and drawings (hereinafter referred to as "this specification, etc."), components similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0011] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upward." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." Thus, for the sake of explanation, the terms "up" and "downward" are used, but the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in the opposite direction to that shown in the illustration. Also, the expression "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer, and other components may be arranged between the substrate and the oxide semiconductor layer. Upward or downward refers to the stacking order in a structure in which multiple layers are stacked. When referring to a pixel electrode above a semiconductor device, the semiconductor device and the pixel electrode may not overlap in a plan view. On the other hand, when referring to a pixel electrode vertically above a semiconductor device, it means that the semiconductor device and the pixel electrode overlap in a plan view. A plan view refers to viewing from a direction perpendicular to the surface of the substrate.

[0012] In this specification, multiple elements formed by processing a single film, such as etching, may be described as elements having different functions or roles. These multiple elements are composed of the same layer structure and the same material, and are described as elements composed of the same layer. That is, when it is stated in this specification that "A and B are the same layer," it means that both element A and element B are elements formed by processing a single layer.

[0013] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise explicitly stated. Furthermore, these expressions do not exclude cases where α includes other components.

[0014] In this specification, "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are included as forms of semiconductor devices. The semiconductor devices of the embodiments shown below can be used, for example, in display devices, integrated circuits (ICs) such as microprocessing units (MPUs), or memory circuits.

[0015] In this specification, "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, although an organic EL display device including an organic EL layer will be used as an example to describe the embodiments described later, the structure in this embodiment can be applied to other display devices including the electro-optical layers described above.

[0016] In this specification, the terms "membrane" and "layer" may be interchangeable as appropriate.

[0017] The source and drain of a transistor may have their functions reversed depending on the voltage supplied to them. Therefore, in this specification, the terms "source" and "drain" may be interchangeable as needed.

[0018] Furthermore, the following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0019] <First Embodiment> (Display device configuration) The following describes a display device 10 according to one embodiment of the present invention. In this embodiment, an organic EL display device is exemplified as the display device 10. The organic EL display device is a display device in which each pixel includes an organic EL element as a light-emitting element and a semiconductor device for driving the light-emitting element.

[0020] Figure 1 is a schematic plan view showing the configuration of a display device 10 including a semiconductor device according to one embodiment of the present invention. As shown in Figure 1, the display device 10 includes a display unit 12 and a peripheral unit 19 provided on a substrate 11. The display unit 12 has a plurality of pixels 13 arranged in a matrix. Each of the plurality of pixels 13 has a semiconductor device composed of a plurality of transistors, which will be described later, and a light-emitting element. A touch sensor 20 is arranged on the display unit 12.

[0021] The peripheral portion 19 is provided so as to surround the display unit 12. The peripheral portion 19 refers to the portion of the substrate 11 from the display unit 12 to the edge of the substrate 11. In other words, the peripheral portion 19 refers to the portion of the substrate 11 other than the portion on which the display unit 12 is provided (specifically, the portion outside the display unit 12). The peripheral portion 19 has gate drive circuits 14-1 and 14-2 and a terminal portion 17 including a plurality of terminals 16. The gate drive circuits 14-1 and 14-2 are provided so as to sandwich the display unit 12. A flexible printed circuit 18 equipped with a driver IC 15 is connected to the terminal portion 17. A plurality of wires (not shown) included in the flexible printed circuit 18 are connected to the driver IC 15 and the terminal portion 17. In the example shown in Figure 1, the source drive circuit is incorporated into the driver IC 15. However, the source drive circuit is not limited to this example and may be formed on the substrate 11 using transistors.

[0022] The driver IC 15 is connected to gate drive circuits 14-1 and 14-2 and to multiple video signal lines VL. Gate drive circuit 14-1 or gate drive circuit 14-2 is connected to the pixels 13 via selection control lines Sg. Of the multiple selection control lines Sg, for example, the selection control lines Sg for odd-numbered rows are connected to gate drive circuit 14-1, and the selection control lines Sg for even-numbered rows are connected to gate drive circuit 14-2. The video signal lines VL are connected to the pixels 13. The display unit 12 is supplied with a control signal SG (see Figure 2) from the driver IC 15 via the gate drive circuits 14-1 and 14-2 and the selection control lines Sg to select each pixel 13. The display unit 12 is also supplied with a video signal Vsig (see Figure 2) from the driver IC 15 via the video signal lines VL. These signals drive multiple transistors included in the pixels 13, enabling the display unit 12 to display an image corresponding to the video signal Vsig. The high-potential power line SLa and the low-potential power line SLb, connected to the pixel 13, are each connected to different terminals 16.

[0023] The substrate 11 can be a glass substrate, a quartz substrate, a ceramic substrate, a flexible plastic substrate, or a resin substrate. When a flexible plastic substrate or a resin substrate is used as the substrate 11, the substrate 11 can be bent between the display unit 12 and the terminal unit 17. This reduces the area of ​​the bezel portion of the display device 10.

[0024] (Pixel circuit configuration) Figure 2 is a schematic circuit diagram showing the circuit configuration of a pixel 13 including a semiconductor device according to one embodiment of the present invention. Each pixel 13 constituting the display device 10 is connected to a high-potential power line SLa, a low-potential power line SLb, a selection control line Sg, and a video signal line VL. The high-potential power line SLa is connected to a high-potential power supply Pvdd. The low-potential power line SLb is connected to a low-potential power supply Pvss. The selection control line Sg is connected to gate drive circuits 14-1 and 14-2. The video signal line VL is connected to a driver IC 15 that supplies the video signal Vsig.

[0025] Each pixel 13 has at least a drive transistor DRT, a selection transistor SST, and a light-emitting element OLED. A high-potential power supply Pvdd is connected to the anode of the light-emitting element OLED via the drive transistor DRT. A low-potential power supply Pvss is connected to the cathode of the light-emitting element OLED. In this embodiment, the anode of the light-emitting element OLED is connected to the pixel electrode 200 (see Figure 3), and the cathode is connected to the common electrode 230 (see Figure 3).

[0026] The drive transistor DRT is connected in series with the light-emitting element OLED between the high-potential power line SLa and the low-potential power line SLb. The drive transistor DRT functions as a current control element that controls the current flowing to the light-emitting element OLED according to the gate-source voltage. The selection transistor SST functions as a switching element that selects conduction or non-conductivity between two nodes and applies a voltage to the gate of the drive transistor DRT that corresponds to the luminescence brightness of the light-emitting element OLED. A retaining capacitor Cs is provided between the gate and source of the drive transistor DRT. The retaining capacitor Cs maintains the gate-source voltage of the drive transistor DRT.

[0027] The selection transistor SST has its gate connected to the selection control line Sg, one of its source or drain connected to the video signal line VL, and the other of its source or drain connected to the gate and retaining capacitance Cs of the drive transistor DRT. The drive transistor DRT has its drain connected to the high-potential power line SLa, and its source connected to the retaining capacitance Cs and the anode of the light-emitting element OLED. The cathode of the light-emitting element OLED is connected to the low-potential power line SLb. The drive transistor DRT outputs a drive current to the light-emitting element OLED in an amount corresponding to the video signal Vsig.

[0028] Although not shown in the diagram, pixel 13 may further include other transistors such as a correction transistor for correcting the threshold of the drive transistor DRT, and a reset transistor for resetting the voltage held in the holding capacitance Cs.

[0029] In this embodiment, oxide semiconductors are used as the semiconductors for the selection transistor SST and the drive transistor DRT. Transistors using oxide semiconductors have the advantage of low power consumption because they have a low off-leak current and can be driven at low frequencies. Therefore, by configuring pixels using oxide semiconductors, the power consumption of the display device 10 can be reduced. Furthermore, transistors using oxide semiconductors have the advantage of not exhibiting a kink effect and having good saturation characteristics compared to transistors using so-called low-temperature polysilicon.

[0030] [Pixel structure] Figure 3 is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. The semiconductor device shown in Figure 3 is a semiconductor circuit including at least transistor Tr1 and transistor Tr2. Figure 3 shows an example in which a semiconductor circuit including transistors Tr1 and Tr2 is provided in the pixel 13 shown in Figure 1, but the pixel 13 may include even more transistors.

[0031] First, the structure of transistor Tr1 will be described. Transistor Tr1 in this embodiment includes a conductive layer 110-1, an insulating layer 120, an oxide semiconductor layer 130-1, an insulating layer 140, a conductive layer 150-1, an insulating layer 160, a conductive layer 180-1, and a conductive layer 180-2, which are provided on a substrate 100 having an insulating surface.

[0032] The substrate 100 is, for example, a glass substrate on which one or more insulating layers are formed, each layer being made of a material selected from insulating oxides such as silicon oxide (SiOx) or silicon oxide nitride (SiOxNy), or insulating nitrides such as silicon nitride (SiNx) or silicon oxide nitride (SiNxOy). Here, silicon oxide nitride (SiNxOy) is a silicon oxide containing oxygen in a smaller proportion than nitrogen (x>y). Silicon oxide nitride (SiOxNy) is a silicon nitride containing nitrogen (N) in a smaller proportion than oxygen (O) (x>y).

[0033] In this embodiment, a substrate 100 having an insulating surface is constructed by laminating a silicon nitride layer and a silicon oxide layer on a glass substrate in that order from bottom to top. The silicon nitride layer serves as a protective layer to prevent the intrusion of contaminants (e.g., alkaline substances) from the glass substrate. However, this is not limited to this example, and a quartz substrate, ceramic substrate, plastic substrate, or resin substrate may be used instead of the glass substrate. Furthermore, the lamination order of the silicon oxide layer, silicon nitride layer, silicon oxide-nitride layer, or silicon nitride-oxide layer is arbitrary.

[0034] The conductive layer 110-1 is provided on the substrate 100. The conductive layer 110-1 functions as the lower gate electrode of the transistor Tr1. The materials that make up the conductive layer 110-1 can be aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a molybdenum-tungsten alloy is used as the material that makes up the conductive layer 110-1. The conductive layer 110-1 also functions as a light-shielding layer that reduces the amount of light reaching the oxide semiconductor layer 130-1 from the lower layer.

[0035] The insulating layer 120 is provided on the conductive layer 110-1. The insulating layer 120 functions as the lower gate insulating layer in transistor Tr1. As the insulating layer 120, one or more layers selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon nitride oxide layer can be used. In this embodiment, as the insulating layer 120, an insulating layer is used in which a silicon nitride layer and a silicon oxide layer are stacked in order from bottom to top. As will be described later, oxide semiconductor layers 130-1 and 130-2 are provided on the insulating layer 120, so it is preferable that the surface of the insulating layer 120 in contact with the oxide semiconductor layers 130-1 and 130-2 is a silicon oxide layer.

[0036] The thickness of the insulating layer 120 is not particularly limited. In this embodiment, the thickness of the insulating layer 120 is 100 nm or more and 1000 nm or less (preferably 200 nm or more and 900 nm or less, and more preferably 300 nm or more and 800 nm or less). In this embodiment, a silicon oxide layer with a thickness of 300 nm is used as the insulating layer 120.

[0037] The oxide semiconductor layer 130-1 is provided on top of the insulating layer 120. The oxide semiconductor layer 130-1 functions as the active layer in the transistor Tr1. As the material constituting the oxide semiconductor layer 130-1, an amorphous oxide semiconductor or an oxide semiconductor having a polycrystalline structure can be used. The thickness of the oxide semiconductor layer 130-1 can be 10 nm or more and 100 nm or less (preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 40 nm or less).

[0038] The oxide semiconductor layer 130-1 can be formed using the sputtering method. The composition of the oxide semiconductor layer 130-1 formed using the sputtering method depends on the composition of the sputtering target.

[0039] The composition of the metal elements constituting the oxide semiconductor layer 130-1 can be determined based on the composition of the metal elements constituting the sputtering target. Alternatively, the composition of the metal elements constituting the oxide semiconductor layer 130-1 can also be determined using X-ray diffraction (XRD). Specifically, the composition of the metal elements constituting the oxide semiconductor layer 130-1 can be determined based on the crystal structure and lattice constants of the oxide semiconductor layer 130-1 obtained from the XRD method. Furthermore, the composition of the metal elements constituting the oxide semiconductor layer 130-1 can also be determined using methods such as X-ray fluorescence analysis or electron probe microanalyzer (EPMA) analysis.

[0040] The insulating layer 140 is provided on top of the oxide semiconductor layer 130-1. The insulating layer 140 functions as the upper gate insulating layer in transistor Tr1. As the insulating layer 140, one or more layers selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon nitride oxide layer can be used. In this embodiment, a silicon oxide layer is used as the insulating layer 140. The insulating layer 140 functions as a gate insulating layer in both transistor Tr1 and transistor Tr2, which will be described later. Therefore, it is preferable to use a silicon oxide layer as the insulating layer 140. It is preferable that the insulating layer 140 has few defects and a composition close to the stoichiometric ratio. Specifically, it is preferable that no defects are observed when the insulating layer 140 is evaluated by the electron spin resonance (ESR) method. The thickness of the insulating layer 140 is not particularly limited. In this embodiment, the thickness of the insulating layer 140 is 50 nm or more and 300 nm or less (preferably 60 nm or more and 200 nm or less, and more preferably 70 nm or more and 150 nm or less).

[0041] The conductive layer 150-1 is provided on top of the insulating layer 140. The conductive layer 150-1 functions as the gate electrode on the upper side of the transistor Tr1. The materials that make up the conductive layer 150-1 can be aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a molybdenum-tungsten alloy is used as the material that makes up the conductive layer 110-1. The conductive layer 150-1 also functions as a light-shielding layer that reduces the amount of light reaching the oxide semiconductor layer 130-1 from the upper side.

[0042] The insulating layer 160 is provided on the conductive layer 150-1. The insulating layer 160 functions as an interlayer insulating layer in transistor Tr1. As the insulating layer 160, one or more layers selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon oxide nitride layer can be used. In this embodiment, a laminated structure including a silicon oxide layer and a silicon nitride layer is used as the insulating layer 160.

[0043] Conductive layers 180-1 and 180-2 are provided on an insulating layer 160. Conductive layer 180-1 is connected to the oxide semiconductor layer 130-1 via a contact hole CH1 provided in the insulating layer 160 and functions as the source electrode in transistor Tr1. Conductive layer 180-2 is connected to the oxide semiconductor layer 130-1 via a contact hole CH2 provided in the insulating layer 160 and functions as the drain electrode in transistor Tr1. In other words, conductive layers 180-1 and 180-2 each function as terminal electrodes in transistor Tr1. Materials that can be used to constitute conductive layers 180-1 and 180-2 include aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a laminated structure including a titanium layer and an aluminum layer is used as the material that constitutes conductive layers 180-1 and 180-2.

[0044] As described above, the transistor Tr1 of this embodiment is a dual-gate transistor that includes a lower gate electrode (conductive layer 110-1) facing the oxide semiconductor layer 130-1 via an insulating layer 120, and an upper gate electrode (conductive layer 150-1) facing the oxide semiconductor layer 130-1 via an insulating layer 140.

[0045] Figure 4 is a schematic plan view showing the configuration of transistor Tr1 of a semiconductor device according to one embodiment of the present invention. As shown in Figure 4, the oxide semiconductor layer 130-1 is divided into a source region SR, a drain region DR, and a channel region CR based on the gate electrode (conductive layer 150-1). The channel region CR is the region that overlaps with the conductive layer 150-1, while the source region SR and the drain region DR are regions that do not overlap with the conductive layer 150-1. The edge of the channel region CR is approximately the same as the edge of the conductive layer 150-1. The source region SR and the drain region DR have greater electrical conductivity than the channel region CR. The source region SR and the drain region DR have conductor properties, while the channel region has semiconductor properties. The source electrode (conductive layer 180-1) and the drain electrode (conductive layer 180-2) are in contact with the source region SR and the drain region DR, respectively.

[0046] As shown in Figure 4, in the channel region CR, the length in the first direction connecting the source electrode and the drain electrode is called the channel length (L1), and the length (width) in the direction perpendicular to the first direction is called the channel width (W1). The channel length (L1) of transistor Tr1 is a parameter relating to the distance traveled by carriers flowing through the channel region CR, and corresponds to the length between the source region SR and the drain region DR in a plan view. The channel width (W1) of transistor Tr1 is a parameter relating to the distance traveled by carriers flowing through the channel region CR, and corresponds to the length in the direction perpendicular to the extension direction of the channel length (L1) in a plan view.

[0047] Next, the structure of transistor Tr2 will be described. Transistor Tr2 includes a conductive layer 110-2, an oxide semiconductor layer 130-2, a conductive layer 135, an insulating layer 140, and a conductive layer 150-2, which are provided on a substrate 100 having an insulating surface.

[0048] The conductive layer 110-2 is provided on the substrate 100 and is the same layer as conductive layer 110-1. That is, the material constituting conductive layer 110-2 is the same as that of conductive layer 110-1. The conductive layer 110-2 functions as a terminal electrode (specifically, a source electrode or a drain electrode) in transistor Tr2.

[0049] The oxide semiconductor layer 130-2 is provided so as to cover the opening OP provided in the insulating layer 120. Specifically, the oxide semiconductor layer 130-2 includes a portion located on the upper surface of the insulating layer 120 and a portion located inside the opening OP. The oxide semiconductor layer 130-2 is the same layer as the oxide semiconductor layer 130-1. The oxide semiconductor layer 130-2 functions as the active layer in the transistor Tr2. Specifically, the portion of the oxide semiconductor layer 130-2 along the side wall of the opening OP functions as the channel of the transistor Tr2.

[0050] The conductive layer 135 is provided on top of the oxide semiconductor layer 130-2. Specifically, the conductive layer 135 is provided on the portion of the oxide semiconductor layer 130-2 located on the upper surface of the insulating layer 120. In other words, the conductive layer 135 is in contact with the upper surface of the oxide semiconductor layer 130-2. The conductive layer 135 functions as a terminal electrode (specifically, a source electrode or drain electrode) in the transistor Tr2. As the material constituting the conductive layer 135, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof can be used. In this embodiment, a laminated structure including a titanium layer and an aluminum layer is used as the material constituting the conductive layer 135. In the transistor Tr2, the conductive layer 135 is located between the oxide semiconductor layer 130-2 and the insulating layer 140.

[0051] The insulating layer 140 functions as a gate insulating layer in transistor Tr2. Specifically, the portion of the insulating layer 140 that runs along the side wall of the opening OP functions as the gate insulating layer of transistor Tr2.

[0052] Conductive layer 150-2 is the same layer as conductive layer 150-1. Conductive layer 150-2 functions as the gate electrode of transistor Tr2. Specifically, the portion of conductive layer 150-2 that runs along the side wall of the opening OP functions as the gate electrode of transistor Tr2.

[0053] Furthermore, the insulating layer 160, which functions as an interlayer insulating layer in transistor Tr1, functions as a protective layer covering the top of transistor Tr2 in transistor Tr2.

[0054] As described above, the transistor Tr2 of this embodiment has a structure in which the oxide semiconductor layer 130-2 and the conductive layer 150-2 face each other via the insulating layer 140 on the inside of the opening OP provided in the insulating layer 120 (specifically, on the side wall of the opening OP). In other words, as shown in Figure 3, the channel of transistor Tr2 extends vertically along the side wall of the opening OP (in a direction substantially perpendicular to the substrate 100), so in this embodiment, transistor Tr2 is called a vertical transistor.

[0055] In a cross-sectional view, the channel direction (the direction in which current flows) of transistor Tr2 intersects with the channel direction of transistor Tr1. In Figure 3, the channel length (L2) of transistor Tr2 is shown as the distance from the upper surface of conductive layer 110-2 to the lower surface of conductive layer 135, but in reality, the channel length (L2) corresponds to the thickness of the insulating layer 120. Therefore, the channel length (L2) of the vertical transistor is smaller than the channel length (L1) of the dual-gate transistor (transistor Tr1). Thus, since transistor Tr2 uses the oxide semiconductor layer 130-2, which is located on the side wall of the opening OP provided in the insulating layer 120, as its channel, the channel length (L2) can be precisely controlled by controlling the thickness of the insulating layer 120.

[0056] Figure 5 is a schematic plan view showing the configuration of transistor Tr2 of a semiconductor device according to one embodiment of the present invention. However, for the sake of explanation, the conductive layer 150-2 located on the conductive layer 135 is omitted from the illustration in Figure 5. As shown in Figure 5, the oxide semiconductor layer 130-2 is provided not only on the bottom surface of the aperture OP but also along the side walls (side surfaces) of the aperture OP. Therefore, the channel width (W2) of transistor Tr2 generally corresponds to the inner circumference of the aperture OP. In this way, the channel width (W2) of transistor Tr2 can be set by the size of the outer shape of the aperture OP. Therefore, transistor Tr2 can have a larger channel width (W1) than transistor Tr1 while keeping the occupied area small.

[0057] As shown in Figure 5, the example illustrates a case where the planar shape of the opening OP is circular, but the planar shape of the opening OP is not limited to this. The planar shape of the opening OP may be elliptical or polygonal. Furthermore, the oxide semiconductor layer 130-2 may be provided not on the entire sidewall of the opening OP, but on a part of the sidewall of the opening OP.

[0058] As shown in Figures 3 and 5, in a plan view, the conductive layer 110-2 is positioned to overlap with the opening OP and is in contact with the lower surface of the oxide semiconductor layer 130-2 on the inside of the opening OP. Also in a plan view, the conductive layer 135 is positioned to be in contact with the upper surface of the oxide semiconductor layer 130-2 on the outside of the opening OP. At this time, the conductive layer 110-2 and the conductive layer 135 function as the source electrode or drain electrode of the second transistor Tr2, so that the portion of the oxide semiconductor layer 130-2 along the side wall of the opening OP functions as a channel.

[0059] As described above, in the display device 10 of this embodiment, a semiconductor device (specifically, a semiconductor circuit) including a dual-gate transistor Tr1 and a vertical transistor Tr2 is arranged in each pixel 13. This semiconductor device constitutes part of the pixel circuit for driving the light-emitting element OLED. As shown in Figure 5, the vertical transistor has a channel formed in the direction of the thickness of the insulating layer 120, and the channel width is determined on the inner circumference of the aperture OP, so it has a very small footprint (i.e., occupied area). Therefore, by using a vertical transistor as the selected transistor SST as in this embodiment, the semiconductor device using an oxide semiconductor can be highly integrated, and a high-definition display unit 12 can be realized.

[0060] Returning to the explanation of Figure 3, an insulating layer 190 is provided on transistors Tr1 and Tr2 as a planarization layer made of resin material. The pixel electrode 200 is connected to the conductive layer 180-1 (i.e., the source electrode of transistor Tr1) via a contact hole CH3 provided in the insulating layer 190. In this embodiment, a laminated structure of a layer containing silver (Ag) and a layer containing a metal oxide (e.g., ITO) is used as the pixel electrode 200, but the invention is not limited to this example.

[0061] A bank 210 made of resin material is provided above the pixel electrode 200. The bank is also called a partition or rib. The bank 210 is provided so as to cover a portion of the pixel electrode 200. In other words, the bank 210 has an opening 212 at a position that overlaps with the pixel electrode 200. The portion of the pixel electrode 200 not covered by the bank 210 (exposed region) functions as the light-emitting region of the pixel 13. A light-emitting layer 220 made of organic EL (electroluminescent) material is provided so as to cover the exposed region of the pixel electrode 200.

[0062] Furthermore, a common electrode 230 is provided so as to cover the bank 210 and the light-emitting layer 220. Although not shown in Figure 3, the common electrode 230 is arranged to span multiple pixels 13. The pixel electrode 200, the light-emitting layer 220, and the common electrode 230 constitute a light-emitting OLED. The pixel electrode 200 functions as the anode of the light-emitting OLED. The common electrode 230 functions as the cathode of the light-emitting OLED.

[0063] A sealing layer 240 is provided on top of the light-emitting element OLED. The sealing layer 240 is a protective layer to prevent the intrusion of moisture and other external elements. In this embodiment, a laminated structure is used for the sealing layer 240, in which an inorganic insulating layer, an organic insulating layer, and another inorganic insulating layer are stacked in that order from the bottom. For example, a silicon nitride layer can be used as the inorganic insulating layer. For example, an organic resin layer (for example, a resin layer composed of polyimide or acrylic) can be used as the organic insulating layer.

[0064] In the pixel 13 described above, a dual-gate transistor is used as the drive transistor DRT (transistor Tr1) that adjusts the amount of current flowing to the light-emitting element OLED. Furthermore, a vertical transistor is used as the selection transistor SST (transistor Tr2) used for switching operations to apply a voltage corresponding to the video signal Vsig to the gate of the drive transistor DRT. Thus, in this embodiment, different types of transistors can be used for the drive transistor DRT and the selection transistor SST. Therefore, in the display device 10 of this embodiment, it is possible to set the transistor characteristics according to the specifications of the drive transistor DRT and the selection transistor SST, respectively.

[0065] Typically, the device characteristics of a transistor vary depending on the thickness of the gate insulating layer and the length of the channel. Therefore, by appropriately setting the thickness of the gate insulating layer and the channel length, it is possible to improve device characteristics such as increasing the on-current (the current that flows when the transistor is in the on state) and improving the subthreshold swing value (hereinafter referred to as "S value"). In particular, reducing the S value means shortening the transition period from the off state to the on state of the transistor, that is, improving the switching characteristics. The selected transistor SST described above requires a large on-current and a steep-rising switching characteristic as device characteristics. Therefore, it is desirable to use a transistor that can easily carry a large current and has excellent switching characteristics as a selected transistor SST.

[0066] On the other hand, the drive transistor DRT requires a large on-current as a device characteristic, but does not require a steep-rising switching characteristic. Since the amount of current flowing through the channel of the drive transistor DRT is controlled by the voltage applied to the gate, a change in gate voltage appears as a change in the amount of current. In this case, if the S value of the drive transistor DRT is small (i.e., the transition period from the off state to the on state in the switching characteristics is short), a problem arises in which the amount of current flowing through the channel changes drastically with even a slight change in gate voltage. In particular, in the low-gradation region where control with minute currents is necessary, a large change in the amount of current flowing through the channel makes fine gradation control difficult, and there is a risk that display unevenness will easily occur in the display unit 12.

[0067] As described above, since the device characteristics required for the drive transistor DRT and the selection transistor SST of the display device 10 are different, it is desirable to appropriately use transistors with different device characteristics. Taking this into consideration, in this embodiment, a dual-gate type transistor is used as the drive transistor DRT and a vertical type transistor is used as the selection transistor SST.

[0068] In a vertical transistor, the channel length (L2) is substantially determined by the thickness of the insulating layer 120. Therefore, the channel length (L2) of the select transistor SST (transistor Tr1) can be adjusted by controlling the thickness of the insulating layer 120. In this embodiment, the thickness of the insulating layer 120 is set to 100 nm or more and 1000 nm or less (preferably 200 nm or more and 900 nm or less, and more preferably 300 nm or more and 800 nm or less). In other words, the channel length (L2) of the select transistor SST can be set to 100 nm or more and 1000 nm or less (preferably 200 nm or more and 900 nm or less, and more preferably 300 nm or more and 800 nm or less).

[0069] On the other hand, in the drive transistor DRT (transistor Tr1), the insulating layer 120 functions as the lower gate insulating layer. In this embodiment, since the drive transistor DRT is a dual-gate type transistor, the transistor characteristics are not determined solely by the thickness of the insulating layer 120. However, by increasing the thickness of the insulating layer 120, it is possible to adjust the switching characteristics of the drive transistor DRT in a direction that slows down (i.e., increases the S value).

[0070] Furthermore, in this embodiment, the thickness of the insulating layer 140, which functions as the gate insulating layer on the upper side of the drive transistor DRT (transistor Tr1), is 50 nm to 300 nm (preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm). The insulating layer 140 functions as the gate insulating layer in the selection transistor SST (transistor Tr2).

[0071] In this embodiment, by setting the film thickness of the insulating layers 120 and 140 as described above, it is possible to arrange a transistor Tr2 with excellent switching characteristics and a transistor Tr1 with a larger S value than transistor Tr2 within the same pixel 13. In this way, the display device 10 of this embodiment can have different characteristics for each transistor constituting a semiconductor device using an oxide semiconductor by forming different types of transistors using oxide semiconductors on the same substrate.

[0072] (Method of manufacturing semiconductor devices) Figure 6 is a flowchart illustrating a method for manufacturing a pixel 13 including a semiconductor device according to one embodiment of the present invention. Figures 7 to 19 are schematic cross-sectional views showing a method for manufacturing a pixel 13 including a semiconductor device according to one embodiment of the present invention. As shown in Figure 6, the method for manufacturing a semiconductor device according to this embodiment includes steps S1010 to S1130. Steps S1010 to S1130 will be described in order below, but the order of the steps in the method for manufacturing a semiconductor device according to this embodiment may be changed. In addition, in the method for manufacturing a semiconductor device according to this embodiment, one or more steps may be omitted, or further steps may be included. For the convenience of explanation, in the following description, the region where transistor Tr1 is formed will be described as transistor formation region TFR1, and the region where transistor Tr2 is formed will be described as transistor formation region TFR2.

[0073] First, as shown in Figures 6 and 7, conductive layers 110-1 and 110-2 having a predetermined pattern shape are formed on the substrate 100 within the transistor formation region TFR1 (step S1010). The patterning of conductive layers 110-1 and 110-2 is performed using photolithography.

[0074] Next, as shown in Figures 6 and 8, an insulating layer 120 is formed to cover the conductive layers 110-1 and 110-2. The insulating layer 120 is deposited using the chemical vapor deposition (CVD) method. Subsequently, an opening OP is formed in the insulating layer 120 within the transistor formation region TFR2 so as to overlap with the conductive layer 110-2 (step S1020).

[0075] The opening OP is formed by patterning the insulating layer 120 using photolithography. As shown in Figure 8, the opening OP is formed to overlap with the conductive layer 110-2. As a result, a portion of the upper surface of the conductive layer 110-2 is exposed by the opening OP.

[0076] Next, as shown in Figures 6 and 9, oxide semiconductor layers 130-1 and 130-2 having a predetermined pattern shape are formed on the insulating layer 120 (step S1030). The oxide semiconductor layer 130-1 is formed so as to overlap with the conductive layer 110-1 within the transistor formation region TFR1. The oxide semiconductor layer 130-2 is formed so as to cover the opening OP within the transistor formation region TFR2. Specifically, the oxide semiconductor layer 130-2 is formed not only on a part of the upper surface of the insulating layer 120, but also inside the opening OP so as to be in contact with the side wall of the opening OP and the upper surface of the conductive layer 110-2.

[0077] The oxide semiconductor layers 130-1 and 130-2 are formed by patterning an oxide semiconductor film, deposited using the sputtering method, into a predetermined shape using photolithography. The oxide semiconductor film deposited using the sputtering method has an amorphous structure. When depositing an oxide semiconductor film using the sputtering method, it is preferable to deposit the oxide semiconductor film while controlling the temperature of the object to be filmed (substrate 100 and the layer formed on the substrate 100) to 100°C or less (preferably 80°C or less, more preferably 50°C or less). It is also preferable to deposit the oxide semiconductor film under conditions of low oxygen partial pressure. For example, the oxygen partial pressure is preferably 2% to 20% (preferably 3% to 15%, more preferably 3% to less than 10%).

[0078] Amorphous oxide semiconductor films can be easily patterned using photolithography. When etching oxide semiconductor films, either wet etching or dry etching may be used. When using wet etching, an acidic etching solution can be used to etch the oxide semiconductor film. For example, oxalic acid solution, PAN (a mixed acid of phosphoric acid, nitric acid, and acetic acid) solution, sulfuric acid solution, hydrogen peroxide solution, or hydrofluoric acid solution can be used as the etching solution.

[0079] Furthermore, the oxide semiconductor layers 130-1 and 130-2 having a predetermined pattern shape are subjected to heat treatment. Hereinafter, the heat treatment performed in step S1030 will be referred to as "OS annealing". In OS annealing, the oxide semiconductor layers 130-1 and 130-2 are held at a predetermined target temperature for a predetermined time. The predetermined target temperature is 300°C to 500°C (preferably 350°C to 450°C). The holding time at the target temperature is 15 minutes to 120 minutes (preferably 30 minutes to 60 minutes).

[0080] Next, as shown in Figures 6 and 10, a second conductive layer (conductive layer 135) is formed on the oxide semiconductor layer 130-2 (step S1040). The conductive layer 135 is formed by depositing a metal layer containing aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or an alloy thereof, and then patterning the metal layer into a predetermined pattern shape.

[0081] The conductive layer 135 is formed on the portion of the oxide semiconductor layer 130-2 located on the upper surface of the insulating layer 120. Specifically, in a plan view, the conductive layer 135 is formed on the oxide semiconductor layer 130-2 so as to surround the opening OP. The conductive layer 135 functions as a terminal electrode (source electrode or drain electrode) of the transistor Tr2 in conjunction with the conductive layer 110-2.

[0082] Next, as shown in Figures 6 and 11, a second insulating layer (insulating layer 140) is formed on the oxide semiconductor layers 130-1 and 130-2, and the conductive layer 135 (step S1050). In this embodiment, a silicon oxide layer with a thickness of 150 nm is used as the insulating layer 140. Furthermore, the insulating layer 140 is subjected to heat treatment. Hereinafter, the heat treatment performed in step S1050 will be referred to as "oxidation annealing". Due to the formation of the oxide semiconductor layers 130-1 and 130-2 and the insulating layer 140, many oxygen vacancies are generated inside the oxide semiconductor layers 130-1 and 130-2. When oxidation annealing is performed, oxygen is supplied from the insulating layer 140 to the oxide semiconductor layers 130-1 and 130-2, and the oxygen vacancies in the oxide semiconductor layers 130-1 and 130-2 are repaired.

[0083] In this embodiment, an example is shown in which oxide annealing is performed after the insulating layer 140 has been formed. However, a process to introduce oxygen into the insulating layer 140 may be performed before oxide annealing. For example, an aluminum oxide layer may be formed on the insulating layer 140 by sputtering, and oxide annealing may be performed with the aluminum oxide layer formed. In this case, oxygen is injected into the interior of the insulating layer 140 when the aluminum oxide layer is formed, increasing the amount of oxygen inside the insulating layer 140. As a result, a sufficient amount of oxygen can be supplied to the oxide semiconductor layers 130-1 and 130-2 by oxide annealing.

[0084] Next, as shown in Figures 6 and 12, a third conductive layer (conductive layers 150-1 and 150-2) is formed on the insulating layer 140 (step S1060). In this embodiment, a metal film made of a molybdenum-tungsten alloy is formed using a sputtering method, and the conductive layers 150-1 and 150-2 are formed by patterning the metal film into a predetermined shape. In this embodiment, the thickness of conductive layers 150-1 and 150-2 is 300 nm, but the embodiment is not limited to this example.

[0085] Next, as shown in Figures 6 and 13, impurities are implanted into the oxide semiconductor layer 130-1 via the insulating layer 140 (step S1070). The impurities can be implanted into the oxide semiconductor layer 130-1, for example, using ion implantation. Examples of impurities that can be used include argon (Ar), phosphorus (P), or boron (B). However, other elements may also be used, not limited to these examples.

[0086] In the transistor formation region TFR1, a conductive layer 150-1 is formed on top of the oxide semiconductor layer 130-1. Therefore, the conductive layer 150-1 acts as a mask, inhibiting the implantation of impurities into the oxide semiconductor layer 130-1. Consequently, in the oxide semiconductor layer 130-1, impurities are not implanted in the region overlapping with the conductive layer 150-1, and the channel region CR is formed in that region. Furthermore, in the oxide semiconductor layer 130-1, the region where impurities are implanted due to not overlapping with the conductive layer 150-1 forms a source region SR and a drain region DR. In the source region SR and drain region DR, oxygen vacancies are generated by the implantation of impurities, and hydrogen is trapped in these oxygen vacancies. As a result, the source region SR and drain region DR are conductive and have higher electrical conductivity than the channel region CR.

[0087] On the other hand, in the transistor formation region TFR2, the conductive layer 150-2 covers the entire oxide semiconductor layer 130-2, so no impurities are implanted into the oxide semiconductor layer 130-2. Therefore, the entire oxide semiconductor layer 130-2 is composed of an oxide semiconductor in the same state as the channel region CR of the oxide semiconductor layer 130-1.

[0088] Next, as shown in Figures 6 and 14, a third insulating layer (insulating layer 160) is formed to cover conductive layers 150-1 and 150-2 (step S1080). In this embodiment, the insulating layer 160, which has a laminated structure in which silicon oxide layers and silicon nitride layers are stacked in order from the bottom layer, is formed by plasma CVD. Furthermore, contact holes 162 and 164 are formed in the portions of insulating layers 140 and 160 that overlap with the source region SR and drain region DR of oxide semiconductor layer 130-1, respectively.

[0089] Next, as shown in Figures 6 and 15, a fourth conductive layer (conductive layers 180-1 and 180-2) is formed on the insulating layer 160 (step S1090). Specifically, a three-layer metal layer consisting of a titanium layer, an aluminum layer, and a titanium layer in that order is formed by sputtering, and conductive layers 180-1 and 180-2 are formed by patterning the metal layer into a predetermined shape. Conductive layers 180-1 and 180-2 are electrically connected to the oxide semiconductor layer 130-1 via contact holes 162 and 164, respectively. In other words, conductive layer 180-1 functions as a source electrode, and conductive layer 180-2 functions as a drain electrode.

[0090] Next, as shown in Figures 6 and 16, a fourth insulating layer (insulating layer 190) is formed to cover the conductive layers 180-1 and 180-2 (step S1100). The insulating layer 190 in this embodiment is formed by applying a resin material (for example, acrylic or polyimide) by a solution coating method. In this embodiment, a photosensitive acrylic material is used as the insulating layer 190. By performing exposure and photosensitization using a photosensitive resin material, an insulating layer 190 having contact holes 192 can be formed. In this embodiment, contact holes 192 are formed in the portion of the insulating layer 190 that overlaps with the conductive layer 180-1.

[0091] In this embodiment, an example is shown in which the insulating layer 190 is formed by a solution coating method, but it is not limited to this example, and it is also possible to form it by other methods such as printing. The insulating layer 190 functions as a planarization layer. Therefore, it is preferable that the thickness of the insulating layer 190 be 1 μm or more and 4 μm or less (preferably 2 μm or more and 3 μm or less).

[0092] Next, as shown in Figures 6 and 17, a pixel electrode 200 is formed on the insulating layer 190 (step S1110). Specifically, a transparent conductive film (metal oxide film) is deposited on the insulating layer 190 by sputtering, and the pixel electrode 200 is formed by patterning it into a predetermined pattern shape. In this embodiment, ITO (indium tin oxide), a metal oxide, is used as the material constituting the pixel electrode 200. The pixel electrode 200 is electrically connected to the conductive layer 180-2, which functions as a source electrode, via a contact hole 192.

[0093] Next, as shown in Figures 6 and 18, a bank 210 is formed on the pixel electrode 200 (step S1120). A resin material (for example, a photosensitive acrylic material) can be used as the material for the bank 210. Specifically, after applying the resin material by a solution coating method or the like, exposure and development are performed to form a bank 210 including an opening 212. As shown in Figure 18, the opening 212 provided in the bank 210 exposes most of the upper surface of the pixel electrode 200.

[0094] After forming the bank 210, an emissive layer 220 made of organic EL material is formed so as to overlap with the opening 212. In this embodiment, the emissive layer 220 is formed by vapor deposition using an organic EL material that emits red, green, or blue light. The emissive layer 220 is formed with different emission colors for each pixel 13. That is, a red-emitting organic EL material is used for pixels 13 that emit red light, a green-emitting organic EL material is used for pixels 13 that emit green light, and a blue-emitting organic EL material is used for pixels 13 that emit blue light. In addition to the emissive layer made of emissive material, the emissive layer 220 may also include functional layers made of functional materials, such as an electron injection layer, an electron transport layer, an electron blocking layer, a hole injection layer, a hole transport layer, or a hole blocking layer.

[0095] A common electrode 230 is formed on the light-emitting layer 220. In this embodiment, a layer containing magnesium silver is formed as the common electrode 230 by a vapor deposition method. The common electrode 230 may be provided across multiple pixels. With the formation of the common electrode 230, a light-emitting OLED composed of the pixel electrode 200, the light-emitting layer 220, and the common electrode 230 is formed.

[0096] Finally, as shown in Figures 6 and 19, a sealing layer 240 is formed to cover the light-emitting element OLED (step S1130). Although not shown in the figures, the sealing layer 240 has a laminated structure in which a silicon nitride layer, an organic resin layer (e.g., an acrylic layer), and a silicon nitride layer are stacked in that order from the bottom. However, this is not limited to this example, and a silicon oxide layer or an amorphous silicon layer may be provided between the silicon nitride layer and the organic resin layer. By providing these layers, the adhesion between the silicon nitride layer and the organic resin layer can be improved. Also, in this embodiment, since a touch sensor 20 (see Figure 1) is provided on the sealing layer 240, an overcoat layer may be provided on the sealing layer 240 for the purpose of planarization.

[0097] Through the process described above, a semiconductor device is completed in which each pixel 13 includes transistors Tr1 and Tr2. In this embodiment, transistor Tr1, which is a dual-gate type transistor, and transistor Tr2, which is a vertical type transistor, are formed on the same substrate using the same process. In other words, according to this embodiment, transistors with completely different structures can be formed using the same process, thereby improving the degree of freedom in circuit design.

[0098] (modified version) In this embodiment, an example is shown in which transistor Tr1 is used as a dual-gate transistor, but the embodiment is not limited to this example. For example, transistor Tr1 can also be used as a top-gate transistor or a bottom-gate transistor.

[0099] When transistor Tr1 is used as a top-gate transistor, in Figure 3, the conductive layer 110-1 does not function as the gate electrode, and only the conductive layer 150-1 functions as the gate electrode. Specifically, transistor Tr1 can be operated as a top-gate transistor by making the conductive layer 110-1 floating (no voltage applied to it) or by applying a predetermined fixed voltage to the conductive layer 110-1.

[0100] When transistor Tr1 is used as a bottom-gate transistor, in Figure 3, the conductive layer 150-1 does not function as the gate electrode, and only the conductive layer 110-1 functions as the gate electrode. Specifically, transistor Tr1 can be operated as a bottom-gate transistor by making the conductive layer 150-1 floating (no voltage applied to it) or by applying a predetermined fixed voltage to the conductive layer 150-1.

[0101] In this embodiment, since transistor Tr1 is used as the drive transistor DRT in the display device 10, it is preferable to make the S value of transistor Tr1 relatively larger than that of transistor Tr2. From this viewpoint, it is preferable to make transistor Tr1 function as a bottom-gate type transistor. This is because, as shown in Figure 3, the insulating layer 140 functions as the gate insulating layer of transistor Tr2, so increasing its thickness would be detrimental to increasing the on-current of transistor Tr2. On the other hand, increasing the thickness of the insulating layer 120 increases the channel length (L2) of transistor Tr2, which is advantageous in increasing the on-current of transistor Tr2.

[0102] <Second Embodiment> In the first embodiment, an example was described in which a dual-gate transistor is used as the drive transistor DRT (transistor Tr1) arranged in each pixel 13 of the display device 10. In this embodiment, an example is described in which a bottom-gate transistor is used as the drive transistor DRT. In the description of this embodiment, elements identical to those in the first embodiment may be denoted by the same reference numerals in the drawings and their descriptions may be omitted.

[0103] [Pixel structure] Figure 20 is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. The semiconductor device shown in Figure 20 is a semiconductor circuit arranged in each pixel 13-1, similar to the first embodiment, and includes at least transistor Tr1-1 and transistor Tr2. Transistor Tr1-1 is a bottom-gate type transistor.

[0104] The transistor Tr1-1 of this embodiment includes a conductive layer 110-1, an insulating layer 120, an oxide semiconductor layer 130-1, and conductive layers 135-1 and 135-2, which are provided on a substrate 100 having an insulating surface. The configuration of the conductive layer 110-1, the insulating layer 120, and the oxide semiconductor layer 130-1 is the same as in the first embodiment. The transistor Tr1-1 includes the conductive layer 135-1 as the source electrode and the conductive layer 135-2 as the drain electrode. The pixel electrode 200 is electrically connected to the conductive layer 135-1.

[0105] The conductive layers 135-1 and 135-2 are the same layer as the conductive layer 135 that constitutes the source electrode or drain electrode of the transistor Tr2. That is, the conductive layers 135-1 and 135-2 are located between the oxide semiconductor layer 130-1 and the insulating layer 140. The conductive layers 135-1 and 135-2 are formed simultaneously when the conductive layer 135 is formed and have a predetermined pattern shape.

[0106] Insulating layers 140 and 160 function as interlayer insulating layers for transistor Tr1-1. In particular, insulating layer 140 is an insulating layer that functions as a gate insulating layer for transistor Tr2 and also functions as a protective layer that protects the channel portion of transistor Tr1-1. As will be described later, insulating layer 140 also has the role of supplying oxygen to oxide semiconductor layer 130-1 during oxide annealing to repair oxygen vacancies inside oxide semiconductor layer 130-1.

[0107] (Method of manufacturing semiconductor devices) Figure 21 is a flowchart illustrating a method for manufacturing a pixel 13-1 including a semiconductor device according to one embodiment of the present invention. Figures 22 to 27 are schematic cross-sectional views showing a method for manufacturing a pixel 13-1 including a semiconductor device according to one embodiment of the present invention. Similar to the first embodiment, the order of each step in the flowchart shown in Figure 21 may be changed. In addition, in the method for manufacturing a semiconductor device of this embodiment, one or more steps may be omitted, or further steps may be included.

[0108] First, steps S1010 to S1030 are performed according to the flowchart in Figure 6 described in the first embodiment. At this point, oxide semiconductor layers 130-1 and 130-2 are formed as shown in Figure 9.

[0109] Next, as shown in Figures 21 and 22, a second conductive layer is formed on the oxide semiconductor layers 130-1 and 130-2 (step S1045). Specifically, conductive layers 135-1 and 135-2 are formed on the oxide semiconductor layer 130-1, and conductive layer 135 is formed on the oxide semiconductor layer 130-2. Thus, in this embodiment, in the formation of the second conductive layer shown in step S1045, conductive layers 135-1 and 135-2 are formed in addition to conductive layer 135. Conductive layers 135-1 and 135-2 are formed so as to overlap with the portions that function as the source region and drain region in the oxide semiconductor layer 130-1 that constitutes the active layer of transistor Tr1-1.

[0110] Next, as shown in Figures 21 and 23, a second insulating layer (insulating layer 140) is formed on the oxide semiconductor layers 130-1 and 130-2, and the conductive layers 135, 135-1, and 135-2 (step S1055). Furthermore, the insulating layer 140 is subjected to heat treatment (oxidation annealing). This step is the same as step S1050 shown in Figure 6 in the first embodiment, so a detailed explanation is omitted.

[0111] Next, as shown in Figures 21 and 24, a third conductive layer (conductive layer 150-2) is formed on the insulating layer 140 (step S1065). In this embodiment, unlike the first embodiment, the third conductive layer (conductive layer 150-2) is formed only in the transistor formation region TFR2, and the third conductive layer is not formed in the transistor formation region TFR1. This step is the same as step S1060 shown in Figure 6 in the first embodiment, so a detailed explanation is omitted.

[0112] Next, as shown in Figures 21 and 25, a third insulating layer (insulating layer 160) is formed to cover the conductive layer 150-2 (step S1085). The formation of the insulating layer 160 is the same as in step S1080 shown in Figure 6 in the first embodiment, so a detailed explanation is omitted. After the insulating layer 160 is formed, contact holes 166 are formed in the portions of the insulating layers 140 and 160 that overlap with the source region SR of the oxide semiconductor layer 130-1. The contact holes 166 are openings for electrically connecting the pixel electrode 200, which will be described later, to the conductive layer 135-1.

[0113] Next, as shown in Figures 21 and 26, a fourth insulating layer (insulating layer 190) is formed on the insulating layer 160 (step S1105). The formation of the insulating layer 190 is the same as in step S1100 shown in Figure 6 in the first embodiment, so a detailed explanation is omitted. In this embodiment, a photosensitive acrylic material is used as the constituent material of the insulating layer 190, and contact holes 194 are formed in the portion of the insulating layer 190 that overlaps with the conductive layer 135-1.

[0114] In a plan view, the contact hole 194 provided in the insulating layer 190 encompasses all or part of the contact hole 166 provided in the insulating layer 160. Specifically, the contact hole 194 is provided superimposed on the contact hole 166 such that a portion of the conductive layer 135-1 is exposed. In this embodiment, an example is shown where the diameter of the contact hole 166 is smaller than the diameter of the contact hole 194, but the invention is not limited to this, and the diameter of the contact hole 194 may be smaller than the diameter of the contact hole 166. That is, the contact hole 194 may be formed inside the contact hole 166.

[0115] Finally, steps S1110 to S1130 are executed according to the flowchart in Figure 6 described in the first embodiment. Through the process described above, a semiconductor device including transistors Tr1-1 and Tr2 in each pixel 13-1 is completed. In this embodiment, transistor Tr1-1, which is a bottom-gate type transistor, and transistor Tr2, which is a vertical type transistor, are formed on the same substrate using the same process. In other words, according to this embodiment, as in the first embodiment, transistors with completely different structures can be formed using the same process, thereby improving the degree of freedom in circuit design.

[0116] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on these embodiments, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0117] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0118] 10…Display device, 11…Substrate, 12…Display unit, 13, 13-1…Pixel, 14-1…Gate drive circuit, 14-2…Gate drive circuit, 16…Terminal, 17…Terminal unit, 18…Flexible printed circuit, 19…Peripheral unit, 20…Touch sensor, 100…Substrate, 110-1, 110-2…Conductive layer, 120…Insulating layer, 130-1, 130-2…Oxide semiconductor layer, 13 5, 135-1, 135-2…conductive layer, 140…insulating layer, 150-1, 150-2…conductive layer, 160…insulating layer, 162, 166…contact hole, 180-1, 180-2…conductive layer, 190…insulating layer, 192, 194…contact hole, 200…pixel electrode, 210…bank, 212…aperture, 220…light-emitting layer, 230…common electrode, 240…sealing layer

Claims

1. A first transistor comprising a first oxide semiconductor layer on a first insulating layer, a second insulating layer on the first oxide semiconductor layer, and a first gate electrode on the second insulating layer, A second transistor comprising a second oxide semiconductor layer covering an opening provided in the first insulating layer, a second insulating layer on the second oxide semiconductor layer, and a second gate electrode on the second insulating layer, Includes, The second transistor is a semiconductor device in which a portion of the second oxide semiconductor layer along the side wall of the opening functions as a channel.

2. The semiconductor device according to claim 1, wherein the second transistor further includes a first terminal electrode that contacts the lower surface of the second oxide semiconductor layer inside the opening, and a second terminal electrode that contacts the upper surface of the second oxide semiconductor layer outside the opening.

3. The semiconductor device according to claim 2, wherein the second terminal electrode is located between the second oxide semiconductor layer and the second insulating layer.

4. The semiconductor device according to claim 2, wherein, in a plan view, the second terminal electrode is arranged to surround the opening.

5. The first transistor further includes a third gate electrode beneath the first insulating layer, The semiconductor device according to claim 2, wherein the third gate electrode and the first terminal electrode are in the same layer.

6. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are the same layer.

7. The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are in the same layer.

8. A first transistor comprising a first gate electrode on an insulating surface, a first insulating layer on the first gate electrode, and a first oxide semiconductor layer on the first insulating layer, A second transistor comprising a second oxide semiconductor layer covering an opening provided in the first insulating layer, a second insulating layer on the second oxide semiconductor layer, and a second gate electrode on the second insulating layer, Includes, The second transistor is a semiconductor device in which a portion of the second oxide semiconductor layer along the side wall of the opening functions as a channel.

9. The semiconductor device according to claim 8, wherein the second transistor further includes a first terminal electrode that contacts the lower surface of the second oxide semiconductor layer inside the opening, and a second terminal electrode that contacts the upper surface of the second oxide semiconductor layer outside the opening.

10. The semiconductor device according to claim 9, wherein the second terminal electrode is located between the second oxide semiconductor layer and the second insulating layer.

11. The semiconductor device according to claim 9, wherein, in a plan view, the second terminal electrode is arranged to surround the opening.

12. The first transistor further includes a third terminal electrode and a fourth terminal electrode on the first oxide semiconductor layer, The semiconductor device according to claim 9, wherein the third terminal electrode, the fourth terminal electrode, and the second terminal electrode are in the same layer.

13. The semiconductor device according to claim 12, wherein the third terminal electrode and the fourth terminal electrode are located between the first oxide semiconductor layer and the second insulating layer.

14. The semiconductor device according to claim 8, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are the same layer.

15. The semiconductor device according to claim 9, wherein the first gate electrode and the first terminal electrode are in the same layer.

16. A display device comprising a semiconductor device according to any one of claims 1 to 15.

17. A display device comprising an organic EL element in each pixel connected to a semiconductor device according to any one of claims 1 to 15, The organic EL element is electrically connected to the source or drain of the first transistor. A display device in which the source or drain of the second transistor is electrically connected to the gate of the first transistor.

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