Semiconductor package including interposer having a glass core layer

Abstract

The present invention provides a semiconductor package that includes spacers placed on a semiconductor chip. [Solution] The semiconductor package 1000 includes a package substrate 400, an interposer structure 300 disposed on the package substrate, and semiconductor chips 100, 200 disposed on the interposer structure and electrically connected to the package substrate via the interposer structure. The interposer structure includes a glass core layer 301, a first through-electrode 310a penetrating the glass core layer, a bridge structure EBC disposed on the first through-electrode, a bridge connecting bump 325 disposed between the bridge structure and the first through-electrode, and a bridge mold layer disposed between the bridge structure and the glass core layer and covering the sides of the bridge connecting bump. Each of the bridge structures includes a base substrate and a bridge through-electrode penetrating the base substrate and overlapping perpendicularly with the bridge connecting bump.

Description

Technical Field

[0001] The present invention relates to a semiconductor package including an interposer having a glass core layer.

Background Art

[0002] Semiconductor devices mounted on electronic devices are required to be miniaturized, have higher performance, and have a larger capacity. In order to achieve this, the development of semiconductor packages that interconnect semiconductor chips arranged side by side in the horizontal direction has been carried out.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor package with improved reliability.

[0004] However, the object of the present invention is not limited to the above object, and can be variously extended within the scope not departing from the idea and scope of the present invention.

Means for Solving the Problems

[0005] A semiconductor package according to one aspect of the present invention, made to achieve the above objective, includes a package substrate including a first core layer and a first through-core electrode penetrating the first core layer; an interposer structure disposed on the package substrate; a semiconductor chip disposed on the interposer structure and electrically connected to the package substrate via the interposer structure; a first connecting bump disposed between the semiconductor chip and the interposer structure and electrically connecting the semiconductor chip and the interposer structure; and a structure disposed between the interposer structure and the package substrate that electrically connects the interposer structure and the package substrate. The interposer structure includes a second connecting bump connected to the package substrate and a third connecting bump disposed below the package substrate, wherein the interposer structure includes a second core layer, a second through-core electrode penetrating the second core layer, a third through-core electrode penetrating the second core layer and separated from the second through-core electrode, at least one bridge structure disposed on the second through-core electrode, a rewiring structure disposed on the third through-core electrode, and a bridge connecting bump disposed between the at least one bridge structure and the second through-core electrode, wherein the at least one bridge structure includes a base substrate and a bridge through-core electrode penetrating the base substrate.

[0006] To achieve the above objective, another aspect of the present invention provides a semiconductor package comprising: a package substrate; an interposer structure disposed on the package substrate; and a semiconductor chip disposed on the interposer structure and electrically connected to the package substrate via the interposer structure, wherein the interposer structure comprises: a glass core layer; a first through-electrode penetrating the glass core layer; a bridge structure disposed on the first through-electrode; a bridge connecting bump disposed between the bridge structure and the first through-electrode; and a bridge mold layer disposed between the bridge structure and the glass core layer and covering the side surface of the bridge connecting bump, wherein each of the bridge structures includes a base substrate and a bridge through-electrode penetrating the base substrate and overlapping perpendicularly with the bridge connecting bump.

[0007] A semiconductor package according to yet another aspect of the present invention made to achieve the above objectives includes a package substrate, an interposer structure disposed on the package substrate, and a semiconductor chip disposed on the interposer structure and electrically connected to the package substrate via the interposer structure, wherein the interposer structure includes a glass core layer, a first through-electrode penetrating the glass core layer, a second through-electrode penetrating the glass core layer and separated from the first through-electrode, a bridge structure disposed on the first through-electrode, a redistribution structure disposed on the second through-electrode, and the bridge structure The bridge structure includes a bridge connecting bump disposed between the fabricated structure and the first through electrode, and a bridge mold layer disposed between the bridge structure and the glass core layer and covering the side surface of the bridge connecting bump, wherein each of the bridge structures includes a base substrate, a bridge through electrode that penetrates the base substrate and overlaps perpendicularly with the bridge connecting bump, a bridge upper pad disposed on the bridge through electrode, and a bridge lower pad disposed below the bridge through electrode, wherein the bridge connecting bump is disposed on the lower surface of the lower pad and the upper surface of the first through electrode, respectively. [Effects of the Invention]

[0008] The semiconductor package according to the present invention includes a package substrate, an interposer structure disposed on the package substrate and including a glass core layer, and a semiconductor chip on the interposer structure. By including a relatively low-cost glass core layer, costs can be reduced. Furthermore, the interposer structure includes a silicon substrate and a bridge structure including through-silicon electrodes penetrating the silicon substrate. The bridge structure is connected to glass through-vias of the glass core layer via bridge connecting bumps on the glass core layer, thereby improving the performance of the semiconductor package and providing a semiconductor package with enhanced reliability.

[0009] However, the effects of the present invention are not limited to those described above, and can be extended in various ways without departing from the concept and technical domain of the present invention. [Brief explanation of the drawing]

[0010] [Figure 1] This is a plan view of a semiconductor package according to an embodiment of the present invention. [Figure 2a] Figure 1 is a cross-sectional view showing one embodiment along the I-I' line of the semiconductor package shown. [Figure 2b] Figure 1 is a cross-sectional view showing another embodiment along the I-I' line of the semiconductor package shown. [Figure 3] Figure 2a is a partially enlarged view of one embodiment of the semiconductor package shown. [Figure 4a] Figure 3 is a partially enlarged view of an embodiment of the semiconductor package shown. [Figure 4b] Figure 3 is a partially enlarged view of an embodiment of the semiconductor package shown. [Figure 5a] Figure 1 is a cross-sectional view showing another embodiment along the I-I' line of the semiconductor package shown. [Figure 5b] Figure 1 is a cross-sectional view showing another embodiment along the I-I' line of the semiconductor package shown. [Figure 6]Partial enlarged view according to an embodiment of a semiconductor package shown in FIG. 5a. [Figure 7] Cross-sectional view showing another embodiment along the line I-I' of the semiconductor package shown in FIG. 1. [Figure 8] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 9] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12a] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12b] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 13] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 14] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 15] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 16] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 17] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 18] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 19] Cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 20] Cross-sectional view showing a method of manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 21]A cross-sectional view showing a method of manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 22] A cross-sectional view showing a method of manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 23] A cross-sectional view showing a method of manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 24] A cross-sectional view showing a method of manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 25] A cross-sectional view showing a method of manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 26] A cross-sectional view showing a method of manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 27] A cross-sectional view showing a method of manufacturing a semiconductor package according to another embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

[0012] FIG. 1 is a plan view of a semiconductor package according to an embodiment of the present invention, FIG. 2a is a cross-sectional view showing one embodiment along the line I-I' of the semiconductor package shown in FIG. 1, FIG. 2b is a cross-sectional view showing another embodiment along the line I-I' of the semiconductor package shown in FIG. 1, FIG. 3 is a partial enlarged view of an embodiment of the semiconductor package shown in FIG. 2a, and FIG. 3 is an enlarged view of the "A" region of the semiconductor package shown in FIG. 2a.

[0013] Referring to FIGS. 1, 2a, and 3, the semiconductor package 1000 includes a package substrate 400, an interposer structure 300 on the package substrate 400, and semiconductor chips 100 and 200 on the interposer structure 300.

[0014] The package substrate 400 includes a first core layer 401, a first through-core electrode 410 penetrating the first core layer 401, a first lower insulating layer 403 positioned below the first core layer 401, a first upper insulating layer 405 positioned on the first core layer 401, a first lower connecting pad 420 positioned on the lower surface of the first lower insulating layer 403, and a lower connecting bump 415 positioned on the lower surface of the first lower insulating layer 403.

[0015] The first core layer 401 comprises a resin or glass fiber. The resin is one of phenolic resin, epoxy resin, or polyimide. In some embodiments, the first core layer 401 comprises at least one substance selected from FR4 (Flame Retardant 4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (Bismaleimide triazine), Thermount, cyanateester, polyimide, prepreg, Ajinomoto Build-up Film (ABF) from Ajinomoto, and liquid crystal polymer. However, it may also include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0016] The first through-core electrode 410 penetrates the first core layer 401 vertically (in the Z direction). The first through-core electrode 410 extends vertically (in the Z direction) from the top surface to the bottom surface of the first core layer 401. The top surface of the first through-core electrode 410 is coplane with the top surface of the first core layer 401, and the bottom surface of the first through-core electrode 410 is coplane with the bottom surface of the first core layer 401.

[0017] The first through-core electrode 410 includes a conductive material, such as at least one of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C), and graphene.

[0018] In one example, the height (corresponding to thickness) of the first core layer 401 in the vertical direction (Z direction) is greater than the height (thickness) of the first lower insulating layer 403 and the height (thickness) of the first upper insulating layer 405.

[0019] The first lower insulating layer 403 is located on the lower surface of the first core layer 401. Within the first lower insulating layer 403 are the first lower wiring 412, the first lower vias 413, and the first intermediate connecting pad 414. In one example, the first lower vias 413 are located between the first lower wiring 412, between the first lower wiring 412 and the first intermediate connecting pad 414, and between the first lower wiring 412 and the first lower connecting pad 420. The first lower wiring 412 and the first lower vias 413 electrically connect the first intermediate connecting pad 414 and the first lower connecting pad 420. That is, the first lower wiring 412 and the first lower vias 413 provide an electrical path for signal and power transmission. In this specification, the first lower wiring 412 and the first lower vias 413 are referred to as the first lower wiring structure.

[0020] The first intermediate connecting pad 414 is positioned on the upper surface of the first lower insulating layer 403 and is in contact with the lower surface of the first core through electrode 410. The first lower connecting pad 420 is positioned on the lower surface of the first lower insulating layer 403.

[0021] The first lower wiring 412, the first lower via 413, the first intermediate connecting pad 414, and the first lower connecting pad 420 contain a metallic material. The metallic material includes at least one metal or an alloy containing two or more metals from among copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C).

[0022] The lower connecting bumps 415 are positioned on the lower surface of the first lower insulating layer 403 and are electrically connected to the first lower connecting pad 420. In one example, the number of lower connecting bumps 415 may be less than the number of intermediate connecting bumps 315, which will be described later.

[0023] The first upper insulating layer 405 is located on the upper surface of the first core layer 401. The first upper wiring 422, the first upper via 423, the first upper connecting pad 424, and the second lower connecting pad 425 are located within the first upper insulating layer 405. In one example, the first upper via 423 is located between the first upper wiring 422, between the first upper wiring 422 and the first upper connecting pad 424, and between the first upper wiring 422 and the second lower connecting pad 425. The first upper wiring 422 and the first upper via 423 electrically connect the first upper connecting pad 424 and the second lower connecting pad 425. In this specification, the first upper wiring 422 and the first upper via 423 are referred to as the first upper wiring structure.

[0024] The first upper connecting pad 424 is located on the lower surface of the first upper insulating layer 405 and is in contact with the upper surface of the first core through electrode 410. The second lower connecting pad 425 is located on the upper surface of the first upper insulating layer 405, and intermediate connecting bumps 315 are located on the upper surface of the second lower connecting pad 425. In one example, the first upper wiring 422, the first upper via 423, the first upper connecting pad 424, and the second lower connecting pad 425 include a metallic material.

[0025] The first lower insulating layer 403 and the first upper insulating layer 405 contain an insulating material, such as silicon oxide or silicon nitride.

[0026] The interposer structure 300 includes a second core layer 301, second and third core-penetrating electrodes 310a and 310b penetrating the second core layer 301, a second lower insulating layer 303 positioned below the second core layer 301, a second upper insulating layer 305 positioned on the second core layer 301, a third lower insulating layer 321 positioned below the second lower insulating layer 303, a third upper insulating layer 331 positioned on the second upper insulating layer 305, and a fourth lower insulating layer 311 positioned below the third lower insulating layer 321.

[0027] The second core layer 301 includes one of the materials exemplified for the first core layer 401, excluding semiconductor materials. For example, the second core layer 301 includes a glass substrate mainly composed of SiO2. In one example, the height of the second core layer 301 in the vertical direction (Z direction) is smaller than the height of the first core layer 401 in the vertical direction (Z direction).

[0028] The second and third through-core electrodes 310a and 310b penetrate the second core layer 301 vertically (in the Z direction). The second and third through-core electrodes 310a and 310b extend vertically (in the Z direction), the upper surfaces of the second and third through-core electrodes 310a and 310b are coplane with the upper surface of the second core layer 301, and the lower surfaces of the second and third through-core electrodes 310a and 310b are coplane with the lower surface of the second core layer 301. The second and third through-core electrodes 310a and 310b are separated from each other horizontally. The second and third through-core electrodes 310a and 310b are through-glass vias (TGVs).

[0029] The second and third through-core electrodes 310a and 310b include metals, metal oxides, conductive metal nitrides, and the like. For example, the second and third through-core electrodes 310a and 310b include copper (Cu), tungsten (W), aluminum (Al), nickel (Ni), cobalt (Co), titanium (Ti), titanium nitride (TiN), and the like. In one example, the second and third through-core electrodes 310a and 310b include copper (Cu). The second and third through-core electrodes 310a and 310b are formed, for example, by electroplating. However, they are not limited to this, and the second and third through-core electrodes 310a and 310b may also be formed by processes such as vapor deposition or sputtering.

[0030] In this specification, the second core layer 301 is referred to as the "glass core layer," the second core through electrode 310a is referred to as the "first through electrode," and the third core through electrode 310b is referred to as the "second through electrode."

[0031] A second lower insulating layer 303 is positioned on the lower surface of the second core layer 301, and the second lower via 313 is positioned within the second lower insulating layer 303 and electrically connected to the second and third core through electrodes 310a and 310b. The second lower via 313 penetrates the second lower insulating layer 303 vertically (in the Z direction) and contacts the lower surfaces of the second and third core through electrodes 310a and 310b. Each of the second lower vias 313 narrows in width towards the top.

[0032] The second lower insulating layer 303 includes at least one of ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), PID (photo-imageable dielectric), and photosensitive polyimide (PSPI).

[0033] The third lower insulating layer 321 is positioned on the lower surface of the second lower insulating layer 303. The third lower via 323 and the third lower wiring layer 322 are positioned within the third lower insulating layer 321. The third lower wiring layer 322 is positioned on the upper surface of the third lower insulating layer 321. The second lower via 313 within the second lower insulating layer 303 is positioned between the third lower wiring layer 322 and the second and third through-core electrodes 310a and 310b, electrically connecting the third lower wiring layer 322 and the second and third through-core electrodes 310a and 310b.

[0034] The third lower via 323 of the third lower insulating layer 321 is positioned between the third lower wiring layer 322 and the fourth lower wiring layer 309, connecting the third lower wiring layer 322 and the fourth lower wiring layer 309. The third lower via 323 is coplane with the lower surface of the third lower insulating layer 321. The width of the third lower via 323 narrows towards the top.

[0035] The fourth lower insulating layer 311 is positioned on the lower surface of the third lower insulating layer 321. The fourth lower via 308 and the fourth lower wiring layer 309 are positioned within the fourth lower insulating layer 311. The fourth lower wiring layer 309 is positioned on the upper surface of the fourth lower insulating layer 311 and is connected to the third lower via 323. The fourth lower via 308 is positioned on the lower surface of the fourth lower wiring layer 309 and is connected to the fourth lower wiring layer 309. The fourth lower via 308 is positioned between the third lower connecting pad 324, which is positioned on the lower surface of the fourth lower insulating layer 311, and the fourth lower wiring layer 309, electrically connecting the third lower connecting pad 324 and the fourth lower wiring layer 309. The width of the fourth lower via 308 narrows towards the top.

[0036] In this specification, the second lower via 313, the third lower wiring layer 322, the third lower via 323, the fourth lower wiring layer 309, and the fourth lower via 308 are referred to as the second lower wiring structure.

[0037] A third lower connecting pad 324 is positioned on the lower surface of the fourth lower insulating layer 311. A fourth lower via 308 within the fourth lower insulating layer 311 is in contact with the third lower connecting pad 324. An intermediate connecting bump 315 is positioned on the lower surface of the third lower connecting pad 324. The fourth lower insulating layer 311 may also be a solder resist layer. The fourth lower insulating layer 311 is a protective layer for protecting the fourth lower wiring layer 309 and the fourth lower via 308. The fourth lower insulating layer 311 contains a photoresist material.

[0038] In one example, the number of intermediate connecting bumps 315 is less than the number of first and second upper connecting bumps 115 and 215. The size of each intermediate connecting bump 315 is smaller than the size of each of the first and second upper connecting bumps 115 and 215.

[0039] The interposer structure 300 and the package substrate 400 are electrically connected via an intermediate connecting bump 315. The intermediate connecting bump 315 is positioned between a second lower connecting pad 425 located on the upper surface of the package substrate 400 and a third lower connecting pad 324 located on the lower surface of the interposer structure 300.

[0040] The semiconductor package 1000 further includes a first underfill material layer 350 that fills the space between the interposer structure 300 and the package substrate 400, and surrounds the sides of the intermediate connecting bump 315 and the sides of the third lower connecting pad 324.

[0041] A second upper insulating layer 305 is disposed on the upper surface of the second core layer 301. The second upper insulating layer 305 contains the same insulating material as the second lower insulating layer 303. For example, it contains at least one of ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), PID (photo-imageable dielectric), and photosensitive polyimide (PSPI). However, it is not limited to these, and the second upper insulating layer 305 may contain insulating materials different from those of the second lower insulating layer 303.

[0042] The bridge structure EBC, the rewiring via 316, and the bridge via 306 placed on the bridge structure EBC are arranged within the second upper insulating layer 305. The bridge structure EBC is placed on the second core through electrode 310a. The rewiring via 316 is placed on the third core through electrode 310b.

[0043] Each of the bridge structures EBCs overlaps the second through-core electrode 310a perpendicularly (in the Z direction). The bridge structure EBC includes a first bridge structure EBC1 and a second bridge structure EBC2 that is separated from the first bridge structure EBC1 in a first direction (in the X direction). In one example, the first bridge structure EBC1 overlaps the first semiconductor chip 100 perpendicularly (in the Z direction). The second bridge structure EBC2 overlaps the second semiconductor chip 200 perpendicularly (in the Z direction). The bridge structure EBC shown in Figure 2a is shown to include two bridge structures, but is not limited thereto. For example, the bridge structure EBC of the semiconductor package 1000 may include three or more bridge structures.

[0044] Each of the first bridge structure EBC1 and the second bridge structure EBC2 includes a base substrate 302, a bridge through electrode 320 penetrating the base substrate 302, an upper bridge pad 326 positioned on the upper surface of the base substrate 302 and overlapping the bridge through electrode 320 in the vertical direction (Z direction), and a lower bridge pad 336 positioned on the lower surface of the base substrate 302 and overlapping the bridge through electrode 320 in the vertical direction (Z direction).

[0045] The base substrate 302 contains semiconductor elements such as silicon and germanium, or compound semiconductors such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide).

[0046] The through-bridge electrodes 320 penetrate the base substrate 302 vertically (Z direction), and the through-bridge electrodes 320 are through-silicon vias (TSVs). The through-bridge electrodes 320 are spaced horizontally apart from each other. Each of the through-bridge electrodes 320 includes a conductive plug and a barrier film surrounding the sides of the conductive plug. The conductive plug includes a metallic material, such as tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu). The barrier film includes an insulating barrier film and / or a conductive barrier film. The insulating barrier film consists of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. The conductive barrier film includes a metallic compound such as tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN).

[0047] The lower bridge pads 336 are positioned on the lower surface of the through-bridge electrodes 320, and the upper bridge pads 326 are positioned on the upper surface of the through-bridge electrodes 320. In one example, the width of each upper bridge pad 326 in the first direction (X direction) is greater than the width of each lower bridge pad 336 in the first direction (X direction). However, it is not limited to this, and the widths of each upper bridge pad 326 in the first direction (X direction) and the widths of each lower bridge pad 336 in the first direction (X direction) may be the same as each other, or the width of each upper bridge pad 326 in the first direction (X direction) may be smaller than the width of each lower bridge pad 336 in the first direction (X direction).

[0048] In one embodiment, the width of the lower bridge pad 336 in the first direction (X direction) is smaller than the width of the second core through electrode 310a in the first direction (X direction). However, it is not limited to this, and the width of the lower bridge pad 336 in the first direction (X direction) may be substantially the same as the width of the second core through electrode 310a in the first direction (X direction).

[0049] The lower bridge pad 336 and the upper bridge pad 326 contain a metallic material. The metallic material includes at least one metal or an alloy containing two or more metals from among copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C).

[0050] Each of the bridge vias 306 is positioned on the bridge upper pad 326. In one example, the upper surface of the bridge via 306 is coplane with the upper surface of the second upper insulating layer 305 and the upper surface of the rewiring via 316.

[0051] A bridge connecting bump 325 is positioned on the lower surface of the bridge lower pad 336. The bridge structure EBC is electrically connected to the second core through electrode 310a via the bridge connecting bump 325. In one example, the bridge connecting bump 325 is positioned between the bridge lower pad 336 and the second core through electrode 310a of the bridge structure EBC. The bridge connecting bump 325 is in contact with each of the upper surfaces of the second core through electrode 310a.

[0052] A bridge mold layer 334 is positioned within the second upper insulating layer 305. In one example, the bridge mold layer 334 fills the space between the bridge structure EBC and the second core layer 301, and surrounds the sides of the bridge connecting bump 325 and the sides of the bridge lower pad 336. The bridge mold layer 334 has, but is not limited to, a MUF (molded underfill) structure. In other embodiments, the bridge mold layer 334 has a CUF (capillary underfill) structure.

[0053] The bridge mold layer 334 completely overlaps each of the bridge structure EBCs in the perpendicular direction (Z direction), but is not limited thereto. In other embodiments, the bridge mold layer 334 covers at least a portion of each side of the bridge structure EBCs. In one example, the bridge mold layer 334 comprises a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a prepreg containing inorganic fillers and / or glass fibers, ABF, FR-4, BT, EMC (epoxy molding compound).

[0054] The second upper insulating layer 305 covers the sides of the bridge mold layer 334 and the sides and top of the base substrate 302 of the bridge structure EBC.

[0055] Each of the redistribution vias 316 penetrates the second upper insulating layer 305 vertically (in the Z direction) and contacts the upper surface of the third core through electrode 310b. Each of the redistribution vias 316 narrows in width towards the bottom. The redistribution vias 316 contain a metallic material. In this specification, the second upper insulating layer 305 is referred to as the "insulating structure," and the redistribution vias 316 are referred to as the "redistribution structure."

[0056] The third upper insulating layer 331 is placed on the upper surface of the second upper insulating layer 305. The third upper via 333 and the third upper wiring layer 332 are placed within the third upper insulating layer 331. The third upper wiring layer 332 is placed on the bridge via 306 and the rewiring via 316. The third upper via 333 is placed on the third upper wiring layer 332. The width of the third upper via 333 narrows towards the bottom. The third upper insulating layer 331 is a solder resist layer. The third upper insulating layer 331 is a protective layer for protecting the second upper insulating layer 305, the bridge via 306 and the rewiring via 316 of the second upper insulating layer 305. The third upper insulating layer 331 contains a photoresist material.

[0057] The fourth lower connecting pads 120 and 220 are positioned on the third upper insulating layer 331. The fourth lower connecting pads 120 and 220 are positioned on the third upper via 333. The fourth lower connecting pads 120 and 220 include a fourth-first lower connecting pad 120 that overlaps the first semiconductor chip 100 in the vertical direction (Z direction), and a fourth-second lower connecting pad 220 that overlaps the second semiconductor chip 200 in the vertical direction (Z direction).

[0058] Semiconductor chips 100 and 200 are placed on the interposer structure 300.

[0059] The first semiconductor chip 100 includes logic chips such as a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), digital signal processor, cryptographic processor, microprocessor, microcontroller, analog-to-digital converter, and ASIC. Depending on the embodiment, the first semiconductor chip 100 is referred to as the first semiconductor chip structure.

[0060] The second semiconductor chip 200 includes, but is not limited to, a chip that performs substantially the same or similar functions as the first semiconductor chip 100. At least one of the second semiconductor chips 200 includes, for example, a high-capacity memory device such as HBM (High Bandwidth Memory). Depending on the embodiment, the second semiconductor chip 200 is referred to as the second semiconductor chip structure.

[0061] The 4-1 upper connecting pad 110 is positioned on the lower surface of the first semiconductor chip 100. The 4-2 upper connecting pad 210 is positioned on the lower surface of the second semiconductor chip 200. The 1 upper connecting bump 115 is positioned between the 4-1 lower connecting pad 120 and the 4-1 upper connecting pad 110. The 2 upper connecting bump 215 is positioned between the 4-2 lower connecting pad 220 and the 4-2 upper connecting pad 210.

[0062] The interposer structure 300 and the first semiconductor chip 100 are electrically connected via a first upper connecting bump 115. The interposer structure 300 and the second semiconductor chip 200 are electrically connected via a second upper connecting bump 215. In one example, the first semiconductor chip 100 is connected to the package substrate 400 via a first bridge structure EBC1 and redistribution vias 316 of the interposer structure 300. The second semiconductor chip 200 is connected to the package substrate 400 via a second bridge structure EBC2 and redistribution vias 316 of the interposer structure 300.

[0063] The first and second upper connecting bumps 115, 215, the intermediate connecting bump 315, and the lower connecting bump 415 include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof. In this specification, the upper connecting bumps 115, 215 are referred to as the "first connecting bump," the intermediate connecting bump 315 as the "second connecting bump," and the lower connecting bump 415 as the "third connecting bump."

[0064] The semiconductor package 1000 further includes a second underfill material layer 150 that fills the space between the interposer structure 300 and the first and second semiconductor chips 100, 200, and surrounds the sides of the first upper connecting bump 115 and the second upper connecting bump 215.

[0065] The first underfill material layer 350 and the second underfill material layer 150 are arranged and / or formed by a CUF (capillary underfill) process, but are not limited thereto. The first underfill material layer 350 and the second underfill material layer 150 contain the same material, but are not limited thereto; the first underfill material layer 350 and the second underfill material layer 150 may contain different materials.

[0066] Referring to Figure 2b, semiconductor package 1000a is an embodiment in which the fourth lower insulating layer 311, the fourth lower via 308, and the fourth lower wiring layer 309 of semiconductor package 1000 in Figure 2a have been removed, and a third lower connecting pad 324 is located below the third lower insulating layer 321. The third lower via 323 in the third lower insulating layer 321 of semiconductor package 1000a is in contact with the third lower connecting pad 324. The lower surface of the third lower insulating layer 321 is in contact with the first underfill material layer 350. In one example, the first and second upper connecting bumps 115, 215 overlap with the intermediate connecting bump 315 in the vertical direction (Z direction). In one example, the bridge structure EBC overlaps with the first and second upper connecting bumps 115, 215 and the intermediate connecting bump 315, which are connected to the bridge structure EBC, in the vertical direction (Z direction). In one example, the bridge connecting bump 325 overlaps the first and second upper connecting bumps 115, 215 and the intermediate connecting bump 315 in the vertical direction (Z direction). That is, the first and second upper connecting bumps 115, 215 and the intermediate connecting bump 315, which are connected to the bridge structure EBC, are arranged together with the bridge connecting bump 325 on a straight line extending vertically (Z direction).

[0067] In this specification, the vertical direction (Z direction) is substantially perpendicular to the top surface of the package substrate 400, the first direction (X direction) and the second direction (Y direction) are referred to as the horizontal direction, and the horizontal direction is parallel to the top surface of the package substrate 400.

[0068] The semiconductor package 1000 according to this embodiment includes a package substrate 400, an interposer structure 300 on the package substrate 400, and semiconductor chips 100 and 200 on the interposer structure 300. The interposer structure 300 includes a glass core layer 301, a bridge structure EBC including through-bridge electrodes 320 which are through-silicon vias on the glass core layer 301, and a redistribution structure 316 on the glass core layer 301. This provides a semiconductor package 1000 with improved electrical performance.

[0069] Figures 4a and 4b are enlarged partial views of an embodiment of the semiconductor package shown in Figure 3, and Figures 4a and 4b are enlarged views of region "B" of the semiconductor package shown in Figure 3.

[0070] Referring to Figure 4a, a bridge connecting bump 325 is positioned between the second through-core electrode 310a and the bridge lower pad 336. The lower surface of the bridge connecting bump 325 is in contact with the upper surface of the second through-core electrode 310a, and the upper surface of the bridge connecting bump 325 is in contact with the lower surface of the bridge lower pad 336. The second through-core electrode 310a has a diameter (or width) having a first size W1. The first size W1 is approximately 90 μm or less. The bridge connecting bump 325 includes a plurality of conductive layers 325a to 325g. In one example, the plurality of conductive layers 325a to 325g include a first conductive layer 325a, a second conductive layer 325b, a third conductive layer 325c, a fourth conductive layer 325d, a fifth conductive layer 325e, a sixth conductive layer 325f, and a seventh conductive layer 325g, which are sequentially positioned on the upper surface of the first through-core electrode 310a. The upper surface of the second through-core electrode 310a is in contact with the first conductive layer 325a, and the lower surface of the bridge lower pad 336 is in contact with the seventh conductive layer 325g. For example, the first conductive layer 325a, the third conductive layer 325c, the fifth conductive layer 325e, and the seventh conductive layer 325g contain copper (Cu), the second conductive layer 325b and the sixth conductive layer 325f contain nickel (Ni), and the fourth conductive layer 325d contains a tin-silver (SnAg) alloy. The interface between the first conductive layer 325a and the second through-core electrode 310a may not be defined.

[0071] In one example, the vertical heights (Z-direction) of the first conductive layer 325a and the seventh conductive layer 325g are greater than the vertical heights (Z-direction) of the second, third, fifth, and sixth conductive layers 325b, 325c, 325e, and 325f, respectively, and less than the vertical height (Z-direction) of the fourth conductive layer 325d.

[0072] Referring to Figure 4b, a bridge connecting bump 325' is positioned between the second through-core electrode 310a' and the bridge lower pad 336. The lower surface of the bridge connecting bump 325' is in contact with the upper surface of the second through-core electrode 310a', and the upper surface of the bridge connecting bump 325' is in contact with the lower surface of the bridge lower pad 336. The second through-core electrode 310a' has a diameter having a second size W2. The second size W2 is greater than approximately 90 μm and less than or equal to approximately 130 μm. The bridge connecting bump 325' includes the first to sixth conductive layers 325a', 325b', 325c', 325e, 325f, and 325g. In one example, the first to sixth conductive layers 325a', 325b', 325c', 325e, 325f, and 325g are sequentially positioned on the upper surface of the second through-core electrode 310a'. The first conductive layer 325a' is in contact with the upper surface of the second through-core electrode 310a', and the sixth conductive layer 325g is in contact with the upper surface of the bridge lower pad 336. For example, the first conductive layer 325a' contains nickel (Ni), the second conductive layer 325b' contains gold (Au), and the third conductive layer 325c' contains microballs and / or tin-silver (Sn-Ag) alloy. The fourth conductive layer 325e and the sixth conductive layer 325g contain copper (Cu), and the fifth conductive layer 325f contains nickel (Ni). The fourth, fifth, and sixth conductive layers 325e, 325f, and 325g of the bridge connecting bump 325' correspond to the fifth, sixth, and seventh conductive layers 325e, 325f, and 325g of the bridge connecting bump 325 in Figure 4a.

[0073] Figure 5a is a cross-sectional view showing another embodiment along the I-I' line of the semiconductor package shown in Figure 1, Figure 5b is a cross-sectional view showing another embodiment along the I-I' line of the semiconductor package shown in Figure 1, Figure 6 is a partially enlarged view of one embodiment of the semiconductor package shown in Figure 5a, and Figure 6 is an enlarged view of the "C" region of the semiconductor package shown in Figure 5a.

[0074] Referring to Figures 5a and 6, the semiconductor package 1000' includes a second-first upper insulating layer 305' positioned on the second core layer 301, and a second-second upper insulating layer 307 covering the sides and top of the second-first upper insulating layer 305'. The semiconductor package 1000' includes a first via 316a that penetrates the second-first upper insulating layer 305' and is connected to the third through-core electrode 310b, a first wiring layer 317 positioned on the second-first upper insulating layer 305' and connected to the first via 316a, and a second via 316b on the first wiring layer 317. The remaining components shown in Figures 5a and 6, excluding the second-first upper insulating layer 305', the second-second upper insulating layer 307, the first and second vias 316a and 316b, and the first wiring layer 317, are identical to or correspond to the configuration shown in Figure 2a.

[0075] The second-first upper insulating layer 305' is positioned on the second core layer 301 and covers the third core through electrode 310b. The second-second upper insulating layer 307 is positioned on the second core layer 301 and covers the sides and top of the second-first upper insulating layer 305'.

[0076] Each of the first vias 316a penetrates the second-first upper insulating layer 305' and is electrically connected to each of the third through-core electrodes 310b. Each of the first wiring layers 317 is positioned on the second-first upper insulating layer 305' and is connected to each of the first vias 316a. Each of the second vias 316b is positioned on each of the first wiring layers 317. The sides and top of the first wiring layers 317 and the sides of the second vias 316b are covered by the second-second upper insulating layer 307. In this specification, the first and second vias 316a, 316b and the first wiring layer 317 are referred to as the “rewiring structure”.

[0077] The upper surface of the second-first upper insulating layer 305' is positioned at a lower level than the upper surface of the bridge structure EBC. The second-second upper insulating layer 307 is in contact with the side surface of the bridge mold layer 334 and the side surface and upper surface of the base substrate 302 of the bridge structure EBC. The upper surface of the second-second upper insulating layer 307, the upper surface of the bridge via 306, and the upper surface of the second via 316b are coplanar.

[0078] The second-first upper insulating layer 305' contains a first insulating material, and the second-second upper insulating layer 307 contains a second insulating material different from the first insulating material. The first insulating material includes at least one of ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), PID (photo-imageable dielectric), and photosensitive polyimide (PSPI). The second insulating material includes silicon oxide or silicon nitride. However, it is not limited thereto, and in other embodiments, the second-first upper insulating layer 305' contains the same insulating material as the second-second upper insulating layer 307. For example, the second-first upper insulating layer 305' and the second-second upper insulating layer 307 both contain ABF (Ajinomoto Build-up Film).

[0079] Referring to Figure 5b, semiconductor package 1000a' is an embodiment in which the fourth lower insulating layer 311, the fourth lower via 308, and the fourth lower wiring layer 309 of semiconductor package 1000' in Figure 5a have been removed, and a third lower connecting pad 324 is positioned below the third lower insulating layer 331.

[0080] Figure 7 is a cross-sectional view showing another embodiment along the I-I' line of the semiconductor package shown in Figure 1.

[0081] Referring to Figure 7, the semiconductor package 1000'' includes a bridge structure EBC'. The remaining configuration shown in Figure 7, excluding the bridge structure EBC', is identical to or corresponds to the configuration shown in Figure 5a.

[0082] The bridge structure EBC' includes a first bridge structure EBC1, a second bridge structure EBC2, and a third bridge structure EBC3 positioned between the first bridge structure EBC1 and the second bridge structure EBC2. The third bridge structure EBC3 is positioned in the lower region between the first semiconductor chip 100 and the second semiconductor chip 200 and is electrically connected to the first semiconductor chip 100 and the second semiconductor chip 200. The third bridge structure EBC3 is positioned at the same level as the first and second bridge structures EBC1 and EBC2, and is positioned between the first bridge structure EBC1 and the second bridge structure EBC2.

[0083] The third bridge structure EBC3 is connected to the fourth-first lower connecting pad 120 via bridge via 306 and connected to the first semiconductor chip 100, and is connected to the fourth-second lower connecting pad 220 via bridge via 306 and connected to the second semiconductor chip 200.

[0084] The second-first upper insulating layer 305' is placed between the first bridge structure EBC1 and the second bridge structure EBC2, and between the second bridge structure EBC2 and the third bridge structure EBC3. Rewiring structures 316a, 316b, and 317 are placed between the first bridge structure EBC1 and the second bridge structure EBC2, and between the second bridge structure EBC2 and the third bridge structure EBC3. The second-second upper insulating layer 307 covers the sides and top of the second-first upper insulating layer 305' and is in contact with the sides and top of the bridge structure EBC'.

[0085] In another embodiment, the semiconductor package 1000'' has the fourth lower insulating layer 311, the fourth lower via 308, and the fourth lower wiring layer 309 removed, and a third lower connecting pad 324 is placed below the third lower insulating layer 331.

[0086] Figures 8 to 19 are cross-sectional views showing a method for manufacturing a semiconductor package according to one embodiment of the present invention. Figures 8 to 12b are simplified cross-sectional views showing the manufacturing process for a glass core layer on which first solder balls are formed on one surface in the semiconductor package manufacturing method, and Figures 13 to 19 are simplified cross-sectional views showing the manufacturing process for the interposer structure of the semiconductor package shown in Figure 2a, which is carried out after the manufacturing process for the glass core layer described with reference to Figures 8 to 12a.

[0087] Referring to Figure 8, the process includes preparing the glass core layer 301 and then forming first openings OPN1a and OPN1b that penetrate the glass core layer 301 to form through electrodes. In one example, the glass core layer 301 includes a first region R1 and a second region R2. The first region R1 defines the region where the bridge structure EBC in Figure 2a is located. The second region R2 defines the region where the rewiring structure in Figure 2a (e.g., the rewiring via 316 in Figure 2a) is formed. The first openings OPN1a and OPN1b include a first-first opening OPN1a formed in the first region R1 and a first-second opening OPN1b formed in the second region R2. The sizes of the first openings OPN1a and OPN1b are the same, but are not limited to this, and the sizes of the first-first opening OPN1a and the first-second opening OPN1b may be different. The first openings OPN1a and OPN1b are formed by a laser drilling process or by an etching process.

[0088] Referring to Figure 9, the process includes the step of forming a through-electrode metal layer 310P that fills the first openings OPN1a and OPN1b. A step of forming a separate seed metal may precede the step of forming the through-electrode metal layer 310P. The through-electrode metal layer 310P fills the first openings OPN1a and OPN1b and is formed on the upper and lower surfaces of the glass core layer 301. The through-electrode metal layer 310P contains copper (Cu).

[0089] Referring to Figure 10, the metal layer 310P for through electrodes on the upper and lower surfaces of the glass core layer 301 is removed by a grinding or polishing process to form the first through electrode 310a in the first region R1 and the second through electrode 310b in the second region R2.

[0090] Referring to Figure 11, the upper surface of the first through electrode 310a formed in the first region R1 is exposed on the glass core layer 301, and a first photoresist pattern PR1 covering the second region R2 is formed.

[0091] Referring to Figure 12a, if each of the first through-electrodes 310a exposed through the first photoresist pattern PR1 has a width of a first size W1, then a first solder ball 10 is formed on the upper surface of each of the first through-electrodes 310a. The first size W1 is approximately 90 μm or less. The first solder ball 10 includes first to fourth conductive layers 11 to 14. For example, the first conductive layer 11 and the third conductive layer 13 contain copper (Cu), the second conductive layer 12 contains nickel (Ni), and the fourth conductive layer 14 contains a tin-silver (SnAg) alloy. Since the first through-electrode 310a and the first conductive layer 11 contain copper (Cu), the interface between the junction surface of the first through-electrode 310a and the first conductive layer 11 may not be defined.

[0092] The height of the first conductive layer 11 in the vertical direction (Z direction) is approximately 8 μm. The height of the second conductive layer 12 in the vertical direction (Z direction) is approximately 3 μm. The height of the third conductive layer 13 in the vertical direction (Z direction) is approximately 3 μm. The height of the fourth conductive layer 14 in the vertical direction (Z direction) is approximately 21 μm. After the first solder ball 10 is formed, the first photoresist pattern PR1 is removed.

[0093] Referring to Figure 12b, if each of the first through-electrodes 310a' exposed through the first photoresist pattern PR1 has a width of a second size W2, then a first solder ball 10' is formed on the upper surface of each of the first through-electrodes 310a. The second size W2 is greater than approximately 90 μm and less than or equal to approximately 130 μm. The first solder ball 10' includes first to third conductive layers 11' to 13'. For example, the first conductive layer 11' contains nickel (Ni), the second conductive layer 12' contains gold (Au), and the third conductive layer 13' contains microballs. In one example, the height of the first conductive layer 11' in the vertical direction (Z direction) is approximately 3 μm. The height of the second conductive layer 12' in the vertical direction (Z direction) is approximately 0.3 μm. The height of the third conductive layer 12' in the vertical direction (Z direction) is approximately 20 μm.

[0094] After the process of forming the first solder balls 10 and 10' in Figures 12a and 12b, the glass core layer 301 in Figures 8 to 12b contains a large number of glass core layers, so the sawing process separates the large number of glass core layers into individual glass core layers.

[0095] Referring to Figure 13, the process includes the steps of positioning a bridge structure EBC already formed on the first through electrode 310a of the first region R1, and performing a reflow process to solder the first solder ball 10 formed on the first through electrode 310a and the second solder ball 20 formed on the lower surface of the bridge lower pad 336 of the bridge structure EBC. The bridge structure EBC includes a base substrate 302, a bridge through electrode 320 penetrating the base substrate 302, a bridge upper pad 326 positioned on the bridge through electrode 320, and a bridge lower pad 336 positioned on the lower surface of the bridge through electrode 320. In one example, the second solder ball 20 has the same structure as the first solder ball 10. In one example, the first conductive layer 11, the second conductive layer 12, the third conductive layer, and the fourth conductive layer 14 shown in Figure 12a are formed sequentially on the lower surface of each of the bridge lower pads 336.

[0096] Referring to Figure 14, the first solder ball 10 formed on the first through electrode 310a of the glass core layer 301 and the second solder ball 20 formed on the lower surface of the bridge lower pad 336 of the bridge structure EBC are joined to form a bridge connecting bump 325 that connects the glass core layer 301 and the bridge structure EBC. The process includes the step of filling the space between the glass core layer 301 and the bridge structure EBC and forming a bridge mold layer 334 that surrounds the sides of the bridge connecting bump 325.

[0097] Referring to Figure 15, a second upper insulating layer 305 is formed on the upper surface of the glass core layer 301, and a second lower insulating layer 303 is formed on the lower surface of the glass core layer 301. The second upper insulating layer 305 covers the upper surface of the second through electrode 310b in the second region R2 on the upper surface of the glass core layer 301, and covers the sides and top of the bridge structure EBC and the sides of the bridge mold layer 334. In one example, the second lower insulating layer 303 covers the lower surfaces of the first and second through electrodes 310a and 310b on the lower surface of the glass core layer 301. The second upper insulating layer 305 and the second lower insulating layer 303 include ABF (Ajinomoto Build-up Film).

[0098] Referring to Figure 16, the process includes the steps of forming second openings OPN2a and OPN2b that penetrate the second upper insulating layer 305, and forming a third opening OPN3 that penetrates the second lower insulating layer 303 and exposes the lower surfaces of the first and second through electrodes 310a and 310b. The second openings OPN2a and OPN2b include a second-first opening OPN2a that penetrates the second upper insulating layer 305 and exposes the upper surface of the bridge upper pad 326 of the bridge structure EBC, and a second-second opening OPN2b that exposes the upper surface of the second through electrode 310b. In one example, the second openings OPN2a and OPN2b become narrower towards the bottom, and the third opening OPN3 becomes narrower towards the top. The second openings OPN2a and OPN2b and the third opening OPN3 are formed by a laser drilling process or by an etching process.

[0099] Referring to Figure 17, in the first region R1, the 2-1 opening OPN2a in Figure 16 is filled with a conductive material to form a bridge via 306, and in the second region R2, the 2-2 opening OPN2b in Figure 16 is filled with a conductive material to form a rewiring via 316. The third opening OPN3 in Figure 16 is filled with the same conductive material to form a second lower via 313. The upper surface of the rewiring via 316 is coplane with the upper surface of the bridge via 306.

[0100] After forming the bridge via 306 and the rewiring via 316, a third upper wiring layer 332 is formed on the second upper insulating layer 305, connected to the bridge via 306 and the rewiring via 316. After forming the second lower via 313, a third lower wiring layer 322 is formed below the second lower insulating layer 303, overlapping with the second lower via 313.

[0101] Referring to Figure 18, a third upper insulating layer 331 is formed on the second upper insulating layer 305 to cover the third upper wiring layer 332, and a third lower insulating layer 321 is formed below the second lower insulating layer 303 to cover the third lower wiring layer 322. A fourth opening OPN4 is formed that penetrates the third upper insulating layer 331 and exposes the upper surface of the third upper wiring layer 332, and a fifth opening OPN5 is formed that penetrates the third lower insulating layer 321 and exposes the lower surface of the third lower wiring layer 322. The third lower insulating layer 321 and the third upper insulating layer 331 are solder resist layers, which are formed by applying and drying liquid photoresist (LPR), or by laminating dry film photoresist (DFR) at a constant pressure.

[0102] The fourth aperture OPN4 and the fifth aperture OPN5 are formed by a laser drilling process or by an etching process.

[0103] Referring to Figure 19, the fourth opening OPN4 in Figure 18 is filled with conductive material to form the third upper via 333, and the fifth opening OPN5 is filled with conductive material to form the third lower via 323. A fourth lower wiring layer 309 is formed below the third lower via 323. After forming the fourth lower wiring layer 309, an opening is formed so that the lower surface of the fourth lower wiring layer 309 is exposed by penetrating the fourth lower insulating layer 311, and then a conductive material is filled to form the fourth lower via 308. Subsequently, a third lower connecting pad 324 is formed on the lower surface of the fourth lower via 308, and a lower solder ball 315P is formed on the lower surface of the third lower connecting pad 324.

[0104] A fourth lower connecting pad 120 is formed on the third upper via 333, and an upper solder ball 115P is formed on the fourth lower connecting pad 120. In one example, the size of each upper solder ball 115P is smaller than the size of each lower solder ball 315P.

[0105] Next, referring to Figures 2a and 19, the lower solder ball 315P is used to bond to the package substrate 400, and the upper solder ball 115P is used to bond to the semiconductor chips 100 and 200. This completes the manufacture of the semiconductor package 1000.

[0106] Figures 20 to 27 are cross-sectional views showing a method for manufacturing a semiconductor package according to another embodiment of the present invention. Figures 20 to 27 are simplified cross-sectional views showing the manufacturing process of the interposer structure of the semiconductor package of Figure 2a, which is carried out after the manufacturing process for the glass core layer described with reference to Figures 8 to 12a.

[0107] Referring to Figure 20, a second-first upper insulating layer 305' is formed on the upper surface of the glass core layer 301, and a second lower insulating layer 303 is formed on the lower surface of the glass core layer 301. The second-first upper insulating layer 305' is in contact with the upper surface of the glass core layer 301 and covers the upper surfaces of the first and second through electrodes 310a and 310b, while the second lower insulating layer 303 is in contact with the lower surface of the glass core layer 301 and covers the lower surfaces of the first and second through electrodes 310a and 310b. The second-first upper insulating layer 305' and the second lower insulating layer 303 include ABF (Ajinomoto Build-up Film).

[0108] Referring to Figure 21, the process includes forming a sixth opening OPN6 that penetrates the second-first upper insulating layer 305' to expose the upper surface of the second through electrode 310b, and a seventh opening OPN7 that penetrates the second lower insulating layer 303 to expose the lower surfaces of the first and second through electrodes 310a and 310b.

[0109] Referring to Figure 22, in the second region R2, the sixth opening OPN6 in Figure 21 is filled with a conductive material to form the first via 316a, and the seventh opening OPN7 in Figure 21 is filled with a conductive material to form the second lower via 313. After forming the first via 316a, a first wiring layer 317 overlapping the first via 316a is formed on the second-first upper insulating layer 305', and after forming the second lower via 313, a third lower wiring layer 322 overlapping the second lower via 313 is formed on the lower surface of the second lower insulating layer 303.

[0110] Referring to Figure 23, the second-first upper insulating layer 305' covering the glass core layer 301 in the first region R1 is removed. A mask (not shown) is placed on the second-first upper insulating layer 305' located in the second region R2, and exposure light is shone on it, followed by development to remove the second-first upper insulating layer 305' located in the first region R1.

[0111] Referring to Figure 24, the process includes the steps of positioning a bridge structure EBC already formed on the first through electrode 310a of the first region R1, and performing a reflow process to solder the first solder ball 10 formed on the first through electrode 310a and the second solder ball 20 formed on the lower surface of the bridge lower pad 336 of the bridge structure EBC. The first solder ball 10 is formed by a manufacturing method for a glass core layer 301 having an upper surface on which the first solder ball 10 is formed, as already described with reference to Figures 11 to 12b.

[0112] Referring to Figure 25, a bridge connecting bump 325 is formed connecting the glass core layer 301 and the bridge structure EBC by the coupling of a first solder ball 10 formed on the first through electrode 310a of the glass core layer 301 and a second solder ball 20 formed on the lower surface of the bridge lower pad 336 of the bridge structure EBC. The process includes a step of filling the space between the glass core layer 301 and the bridge structure EBC and forming a bridge mold layer 334 that surrounds the sides of the bridge connecting bump 325. After forming the bridge mold layer 334, a second-second upper insulating layer 307 is formed that covers the bridge structure EBC and the second-first upper insulating layer 305'. The second-second upper insulating layer 307 covers the sides and top of the second-first upper insulating layer 305', the first wiring layer 317, and the bridge structure EBC.

[0113] Referring to Figure 26, in the first region R1, an 8-1 opening OPN8a is formed that penetrates the 2-2 upper insulating layer 307 and exposes at least a portion of the upper surface of the bridge upper pad 326 of the bridge structure EBC, and in the second region R2, an 8-2 opening OPN8b is formed that penetrates the 2-2 upper insulating layer 307 and exposes at least a portion of the upper surface of the first wiring layer 317.

[0114] Referring to Figure 27, in the first region R1, a bridge via 306 is formed by filling the opening OPN8a of 8-1 in Figure 26 with a conductive material, and in the second region R2, a second via 316b is formed by filling the opening OPN8b of 8-2 in Figure 26 with a conductive material. After forming the bridge via 306 and the rewiring via 316, a third upper wiring layer 332 is formed on the second upper insulating layer 305, which is connected to the bridge via 306 and the rewiring via 316. After forming the third upper wiring layer 332, a third upper insulating layer 331 is formed, an opening (not shown) is formed so that the upper surface of the third upper wiring layer 332 is exposed, a conductive material is filled into the opening to form a third upper via 333, a fourth lower connecting pad 120 is formed on the third upper via 333, and an upper solder ball 115P is formed on the fourth lower connecting pad 120.

[0115] A third lower insulating layer 321 is formed on the lower surface of the second lower insulating layer 303 to cover the third lower wiring layer 322, an opening is formed that penetrates the third lower insulating layer 321 to expose the lower surface of the third lower wiring layer 322, and a conductive material is filled into the opening to form a third lower via 323.

[0116] A fourth lower wiring layer 309 is formed below the third lower via 323. After forming the fourth lower wiring layer 309, an opening is formed so that the lower surface of the fourth lower wiring layer 309 is exposed by penetrating the fourth lower insulating layer 311, and then conductive material is filled to form the fourth lower via 308. Subsequently, a third lower connecting pad 324 is formed on the lower surface of the fourth lower via 308, and a lower solder ball 315P is formed on the lower surface of the third lower connecting pad 324.

[0117] Next, referring to Figure 5a, the lower solder ball 315P is connected to the package substrate 400, and the upper solder ball 115P is connected to the semiconductor chips 100 and 200. This is how the semiconductor package 1000' is manufactured.

[0118] Although embodiments of the present invention have been described above with reference to the present invention, those skilled in the art will understand that the present invention can be modified and altered in various ways without departing from the spirit and technical domain of the present invention. [Explanation of Symbols]

[0119] 1000 semiconductor packages EBC Bridge Structure 100 First Semiconductor Chip 200 Second Semiconductor Chip 300 Interposer Structures 301 Second Core Layer 302 Base board 303 Second lower insulating layer 305 Second upper insulating layer 310a Second core through-electrode 310b Third core through-electrode 315 Intermediate connecting bump 320 Bridge Through-Electrode 325 Bridge connecting bump 334 Bridge mold layer 350 First underfill material layer 400 Package Substrates 401 First Core Layer 403 First lower insulating layer 405 First upper insulating layer 410 First core through electrode 414 First Intermediate Connecting Pad 415 Lower connecting bump 420 First lower connecting pad 424 First upper connecting pad 425 Second lower connecting pad

Claims

1. A package substrate including a first core layer and a first through-core electrode penetrating the first core layer, An interposer structure disposed on the aforementioned package substrate, A semiconductor chip is placed on the interposer structure and electrically connected to the package substrate via the interposer structure, A first connecting bump is disposed between the semiconductor chip and the interposer structure and electrically connects the semiconductor chip and the interposer structure, A second connecting bump is positioned between the interposer structure and the package substrate, electrically connecting the interposer structure and the package substrate. It includes a third connecting bump positioned below the package substrate, The aforementioned interposer structure is The second core layer, A second core-penetrating electrode that penetrates the second core layer, A third core-penetrating electrode penetrates the second core layer and is separated from the second core-penetrating electrode, A bridge structure disposed on the second core through electrode, A rewiring structure disposed on the third core through electrode, The bridge connecting bump is positioned between the bridge structure and the second core through electrode, The semiconductor package is characterized in that the bridge structure includes a base substrate and a bridge through-electrode penetrating the base substrate.

2. The semiconductor package according to claim 1, characterized in that the bridge connecting bumps are in contact with each of the upper surfaces of the second through-core electrodes.

3. The semiconductor package according to claim 1, further comprising a bridge mold layer that fills the space between the bridge structure and the second core layer and surrounds the side surface of the bridge connecting bump.

4. The semiconductor package according to claim 3, further comprising an insulating structure surrounding the side and top surfaces of the base substrate of the bridge structure, the side surfaces of the bridge mold layer, and the side surfaces of the redistribution structure.

5. The semiconductor package according to claim 4, characterized in that the redistribution structure includes a redistribution via that penetrates the insulating structure and is connected to the third through-core electrode.

6. Package substrate and An interposer structure disposed on the aforementioned package substrate, A semiconductor chip is disposed on the interposer structure and electrically connected to the package substrate via the interposer structure, The aforementioned interposer structure is Glass core layer, A first through-electrode penetrating the glass core layer, A bridge structure disposed on the first through electrode, A bridge connecting bump is positioned between the bridge structure and the first through electrode, The bridge mold layer is disposed between the bridge structure and the glass core layer and covers the side surface of the bridge connecting bump, A semiconductor package characterized in that each of the bridge structures includes a base substrate and a bridge-through electrode that penetrates the base substrate and overlaps perpendicularly with the bridge connecting bump.

7. The aforementioned interposer structure is A second through electrode penetrates the glass core layer and is spaced horizontally apart from the first through electrode, An upper wiring structure positioned on the second through electrode, A lower wiring structure positioned below the first and second through electrodes, The semiconductor package according to claim 6, further comprising an insulating structure covering the side surface of the upper wiring structure on the glass core layer.

8. The interposer structure further includes bridge vias connected to the bridge through electrodes of the bridge structure on the bridge structure, The upper wiring structure includes a first via disposed on the second through electrode, a first wiring layer on the first via, and a second via on the first wiring layer. The semiconductor package according to claim 7, characterized in that the upper surface of the bridge via is coplane with the upper surface of the second via.

9. The insulating structure includes a first insulating layer surrounding the side surface of the first via on the second through electrode, and a second insulating layer surrounding the side surface and top surface of the first wiring layer and the side surface of the second via. The first insulating layer comprises a first insulating material. The semiconductor package according to claim 8, characterized in that the second insulating layer contains a second insulating material different from the first insulating material.

10. Package substrate and An interposer structure disposed on the aforementioned package substrate, A semiconductor chip is disposed on the interposer structure and electrically connected to the package substrate via the interposer structure, The aforementioned interposer structure is Glass core layer, A first through-electrode penetrating the glass core layer, A second through electrode penetrates the glass core layer and is separated from the first through electrode, A bridge structure disposed on the first through electrode, A rewiring structure placed on the second through electrode, A bridge connecting bump is positioned between the bridge structure and the first through electrode, The bridge mold layer is disposed between the bridge structure and the glass core layer and covers the side surface of the bridge connecting bump, Each of the aforementioned bridge structures is, Base board and A bridge-penetrating electrode that penetrates the base substrate and overlaps perpendicularly with the bridge connecting bump, A bridge upper pad positioned on the bridge through electrode, Includes a bridge lower pad positioned below the bridge through electrode, The semiconductor package is characterized in that the bridge connecting bumps are arranged on the lower surface of the lower pad and on the upper surface of the first through electrode, respectively.

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