Method for manufacturing a semiconductor device having multiple shield electrodes and structures

Abstract

The present invention provides a method and structure for manufacturing a semiconductor device equipped with multiple shielding electrodes. [Solution] A method for manufacturing a semiconductor device includes providing a region 11 of semiconductor material including a top surface 18, an edge region 101, a dual shield conductor contact area 102 within the edge region, an active area 103, and an upper shield contact area 104, and providing an active trench 22A. The active trench includes a lower shield conductor 21A, a shield dielectric 24 that isolates the lower shield conductor from the region of semiconductor material, an upper shield conductor 21B, and a shield dielectric 240 that isolates the lower shield conductor from the upper shield conductor within the active area. The lower and upper shield conductors are coupled together in the dual shield conductor contact area. The method also includes a shield contact 210A in the upper shield contact area coupled to the upper shield conductor in the active trench.

Description

[Technical Field]

[0001] (Cross-reference of related applications) Not applicable.

[0002] (Field of Invention) The present invention relates in general to electronic devices, and more specifically to semiconductor device structures and methods for forming semiconductor devices. [Background technology]

[0003] Insulated gate field-effect transistors (IGFETs), such as metal oxide semiconductor field-effect transistors (MOSFETs), have been used in many power switching applications, including DC-DC converters. In a typical MOSFET, the gate electrode provides turn-on and turn-off control with the application of an appropriate gate voltage. For example, in an N-type enhancement-mode MOSFET, turn-on occurs when a conductive N-type inversion layer (i.e., the channel region) is formed in the P-type body region in response to the application of a positive gate voltage exceeding a certain threshold voltage. The inversion layer connects the N-type source region to the N-type drain region, enabling majority carrier conduction between these regions.

[0004] There is a class of MOSFET devices in which the gate electrode is formed in a trench extending downward from the main surface of a semiconductor material such as silicon. In such trench-gate MOSFET devices, the current flow is mainly perpendicular through the device, which in turn allows for a higher density of device cells to be mounted. All other things being equal, a higher density of mounted device cells can increase the current carrying capability and reduce the on-resistance of the device.

[0005] A variation of the trench-gate MOSFET includes a shield-gate MOSFET in which a shield electrode is placed in a trench beneath the gate electrode and electrically isolated from the gate electrode. In some examples, the shield electrode can be connected to the source potential. The shield electrode, electrically isolated from the drift region by a dielectric thicker than the gate dielectric, provides a charge equilibrium effect to the drift region. This allows for higher doping within the drift region and results in reduced on-resistance. In addition, the shield electrode functions to shield the gate electrode from the drift region, which reduces the gate-drain capacitance C gd Reduces performance and improves switching performance.

[0006] In some applications, multiple shielding electrodes have been used for vertical charge control to improve forward voltage loss and blocking capability. However, manufacturing challenges have made it difficult to implement semiconductor devices such as MOSFET devices that have multiple shielding electrodes.

[0007] Therefore, a method and structure for manufacturing a semiconductor device having multiple shielding electrodes is required. In addition, a method and structure for providing electrical contact to multiple shielding electrodes separated by a dielectric is required. [Brief explanation of the drawing]

[0008] [Figure 1] This explanation illustrates a partial top view of an exemplary cell topography of a semiconductor device. [Figure 2] Figure 1 illustrates an example of cell topography, specifically a partial cross-sectional view of a semiconductor device along the reference line 2A-2A. [Figure 3] Figure 1 illustrates an example of cell topography, specifically a partial cross-sectional view of a semiconductor device along the reference line 3A-3A. [Figure 4] Figure 1 illustrates a partial cross-sectional view of a semiconductor device in an exemplary cell topography along the reference line 4A-4A. [Figure 5] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 6] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 7] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 8] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 9] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 10] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 11] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 12] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 13] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 14] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 15] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 16] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 17] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 18] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 19] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 20] This explanation illustrates partial cross-sectional diagrams of semiconductor devices at various stages of manufacturing. [Figure 21] Illustrates a partial cross-sectional view of a portion of a semiconductor device of an exemplary cell topography of FIG. 1 along reference line 21A''-21A''. [Figure 22] Illustrates a partial cross-sectional view of a portion of a semiconductor device according to this specification. [Figure 23] Illustrates partial cross-sectional views of a semiconductor device at various stages of fabrication along reference line 23A-23A of FIG. 1 according to this specification. [Figure 24] Illustrates partial cross-sectional views of a semiconductor device at various stages of fabrication along reference line 23A-23A of FIG. 1 according to this specification. [Figure 25] Illustrates partial cross-sectional views of a semiconductor device at various stages of fabrication along reference line 23A-23A of FIG. 1 according to this specification. [Figure 26] Illustrates partial cross-sectional views of a semiconductor device at various stages of fabrication along reference line 23A-23A of FIG. 1 according to this specification. [Figure 27] Illustrates partial cross-sectional views of a semiconductor device at various stages of fabrication along reference line 23A-23A of FIG. 1 according to this specification. [Figure 28] Illustrates partial cross-sectional views of a semiconductor device at various stages of fabrication along reference line 23A-23A of FIG. 1 according to this specification.

[0009] The following description provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the appended claims should not be limited to the specific examples disclosed. In the following description, the terms "example" and "for example" are non-limiting.

[0010] For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and like reference numerals in different figures refer to like elements. Further, descriptions and details of well-known steps and components are omitted for simplicity of the description.

[0011] For clarity in the drawings, certain regions of the device structure, such as doped or dielectric regions, trenches, or contacts, may be illustrated as having substantially straight edges and precisely angled corners. However, those skilled in the art will understand that due to dopant diffusion and activation or layer formation, the edges of such regions may not be generally straight, and the corners may not be precisely angled.

[0012] In this specification, semiconductor devices are described as having specific N-type conductive regions and specific P-type conductive regions, but those skilled in the art will understand that the conductivity type can be reversed, and that this is also possible in accordance with this description, taking into account any necessary polarity reversal of the voltage, transistor type and / or current direction reversal, etc.

[0013] Furthermore, the terms used herein are intended solely to illustrate specific examples and are not intended to limit this disclosure. Where used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0014] As used herein, “conducting electrode” means an element of a device through which current is conducted, such as the source or drain of a MOS transistor, the emitter or collector of a bipolar transistor, or the cathode or anode of a diode; and “control electrode” means an element of a device that controls current through a device, such as the gate of a MOS transistor or the base of a bipolar transistor.

[0015] When used in relation to semiconductor regions, wafers, or substrates, the term “primary surface” means the surface of a semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, insulator, conductor, or polycrystalline semiconductor. The primary surface may have a topography that varies in the x, y, and z directions.

[0016] In addition, the structure described herein can embody either a cell-based design (where the body region consists of multiple separate, isolated cell or stripe regions) or a single-based design (where the body region is a single region formed in a central part with an elongated pattern, typically a meandering pattern, or connected appendages). However, one embodiment of this description will be described as a cell-based design throughout the description for ease of understanding. It is understood that this description encompasses both cell-based and single-based designs.

[0017] The terms “comprises,” “comprising,” “includes,” “including,” “has,” “have,” and / or “having,” as used herein, are open-ended terms that specify the presence of the described features, numbers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, actions, elements, components, and / or groups thereof.

[0018] The term "or" means any one or more items in the list joined by "or". For example, "x or y" means any element in the set of three elements {(x), (y), (x,y)}. Another example is "x, y, or z" meaning any element in the set of seven elements {(x), (y), (z), (x,y), (x,z), (y,z), (x,y,z)}.

[0019] As used herein, the term “step” means one or more unit processes used to manufacture a semiconductor device, and a process step such as an etching step, a photoresist masking step, a deposition step, or a doping step may include multiple or a series of unit processes. Such unit processes may include, but are not limited to, a cleaning process, a drying process, an exposure process, a developing process, a stripping process, and unit processes commonly used within a process step.

[0020] The terms “first,” “second,” and so on may be used herein to describe various members, elements, regions, layers, and / or sections, but these members, elements, regions, layers, and / or sections should not be limited by these terms. These terms are used solely to distinguish one member, element, region, layer, and / or section from another. Thus, for example, the first member, first element, first region, first layer, and / or first section described below may be referred to as the second member, second element, second region, second layer, and / or second section without departing from the teachings of this disclosure.

[0021] When used herein in relation to circuit operation, the terms “during,” “while,” and “when” are not precise terms meaning that an action occurs immediately upon an initiation action, and it will be recognized by those skilled in the art that there may be some small, reasonable delay, such as a transmission delay between responses initiated by an initiation action. Furthermore, the term “while” means that a particular action occurs within at least a portion of the duration of the initiation action.

[0022] The use of the words "about," "approximately," or "substantially" means that the value of an element is expected to be close to the state value or position. However, as is well known in the art, there are usually small differences that prevent the value or position from being accurately described.

[0023] Unless otherwise specified, as used herein, the terms “over” or “on” include any orientation, arrangement, or relationship that the specified element may directly or indirectly come into physical contact with.

[0024] Unless otherwise specified, as used herein, the term “overlap” includes orientations, arrangements, or relationships in which the specified elements can at least partially or completely coincide or align within the same or different planes.

[0025] It should be further understood that the examples illustrated and described below as preferred may include examples not specifically disclosed herein, and / or may be carried out in the absence of any elements not specifically disclosed herein. [Modes for carrying out the invention]

[0026] In general, this example relates to semiconductor device structures and methods for fabricating semiconductor devices, including trench-gate MOSFET devices having multiple shield electrodes, which have improved manufacturability and performance. In some examples, structures are described that include cell topography structures to facilitate electrical connections between the multiple shield electrodes. Such structures may be provided, for example, at the tip of an active trench. In some examples, such structures may be provided at the end of a termination trench enclosing the tip of an active trench. In some examples, methods are described to improve the manufacturability of the electrical connection structure between the multiple shield electrodes and the electrical connections to the termination trench, thereby improving the overall reliability of the semiconductor device. Such methods include using a negative photoresist when preparing to remove portions of the shield dielectric and using a multi-step removal process when providing the upper shield conductor. In addition, the methods and structures simplify the interconnection scheme between shield conductors, which saves layout space, simplifies cell topography, and reduces the impact on die size. Further advantages and benefits will become apparent to those skilled in the art based on the following description.

[0027] In one example, a method for manufacturing a semiconductor device includes providing a region of semiconductor material comprising a top surface, an edge region, multiple shield conductor contact areas within the edge region, an active area, and an upper shield contact area. The method includes providing an active trench extending from the top surface into the region of semiconductor material. The active trench includes a lower shield conductor, a first shield dielectric that isolates the lower shield conductor from the region of semiconductor material, an upper shield conductor, and a second shield dielectric that isolates the lower shield conductor from the upper shield conductor within the active area. The active trench extends laterally from the active area into the multiple shield conductor contact area within the region of semiconductor material, and the lower and upper shield conductors are coupled together within the multiple shield conductor contact area. The method includes providing a shield contact within the upper shield contact area coupled to the upper shield conductor in the active trench.

[0028] In one example, a method for manufacturing a semiconductor device includes providing a region of semiconductor material comprising a top surface, an edge region adjacent to the top surface, a plurality of shield conductor contact areas, an active area adjacent to the top surface, and an upper shield contact area adjacent to the top surface and outside the plurality of shield conductor contact areas. The method includes providing an active trench extending from the top surface into the region of semiconductor material. The active trench includes a lower shield conductor, a first shield dielectric that isolates the lower shield conductor from the region of semiconductor material, an upper shield conductor, and a second shield dielectric that isolates the lower shield conductor from the upper shield conductor within the active area. The active trench extends laterally from the active area into the plurality of shield conductor contact areas within the region of semiconductor material, and the lower and upper shield conductors are coupled together within the plurality of shield conductor contact areas. The method also includes providing a termination trench extending from the top surface into a second portion of the region of semiconductor material. The termination trench includes a lower shield conductor, a first shield dielectric that isolates the lower shield conductor from the semiconductor material region, an upper shield conductor, and a second shield dielectric that isolates the lower shield conductor from the upper shield conductor within the active area. The termination trench extends laterally from the active area into the multiple shield conductor contact area within the semiconductor material region, and the lower and upper shield conductors are coupled together within the multiple shield conductor contact area. The method includes providing a shield contact within the upper shield contact area coupled to the upper shield conductor in the active trench.

[0029] In one example, a semiconductor device includes a region of semiconductor material comprising a top surface, an edge region, a multi-shield conductor contact area, an active area, and an upper shield contact area outside the multi-shield conductor contact area. The active trench extends from the top surface into the region of semiconductor material and includes a lower shield conductor, a first shield dielectric that isolates the lower shield conductor from the region of semiconductor material, an upper shield conductor, and a second shield dielectric that isolates the lower shield conductor from the upper shield conductor within the active area. The active trench extends laterally from the active area into the multi-shield conductor contact area within the region of semiconductor material, and the lower and upper shield conductors are coupled together within the multi-shield conductor contact area. The shield contacts are located in the upper shield contact area coupled to the upper shield conductor within the active trench.

[0030] This disclosure includes other examples, which may be found in the drawings, claims, or description of this disclosure.

[0031] Figure 1 illustrates a partial top view of the cell topography 100 of an exemplary semiconductor device 10 as described herein. Figure 2 illustrates a partial cross-sectional view of a portion of the semiconductor device 10 along the reference line 2A-2A in Figure 1. Figure 3 illustrates a partial cross-sectional view of another portion of the semiconductor device 10 along the reference line 3A-3A in Figure 1, and Figure 4 illustrates a partial cross-sectional view of yet another portion of the semiconductor device 10 along the reference line 4A-4A in Figure 1. The following parts of the description will refer to Figures 1 to 4.

[0032] The semiconductor device 10 is an example of a trench-gate MOSFET with a multi-shield electrode configuration. In this example, the semiconductor device 10 has a dual-shield electrode configuration in which the shield electrodes are separated by a shield dielectric in one or more first portions of the cell topography 100 and coupled together in one or more second portions of the cell topography 100. This description is not limited to MOSFET devices and is understood to be useful for other devices such as insulated-gate bipolar transistor (IIGBT) devices, thyristor devices, or devices that utilize shield electrodes. Furthermore, although this example uses a dual-shield electrode configuration, this description is understood to relate to configurations that use more than two shield conductors.

[0033] The cell topography 100 may also comprise or be referred to as a device layout or cell layout, and the semiconductor device 10 may also be referred to as a semiconductor component, an electronic device structure, or an electronic component. Referring to Figure 2, the semiconductor device 10 comprises a region 11 of semiconductor material having a top surface 18 and a bottom surface 19 facing the top surface 18. In this example, the cell topography 100 of the semiconductor device 10 comprises a device layout or configuration adjacent to and extending across the top surface 18.

[0034] In some examples, the cell topography comprises an edge region 101 adjacent to a portion of the top surface 18, a dual-shielded conductor contact area 102 within the edge region 101, an active area 103 adjacent to another portion of the top surface 18, an upper shield contact area 104 adjacent to a further portion of the top surface 18, and a region 106 in which the lower shield conductor 21A is electrically isolated from the upper shield conductor 21B by the shield dielectric 240. Region 106 may also comprise, or be referred to as, a dual-shielded isolation region in which the shield dielectric 240 (see, for example, Figures 2 to 4) isolates or separates the lower shield conductor 21A from the upper shield conductor 21B. In this example, the active area 103 and the upper shield contact area 104 are located within region 106. In addition, the upper shield contact area 104 is outside the dual-shielded conductor contact area 102 or laterally spaced therefrom.

[0035] In some examples, the edge region 101 may correspond to a portion of the cell topography 100, with each activated trench 22A terminating at a tip region 220, and a terminating trench 22B enclosing the tip region 220 of the activated trench 22A and entering into an additional activated trench 22A, the additional activated trench 22A extending in the opposite direction and terminating at a tip region 220 in the opposite edge region of the cell topography 100. In some examples, the edge region 101 includes a gate contact 280 coupled to a gate electrode 28 and a conductor 44B (see, for example, Figure 2).

[0036] In some examples, the cell topography 100 is suitable for medium-voltage semiconductor devices 10, such as 30-volt to 100-volt shielded gate trench MOSFET devices. However, the structures and methods described herein are also relevant to higher-voltage devices. In the top view of Figure 1, the source conductor 44A and gate conductor 44B of the semiconductor device 10 are illustrated with dashed lines to better illustrate the following structure, which is further illustrated in the cross-sectional views of Figures 2, 3, and 4. In this example, the cell topography 100 can represent the upper right portion of the device cell, and it is understood that its illustrated topography can be replicated and reoriented (e.g., inverted vertically and / or horizontally) to provide a complete cell topography of the semiconductor device 10 having a desired number of active trenches 22A and terminating trenches 22B.

[0037] In this example, the semiconductor device 10 comprises a body 11 of semiconductor material which may include a semiconductor substrate 12 and a semiconductor region 14 provided on or as part of the semiconductor substrate 12. The semiconductor device 10 further comprises active trenches 22A and one or more termination trenches 22B. In this example, the active trenches 22A are provided as a plurality of elongated stripe active trenches, each terminated at a leading region 220. In this example, the active trenches 22A illustrated in Figure 1, having leading regions 220, can be coupled or connected at opposing edges of the cell topography 100, for example, to the opposite or lower surface of the termination trenches 22B. In this example, one or more active trenches 21A extend laterally from the active area 103 to the dual-shielded conductor contact area 102, together with the region 11 of semiconductor material.

[0038] In this example, the semiconductor device 10 comprises a lower shield conductor 21A, an upper shield conductor 21B, a shield dielectric 24 that isolates the lower shield conductor 21A and the upper shield conductor 21B from the semiconductor region 14, and a gate electrode 28 located above the upper shield conductor 21B and isolated from the upper shield conductor 21B by an inter-electrode dielectric 27 and isolated from the semiconductor region 14 by a gate dielectric 26. In this example, the portion of the lower shield conductor 21A is isolated from the portion of the upper shield conductor 21B by a shield dielectric 240 to provide a dual-shield configuration. It is understood that multiple shield conductor configurations can be provided for the semiconductor device 10 by using additional shield conductors or electrodes and shield dielectrics.

[0039] Shield dielectric 24 may be an example of a first shield dielectric, and shield dielectric 240 may be an example of a second shield dielectric. Lower shield conductor 21A may be an example of a first shield conductor or first shield electrode, and upper shield conductor 21B may be an example of a second shield conductor or second shield electrode. In this example, dual shield electrode 21' may be used to describe a portion of semiconductor device 10 (including active trench 22A and termination trench 22B) in which shield dielectric 240 isolates lower shield conductor 21A from upper shield conductor 21B, and shield electrode 21'' may be used to describe a portion of semiconductor device 10 in which lower shield electrode 21A is coupled to upper shield conductor 21B.

[0040] According to this description, one or more regions without a shield dielectric 240 are provided within the semiconductor device 10, and a recessed contact region 212 is provided between the lower shield conductor 21A and the upper shield conductor 21B (see, for example, Figures 2 and 4). More specifically, the recessed contact region 212 is located inside the active trench 22A and termination trench 22B below the top surface 18, where the lower shield conductor 21A contacts or connects to the upper shield electrode 22B. In this example, a dual shield conductor contact area 102 is provided within the cell topography 100, which is an exemplary location for the recessed contact region 212. The dual shield conductor contact area 102 comprises or may be referred to as a multiple shield conductor contact area, multiple shield conductor contact region, or recessed shield conductor contact area, and refers to the portion of the cell topography 100 where the recessed contact region 212 is located. In some examples, one or more recessed contact areas 212 extend laterally beneath the gate contact 280, as schematically illustrated in Figure 2. In this example, the dual shielded conductor contact area 102 does not have a shielded contact 210A.

[0041] In some examples, the shield contact 210A is provided within the upper shield contact area 104 of the cell topography 100, and the shield dielectric 240 is coupled to the upper shield conductor 21B within a region of the semiconductor device 10 that isolates the upper shield conductor 21B from the lower shield electrode 21A (see, for example, Figures 2 and 3). In this way, the upper shield conductor 21B provides a lateral conduction path from the upper shield contact area 104 to a dual shield conductor contact area 102, which is provided with a recessed contact area 212 between the lower shield conductor 21A and the upper shield conductor 21B. According to this description, the interconnection scheme or layout between the lower shield conductor 21A and the upper shield conductor 21B is advantageous because it does not require the use of a separate shield contact structure for the lower shield conductor 21A. In this interconnection scheme, the shield contact 210A provides direct contact with the upper shield conductor 21B and indirect contact with the lower shield conductor 21A. In particular, this saves space and avoids an increase in die size.

[0042] In this example, the termination trench 22B also includes both the lower shield conductor 21A and the upper shield conductor 21B. Similar to the active trench 22A, a portion of the termination trench 22B includes a shield dielectric 240 that isolates the lower shield conductor 21A from the upper shield conductor 21B, which is illustrated, for example, in Figures 2 and 3. In this example, one of the recessed contact regions 212 couples the lower shield conductor 21A and the upper shield conductor 21B together in the dual shield conductor contact area 102 of the cell topography 100, which is further illustrated in Figures 2 and 4.

[0043] Referring to Figures 3 and 4, the semiconductor device 10 comprises a region 11 of semiconductor material, which may also comprise, or be referred to as, a body of semiconductor material, a semiconductor workpiece, a semiconductor region, or semiconductor material. In some examples, the region 11 of semiconductor material includes silicon. In other examples, the region 11 or a portion thereof may include, but is not limited to, silicon-germanium, silicon-germanium-carbon, carbon-doped silicon, silicon carbide, gallium nitride, or other related or equivalent materials known to those skilled in the art.

[0044] In some examples, the semiconductor material region 11 may comprise a substrate 12 such as an N-type silicon substrate, and the semiconductor region 14 may be adjacent to the substrate 12. The substrate 12 may also be referred to as the semiconductor substrate or starting substrate, and the semiconductor region 14 may also be referred to as the semiconductor layer or extended drain region. In some examples, the substrate 12 has a resistivity in the range of about 0.0005 ohm-cm to about 0.005 ohm-cm. For example, the substrate 12 may be doped with phosphorus, arsenic, or antimony. In the illustrated examples, the substrate 12 provides a drain region, drain contact, or first current-carrying contact for the semiconductor device 10. The semiconductor material region 11 comprises a top surface 18 and a bottom surface 19 opposite the top surface 18. The top surface 18 may also be referred to as the top surface or first main surface, and the bottom surface 19 may also be referred to as the back surface or second main surface.

[0045] In some examples, the semiconductor region 14 can be formed using semiconductor epitaxial growth techniques. Alternatively, the semiconductor region 14 can be formed using semiconductor doping and diffusion techniques, or other techniques known to those skilled in the art. In a suitable example for a 50-volt device, the semiconductor region 14 has N-type conductivity and approximately 1.0 × 10⁻¹⁶ 16 atoms / cm 3 ~Approx. 5.0×10 17 atoms / cm 3The dopant concentration can be such that the semiconductor region 14 has a thickness of approximately 3 to 5 microns. The dopant concentration and thickness of the semiconductor region 14 are determined by the desired drain-source breakdown voltage (BV) of the semiconductor device 10. DSS ) can be increased or decreased according to the rating. In some examples, the semiconductor region 14 can include a gradient dopant profile. In another example, the conductivity type of the substrate 12 can be opposite to that of the semiconductor region 14 to form, for example, an IGBT semiconductor device.

[0046] The shield dielectric 24 may be one or more dielectric or insulating materials. In some examples, the shield dielectric 24 may comprise a thermal oxide layer having a thickness ranging from about 0.1 microns to about 1.5 microns. In some examples, the shield dielectric 24 may consist of multiple layers of similar or different materials, such as thermal and deposited dielectric or insulating materials. The thickness of the shield dielectric depends on the BV required by the device. DSS It changes depending on the higher BV DSS This requires a thicker layer. The shield dielectric 240 may be one or more dielectric or insulating materials. In some examples, the shield dielectric 240 may be a thermal oxide layer having a thickness in the range of about 0.05 microns to about 0.5 microns. In some examples, the shield dielectric 240 may be multiple layers of similar or different materials, such as thermal and deposited dielectric or insulating materials. In some examples, the shield dielectric 240 may be thinner than the shield dielectric 24 but thicker than the gate dielectric 26. In some examples, the shield dielectric 240 may be thinner than the interelectrode dielectric 27.

[0047] The gate dielectric 26 and the inter-electrode dielectric 27 may include oxides, nitrides, tantalum pentoxide, titanium dioxide, barium strontium titanate, high-k dielectric materials, combinations thereof, or other relevant or equivalent materials known to those skilled in the art. In some examples, the gate dielectric 26 and the inter-electrode dielectric 27 may be silicon oxide. In some examples, the gate dielectric 26 may have a thickness of about 0.02 microns to about 0.1 microns, and the inter-electrode dielectric 27 may have a thickness greater than that of the gate dielectric 26. In some examples, the inter-electrode dielectric may have a thickness of about 0.1 microns to about 0.5 microns. In some examples, the dielectric 24 may have a thickness greater than that of the gate dielectric 26 and the inter-electrode dielectric 27.

[0048] In some examples, the gate electrode 28, the lower shield conductor 21A, and the upper shield conductor 21B include a doped polycrystalline semiconductor material such as doped polysilicon. In some examples, an N-type conductive dopant material can be used to dope the polysilicon. In some examples, a metal, silicide, or other conductor can be included as part of the gate electrode 28, the lower shield conductor 21A, or the upper shield conductor 21B.

[0049] The semiconductor device 10 includes a body region 31 that extends inward from the top surface 18 into a region of semiconductor material 11 adjacent to the active trench region 22A (for example, extending inward into the semiconductor region 14). The body region 31 also comprises a doped region or a base region, or may be referred to as such. The body region 31 may have a conductivity type opposite to that of the semiconductor region 14. For example, if the semiconductor region 14 contains an N-type conductivity, the body region 31 contains a P-type conductivity. The body region 31 contains a dopant concentration suitable for forming an inversion layer that acts as a channel region of the semiconductor device 10. In some examples, the body region 31 may extend from the top surface 18 to a depth of about 0.3 microns to about 1.5 microns. The body region 31 may be formed using doping techniques such as ion implantation and annealing techniques. In some examples, the body region 31 is a single continuous and interconnected region. In other examples, the body region 31 may be multiple regions that are separated or contain distinct regions or cells.

[0050] The semiconductor device 10 may further comprise a doped region 33 within the body region 31. In some examples, the doped region 33 may be omitted from the body region 31 that is in direct contact with the termination trench 22B. The doped region 33 may also be referred to as a source region, current carrier region, or current conduction region. The doped region 33 contains N-type conductivity when the body region 31 contains P-type conductivity and can be formed using, for example, a phosphorus or arsenic dopant source. In some examples, the doped region 33 can be formed within the body region 31 using an ion implantation doping process. The doped region 33 may extend from the top surface 18 to a depth of, for example, about 0.2 microns to about 0.5 microns. The doped region 33 may be an example of a second current carrier region.

[0051] In some examples, the semiconductor device 10 further comprises an interlayer dielectric (ILD) 41 on top of the gate electrode 28. In some examples, the interlayer dielectric 41 includes silicon oxide, such as doped or undoped deposited silicon oxide. In some examples, the interlayer dielectric 41 may include one layer of phosphorus or boron and phosphorus-doped deposited silicon oxide and one layer of undoped oxide. In some examples, the interlayer dielectric 41 may have a thickness of about 0.25 microns to about 1.0 micron. In some examples, the interlayer dielectric 41 can be planarized to provide a more uniform surface topography, which improves manufacturability.

[0052] In some examples, the semiconductor device 10 further comprises a body contact region 36 within the body region 31. The body contact region 36 may also be referred to as a doped region, enhancement region, or contact region. In some examples, the body contact region 36 may contain P-type conductivity and be configured to provide lower contact resistance to the body region 31. The body contact region 36 can be formed using ion implantation techniques (e.g., using boron) and annealing techniques.

[0053] In some examples, the semiconductor device 10 further comprises a conductive region 43 configured to provide electrical contact to the doped region 33 and the body region 31 via a body contact region 36. In some examples, the conductive region 43 comprises a conductive plug or plug structure. In some examples, the conductive region 43 may include a conductive barrier structure or liner and a conductive filler material. In some examples, the barrier structure may include a metal / metal nitride composition such as titanium / titanium nitride, or other related materials or equivalent materials known to those skilled in the art. In other examples, the barrier structure may further include a metal silicide structure. In some examples, the conductive filler material includes tungsten. In some examples, the conductive region 43 may be planarized to provide a more uniform surface topography.

[0054] In some examples, conductors 44A and 44B can be formed adjacent to the top surface 18, and conductor 46 can be formed adjacent to the bottom surface 19. Conductors 44A and 44B can also be referred to as top metal or top conductor, and conductor 46 can also be referred to as bottom conductor or backside metal. Conductors 44A, 44B, and 46 can be configured to provide electrical connection between individual cells of the semiconductor device 10 and the next level of assembly. In some examples, conductors 44A and 44B include titanium / titanium nitride / aluminum-copper, or other relevant or equivalent materials known to those skilled in the art, and are configured as source electrodes or terminals. In some examples, conductor 46 includes a solderable metal structure such as titanium-nickel-silver, chromium-nickel-gold, or other relevant or equivalent materials known to those skilled in the art, and is configured as a drain electrode or terminal. In some examples, a further passivation layer (not shown) can be formed adjacent to conductors 44A and 44B. In some examples, shield electrodes 21' and 21'' can be connected to conductor 44A such that shield electrodes 21' and 21'' are at the same potential as the doped region 33 when the semiconductor device 10 is in use. In other examples, shield electrodes 21' and 21'' can be configured to be independently biased or can be electrically floating.

[0055] In one example, the operation of the semiconductor device 10 can proceed as follows. When conductors 44A and shield electrodes 21' and 21'' are operating at a potential V of 0 volts S and the gate electrode 28 receives a control voltage V of 10 volts, which is greater than the conduction threshold of the semiconductor device 10 G and the drain electrode (or output terminal) 46 operates at a drain potential V of less than 2.0 volts. D V G and V SDepending on the value of the device current I, the body region 31 will invert the adjacent gate electrode 28 to form a channel region, which will electrically connect the doped region 33 to the semiconductor region 14 in the active trench 22A. DS It flows from conductor 46 and is sent to conductor 44B through semiconductor region 14, channel region, and doped region 33. In some examples, I DS This is approximately 10.0 amperes. A control voltage V is used to switch the semiconductor device 10 to the off state, which is below the semiconductor conduction threshold. G A control voltage is applied. Such a control voltage eliminates the channel region and I DS The current no longer flows through the semiconductor device 10. According to this description, the configuration of the semiconductor device 10 described herein is improved BV through charge equilibrium technology. DSS To achieve the performance, a multi-shielded electrode configuration is used with local coupling between shield conductors (i.e., coupling is facilitated using the dual-shielded conductor contact area 102), and the gate-drain capacitance C gd This also reduces Qrr, thereby improving switching performance in particular.

[0056] Figures 5 to 20 illustrate partial cross-sectional views of a semiconductor device at various stages of fabrication according to this description. The method described in Figures 5 to 20 can be used, for example, to fabricate, form, or manufacture a semiconductor device 10 as described in Figures 1 to 4. In particular, the method described herein illustrates the step of providing a region of the semiconductor device 10 comprising a shield dielectric 240 that isolates the lower shield conductor 21A from the upper shield conductor 21B, and a region of the semiconductor device 10 to which the lower shield conductor 21A is coupled, including being electrically coupled to the upper shield conductor 21B through one of the recessed contact regions 212. Each of the regions described above may be illustrated in a side-by-side configuration in some of the following cross-sectional views, for the sake of simplicity, and it should be understood that each region may be laterally separated or provided in a particular part of the semiconductor device 10, as illustrated in Figure 1. However, in other examples, each region may be in a side-by-side configuration as illustrated.

[0057] Figure 5 illustrates a semiconductor device 10 in the initial stages of fabrication. In this example, a region 11 of semiconductor material comprising a substrate 12 and a semiconductor region 14 can be provided, as described earlier. In some examples, masking and etching processes can be used to form active trenches 22A and termination trenches 22B extending from the top surface 18 of the semiconductor material body 11 into the semiconductor region 14 and terminating within the semiconductor region 14. When the region 11 of semiconductor material contains silicon, the active trenches 22A and termination trenches 22B can be provided using fluorine etching chemistry or similar chemistry known to those skilled in the art. In some examples, the active trenches 22A may have a width in the range of about 500 nanometers to about 700 nanometers, and the termination trenches 22B may have a width similar to or different from the width of the active trenches 22A. In some examples, the active trenches 22A are provided as elongated striped trenches with a tip region 220, as illustrated in Figures 1 and 2. In some examples, the active trench 22A and the terminating trench 22B may have inclined sidewall surfaces and rounded bottom surfaces. In the next step, the dielectric 246 is provided on the top surface 18 and on the surfaces of the active trench 22A and the terminating trench 22B. In some examples, the dielectric 246 comprises a thermal oxide having a thickness in the range of about 0.1 microns to about 1.5 microns.

[0058] Figure 6 illustrates a semiconductor device 10 after further processing. In this example, dielectric 247 can be provided on dielectric 246. In some examples, dielectric 247 may include a deposited oxide formed using chemical vapor deposition (CVD) technique. In some examples, dielectric 247 may have a thickness of about 0.05 microns to about 0.3 microns. In this example, dielectric 246 and dielectric 247 form the shield dielectric 24 of the semiconductor device 10.

[0059] Figure 7 illustrates a semiconductor device 10 after further processing. In this example, the conductive material 211A is provided within the active trench 22A and the termination trench 22B. The conductive material 211A may include, or be referred to as, a shielding conductor or shielding conductive material. In some examples, the conductive material 211A includes a polycrystalline semiconductor material such as doped polysilicon. In some examples, the conductive material 211A includes polysilicon doped with an N-type dopant and may be provided using CVD techniques. In some examples, a planarization process can be used to planarize and remove the portion of the conductive material 211A on the top surface 18, leaving the other portion of the conductive material 211A within the active trench 22A and the termination trench 22B. In some examples, a chemical mechanical planarization (CMP) technique can be used to planarize the conductive material 211A. In some examples, the planarization process leaves the top surface of the conductive material 211A substantially coplanar with the top surface of the dielectric 247. The conductive material 211A can be an example of the first conductive material.

[0060] Figure 8 illustrates the semiconductor device 10 after further processing. In this example, the portion of the conductive material 211A is removed from within the upper part of the active trench 22A and the termination trench 22B to form the lower shield conductor 21A. In some examples, when the conductive material 211A contains polysilicon, the lower shield conductor 21A can be formed using a dry etching technique with fluorine chemistry. In some examples, the lower shield conductor 21A can have a thickness or height in the range of about 0.3 microns to about 2.0 microns.

[0061] Next, as illustrated in Figure 9, a shield dielectric 240 can be provided on the lower shield conductor 21A. In some examples, the shield dielectric 240 contains a thermal oxide. In some examples, the shield dielectric 240 can have a thickness of about 0.03 microns to about 0.15 microns.

[0062] Figures 10 and 11 illustrate a semiconductor device 10 after further processing. More specifically, Figures 10 and 11 illustrate process steps for forming a recessed contact region 212 in a selected region of the semiconductor device 10, while leaving the shield dielectric 240 in other regions of the semiconductor device 10. In this example, the photoresist layer 51 is provided on a region 11 of the semiconductor material, including within the active trench 22A and the termination trench 22B. Through experimentation, it was found that in some examples, when removing the shield dielectric 240 from a specific region of the semiconductor device 10, it is preferable for the photoresist layer 51 to be a negative-type photoresist layer rather than a positive-type photoresist. It was found that with a positive-type photoresist, overexposure of the positive-type photoresist is required to clear the positive-type photoresist from within the active trench 22A and the termination 22B from which the shield dielectric 240 is removed. In some cases, it is difficult to completely remove the positive type after exposure, resulting in inconsistency and reduced manufacturing yield and cycle time. In positive-type photoresists, exposure to UV light is necessary to alter the chemical structure of the resist so that it becomes more soluble in the photoresist developer. In negative-type photoresists, exposure to UV light polymerizes the chemical structure of the photoresist, which is the opposite of positive-type resists. Instead of becoming more soluble in the photoresist developer, the exposed negative-type photoresist becomes difficult to dissolve. Therefore, by having the photoresist layer 51 contain a negative-type photoresist, overexposure is not required deep within the trench; instead, exposure is only needed to reach the portion of the top surface 18 that is in direct contact with the active trench 22A and the terminal trench 22B.

[0063] As illustrated in Figure 10, a mask 52 is provided over a region of the semiconductor device 10 where one or more recessed contact regions 212 are provided, and a photoresist layer 51 is exposed to a UV light source 53. In this example, this results in the photoresist layer 51 being superimposed over the left active trench of the active trench 22A and over the terminal trench 22B. After exposure to the UV light source 53, the photoresist layer 51 is developed, thereby removing the unexposed portion of the photoresist layer 51 above and inside the first portion of the right active trench of the active trench 22A that forms an opening 510, as illustrated in Figure 11. For example, the first portion may be within a leading region 220 having an active trench 22A configured as an elongated active trench. It is understood that the exposed portion of the photoresist layer 51 may remain on or cover the second portion of the right active trench 22A (which may be represented, for example, by the left active trench of the active trench in Figure 10) within the active area 103 of the cell topography 100. According to this description, manufacturing yield and cycle time are improved by providing a photoresist layer 51 that includes a negative-type photoresist.

[0064] After removing the photoresist layer 51 to provide an opening 510, the shield dielectric 240 can be removed from the active trench 22A exposed through the opening 510 using a wet or dry dielectric etching process. In some examples, the removal of the shield dielectric 240 can also remove the exposed portions of dielectric 247 and dielectric 246, which may leave recessed edge portions 510A in direct contact with the active trench 22A exposed through the opening 510. After the shield dielectric 240 has been removed, the photoresist layer 51 can be removed using conventional processing techniques.

[0065] Figure 12 illustrates a semiconductor device 10 after further processing. In this example, the conductive material 211B is provided within the active trench 22A and termination trench 23 above the lower shield conductor 21A. The conductive material 211B may include or be referred to as a shield conductor or shield conductive material. In some examples, the conductive material 211B includes a polycrystalline semiconductor material such as doped polysilicon. In some examples, the conductive material 211B includes polysilicon doped with an N-type dopant and may be provided using the CVD technique. In some examples, a planarization process can be used to planarize and remove a portion of the conductive material 211B on the top surface 18, leaving the other portion of the conductive material 211B within the active trench 22A and termination trench 22B. In some examples, a portion 211B' of the conductive material 211B may remain on the recessed edge portion 510A after the planarization process. In some examples, the CMP technique can be used to planarize the conductive material 211B. In some examples, the planarization process leaves the top surface of the conductive material 211B substantially coplanar with the top surface of the dielectric 247. The lower shield conductor 21A is coupled, including being electrically coupled to the upper shield conductor 21B through one of the recessed contact regions 212, by first removing the shield dielectric 240 in the right-hand active trench of the active trench 22A. The shield dielectric 240 electrically isolates the lower shield conductor 21A from the upper shield conductor 21B in the left-hand active trench of the active trench 22A and in the termination trench 22B. Conductive material 211B is an example of a second conductive material.

[0066] Figure 13 illustrates a semiconductor device 10 after further processing. In this example, the portion of the conductive material 211B, including portion 211B', is removed from within the upper part of the active trench 22A and the termination trench 22B in a first recess step, which is part of the two-step removal process described herein. The first step may include, or may be referred to as, a blanket removal step, a global removal step, or an unmasked removal step. In some examples, the first recess step provides the upper surface of the conductive material 211B in both the active trench 22A and the termination trench 21B, below the upper surface of the dielectric 247 and in close proximity to the top surface 18. In some examples, when the conductive material 211B contains polysilicon, a dry etching technique using fluorine chemistry may be used for the first recess step. In this example, the first recess step provides the upper shield conductor 21B within the termination trench 22B.

[0067] Figure 14 illustrates the semiconductor device 10 after further processing. In this example, a masking layer 53 is provided on the top surface 18 and patterned to provide an opening 530 that exposes the active trench 22A. A portion of the masking layer 53 remains on the termination trench 22B. Other portions of the masking layer 53 also remain on the leading region 220 of the active trench 22A (e.g., within the edge region 101 of the cell topography 100) and where the shield contact 210A is provided (e.g., within the upper shield contact area 104 of the cell topography 100). In some examples, the masking layer 53 may include a photoresist material. Next, an additional portion of the conductive material 211B is removed in a second recess step to provide the upper shield conductor 21B within the active trench 22A. After the second recess step, the masking layer 53 can be removed. In this example, the upper shield conductor 21B in the active trench 22A is recessed below the top surface 18 by a greater distance compared to the upper shield conductor 21B in the terminal trench 22B. In some examples, the upper shield conductor 21B in the active trench 22A can have a thickness in the range of approximately 0.5 microns to approximately 3.0 microns.

[0068] The method illustrated in Figures 13 and 14 is an exemplary process improvement in which the first recess is provided in a two-step process. Through experiments, it was found that without the first recess step described in Figure 13, an undercut effect occurs in the upper shield conductor 21B within the termination trench 22B. This undercut effect results in an incorrectly shaped upper topography of the upper shield conductor 21B, increasing the occurrence of open contacts or floating contacts for the shield contact 210B within the termination trench 22B as shown in Figures 1 and 21. The two-step recess process described herein improves the quality of the upper topography and reduces the open contact and floating contact problems associated with single-step recess processes.

[0069] Figure 15 illustrates a semiconductor device 10 after further processing. In this example, the dielectric 270 is provided on a top surface 18, including the top surface of the shield conductor 21B. In some examples, the dielectric 270 may include a borosilicate glass (BSG) dielectric or a thermal oxide. In subsequent steps, as illustrated in Figure 16, a planarization process may be used to remove portions of dielectric 270, dielectric 247, and dielectric 246. In some examples, CMP may be used to provide the top surface of dielectric 270 that is substantially coplanar with the top surface 18 of the semiconductor material region 11.

[0070] Figure 17 illustrates a semiconductor device 10 after further processing. In this example, an etching process using hydrofluoric (HF) acid can be used to remove portions of dielectric 247 and dielectric 246 above the top surface 18. In some examples, this step can cause pitting of dielectric 247 and dielectric 246 below the top surface 18, and if dielectric 247 contains deposited oxide and dielectric 246 contains thermal oxide, dielectric 247 is etched at a faster rate than dielectric 246.

[0071] Figure 18 illustrates the semiconductor device 10 after further processing. In this example, a masking layer 54 is provided on the top surface 18 and patterned to provide an opening 540 that exposes the active trench 22A. The masking layer 54 remains on the termination trench 22B. In some examples, the masking layer 54 comprises a photoresist layer. In some examples, after the opening 540 is formed, buffered oxide etching (BOE) can be used to further remove portions of dielectric 270, dielectric 247, and dielectric 246. In this example, this forms an interlayer dielectric 27 on the upper shield conductor 21B and exposes the upper sidewall of the active trench 22A.

[0072] In a subsequent step, the masking layer 54 can be removed, as illustrated in Figure 19, and the gate dielectric 26 can be provided on the exposed upper sidewall of the active trench 22A. The gate dielectric 26 and interlayer dielectric 27 may include oxides, nitrides, tantalum pentoxide, titanium dioxide, barium strontium titanate, high-k dielectric materials, combinations thereof, or other relevant or equivalent materials known to those skilled in the art. In some examples, the gate dielectric 26 may be silicon oxide formed using a thermal oxidation technique. In some examples, the gate dielectric 26 may have a thickness of about 0.02 microns to about 0.1 microns. In some examples, when the gate dielectric 26 is formed, a dielectric 261 may be provided on the shield conductor 21B in the termination trench 22B. Based on the polycrystalline structure of the upper shield conductor 21B, the dielectric 261 may have a thicker gate dielectric 26.

[0073] Figure 20 illustrates a semiconductor device 10 after further processing. In this example, a gate conductor can be provided on the top surface 18 and planarized to provide a gate electrode 28 within the active trench 22A. In some examples, the gate electrode 28 comprises a doped polycrystalline semiconductor material such as doped polysilicon and can be formed using a CVD processing technique. In some examples, CMP can be used to planarize the deposited material to provide the gate electrode 28. The semiconductor device 10 can be further processed to provide a body region 31, a doped region 33, a body contact region 36, an ILD 41, a conductive region 43, and conductors 44a, 44B, and 46, as described earlier. According to this description, the method of Figures 5 to 20 provides a semiconductor device 10 comprising a region including a shield dielectric 240 that isolates a lower shield conductor 21A from an upper shield conductor 21B, and a region in which the lower shield conductor 21A is coupled to the upper shield conductor 21B through one or more recessed contact regions 212.

[0074] Figure 21 illustrates a partial cross-sectional view of the termination trench 22B of the semiconductor device 10 along the reference line 21A''-21A'' in Figure 1. In this example, the shield contact 210B is provided in the peripheral region of the cell topography 100 and contacts the upper shield conductor 21B at a location on the semiconductor device 10 where the shield dielectric 240 isolates the upper shield conductor 21B from the lower shield conductor 21A. In this way, the upper shield conductor 21A provides a lateral conduction path to the dual shield conductor contact area 102, and one of the recessed contact areas 212 connects the upper shield conductor 21B and the lower shield conductor 21A within the termination trench 22B. The shield contact 210B is an example of a second shield contact.

[0075] Figure 22 illustrates a partial cross-sectional view of an example of a semiconductor device 10A according to this description. The semiconductor device 10A in Figure 22 has some similarities in its configuration to the semiconductor device 10, and such similarities will not be repeated here. In this example, the semiconductor device 10A is provided with a shield silicide 218B on top of the upper shield conductor 21B, which can be used to reduce the shield resistance. In some examples, the semiconductor device 10A may further be provided with a shield silicide 218A on top of the lower shield conductor 21A to further reduce the shield resistance. In examples in which shield silicide 218A is included, the shield dielectric 240 may include a deposited oxide. Shield silicide 218A and shield silicide 218B may include cobalt silicide or other materials known to those skilled in the art. In some examples, the semiconductor device 10A is provided with a gate silicide 282 on top of the gate electrode 28, which can be used to reduce the gate resistance. In some examples, the shield silicide 218A can be used where a recessed contact area 212 connects the lower shield conductor 21A to the upper shield conductor 21B.

[0076] Figures 23 to 28 illustrate partial cross-sectional views of the semiconductor device 10 according to this description at various stages of fabrication. More specifically, Figures 23 to 28 are examples of the semiconductor device 10 along the reference line 23A-23A in Figure 1, which corresponds to a portion of the dual shield conductor contact area 102 of the cell topography 100, where the recessed contact region 212 connects the lower shield conductor 21A to the upper shield conductor 21B in the active trench 22A and the termination trench 22B.

[0077] Figure 23 illustrates a semiconductor device 10 in a fabrication step in which the lower shield conductor 21B is provided within the active trench 22A and the termination trench 22B, and the shield dielectric 240 is provided on top of the lower shield conductor 21B. In this example, the right-hand active trench of the active trench 22A in Figure 23 corresponds to one of the leading regions 220, and the left-hand active trench of the active trench 22A corresponds to an active trench extending in the opposite direction from the termination trench 22B, as illustrated in Figure 1.

[0078] Figure 24 illustrates the semiconductor device 10 after further processing. In this example, a masking layer 56 is provided on the top surface 18 and patterned to provide openings 560 that expose the active trench 22A and the termination trench 22B. According to this description, the masking layer 56 preferably comprises a negative photoresist as described earlier with respect to Figures 10 and 11. Next, the shield dielectric 240 is removed from the active trench 22A and the termination trench 22B using a wet etching process or a dry etching process, as illustrated in Figure 25. In some examples, the dielectric 247 can be removed in locations above the top surface 18 where the masking layer 56 is absent. The masking layer 56 remains in place during the etching process to protect the shield dielectric 240 in those locations on the semiconductor device 10 where it is desired that the lower shield conductor 21A be isolated from the upper shield conductor 21B. The masking layer 56 can then be removed.

[0079] Figure 26 illustrates the semiconductor device 10 after further processing. In this example, the conductive material 211B is provided within the active trench 22A and the termination trench 22B and coupled to the lower shield conductor 21A through a recessed contact region 212. The conductive material 211B may be provided as previously described with respect to Figure 12.

[0080] Figure 27 illustrates the semiconductor device 10 after further processing. In this example, the portion of the conductive material 211B is removed from within the upper part of the active trench 22A and termination 22B in the first recess step, as previously described in Figure 13. In this example, the first recess step provides the upper shield conductor 21B within the termination trench 22B.

[0081] Figure 28 illustrates the semiconductor device 10 after further processing. In this example, a masking layer 53 is provided on the top surface 18 and patterned to provide an opening 530 that exposes the active trench 22A. A portion of the masking layer 53 remains on the termination trench 22B. In some examples, the masking layer 53 may include a photoresist material. Next, an additional portion of the conductive material 211B is removed in a second recessing step to provide the upper shield conductor 21B within the active trench 22A. After the second recessing step, the masking layer 53 can be removed.

[0082] The method illustrated in Figures 27 and 28 has the same advantages as those previously described with respect to Figures 13 and 14, including an improved contact surface for the upper shield conductor 21B in the termination trench 22B. The improved contact surface reduces the possibility of open contact or floating contact for the shield contact 210B in the termination trench 22B, as shown in Figures 1 and 21.

[0083] From all of the foregoing, a person skilled in the art can determine that an exemplary method includes providing a region of semiconductor material, the region of semiconductor material comprising a top surface, an edge region, a plurality of shield conductor contact areas within the edge region, an active area, and an upper shield contact area. The method includes providing an active trench extending from the top surface into the region of semiconductor material, the active trench comprising a lower shield conductor, a first shield dielectric separating the lower shield conductor from the region of semiconductor material, an upper shield conductor, and a second shield dielectric separating the lower shield conductor from the upper shield conductor within the active area, the active trench extending laterally from the active area into the plurality of shield conductor contact areas within the region of semiconductor material, the lower shield conductor and the upper shield conductor being coupled together within the plurality of shield conductor contact areas. The method includes providing a shield contact within an upper shield contact area coupled to the upper shield conductor in the active trench.

[0084] In another example, providing an active trench includes providing a recessed contact area between a lower shield conductor and an upper shield conductor within a multi-shield conductor contact area. In yet another example, providing a region of semiconductor material includes providing a multi-shield conductor contact area in which there are no shield contacts in contact with the upper surface of the upper shield conductor.

[0085] In another example, the method includes providing a termination trench extending from the top surface into a second portion of a region of semiconductor material, the termination trench comprising a lower shielding conductor, a first shielding dielectric separating the lower shielding conductor from the region of semiconductor material, an upper shielding conductor, and a second shielding dielectric separating the lower shielding conductor from the upper shielding conductor within an active area, the termination trench extending laterally from the active area into a plurality of shielding conductor contact area within the region of semiconductor material, the lower and upper shielding conductors being coupled together within the plurality of shielding conductor contact area. In a further example, the method includes providing a second shielding contact outside the plurality of shielding conductor contact area coupled to the upper shielding conductor within the termination trench.

[0086] In another example, the method includes providing an active trench and a termination trench, providing a lower shield conductor within the active trench and the termination trench, providing a conductive material within the active trench and the termination trench above the lower shield conductor, removing a first portion of the conductive material within the active trench and the termination trench, providing a masking layer over the conductive material in the termination trench, and removing a second portion of the conductive material within the active trench to provide an upper shield conductor within the active trench.

[0087] In a further example, providing a masking layer includes providing a masking layer after removing the first portion. In another example, removing the first portion provides an upper shielding conductor within the termination trench.

[0088] In a further example, providing an active trench includes providing an active trench as an elongated active trench having a tip portion within a plurality of shield conductor contact areas; providing a first shield dielectric within the elongated active trench; providing a lower shield conductor on the first shield dielectric; providing a second shield dielectric on the lower shield conductor; and providing a masking layer having a negative photoresist and an opening, wherein the opening exposes the second shield dielectric in the first portion of the elongated active trench within the plurality of shield conductor contact areas, and the masking layer covers the second portion of the elongated active trench within the active area; removing the second shield dielectric from the elongated active trench within the plurality of shield conductor contact areas; and removing the masking layer, thereby leaving the second shield dielectric on the lower shield conductor within the active area.

[0089] In another example, providing an active trench includes providing an interlayer dielectric on top of an upper shield conductor, providing a gate dielectric along the upper sidewall of the active trench, and providing a gate electrode within the active trench.

[0090] In a further example, the method includes providing a gate contact coupled to a gate electrode, and providing an active trench includes providing a recessed contact region between a lower shield conductor and an upper shield conductor within a multi-shield conductor contact area, the gate contact being located within the multi-shield conductor contact area, and the gate contact overlapping the recessed contact region in a cross-sectional view.

[0091] In a further example, the method includes providing a shield silicide on top of the upper shield conductor.

[0092] In summary, structures and methods for semiconductor devices having improved manufacturability and performance have been described. In some examples, the structures include cell topography structures that facilitate electrical connections between multiple shield electrodes. Such structures can be provided, for example, at the tip of an active trench. In some examples, such structures can be provided at the end of a termination trench enclosing the tip of an active trench. In some examples, methods have been described to improve the manufacturability of the electrical connection structure between multiple shield electrodes and electrical connections to termination trenches, thereby improving the overall reliability of the semiconductor device. In addition, the methods and structures simplify the interconnection scheme between shield conductors, which saves layout space, simplifies cell topography, and reduces the impact on die size.

[0093] In some examples, a negative photoresist is used in part of the method to provide a masking layer that protects the portion of the structure in which the shield dielectric remains in place. In some examples, a two-step recess process is used to provide the upper shield conductor in both the active trench and the termination trench.

[0094] In this explanation, multiple lower shield conductors 21A may be referred to as lower shield conductors 21A, and multiple upper shield conductors 21B may be referred to as upper shield conductors 21B. However, in some examples, it is understood that the lower shield conductors 21A or upper shield conductors 21B can be a single continuous structure.

[0095] It will be understood that the different examples described herein may be combined with any of the other examples described herein to obtain different embodiments.

[0096] The subject matter of the present invention is described with specific preferred examples, but the aforementioned drawings and descriptions merely illustrate typical examples of the subject matter and should not be considered as limiting its scope. It will be obvious that many alternatives and modifications will be apparent to those skilled in the art. For example, the conductivity types in various regions can be reversed. Other IV-IV semiconductor materials other than SiC, such as SiGe or SiGeC, can be used. In addition, other compound semiconductor materials can be used. Furthermore, the structures and methods described herein can be used in high-voltage devices (e.g., above 100 volts) or low-voltage devices (e.g., below 30 volts).

[0097] As reflected in the claims below, aspects of the invention may have fewer features than all the features of a single example disclosed above. For this reason, the claims expressed below are explicitly incorporated herein, and each claim is independent of the others as a separate example of the invention. Furthermore, some examples described herein include some of the other features included in other examples, but not all of the other features, and as will be understood by those skilled in the art, combinations of features of different examples are within the scope of the invention and form different examples.

Claims

1. A method for manufacturing semiconductor devices, To provide a region of semiconductor material, wherein the region of semiconductor material is Top surface and The edge region adjacent to the top surface, Multiple shielded conductor contact areas, The active area adjacent to the top surface, To provide a device comprising an upper shield contact area adjacent to the top surface and located outside the plurality of shield conductor contact areas, To provide an active trench extending from the top surface into the region of the semiconductor material, The activated trench, Lower shield conductor and A first shield dielectric that isolates the lower shield conductor from the region of the semiconductor material, Upper shield conductor and, The system comprises a second shield dielectric that isolates the lower shield conductor from the upper shield conductor within the active area, The activated trench extends laterally from the activated area within the region of the semiconductor material into the plurality of shield conductor contact areas. The lower shield conductor and the upper shield conductor are coupled together in the multiple shield conductor contact area, to provide To provide a terminal trench extending from the top surface into a second portion of the region of the semiconductor material, The aforementioned terminal trench, The lower shield conductor and, The first shield dielectric isolates the lower shield conductor from the region of the semiconductor material, The upper shield conductor and, The system comprises a second shield dielectric that isolates the lower shield conductor from the upper shield conductor within the active area, The termination trench extends laterally from the active area to the plurality of shield conductor contact areas within the region of the semiconductor material. The lower shield conductor and the upper shield conductor are coupled together in the multiple shield conductor contact area, to provide A method comprising providing a shield contact in the upper shield contact area coupled to the upper shield conductor in the activated trench.

2. The invention further includes providing a second shield contact coupled to the upper shield conductor within the termination trench and located outside the plurality of shield conductor contact areas, To provide the activated trench and the terminal trench, To provide the lower shield conductor in the activated trench and the termination trench, To provide a conductive material in the activated trench and the termination trench above the lower shield conductor, Removing the first portion of the conductive material in the activated trench and the terminal trench, After removing the first portion, a masking layer is provided on the conductive material in the terminal trench. The method according to claim 1, comprising removing the second portion of the conductive material in the activated trench to provide the upper shield conductor in the activated trench.

3. To provide the aforementioned activated trench, To provide the active trench as an elongated active trench having its tip portion within the multiple shield conductor contact areas, To provide the first shielding dielectric within the elongated active trench, To provide the lower shielding conductor on the first shielding dielectric, To provide the second shield dielectric on the lower shield conductor, To provide a masking layer having a negative type photoresist and an aperture, The opening exposes the second shield dielectric within the first portion of the elongated active trench within the plurality of shield conductor contact areas. The masking layer provides that it covers the second portion of the elongated active trench within the active area. To remove the second shield dielectric from the elongated active trench within the multiple shield conductor contact area, The method according to claim 1, comprising removing the masking layer, thereby leaving the second shield dielectric on the lower shield conductor within the active area.

4. It is a semiconductor device, In the field of semiconductor materials, Top surface and Edge region and Multiple shielded conductor contact areas, Active area and A region of semiconductor material comprising an upper shield contact area located outside the plurality of shield conductor contact areas, An active trench extending from the top surface into the region of the semiconductor material, The activated trench, Lower shield conductor and A first shield dielectric that isolates the lower shield conductor from the region of the semiconductor material, Upper shield conductor and, The system comprises a second shield dielectric that isolates the lower shield conductor from the upper shield conductor within the active area, The activated trench extends laterally from the activated area within the region of the semiconductor material into the plurality of shield conductor contact areas. The lower shield conductor and the upper shield conductor are coupled together in the multiple shield conductor contact area, forming an activated trench. A semiconductor device comprising a shield contact in an upper shield contact area coupled to the upper shield conductor in the activated trench.

5. A terminal trench extending from the top surface into a second portion of the semiconductor material region, The system further comprises a second shield contact located outside the plurality of shield conductor contact areas, The aforementioned terminal trench, The lower shield conductor and, The first shield dielectric isolates the lower shield conductor from the region of the semiconductor material, The upper shield conductor and, The system comprises a second shield dielectric that isolates the lower shield conductor from the upper shield conductor within the active area, The termination trench extends laterally from the active area to the plurality of shield conductor contact areas within the region of the semiconductor material. The lower shield conductor and the upper shield conductor are coupled together in the multiple shield conductor contact area. The second shield contact is coupled to the upper shield conductor in the termination trench. The plurality of shield conductor contact areas are the edge regions, The semiconductor device according to claim 4, wherein no shield contacts are present in the plurality of shield conductor contact areas that contact the upper surface of the upper shield conductor.

Images