Semiconductor device and method for manufacturing the same

Abstract

The present invention provides semiconductor devices and methods for manufacturing the same. [Solution] The semiconductor element includes a support structure layer, a plurality of channel structures protruding in a fin shape on a first surface of the support structure layer and containing a semiconductor material, source-drain structures positioned at both ends of each of the plurality of channel structures on the first surface of the support structure layer, a plurality of gate structures positioned on the first surface of the support structure layer parallel to the first surface and spaced apart along a second direction different from the first direction, and positioned at different locations in the second direction to surround three faces of each of the plurality of channel structures, a back contact electrode connected to a part of the source-drain structure and exposed on a second surface of the support structure layer, and a sacrificial structure located inside the support structure layer and supporting the remaining part of the source-drain structure. The support structure layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer may be formed between the plurality of channel structures and the first dielectric layer with the same thickness as the sacrificial structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A transistor is a semiconductor device that serves as an electrical switch and is employed in various integrated circuit devices including memories, drive ICs (Integrated Circuits), and logic elements. In order to increase the integration degree of integrated circuit devices and improve the gate control power, a transistor having a three-dimensional structure in which a gate electrode surrounds three surfaces of a channel has been proposed.

[0003] Thus, in a semiconductor device in which transistors having a three-dimensional structure are integrated, the process of connecting the source-drain structure to the back wiring may cause an attack on the gate electrode or the channel. Therefore, a method for forming a back contact electrode while minimizing defects generated during the process has been sought.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device provided with a back contact electrode and a method for manufacturing the same.

Means for Solving the Problems

[0005] According to the embodiment, a support structure layer comprising a first dielectric layer and a second dielectric layer, having a first surface and a second surface facing each other; a plurality of channel structures comprising a semiconductor material, arranged spaced apart on the first surface of the support structure layer along a first direction parallel to the first surface, protruding in a fin shape along a direction away from the support structure layer; source drain structures arranged at both ends of each of the plurality of channel structures on the first surface of the support structure layer; and arranged spaced apart on the first surface of the support structure layer along a second direction parallel to the first surface and different from the first direction, at different positions in the second direction, the plurality of channel structures A semiconductor device is provided, comprising: a plurality of gate structures arranged to surround each of the three faces; a back contact electrode connected to a portion of the source-drain structure and penetrating the support structure layer to be exposed on a second surface of the support structure layer; a sacrificial structure located inside the support structure layer and supporting the remaining portion of the source-drain structure; wherein the first dielectric layer is disposed below the plurality of channel structures and at a distance from the plurality of channel structures, and the second dielectric layer is disposed between the plurality of channel structures and the first dielectric layer, the thickness of the second dielectric layer directly below the channel structures being the same as the thickness of the sacrificial structure.

[0006] The first dielectric layer and the second dielectric layer have different etching ratios. The first dielectric layer comprises a silicon oxide, and the second dielectric layer comprises a silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonate nitride.

[0007] The sacrificial structure comprises a material different from that of the first dielectric layer and the second dielectric layer. The aforementioned sacrificial structure includes SiGe.

[0008] The first dielectric layer includes a plurality of regions that are opposite to each of the plurality of channel structures and are spaced apart from each other.

[0009] Each of the plurality of regions of the first dielectric layer has a shape that extends from the second surface of the support structure layer into the interior of the support structure layer.

[0010] The support structure layer is disposed between each of the plurality of channel structures and the first dielectric layer and further includes a residual sacrificial pattern made of the same material as the sacrificial structure.

[0011] The thickness of the residual sacrificial pattern is the same as the thickness of the sacrificial structure. The residual sacrifice pattern is located opposite the region between the multiple gate structures.

[0012] Between each of the multiple regions of the first dielectric layer and each of the multiple channel structures, the regions of the second dielectric layer and the residual sacrificial pattern are alternately located along the second direction.

[0013] The second dielectric layer includes a first region extending from the second surface of the support structure layer toward the first surface with a predetermined thickness, and a plurality of second regions protruding from the first region toward the first surface, at a position that does not overlap with the channel structure when viewed from a third direction perpendicular to the first surface of the support structure layer.

[0014] Each of the aforementioned multiple second regions faces each of the aforementioned multiple gate structures. Among the plurality of second regions and the plurality of gate structures, the second regions and gate structures at positions facing each other have a continuous side profile.

[0015] The support structure layer further includes a third dielectric layer disposed between the plurality of second regions and containing the same material as the first dielectric layer.

[0016] The support structure layer further includes a fourth dielectric layer conformally formed between the second dielectric layer and the third dielectric layer, in accordance with the shape of the second dielectric layer.

[0017] The fourth dielectric layer is formed to extend from the side surface of the second region along the side surface of the gate structure. The fourth dielectric layer contains the same material as the second dielectric layer.

[0018] According to the embodiment, the system includes a semiconductor element and a controller for controlling the semiconductor element, wherein the semiconductor element is A support structure layer comprising a first dielectric layer and a second dielectric layer, having a first surface and a second surface facing each other; a plurality of channel structures comprising semiconductor material, arranged spaced apart on the first surface of the support structure layer along a first direction parallel to the first surface, protruding in a fin shape along a direction away from the support structure layer; source drain structures arranged at both ends of each of the plurality of channel structures on the first surface of the support structure layer; and arranged spaced apart on the first surface of the support structure layer along a second direction parallel to the first surface and different from the first direction, with each of the plurality of channel structures having three fin-shaped fins at different positions in the second direction. An electronic device is provided, comprising: a plurality of gate structures arranged to surround one face; a back contact electrode connected to a portion of the source-drain structure and penetrating the support structure layer to be exposed on a second face of the support structure layer; a sacrificial structure located inside the support structure layer and supporting the remaining portion of the source-drain structure; wherein the first dielectric layer is disposed below the plurality of channel structures and spaced apart from them, and the second dielectric layer is disposed between the plurality of channel structures and the first dielectric layer, the thickness of the second dielectric layer directly below the channel structures being the same as the thickness of the sacrificial structure.

[0019] According to an embodiment, a step of forming a plurality of three-dimensional structures including a first silicon layer, a sacrificial material layer, and a second silicon layer on a bulk silicon layer and arranged along a first direction; a step of forming an isolation layer between the plurality of three-dimensional structures on the bulk silicon layer; a step of forming a plurality of dummy gates that intersect the plurality of three-dimensional structures and are arranged along a second direction different from the first direction on the plurality of three-dimensional structures; a step of patterning the isolation layer using a hard mask used when forming the plurality of dummy gates; a step of forming a support structure layer composed of a plurality of types of dielectric layers having different etching selectivity ratios on the patterned isolation layer, and then forming a plurality of source-drain structures that contact both ends of the second silicon layer of each of the plurality of three-dimensional structures and contact the upper surface of the sacrificial material layer; a step of removing the bulk silicon layer and the isolation layer to expose a partial region of the sacrificial material layer; a step of removing the exposed sacrificial material layer of the sacrificial material layer to form a sacrificial structure in contact with the source-drain structure; and a step of forming a back contact electrode that is connected to any one of the plurality of source-drain structures and is exposed on the back surface of the support structure layer are provided, and a method for manufacturing a semiconductor device is provided.

Brief Description of the Drawings

[0020] [Figure 1] It is a perspective view showing a schematic structure of a semiconductor device according to an embodiment. [Figure 2A] It is a plan view of the semiconductor device of FIG. 1. [Figure 2B] It is a cross-sectional view taken along line BB of FIG. 2A. [Figure 2C] It is a cross-sectional view taken along line CC of FIG. 2A. [Figure 2D] It is a cross-sectional view taken along line DD of FIG. 2A. [Figure 2E] It is a cross-sectional view taken along line EE of FIG. 2A. [Figure 3] It is a perspective view showing a schematic structure of a semiconductor device according to another embodiment. [Figure 4A]It is a cross-sectional view taken along line AA of FIG. 3. [Figure 4B] It is a cross-sectional view taken along line BB of FIG. 3. [Figure 5] It is a flowchart schematically explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 7A] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 7B] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 7C] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 8A] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 8B] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 8C] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 9A] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 9B] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 9C] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 10A] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 10B] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 10C] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 11A] It is a diagram for explaining in detail an exemplary manufacturing method of a semiconductor device according to an embodiment. [Figure 11B]This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 11C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 12A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 12B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 12C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 13A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 13B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 13C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 14A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 14B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 14C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 15A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 15B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 15C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 16A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 16B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 16C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 17A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 17B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 17C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 18A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 18B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 18C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 19A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 19B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 19C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 20A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 20B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 20C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 21A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 21B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 21C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 22A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 22B]This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 22C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 22D] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 22E] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 23A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 23B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 23C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 23D] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 24A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 24B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 24C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 24D] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 25A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 25B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 25C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 25D] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 26A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 26B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 26C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 26D] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 27] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 28A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 28B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 28C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 29A] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 29B] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 29C] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 29D] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 29E] This figure illustrates in detail an exemplary manufacturing method for a semiconductor device according to the embodiment. [Figure 30] This is a schematic block diagram of a display driver integrated circuit (Display Driver IC: DDI) and a display device equipped with a DDI according to an embodiment. [Figure 31] This is a circuit diagram of a CMOS inverter according to the embodiment. [Figure 32] This is a circuit diagram of a CMOS SRAM element according to the embodiment. [Figure 33] This is a circuit diagram of a CMOS NAND circuit according to the embodiment. [Figure 34]This is a block diagram of an electronic device according to an embodiment. [Figure 35] This is a block diagram of an electronic device according to an embodiment. [Modes for carrying out the invention]

[0021] The embodiments will now be described in detail with reference to the attached drawings. The embodiments described are merely illustrative, and various modifications are possible from these embodiments. In the following drawings, similar reference numerals refer to similar components, and the sizes of each component in the drawings may be exaggerated for clarity and convenience of explanation.

[0022] In the following, "upper" or "above" refers not only to items that are in contact and directly above, but also to items that are not in contact and are located above.

[0023] The terms "1st," "2nd," etc., may be used to describe various components, but are used solely for the purpose of distinguishing one component from others. These terms do not limit the components to differences in material or structure.

[0024] A singular expression includes multiple expressions unless the context clearly indicates otherwise. Furthermore, when a part "contains" a component, this means, unless otherwise specified, that it can contain other components, rather than excluding them.

[0025] Furthermore, terms such as "~part" and "~module" used in the specification refer to a unit that processes at least one function or operation, which may be implemented in hardware or software, or through a combination of hardware and software.

[0026] The use of the term "the aforementioned" and similar demonstrative terms applies to both singular and plural nouns.

[0027] The steps constituting the method may be performed in any order unless explicitly stated otherwise. Furthermore, the use of all exemplary terms (e.g., etc.) is solely for the purpose of detailing the technical idea, and the scope of the invention is not limited by these terms unless limited by the claims.

[0028] Figure 1 is a perspective view showing the schematic structure of a semiconductor device according to an embodiment, Figure 2A is a plan view of the semiconductor device of Figure 1, and Figures 2B, 2C, and 2D are cross-sectional views of Figure 2A, specifically BB, CC, and DD, respectively.

[0029] The semiconductor device 10 includes a support structure layer SP, and a plurality of channel structures CH and a plurality of gate electrodes GA disposed on the support structure layer SP. Source-drain structures SD are disposed at both ends of the channel structures CH. A gate insulating layer GI is disposed between the channel structures CH and the gate electrodes GA. A dielectric layer DL may be formed on the support structure layer SP, covering the plurality of channel structures CH and the plurality of gate electrodes GA overall. The dielectric layer DL may contain one or more dielectric materials.

[0030] The semiconductor element 10 is a fin-FET (field-effect transistor) element. Multiple channel structures CH are arranged spaced apart along a first direction (Y direction) on the first surface SPa of the support structure layer SP, and multiple gate electrodes GA are arranged spaced apart along a second direction (X direction). The multiple gate electrodes GA can surround three faces of each channel structure CH at multiple positions in the second direction. The number of channel structures CH and gate electrodes GA shown is illustrative. For example, a transistor channel can be defined depending on the number of intersections between the channel structures CH and gate electrodes GA. In Figure 1, the detailed structure of the support structure layer SP and the gate insulating layer GI are omitted for convenience.

[0031] As shown in Figures 2B and 2C, a portion of the source-drain structure SD is connected to the back contact electrode BCE exposed on the lower surface of the support structure layer SP, i.e., the second surface SPb, and a sacrificial structure PH may be placed in the lower part of the source-drain structure SD that is not connected to the back contact electrode BCE. The sacrificial structure PH may contain, for example, SiGe. The drawings show an example in which one source-drain structure SD is connected to the back contact electrode BCE, but this is illustrative and not limited to this. The number and position of source-drain structures SD connected to the back contact electrode BCE can be selected in various ways.

[0032] The sacrificial structure PH is a pattern formed by a sacrificial material layer used in the process of forming the channel structure CH and the source-drain structure SD. The sacrificial material layer may be formed to provide overall support to the underside of the channel structure CH and the source-drain structure SD. Subsequently, a portion of the sacrificial material layer is removed, but the sacrificial material layer remains unetched under all of the source-drain structure SD and can be patterned to form the sacrificial structure PH. Next, the sacrificial structure PH located under the source-drain structure SD that is directly connected to the back-facing contact electrode BCE may be selectively removed, after which the back-facing contact electrode BCE that directly contacts the source-drain structure SD can be formed. Such exemplary manufacturing methods are described in detail in Figure 6 and subsequent figures.

[0033] The support structure layer SP has a first surface SPa and a second surface SPb. The support structure layer SP can include multiple types of dielectric materials. The support structure layer SP includes, for example, a first dielectric layer DI1 and a second dielectric layer DI2. The first dielectric layer DI1 contains silicon oxide, and the second dielectric layer DI2 contains silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonate. The second dielectric layer DI2 includes, for example, SiN, SiON, SiCN, or SiOCN. The first dielectric layer DI1 and the second dielectric layer DI2 may be materials having different etching ratios. The second dielectric layer DI2 may be a material having a lower etching ratio than the first dielectric layer DI1.

[0034] As shown in Figures 2C and 2D, the first dielectric layer DI1 can form a pattern extending from the second surface SPb, which is the lower surface of the support structure layer SP, toward the interior of the support structure layer SP. The width of the pattern formed by the first dielectric layer DI1 may narrow in the first direction (Y direction) depending on the change in depth from the lower surface of the support structure layer SP toward the interior. However, this is illustrative and not limited to this. The pattern formed by the first dielectric layer DI1 may have multiple ends da facing each of the multiple channel structures CH at the same depth position within the support structure layer SP.

[0035] The second dielectric layer DI2 is positioned between the edge da and the channel structure CH. The second dielectric layer DI2 may be formed to extend from the edge da of the pattern formed by the first dielectric layer DI1 to the first surface SPa, and further extend in the direction in which the multiple gate electrodes GA separate, i.e., the second direction (X direction), and along the second surface SPb of the support structure layer SP. The second dielectric layer DI2 can occupy most of the region within the support structure layer SP excluding the first dielectric layer DI1.

[0036] The distance between the edge da of the pattern formed by the first dielectric layer DI1 and the channel structure CH, i.e., the thickness of the second dielectric layer DI2 located directly beneath the channel structure CH, may be the same as the thickness of the sacrificial structure PH.

[0037] Figure 2E shows a cross-sectional view of EE at a position that does not penetrate the channel structure CH. The region of the second dielectric layer DI2 includes a first region DI2a that extends with a predetermined thickness from the second surface SPb, which is the lower surface of the support structure layer SP, toward the first surface SPa, which is the upper surface, and a plurality of second regions DI2b that protrude from this thickness position toward the second surface SPb. The plurality of second regions DI2b face a plurality of gate electrodes GA in a one-to-one correspondence. The side profile profile PRD of the second region DI2b may be the same as the side profile profile PRG of the gate structure GS. Here, the gate structure GS refers to a structure that includes the gate electrode GA and the gate insulating layer GI. It is not limited to the second region DI2b and the gate structure GS having the same width. The side profile profile PRD of the second region DI2b and the side profile profile PRG of the gate structure GS are due to a dummy gate process that precedes the formation of the gate structure GS. For example, when a hard mask used to form a dummy gate is used to pattern the material at the location of the second region DI2b, the finished device may have a continuous shape between the side profile PRG of the gate structure GS and the side profile PRD formed by the second region DI2b of the second dielectric layer DI2. An example of a manufacturing method related to this will be described in Figure 6 and subsequent figures.

[0038] A third dielectric layer DI3 may be placed on both sides of the second region DI2b. The third dielectric layer DI3 contains a different material from the first dielectric layer DI1 and the second dielectric layer DI2. Alternatively, the third dielectric layer DI3 may contain the same material as the first dielectric layer DI1.

[0039] Figure 3 is a perspective view showing a schematic structure of a semiconductor device according to another embodiment, and Figures 4A and 4B are cross-sectional views AA and BB of Figure 3, respectively.

[0040] The semiconductor element 100 is a fin-FET (field effect transistor) element similar to the semiconductor element 10 described in Figures 1 to 2E, and includes a support structure layer 110 and a plurality of channel structures 130 and a plurality of gate electrodes 150 arranged on the support structure layer 110. Source-drain structures 180 are arranged at both ends of the channel structure 130. A gate insulating layer 125 is arranged between the channel structure 130 and the gate electrodes 150.

[0041] The support structure layer 110 contains multiple types of dielectric materials and further has a first surface 110a which is the upper surface and a second surface 110b which is the back surface.

[0042] Multiple channel structures 130 are formed on the first surface 110a, protruding away from the support structure layer 110 and spaced apart along a first direction (Y direction) parallel to the first surface 110a.

[0043] On the first surface 110a of the support structure layer 110, source drain structures 180 are formed at both ends of each of the multiple channel structures 130. In the drawing, only the source drain structures 180 located at one end of each of the multiple channel structures 130 are shown.

[0044] Multiple gate electrodes 150 are arranged on the first surface 110a of the support structure layer 110, spaced apart along a second direction (X direction) that is parallel to the first surface 110a and different from the first direction, and are formed to surround three faces of each of the multiple channel structures 130 at different positions in the second direction.

[0045] A portion of the source-drain structure 180 penetrates the support structure layer 110 and is connected to a back-facing contact electrode 190 that is exposed on the second surface 110b, which is the back surface of the support structure layer 110. The remaining portion of the source-drain structure 180, i.e., the portion not connected to the back-facing contact electrode 190, is connected to a sacrificial structure 170 located within the support structure layer 110.

[0046] The support structure layer 110 contains multiple types of dielectric materials with different etching ratios, and includes dielectric layers 127 and 146 with different etching ratios. Dielectric layer 127 may contain silicon oxide, while dielectric layer 146 may contain silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonate nitride.

[0047] The dielectric layer 127 includes multiple regions that face each of the multiple channel structures 130 and are spaced apart from one another. Similar to the arrangement direction of the multiple channel structures 130, the arrangement direction of the multiple regions of the dielectric layer 127 is the first direction (Y direction). Each of the multiple regions of the first dielectric layer 127 has a shape that extends from the second surface 110b of the support structure layer 110 toward the interior of the support structure layer 110. The shape of the dielectric layer 127 shown is illustrative and not limited thereto.

[0048] The dielectric layer 146 is positioned between the dielectric layer 127 and the channel structure 130, and the thickness td of the second dielectric layer 146 directly beneath the channel structure 130 may be the same as the thickness tp of the sacrificial structure. The thickness of the sacrificial structure 170 may not be constant because a portion of the sacrificial structure 170 is etched during the process of forming the source-drain structure 180. In this case, the thickness of the thickest part of the sacrificial structure 170 can be defined as tp. In other words, the thickness td of the dielectric layer 146 directly beneath the channel structure 130 is less than or equal to the thickness tp of the sacrificial structure, and is substantially almost the same.

[0049] The support structure layer 110 may further include a dielectric layer 123 located on top of the dielectric layer 146. The dielectric layer 123 contains the same material as the dielectric layer 127.

[0050] A dielectric layer 142 may be further formed between dielectric layer 146 and dielectric layer 123. Dielectric layer 142 may be formed conformally to the shape of dielectric layer 146. Dielectric layer 146 is formed to extend perpendicular to the first surface 110a of the support structure layer 110 and along the side surface of the gate structure GS. The gate structure GS refers to a structure including a gate electrode 150 and a gate insulating layer 125. Dielectric layer 142 may contain the same material as dielectric layer 146.

[0051] A dielectric layer 143 may be further formed on the first surface 110a of the support structure layer 110, and may have a shape that surrounds the source-drain structure 180. The dielectric layer 143 is formed to extend along the side surface of the gate structure GS. A dielectric layer 124 may be formed on the remaining region of the support structure layer 110. The dielectric layer 124 contains, but is not limited to, the same material as dielectric layers 127 and 123.

[0052] The above-mentioned configuration of the semiconductor element 100 is presented as a result of the detailed manufacturing process that forms the back contact electrode 190 which is in direct contact with the source-drain structure 180. Therefore, a more detailed explanation of the structure will be given later, along with a description of the manufacturing method.

[0053] Figure 5 is a flowchart illustrating the manufacturing method of a semiconductor device according to the embodiment.

[0054] First, multiple three-dimensional structures are formed, including a sacrificial material layer and a channel structure (S310).

[0055] The three-dimensional structure includes a first semiconductor layer, a sacrificial layer, and a second semiconductor layer, the first and second semiconductor layers containing silicon. The three-dimensional structure can be formed on bulk silicon.

[0056] Next, an isolation layer is formed between multiple three-dimensional structures (S320). Next, multiple dummy gates intersect with multiple three-dimensional structures (S330).

[0057] The isolation layer is patterned using the hard mask used to form the dummy gate (S340).

[0058] Next, multiple types of dielectric layers are formed on the isolation layer to form a source-drain structure (S350).

[0059] Multiple types of dielectric layers can include two or more dielectrics with different etching ratios, and these multiple types of dielectric layers formed in this way function as support structure layers for removing the isolation layer in a subsequent process. The source-drain structure is formed in contact with both ends of the second semiconductor layer provided on each of the multiple three-dimensional structures, and also in contact with the sacrificial material layer.

[0060] Next, the isolation layer is removed to expose a portion of the sacrificial material layer (S360). Next, the exposed sacrificial material layer is removed (S370). The remaining sacrificial material layer functions as a sacrificial structure supporting the source-drain structure.

[0061] Next, a back contact electrode is formed that is connected to the source-drain structure and exposed on the back surface of the support structure layer (S380). To form the back contact electrode, a mask is used to open the source-drain structure connected to the back contact electrode, and a portion of the sacrificial material layer and the dielectric layer on the sacrificial material layer that are in contact with the source-drain structure are removed.

[0062] Figures 6 to 29E illustrate in detail an exemplary manufacturing method of a semiconductor device according to the embodiment.

[0063] Referring to Figure 6, a structure is provided that includes a first semiconductor layer 131, a sacrificial material layer 172, and a second semiconductor layer 132. The sacrificial material layer 172 and the second semiconductor layer 132 are sequentially stacked on the first semiconductor layer 131. After forming the sacrificial material layer 172 on the first semiconductor layer 131, the second semiconductor layer 132 is formed on the sacrificial material layer 172. The first semiconductor layer 131, the sacrificial material layer 172, and the second semiconductor layer 132 can be formed according to a general semiconductor growth method.

[0064] The first semiconductor layer 131 and the second semiconductor layer 132 contain silicon, or germanium (Ge), or a compound semiconductor. The first semiconductor layer 131 and the second semiconductor layer 132 may further contain a P-type or N-type dopant. The first semiconductor layer 131 and the second semiconductor layer 132 may, but are not limited to, contain the same semiconductor material. The sacrificial material layer 172 contains SiGe.

[0065] Referring to Figure 7A, a structure is provided in which a second semiconductor layer 132 is patterned and multiple channel structures 130 are formed. Figures 7B and 7C show the BB and CC cross-sectional views of Figure 7A, respectively.

[0066] In the structure shown in Figure 6, first, the second semiconductor layer 132 is patterned to form multiple channel structures 130. Although two channel structures 130 are shown, these are illustrative examples, and multiple channel structures may be formed along the first direction (Y direction). When forming the channel structures 130, the sacrificial material layer 172 and the first semiconductor layer 131 are simultaneously patterned according to the pattern corresponding to the channel structures 130. The etching depth of the sacrificial material layer 172 corresponds to the thickness of the sacrificial material layer 172, while the first semiconductor layer 131 is etched to a predetermined depth that is shallower than that. The portion of the first semiconductor layer 131 that has a shape corresponding to the channel structures 130 is shown as the first semiconductor layer 131a. Next, an isolation layer 121 is formed on the etched region of the first semiconductor layer 131. That is, the isolation layer 121 is formed in the region between the first semiconductor layer 131a of the pattern corresponding to the channel structures 130. The thickness of the isolation layer 121 can be set to such an extent that the sacrificial material layer 172 is not exposed. The height of the upper surface of the isolation layer 121, i.e., the position in the third direction (Z direction), which is the stacking direction, may be the same as the height of the sacrificial material layer 172, or it may be set higher. The height of the upper surface of the isolation layer 121 shown in the drawings is illustrative and not limited to the shown height. The isolation layer 121 contains a dielectric material, such as silicon oxide.

[0067] The thickness td of the sacrificial material layer 172 is not limited to the thickness shown. The thickness of the sacrificial material layer 172 may be smaller than the thickness of the channel structure 130, for example, as shown, but is not limited to this, and may also be larger than the thickness of the channel structure 130.

[0068] Referring to Figure 8A, the structure in which the dummy gate 152 is formed is shown. Figures 8B and 8C are cross-sectional views of BB and CC of Figure 8A, respectively.

[0069] First, a dielectric layer 122 is formed surrounding three sides of the channel structure 130. The dielectric layer 122 may be formed conformally to the shape of the channel structure 130. The dielectric layer 122 contains a dielectric material, for example, the same dielectric material as that which constitutes the isolation layer 121. Next, a dummy material layer for forming a dummy gate 152 is formed to cover the entire channel structure 130 surrounded by the dielectric layer 122, and then patterned in a predetermined pattern to form the dummy gate 152. The dummy material layer may contain, for example, a polysilicon (Poly-Si) material. The dielectric layer 141 is a hard mask used when patterning the dummy material layer. The dielectric layer 141 may contain, for example, silicon nitride. The material of the dielectric layer 141 is not limited to this and may also contain SiN, SiOCN, SiN, or SiCN. The material of the dielectric layer 141 may have a different etching ratio than the material that constitutes the isolation layer 121, and may even have a lower etching ratio. Although two dummy gates 152 are shown, these are illustrative examples, and multiple gates may be formed along the second direction (X direction).

[0070] Referring to Figure 9A, the structure after further etching of the isolation layer 121 is shown. Figures 9B and 9C are cross-sectional views of BB and CC of Figure 9A, respectively.

[0071] For etching the isolation layer 121, the dielectric layer 141, which was used as a hard mask when patterning the dummy gate 152, may be used as an etching mask. This may create a protruding shape in the isolation layer 121 having a side profile PRD that is continuous with the side profile PRG of the dummy gate 152. The depth to which the isolation layer 121 is etched is such that the sacrificial material layer 172 is entirely exposed. In the process of etching the isolation layer 121, the dielectric layer 122 surrounding the channel structure 130 may also be etched simultaneously. The dummy gate 152 is protected in the etching process by the dielectric layer 141, which contains a material with a lower etching ratio than the isolation layer 121, and furthermore, the dielectric layer 122 between the dummy gate 152 and the channel structure 130 remains intact.

[0072] Referring to Figure 10A, a structure is shown in which an isolation layer 121 and a dielectric layer 142 are further formed on the structure exposed on the isolation layer 121. Figures 10B and 10C are cross-sectional views of BB and CC of Figure 10A, respectively.

[0073] The dielectric layer 142 can be formed conformally on the structure formed as shown in Figure 9A. The dielectric layer 142 contains a material having a lower etching ratio than the isolation layer 121. The dielectric layer 142 contains the same material as the dielectric layer 141, but is not limited to this. Such a dielectric layer 142 can serve as an etching stop layer in subsequent processes.

[0074] Referring to Figure 11A, a structure is shown in which a dielectric layer 123 is further formed on the structure formed as in Figure 10A. Figures 11B and 11C are cross-sectional views of BB and CC of Figure 11A, respectively.

[0075] The dielectric layer 123 can flatly cover the entire structure of Figure 10A. The dielectric layer 123 contains a dielectric material similar to that of the isolation layer 121, for example, silicon oxide, but is not limited to this.

[0076] Referring to Figure 12A, a structure is shown in which the dielectric layer 123 has been etched to a predetermined depth. Figures 12B and 12C are cross-sectional views of BB and CC of Figure 12A, respectively.

[0077] The upper surface of the dielectric layer 123 may be at a height greater than or equal to the upper surface of the sacrificial material layer 172. In other words, in the structure of Figure 11A, the etching depth of the dielectric layer 123 is determined such that the height of the upper surface of the dielectric layer 123 is greater than or equal to the height of the sacrificial material layer 172. The height of the upper surface of the dielectric layer 123 may be the same as, for example, the height of the isolation layer 121 in Figure 7A. However, it is not limited to this.

[0078] Referring to Figure 13A, a structure is shown in which the dielectric layer 143 is formed on the upper surface of the dielectric layer 123 and on the surface of the dielectric layer 142. Figures 13B and 13C are cross-sectional views of Figure 13A, BB and CC, respectively.

[0079] The dielectric layer 143 may be conformally formed along the upper surface of the dielectric layer 123 and the surface of the dielectric layer 142. The dielectric layer 143 contains SiOCN. The dielectric layer 143 is not limited to this and may also contain SiN, SiCN, or SiCN. The dielectric layer 143 may contain the same material as the dielectric layer 142 or a different material.

[0080] Referring to Figure 14A, the structure of the channel structure 130 with its end etched is shown. Figures 14B and 14C are cross-sectional views BB and CC of Figure 14A, respectively.

[0081] The ends of the channel structure 130 on the sacrificial material layer 172 are etched to form a retraction hole SDH for forming a source-drain structure. In the process of etching the ends of the channel structure 130 located on the sacrificial material layer 172, the sacrificial material layer 172 may also be partially etched. The partially etched form of the sacrificial material layer 172 shown in Figure 14C is illustrative and not limited thereto. This representation is omitted for convenience in the following drawings.

[0082] Referring to Figure 15A, a structure is shown in which a source drain structure 180 is formed by connecting to the end of a channel structure 130. Figures 14B and 14C are cross-sectional views BB and CC of Figure 14A, respectively.

[0083] The source-drain structure 180 is grown from the channel structure 130, supported by a sacrificial material layer 172, and can fill the retraction hole SDH shown in Figure 14C. The source-drain structure 180 contains a semiconductor material and contains a P-type or N-type dopant. The source-drain structure 180 is formed by, for example, metal-organic chemical vapor deposition (MOCVD) method, but is not limited thereto.

[0084] Referring to Figure 16A, a dielectric layer 143 is further formed on the structure of Figure 15A, and the structure is planarized by the dielectric layer 124. Figures 16B and 16C are cross-sectional views of BB and CC of Figure 16A.

[0085] The dielectric layer 143 is conformally formed along the surface of the structure in Figure 15A, followed by the dielectric layer 124 filling the remaining space. The dielectric layer 124 contains the same material as the isolation layer 121, dielectric layer 122, and dielectric layer 123. The dielectric layer 121 contains, but is not limited to, silicon oxide. The planarization process is carried out until the dummy gate 152 is exposed on the upper surface.

[0086] Referring to Figure 17A, the dummy gate 152 is removed, providing a structure with a gate hole GH for gate electrode formation. Figures 17B and 17C are cross-sectional views of BB and CC of Figure 17A, respectively.

[0087] The dielectric layer 122 surrounding three sides of the channel structure 130 is shown as remaining, but it may be removed or thinned. The dielectric layer 122 remaining on the channel structure 130 functions as part of the gate insulating layer.

[0088] Referring to Figure 18A, a structure in which the gate electrode 150 is formed is provided. Figures 18B and 18C are cross-sectional views of Figure 18A, BB and CC, respectively.

[0089] Before forming the gate electrode 150, a gate insulating layer 125 is first applied along the inner wall of the gate hole GH, and then the gate electrode 150 is formed. The gate insulating layer 125 contains, for example, HfO2. However, it is not limited to this, and the gate insulating layer 125 may contain silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), titanium oxide (TiO2), or zirconium oxide (ZrO2). The remaining dielectric layer 122, together with the gate insulating layer 122, serves as a gate insulating film. The gate electrode 150 contains a conductive material, for example, a metal, metal nitride, metal carbide, or polysilicon. The gate electrode 150 contains, for example, TiN, TiAlC, or TiAlN. The gate insulating layer 125 and the gate electrode 150 are formed, for example, by the Atomic Layer Deposition (ALD) method. However, they may also be formed by methods such as Chemical Vapor Deposition (CVD) or sputtering.

[0090] Referring to Figure 19A, in the structure of Figure 18A, a portion of the upper part of the gate electrode 150 and the adjacent gate insulating layer 125 and dielectric layer 142 are removed, and a structure is provided in which the dielectric layer 145 fills this position. Figures 19B and 19C are cross-sectional views of Figure 19A, BB and CC, respectively.

[0091] In this process, the step of filling the dielectric layer 145 may be omitted. In other words, this process may be terminated as a step of reducing the height of the gate electrode 150.

[0092] Referring to Figure 20A, a back-side-up structure of the structure in Figure 19A is provided for the back-side process. This process, although not shown, may be performed after bonding the structure in Figure 19A to the carrier wafer. Figures 20B and 20C are cross-sectional views of Figure 20A, specifically BB and CC.

[0093] Referring to Figure 21A, a structure is provided in which most of the first semiconductor layer 131 is etched, as in the structure of Figure 20A. Figures 21B and 21C are cross-sectional views BB and CC of Figure 21A.

[0094] The etching process of the first semiconductor layer 131 is carried out until the isolation layer 121 is exposed. That is, the bulk semiconductor portion of the first semiconductor layer 121 is entirely etched away, leaving only the first semiconductor layer 131a, which is patterned in the same pattern as the channel structure 130.

[0095] Referring to Figure 22A, a structure in which the isolation layer 121 has been removed is provided. Figures 22B, 22C, and 22D are cross-sectional views BB, CC, and DD of Figure 22A, respectively. Figure 22E is a plan cross-sectional view showing the bottom surface of the first semiconductor layer 131a in Figure 22A, and the illustration of the first semiconductor layer 131a is omitted.

[0096] Referring also to Figure 21A, in Figure 22A, the isolation layer 121 is selectively removed from the structure in Figure 21A, which can then form etching holes EH for etching the sacrificial material layer 172 in the next step. A dielectric layer 142 having a lower etching ratio than the isolation layer 121 can act as an etching stop layer in this step.

[0097] Referring to Figure 22E, the region of the sacrificial material layer 172 includes both portions exposed to the etching hole EH and portions that are not exposed. The portion shown by the dashed ellipse represents the region of the sacrificial material layer 172 exposed to the etching hole EH.

[0098] Referring to Figure 23A, the etching process provides a structure in which the sacrificial material layer 172 exposed in the etching hole EH has been removed. Figures 23B, 23C, and 23D are cross-sectional views of Figure 23A, BB, CC, and DD, respectively.

[0099] In Figure 23B, the location where a portion of the material constituting the sacrificial layer 172 has been removed is shown as space H1. Space H1 is the location opposite the channel. The channel can be defined as the region of the channel structure 130 at the location where the channel structure 130 and the gate electrode 150 intersect. However, the width of space H1 is not limited to being the same as the channel width defined above. Hereafter, the portion of the sacrificial layer 172 located on the source-drain structure 180 will be referred to as the sacrificial structure 170, and the remaining portion will be referred to as the residual sacrificial pattern 173.

[0100] Referring to Figure 23B, the residual sacrificial pattern 173 is repeatedly formed alternately with space H1 along the second direction (X direction). The width of the illustrated residual sacrificial pattern H1 is an example and is not limited thereto. Depending on the spacing of the multiple gate electrodes 150 arranged along the second direction (X direction), the width of the residual sacrificial pattern H1 may be smaller, and in some cases, the residual sacrificial pattern H1 may be almost nonexistent.

[0101] Referring to Figure 24A, a structure is provided in which the structure of Figure 23A is covered by a dielectric layer 146. Figures 24B, 24C, and 24D are cross-sectional views of Figure 24A, BB, CC, and DD, respectively.

[0102] The height at which the dielectric layer 146 is formed is such that the upper surface of the first semiconductor layer 131a is exposed. For example, after the dielectric layer 146 is formed to a thickness that completely covers the first semiconductor layer 131a, a planarization process is performed so that the upper surface of the first semiconductor layer 131a is exposed. The dielectric layer 146 may be made of the same material as the dielectric layer 142.

[0103] Referring to Figure 25A, a structure is provided in which the first semiconductor layer 131a is removed and space H2 is formed, in the structure of Figure 24A.

[0104] The first semiconductor layer 131a has a different etching selectivity ratio than the dielectric layer 146 and the sacrificial structure 170, meaning that only the first semiconductor layer 131a can be selectively etched.

[0105] Referring to Figure 26A, a structure is provided in which the space H2 in Figure 25A is filled with a dielectric layer 127. Figures 26B, 26C, and 26D are cross-sectional views of Figure 26A, BB, CC, and DD, respectively.

[0106] After forming the dielectric layer 127 so as to fill the space H2 in Figure 25A and cover the upper surface of the dielectric layer 146, a planarization process is carried out until the dielectric layer 146 is exposed. The dielectric layer 127 may be made of the same material as the dielectric layers 123 and 124.

[0107] Referring to Figure 27, a structure is provided in which a mask 160 for forming a back contact electrode is placed on the structure of Figure 26A.

[0108] The mask 160 has a shape that exposes the dielectric layer 127 at a position corresponding to the source-drain structure 180 connected to the back contact electrode. By etching using the mask 160, the dielectric layer 127 and the sacrificial structure 170 on the source-drain structure 180 connected to the back contact electrode can be etched.

[0109] Referring to Figure 28A, a structure is provided in which a space H3 is formed that exposes the source drain structure 180 connected to the back contact electrode. Figures 28B, 28C, and 28D are cross-sectional views BB, CC, and DD of Figure 28A, respectively.

[0110] In the etching process that forms space H3, the sacrificial structure 170 on the source-drain structure 180 connected to the back contact electrode is completely removed, and the source-drain structure 180 may also be partially etched.

[0111] Referring to Figure 29A, a semiconductor element 100 is provided having a structure comprising a source-drain structure 180 and a back-facing contact electrode 190 connected thereto. Figures 29B, 29C, 29D, and 29E are cross-sectional views of Figure 29A, specifically BB, CC, DD, and EE, respectively.

[0112] The detailed configuration of the semiconductor device 100 manufactured based on the above description is as follows, with reference to Figures 29A to 29E.

[0113] The support structure layer 110 contains multiple types of dielectric materials and further has a first surface 110a and a second surface 110b. Figure 29A is shown for convenience with the back contact electrode 190 of the semiconductor element 100 visible on the upper side, with the first surface 110a referred to as the top surface and the second surface 110b as the back surface.

[0114] Multiple channel structures 130 are formed on the first surface 110a, protruding away from the support structure layer 110 and spaced apart along a first direction (Y direction) parallel to the first surface 110a.

[0115] On the first surface 110a of the support structure layer 110, source drain structures 180 are formed at both ends of each of the multiple channel structures 130. In the drawing, only the source drain structures 180 located at one end of each of the multiple channel structures 130 are shown.

[0116] Multiple gate electrodes 150 are arranged on the first surface 110a of the support structure layer 110, spaced apart along a second direction (X direction) parallel to the first surface 110a and different from the first direction, and are formed to surround three sides of each of the multiple channel structures 130 at different positions in the second direction. A gate insulating layer 125 is located between the channel structure 130 and the gate electrodes 150, and the structure of the gate electrodes 150 and the gate insulating layer 125 combined is called the gate structure GS.

[0117] A portion of the source drain structure 180 penetrates the support structure layer 110 and is connected to a back contact electrode 190 that is exposed on the second surface 110b, which is the back surface of the support structure layer 110.

[0118] The remaining portion of the source drain structure 180, i.e., the portion not connected to the back contact electrode 190, is connected to the sacrificial structure 170 located within the support structure layer 110.

[0119] The support structure layer 110 includes multiple types of dielectric materials with different etching ratios, as described in the manufacturing process above. In the following description, dielectric layer 127 will be referred to as the first dielectric layer 127, and dielectric layer 146 as the second dielectric layer 146. The first dielectric layer 127 contains silicon oxide, and the second dielectric layer 146 contains silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonate nitride.

[0120] Numerous material layers, including a first dielectric layer 127 and a second dielectric layer 146, are formed within the support structure layer 110. The detailed configuration of the support structure layer 110 is as follows.

[0121] The first dielectric layer 127 includes multiple regions that face each of the multiple channel structures 130 and are spaced apart from one another. Similar to the arrangement direction of the multiple channel structures 130, the arrangement direction of the multiple regions of the first dielectric layer 127 is the first direction (Y direction). Each of the multiple regions of the first dielectric layer 127 has a shape that extends from the second surface 110b of the support structure layer 110 toward the interior of the support structure layer 110, and as shown in Figure 29D, the ends da of the multiple regions are located at the same depth position within the support structure layer 110.

[0122] The second dielectric layer 146 is positioned between the first dielectric layer 127 and the channel structure 130, and the thickness td of the second dielectric layer 146 directly beneath the channel structure 130 may be the same as the thickness tp of the sacrificial structure. If the thickness of the sacrificial structure 170 is not constant, the thickest thickness can be defined as tp. This is because, as mentioned above, a portion of the sacrificial structure 170 may be etched during the process of forming the source-drain structure 180. In other words, the thickness td of the dielectric layer 146 directly beneath the channel structure 130 may be less than or equal to the thickness tp of the sacrificial structure, and may be substantially almost the same.

[0123] As shown in Figure 29B, a residual sacrificial pattern 173, made of the same material as the sacrificial structure 170, exists between the channel structure 130 and the first dielectric layer 127. The thickness tp of the residual sacrificial pattern 173 can also be the same as the thickness tp of the sacrificial structure 170. The residual sacrificial pattern 173 is a pattern that remains when the region of the sacrificial material layer 172 exposed to the etching hole EH is removed, as described in the process from Figures 22A to 22E. Therefore, the residual sacrificial pattern 173 does not remain at the location where the etching hole EH was located, i.e., the location opposite the gate electrode 150, and this location functions as the region of the second dielectric layer 146. When viewed from a direction perpendicular to the first surface 110A of the support structure layer 110, the residual sacrificial pattern 173 does not overlap with the gate electrode 150. Between the first dielectric layer 127 and the channel structure 130, the region of the second dielectric layer 146 and the residual sacrificial pattern 173 are alternately arranged along the second direction (X direction). In other words, the second dielectric layer 146 is located opposite the gate structure GS, and the residual sacrificial pattern 173 is located opposite the region between the multiple gate structures GS. Here, the gate structure GS refers to a structure that includes a gate electrode 150 and a gate insulating layer 125.

[0124] Looking at Figure 29E, a cross-sectional view of EE that does not penetrate the channel structure CH, the region of the second dielectric layer 146 includes a first region 146a that extends with a predetermined thickness from the second surface 110b of the support structure layer 110 toward the first surface 110a, and a plurality of second regions 146b that protrude from this thickness position toward the second surface 110b. The plurality of second regions 146b face the plurality of gate structures GS in a one-to-one correspondence. The side profile profile PRD of the second region 146b may be the same as the side profile profile PRG of the gate structure GS. However, it is not limited to the second region 146b and the gate structure GS having the same width. The side profile profile PRD of the second region 146b and the side profile profile PRG of the gate structure GS are the result of patterning the isolation layer 121 using the dielectric layer 141, which was used as a hard mask when forming the dummy gate 152, as explained in Figure 9A. In Figure 9A, the profile PRG on the side of the dummy gate 152 and the profile PRD on the protruding side of the isolation layer 121 are formed continuously. Similarly, in the completed semiconductor device 100, the side profile PRG of the gate structure GS and the profile PRD formed on the side of the second region 146b of the second dielectric layer 146 are in a continuous form.

[0125] Dielectric layers 123 may be arranged on both sides of the second region 146b. Dielectric layer 123 is referred to as the third dielectric layer 123. The third dielectric layer 123 contains a different material from the first dielectric layer 127 and the second dielectric layer 146. Alternatively, the third dielectric layer 123 may contain the same material as the first dielectric layer 127.

[0126] A dielectric layer 142 may be located between the second dielectric layer 146 and the third dielectric layer 123. This dielectric layer 142 is referred to as the fourth dielectric layer 142. The fourth dielectric layer 142 may be formed conformally along the shape of the second dielectric layer 146. The fourth dielectric layer 142 may be formed to extend from the side surface of the second region 126B along the side surface of the gate structure GS. The fourth dielectric layer 142 contains the same material as the second dielectric layer 146.

[0127] A dielectric layer 143 may be further formed on the first surface 110a of the support structure layer 110, and may have a shape that surrounds the source-drain structure 180. The dielectric layer 143 is formed to extend along the side surface of the gate structure GS. A dielectric layer 124 may be formed on the remaining region of the support structure layer 110. The dielectric layer 124 contains, but is not limited to, the same material as dielectric layers 127 and 123.

[0128] The semiconductor element provided by the embodiment and its manufacturing method can exhibit excellent electrical characteristics in an ultra-compact structure and can be applied to integrated circuit elements. The semiconductor element according to the embodiment can be used as a logic transistor and can be applied to various electronic devices together with a controller that controls the logic transistor.

[0129] The aforementioned semiconductor elements 100 and 200 can be used, for example, in display driver integrated circuits, CMOS inverters, CMOS SRAM elements, CMOS NAND circuits, and / or a variety of other electronic devices.

[0130] Figure 30 is a schematic block diagram of a display driver integrated circuit (Display Driver IC: DDI) and a display device equipped with the DDI according to an embodiment.

[0131] Referring to Figure 30, the display driving integrated circuit 500 includes a controller 502, a power supply circuit 504, a driver block 506, and a memory block 508. The controller 502 receives and decodes instructions from the main processing unit (MPU) 522 and controls each block of the DDI 500 to implement the operation of the instructions. The power supply circuit 504 generates a drive voltage in response to the control of the controller 502. The driver block 506 drives the display panel 524 using the drive voltage generated by the power supply circuit 504 in response to the control of the controller 502. The display panel 524 is, for example, a liquid crystal display panel, an organic light-emitting device (OLED) display panel, or a plasma display panel. The memory block 508 is a block that temporarily stores instructions input to the controller 502 or control signals output from the controller 502, or stores necessary data, and includes memory such as RAM or ROM. The power supply circuit 504 and the driver block 506 may include either of the semiconductor elements 10 and 100 according to the exemplary embodiment described above, or semiconductor elements that are modified or combined thereof.

[0132] Figure 31 is a circuit diagram of a CMOS inverter according to an embodiment. Referring to Figure 31, the CMOS inverter 600 includes a CMOS transistor 610. The CMOS transistor 610 consists of a PMOS transistor 620 and an NMOS transistor 630 connected between the power supply terminal Vdd and the ground terminal. The CMOS transistor 610 may include either of the semiconductor elements 10 and 100 described above in exemplary embodiments, or semiconductor elements which are modified or combined thereof.

[0133] Figure 32 is a circuit diagram of the CMOS SRAM element 700 according to the embodiment. Referring to Figure 32, the CMOS SRAM element 700 includes a pair of drive transistors 710. The pair of drive transistors 710 consists of a PMOS transistor 720 and an NMOS transistor 730, respectively, connected between a power supply terminal Vdd and a ground terminal. The CMOS SRAM element 700 further includes a pair of transfer transistors 740. The sources of the transfer transistors 740 are cross-connected to the common node of the PMOS transistors 720 and NMOS transistors 730 that constitute the drive transistors 710. The power supply terminal Vdd is connected to the source of the PMOS transistor 720, and the ground terminal is connected to the source of the NMOS transistor 730. The word line WL is connected to the gates of the pair of transfer transistors 740, and the bit line BL and the inverted bit line are connected to the drains of each of the pair of transfer transistors 740, respectively. At least one of the drive transistors 710 and transfer transistors 740 of the CMOS SRAM element 700 may include either of the semiconductor elements 10 and 100 described above according to the exemplary embodiment, or a semiconductor element that is a modification or combination thereof.

[0134] Figure 33 is a circuit diagram of a CMOS NAND circuit according to the embodiment. Referring to Figure 33, the CMOS NAND circuit 800 includes a pair of CMOS transistors through which different input signals are transmitted. The CMOS NAND circuit 800 may include either of the semiconductor elements 10 and 100 described above in the exemplary embodiment, or semiconductor elements which are modified or combined thereof.

[0135] Figure 34 is a block diagram of an electronic device according to an embodiment. Referring to Figure 34, the electronic device 900 includes a memory 910 and a memory controller 920. The memory controller 920 controls the memory 910 for reading data from and / or writing data in response to a request from the host 930. At least one of the memory 910 and the memory controller 920 may include either of the semiconductor elements 10 and 100 described above in the exemplary embodiment, or a semiconductor element which is a modification or combination thereof.

[0136] Figure 35 is a block diagram of an electronic device according to an embodiment. Referring to Figure 35, the electronic device 1000 constitutes a wireless communication device, or a device capable of transmitting and / or receiving information in a wireless environment. The electronic device 1000 includes a controller 1010, an input / output device (I / O) 1020, a memory 1030, and a wireless interface 1040, which are interconnected via a bus 1050.

[0137] The controller 1010 includes at least one of a microprocessor, a digital signal processor, or a similar processing unit. The input / output device 1020 includes at least one of a keypad, a keyboard, or a display. The memory 1030 is used to store instructions executed by the controller 1010. For example, the memory 1030 is used to store user data. The electronic device 1000 uses the wireless interface 1040 to transmit / receive data over a wireless communication network. The wireless interface 1040 includes an antenna and / or a wireless transceiver. In some embodiments, the electronic device 1000 is used for a third-generation communication system, such as a communication interface protocol for a third-generation communication system, e.g., CDMA (code division multiple access), GSM (global system for mobile communications), NADC (north American digital cellular), E-TDMA (extended-time division multiple access), and / or WCDMA (wide band code division multiple access). The electronic device 1000 may include either of the semiconductor elements 10 and 100 according to the exemplary embodiments described above, or semiconductor elements obtained by modifying or combining them.

[0138] The semiconductor elements, electronic devices containing them, and methods for manufacturing semiconductor elements described above have been explained with reference to embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will understand that a variety of modifications and equivalent other embodiments are possible therefrom. Therefore, the disclosed embodiments should be considered in an explanatory rather than restrictive manner. The scope of the present invention is shown in the claims rather than in the foregoing description, and all differences within an equivalent scope should be construed as being included in the present invention. [Explanation of symbols]

[0139] 10, 100 semiconductor devices 110, SP support structure layer 121 Isolation layer 122, 123, 124, 127 Dielectric layer 125. GI gate insulating layer 130, CH channel structure 131, 131a First semiconductor layer 132 Second Semiconductor Layer 141, 142, 143, 145, 146 Dielectric layer 150, GA gate 152 Dummy Gate 170 Sacrificial Structures 172 Sacrificial Material Layer 173 Remaining Sacrifice Pattern Layer 180, SD Source-Drain Structure 190 Back contact electrodes

Claims

1. A support structure layer comprising a first dielectric layer and a second dielectric layer, and having a first surface and a second surface facing each other, On the first surface of the support structure layer, a plurality of channel structures are arranged spaced apart along a first direction parallel to the first surface, protruding in a fin shape along a direction away from the support structure layer, and comprising a semiconductor material. On the first surface of the support structure layer, source drain structures are arranged at both ends of each of the plurality of channel structures, On the first surface of the support structure layer, a plurality of gate structures are arranged parallel to the first surface and spaced apart along a second direction different from the first direction, and at different positions in the second direction, they surround three faces of each of the plurality of channel structures. A back contact electrode is connected to a part of the source drain structure, penetrates the support structure layer, and is exposed on the second surface of the support structure layer, Includes a sacrificial structure located within the support structure layer and supporting the remaining portion of the source drain structure, The first dielectric layer is disposed below the plurality of channel structures, spaced apart from the plurality of channel structures. A semiconductor device in which the second dielectric layer is disposed between the plurality of channel structures and the first dielectric layer, and the thickness of the second dielectric layer directly beneath the channel structures is the same as the thickness of the sacrificial structure.

2. The semiconductor device according to claim 1, wherein the first dielectric layer and the second dielectric layer have different etching ratios.

3. The first dielectric layer contains silicon oxide, The semiconductor device according to claim 1, wherein the second dielectric layer comprises silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonate nitride.

4. The semiconductor device according to claim 1, wherein the sacrificial structure comprises a material different from the first dielectric layer and the second dielectric layer.

5. The semiconductor device according to claim 1, wherein the sacrificial structure includes SiGe.

6. The semiconductor device according to claim 1, wherein the first dielectric layer includes a plurality of regions that are opposite to and separated from each of the plurality of channel structures.

7. The semiconductor element according to claim 6, wherein each of the plurality of regions of the first dielectric layer has a shape that extends from the second surface of the support structure layer into the interior of the support structure layer.

8. The aforementioned support structure layer is The semiconductor device according to claim 7, further comprising a residual sacrificial pattern disposed between each of the plurality of channel structures and the first dielectric layer, and made of the same material as the sacrificial structure.

9. The semiconductor element according to claim 8, wherein the thickness of the residual sacrificial pattern is the same as the thickness of the sacrificial structure.

10. The semiconductor element according to claim 8, wherein the residual sacrificial pattern is located opposite the region between the plurality of gate structures.

11. Between each of the plurality of regions of the first dielectric layer and each of the plurality of channel structures, The semiconductor element according to claim 8, wherein the region of the second dielectric layer and the residual sacrificial pattern are alternately located along the second direction.

12. The aforementioned second dielectric layer is At a position that does not overlap with the channel structure when viewed from a third direction perpendicular to the first surface of the support structure layer, The semiconductor element according to claim 1, comprising a first region extending with a predetermined thickness from the second surface toward the first surface of the support structure layer, and a plurality of second regions protruding from the first region toward the first surface.

13. Each of the aforementioned multiple second regions is: The semiconductor element according to claim 12, which faces each of the plurality of gate structures.

14. The semiconductor element according to claim 13, wherein, among the plurality of second regions and the plurality of gate structures, the second regions and gate structures at positions facing each other have a continuous side profile.

15. The aforementioned support structure layer is The semiconductor device according to claim 12, further comprising a third dielectric layer disposed between the plurality of second regions and containing the same material as the first dielectric layer.

16. The semiconductor element according to claim 15, wherein the support structure layer further includes a fourth dielectric layer conformally formed between the second dielectric layer and the third dielectric layer, in accordance with the shape of the second dielectric layer.

17. The semiconductor element according to claim 16, wherein the fourth dielectric layer is formed to extend from the side surface of the second region along the side surface of the gate structure.

18. The semiconductor device according to claim 17, wherein the fourth dielectric layer comprises the same material as the second dielectric layer.

19. Semiconductor elements and Includes a controller for controlling the semiconductor element, The aforementioned semiconductor device is A support structure layer comprising a first dielectric layer and a second dielectric layer, and having a first surface and a second surface facing each other, On the first surface of the support structure layer, a plurality of channel structures are arranged spaced apart along a first direction parallel to the first surface, protruding in a fin shape along a direction away from the support structure layer, and comprising a semiconductor material. On the first surface of the support structure layer, source drain structures are arranged at both ends of each of the plurality of channel structures, On the first surface of the support structure layer, a plurality of gate structures are arranged parallel to the first surface and spaced apart along a second direction different from the first direction, and at different positions in the second direction, they surround three faces of each of the plurality of channel structures. A back contact electrode is connected to a part of the source drain structure, penetrates the support structure layer, and is exposed on the second surface of the support structure layer, Includes a sacrificial structure located within the support structure layer and supporting the remaining portion of the source drain structure, The first dielectric layer is disposed below the plurality of channel structures, spaced apart from the plurality of channel structures. An electronic device wherein the second dielectric layer is disposed between the plurality of channel structures and the first dielectric layer, and the thickness of the second dielectric layer directly beneath the channel structures is the same as the thickness of the sacrificial structure.

20. The steps include forming a plurality of three-dimensional structures on a bulk silicon layer, comprising a first silicon layer, a sacrificial material layer, and a second silicon layer, arranged along a first direction, The steps include forming an isolation layer between a plurality of three-dimensional structures on the bulk silicon layer, The steps include forming a plurality of dummy gates on the plurality of three-dimensional structures, which intersect with the plurality of three-dimensional structures and are arranged along a second direction different from the first direction, The steps include: patterning the isolation layer using the hard mask used to form the plurality of dummy gates; The steps include forming a support structure layer consisting of multiple types of dielectric layers with different etching selectivity ratios on the patterned isolation layer, and then forming multiple source-drain structures that are in contact with both ends of the second silicon layer of each of the multiple three-dimensional structures and are in contact with the upper surface of the sacrificial material layer, The steps include removing the bulk silicon layer and the isolation layer to expose a portion of the sacrificial material layer, The steps include removing the exposed portion of the sacrificial material layer to form a sacrificial structure that is in contact with the source drain structure, A method for manufacturing a semiconductor device, comprising the step of forming a back contact electrode that is connected to any one of the plurality of source-drain structures and exposed on the back surface of the support structure layer.

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