Dual contact and power rail for high-performance standard cells

Abstract

This invention provides a layout that can reduce the resistance within a standard cell in a standard cell implemented in a FinFET device or a nanosheet FET device. [Solution] A standard cell includes power connections from both the upper metal layer (first metal layer) and the back metal layer (second metal layer). Devices within a standard cell can be connected to both the upper and back metal layers. Various cell layouts may include a control signal path that goes from the first device into the back layer and then under the second device.

Description

Technical Field

[0001] The embodiments described in this specification relate to semiconductor devices. More particularly, the embodiments described herein relate to a layout for making connections to transistors on a semiconductor substrate.

Background Art

[0002] A standard cell is a group of transistors, passive structures, and interconnect structures that can provide logical functions, memory functions, and the like. The current trend in the standard cell methodology is to reduce the size of the standard cell while increasing the complexity (e.g., circuit density and number of components) within the standard cell. However, as the standard cell design becomes smaller, it becomes more difficult to provide access (e.g., connection) to the components within the standard cell.

[0003] Furthermore, the performance of the standard cell may become more affected by the characteristics within the cell as the size of the standard cell decreases. For example, the resistance within the standard cell, such as a metal trace or interface between a diffusion region and a metal trace within the cell, may reduce the performance of the cell, and as the cell becomes smaller, the impact on performance becomes a more significant problem. Therefore, by reducing the resistance within the standard cell, the performance of the cell can be improved.

Brief Description of the Drawings

[0004] The features and advantages of the methods and apparatuses of the embodiments described in this disclosure will be more fully understood by reference to the following detailed description of presently preferred but nonetheless exemplary embodiments according to the embodiments described in this disclosure in conjunction with the accompanying drawings.

[0005] [Figure 1] A top view of one embodiment of a standard cell having an upper connection is shown.

[0006] [Figure 2] Figure 1 shows a cross-sectional view of one embodiment of a standard cell along the cutting line.

[0007] [Figure 3] This shows a bottom view of one embodiment of a standard cell with rear-side power connections.

[0008] [Figure 4] Figure 3 shows a cross-sectional view of one embodiment of a standard cell along the cutting line shown.

[0009] [Figure 5] This shows a bottom view of one embodiment of a standard cell having both top and bottom connections.

[0010] [Figure 6] Figure 5 shows a cross-sectional view of one embodiment of a standard cell along the cutting line 6-6 shown.

[0011] [Figure 7] Figure 5 shows a cross-sectional view of one embodiment of a standard cell along the cutting line 7-7 shown.

[0012] [Figure 8] A cross-sectional view of one embodiment of a system having two standard cells with via programming is shown.

[0013] [Figure 9] This shows a bottom view of one embodiment of a cell, including both upper and lower power connections, along with the rear signal routing connection.

[0014] [Figure 10] The bottom views of the layouts according to several embodiments are shown.

[0015] [Figure 11] The following are top views of the layout according to several embodiments.

[0016] [Figure 11] Shows a top view of a layout according to some embodiments.

[0017] [Figure 12] Shows a cross-sectional view of an embodiment of a layout along cutting line 12-12 of FIGS. 10 and 11 according to some embodiments.

[0018] [Figure 13] Shows a cross-sectional view of an embodiment of a layout along cutting line 13-13 of FIGS. 10 and 11 according to some embodiments.

[0019] [Figure 14] Shows a cross-sectional view of an embodiment of a layout along cutting line 14-14 of FIGS. 10 and 11 according to some embodiments.

[0020] [Figure 15] Shows a top view of a memory array showing bit cells and bit lines according to some embodiments.

[0021] [Figure 16] Shows a top view of a memory array having single-ended bit lines in bit cells according to some embodiments.

[0022] [Figure 17] Shows a top view of a memory array showing bit cells and word lines according to some embodiments.

[0023] [Figure 18] Shows a top view of a memory array having both bit lines and word lines in upper and back metal layers according to some embodiments.

[0024] [Figure 19] Shows a top view of a large memory megacell replacing two smaller memory megacells according to some embodiments.

[0025] [Figure 20] The image shows a top view of a tall memory megacell that replaces a wide memory megacell according to several embodiments.

[0026] [Figure 21] The image shows a top view of a memory array with hierarchical bit lines according to several embodiments.

[0027] [Figure 22] This is a block diagram of one embodiment of an exemplary system.

[0028] The embodiments disclosed herein are open to various modifications and alternative forms, but specific embodiments are shown in the drawings and described in detail herein for illustrative purposes. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed in the claims. On the contrary, this application is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the disclosure of this application, as set forth in the appended claims. [Modes for carrying out the invention]

[0029] This disclosure relates to the use of a back-side metal layer to provide power and / or control signal connections to transistors within an integrated circuit cell (such as a standard cell). As used herein, the term “standard cell” refers to a group of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or memory functions that are standard for various implementations. Integrated circuit cells may also include custom circuit design cells that are individually designed for specific implementations. Many current cell designs provide connections and routing for power or signals to transistors (or other structures) on top of each other. For example, connections and routing for power or signals may be provided within the upper layer of the device (e.g., the layer above the active layer of the transistors in the device when viewed in a typical cross-sectional view). As used herein, the term “upper” refers to a region within the device that is vertically above the active layer of the device (e.g., above the transistor region of the device). For example, upper may refer to components such as contacts or layers that are above the transistor region in the vertical dimension, as shown in the figures and described herein. In some cases, the term “front” may be used interchangeably with the term “upper.”

[0030] Figure 1 shows a top view of one embodiment of a standard cell 100 having an upper connection. For simplicity, the representation of the cell disclosed herein shows only the components relevant to this disclosure. Those skilled in the art will understand that additional components may be present in any of the cells shown herein.

[0031] In the illustrated embodiment of Figure 1, the standard cell 100 includes a gate 102, a device 104, a source / drain contact 106, and a metal layer 108. The gate 102 (e.g., gates 102A, 102B, 102C) may be a polyline (e.g., a polysilicon layer or a metal layer). In various embodiments, the gate diagram in this disclosure includes a gate spacer 103. The device 104 may be a transistor, such as a FinFET device, a nanosheet FET (NSH) device, or a GAAFET ("gate all-around" FET) device. Other embodiments of the transistor device may also be contemplated. In various embodiments, the contact 106 or via 107 provides a connection between the device 104 and the metal layer 108. In embodiments having multiple metal layers, the metal layer 108 may include one or more metal layers having contacts 106 and vias 107 that provide various connections to different metal layers. For example, contact 106 may provide a connection between a region within device 104 (e.g., a source / drain region within the device) and a first metal layer (e.g., a ground metal layer), and via 107 may provide a connection between a region within the device and other higher metal layers (e.g., a layer above the first metal layer). In certain embodiments, metal layer 108 provides routing from device 104 to Vdd (e.g., supply voltage) and Vss (e.g., ground). Metal layer 108 may also provide routing for connections to / from control signals to / from device 104, as described herein.

[0032] Figure 2 shows a cross-sectional view of an embodiment of the standard cell 100 along the cutting line shown in Figure 1, according to several embodiments. In the illustrated embodiments, the standard cell 100 includes a substrate 200 having an insulating layer 202 formed on a gate 102. In some embodiments, as shown in Figure 2, gate 102B is an active gate, and gates 102A and 102C are isolated gates on either side of the active gate. In certain embodiments, the substrate 200 is a silicon substrate, and the insulating layer 202 is an oxide layer. In various embodiments, the substrate 200 may include additional components or features for the mounting configuration in the device 104. For example, the substrate 200 may include an insulating layer, a diffusion (e.g., oxide diffusion) region, or a doped region for the mounting configuration in the device 104.

[0033] For simplicity in the drawings, the substrate 200 and the insulating layer 202 are shown as a single layer. In some embodiments, the insulating layer 202 includes one or more insulating layers formed on the substrate. For example, the substrate 200 may be a silicon substrate having one or more oxide layers formed on the substrate. The insulating layer 202 may include a single insulating layer or multiple insulating layers. For example, the insulating layer 202 may include multiple oxide layers. In various embodiments, the insulating layer 202 at least partially surrounds or encapsulates areas of the device 104 (e.g., the gate 102, the source / drain area 204, the contacts 106, etc.).

[0034] In certain embodiments, as shown in Figure 2, the source / drain region 204 of the device 104 is located above the substrate 200 within the standard cell 100. The source / drain region 204 may be, for example, a fin or nanosheet stack within a FinFET or NSH device. Various embodiments may also be conceived in which the source / drain region 204 is located within the substrate 200, or in which only a portion of the source / drain region is located within the substrate.

[0035] As shown in Figure 2, contact 106, via 107, and metal layer 108 are located in the upper layer of device 104 above the source / drain region 204 and gate 102. In various embodiments, via 107 provides a signal connection to the source / drain region 204A, and contact 106 provides a power signal connection to the source / drain region 204B. For example, in the embodiments shown in Figures 1 and 2, contact 106B connects the source / drain region 204B to Vdd via routing in the metal layer 108 (note that contact 106B extends horizontally from device 104 to the portion of the metal layer 108 connected to Vdd, as shown in Figure 1), and via 107 connects the source / drain region 204A to the signal routing in the metal layer 108 (via contact 106A). Thus, the metal layer 108 may include routing for both power and control signal connections. As shown in Figures 1 and 2, providing connections and routing for both power and control signals above device 104 using contacts 106 and vias 107 may incur area costs above the device within standard cell 100.

[0036] Some intended embodiments for the design of a standard cell move the connections and routing for power connections to the metal layer beneath the transistor. For example, the connections and routing for power may be provided within the back layer of the device (e.g., the layer beneath the active layer of the transistor in the device when viewed in a typical cross-sectional view). As used herein, the term “back side” refers to a region within the device that lies vertically below the active layer of the device (e.g., below the transistor region of the device). For example, the back side may refer to components such as contacts or layers that are below the transistor region in the vertical dimension, as shown in the figures and described herein. As used herein, it should be noted that back side elements located beneath the active layer may be located above, inside, or below the silicon substrate on which the active layer is manufactured. That is, as used herein, “back side” is relative to the active layer, not the silicon substrate.

[0037] Figure 3 shows a bottom view of one embodiment of a standard cell 300 having a back layer power connection. In the embodiment shown in Figure 3, the standard cell 300 includes a gate 302, a device 304, a back via 306, and a back metal layer 308. The gate 302 and device 304 may be substantially the same as the gate 102 and device 104 shown in Figure 1. The via 306 provides a connection between the device 304 (e.g., a source / drain region within the device) and the back metal layer 308. The back metal layer 308 may include one or more metal layers that provide power routing from the device 304 to Vdd (e.g., supply voltage) and Vss (e.g., ground).

[0038] Figure 4 shows a cross-sectional view of an embodiment of a standard cell 300 along the cutting line shown in Figure 3, according to several embodiments. In the illustrated embodiment, the standard cell 300 includes a substrate 200 having a gate 302, a gate spacer 303, and a source / drain region 404 formed within a device 304. As shown in Figure 4, the source / drain region 404 of the device 304 is located above the substrate 200 and below the insulating layer 202 within the device. The source / drain region 404 may be, for example, a fin or nanosheet stack in a FinFET, NSH, or GAAFET device. Power connection to the source / drain region 404B is made by a back via 306 from a back metal layer 308. Thus, in the illustrated embodiment of Figure 4, the back via 306 routes from the source / drain region 404B to the back metal layer 308, and the back metal layer replaces the power routing within the metal layer 108 to provide power connection to the device 304.

[0039] As shown in Figure 4, the back via 306 and the back metal layer 308 are located beneath the device 304 (e.g., within the back layers of the device beneath the source / drain region 404). In certain embodiments, the back via 306 includes a buried via that penetrates the substrate 200 to connect the source / drain region 404 and the back metal layer 308. In some embodiments, as shown in the illustrated embodiments, the back metal layer 308 is formed on or near the bottom surface of the substrate 200. In certain embodiments, the back metal layer 308 is one or more back layers of the active layers of the device 304 (e.g., the back metal layer 308 is vertically below the transistor region of the device 304). In some embodiments, the back metal layer 308 is one or more buried layers within the substrate 200 (e.g., the metal layer is embedded or embedded beneath the bottom surface of the substrate). In some embodiments, the back metal layer 308 is embedded beneath a carrier substrate layer (e.g., a silicon carrier substrate). An additional embodiment may be conceived in which the back metal layer 308 is not placed within the substrate 200.

[0040] As shown in Figures 3 and 4, the available area on the device is increased by moving the power connections to the source / drain region 404 below the device 304. Note that contacts 106 and metal layer 108 are shown above the source / drain region 404 in the device 304 in Figure 4, as the upper metal layer may be used for other connections within the standard cell 300 (e.g., control signal connections). For example, in some embodiments, power connections to the source / drain region 404B may be made using the back via 306 and back metal layer 108, while control signal connections to the source / drain region 404A may be made using contact 106A to the metal layer 308. In some embodiments, the space for contact 106 above the source / drain region 404B may be left empty to increase the available area on the source / drain region and the device 304. This empty space may be left empty or may be used for routing other resources (e.g., additional contacts for control signals or contacts for other signals).

[0041] The embodiments of the standard cell 300 shown in Figures 3 and 4 can improve the utilization of area within the cell layout, as described above. However, interfacial resistance within the cell (e.g., resistance at the interface between the source / drain region 404 and the back via 306) can present problems within the cell, especially as the cell size decreases. This disclosure recognizes that redundant power connections can be made above and below the device to reduce interfacial resistance in a standard cell layout.

[0042] Specific embodiments disclosed herein include three broad elements: 1) a transistor having a gate region, a source region, and a drain region, positioned above the substrate in a vertical dimension perpendicular to the substrate; 2) a first metal layer positioned above the transistor in a vertical dimension (e.g., on the top side of the transistor); and 3) a second metal layer positioned below the transistor in a vertical dimension (e.g., on the back side of the transistor). In some embodiments, one or more rails (e.g., a power rail) are connected to both the first and second metal layers. For example, both a supply voltage rail and a ground rail may be connected to both the first and second metal layers (the metal layers having separate routing for supply voltage and ground). In certain embodiments, either the source region or the drain region of the transistor is connected to both the first and second metal layers. Connecting the source / drain region to both the first and second metal layers provides redundant connections between the source / drain region and the supply voltage rail, the ground rail, or both rails.

[0043] In certain embodiments, the source region is connected to a supply voltage rail, and the drain region is connected to a grounding rail via both a first and a second metal layer. For example, the source region is connected to supply voltage routing in both the first and second metal layers, and the routing in both metal layers is connected to the supply voltage rail. Similarly, the drain region is connected to grounding routing in both the first and second metal layers, and the routing in both metal layers is connected to the grounding rail.

[0044] In various embodiments, the rails connected to the first and second metal layers may be signal rails. For example, an embodiment may be conceived in which the rails provide bit cell signals. Providing redundant signal connections between the source / drain regions and the signal rails may allow signals to escape the device with less resistance than a single connection. In some embodiments, source or drain regions from adjacent devices (e.g., adjacent transistors) may be selectively connected to the first or second metal layer. For example, via programming may be implemented in a multi-transistor layout to alternate connections from the source / drain regions between the first and second metal layers in alternating transistors.

[0045] In short, the inventors recognized that providing connections to both the device above and below the device in the cell layout improves cell performance. By providing redundant connections above and below the device, interfacial resistance within the cell is reduced. For example, the interfacial resistance between the diffusion region and the metal within the cell is reduced using redundant connections, thereby improving cell performance. The inventors also recognized that providing redundant connections above and below the device has an area cost for the connections above the device, but the reduction in interfacial resistance within the cell still improves cell performance compared to cells with connections only below the device (as shown in Figures 3 and 4). Furthermore, redundant connections can reduce interfacial resistance within the cell and improve cell performance without increasing the cell size or supplying extra power to the cell.

[0046] Figure 5 shows a bottom view of one embodiment of a standard cell 500 having power connections on both the top and bottom sides. In the illustrated embodiment, the standard cell 500 includes a gate 502 and a device 504. The gate 502 and device 504 may be the same as those in other embodiments described herein. In certain embodiments, the gate 502 is a polyline formed from a polysilicon layer or a metal layer, and the device 504 is a transistor (e.g., a FinFET device or a nanosheet FET device). The standard cell 500 includes both an upper (source / drain) contact 506, an upper via 507 to an upper metal layer 508, and a back via 510 to a back metal layer 512. Although the upper via 507 is shown in Figure 5, it should be noted that the upper via is typically hidden by the upper contact 506 in the bottom view. In some embodiments, the upper contact 506 provides a control signal connection between the device 504 and the upper metal layer 508, and the upper via 507 and the back via 510 provide power connections from the device to the upper metal layer 508 and the back metal layer 512, respectively.

[0047] In certain embodiments, power routing within the upper metal layer 508 and power routing within the back metal layer 512 are connected to rails 514 and 516. In the illustrated embodiment, rail 514 is the supply voltage rail, and rail 516 is the ground rail for the power supply connected to the rail. Other embodiments may be contemplated in which rails 514 and 516 are connected to different power supplies or carry different potentials. In various embodiments, the upper metal layer portion 508A and the back metal layer portion 512A provide routing from device 504 to Vdd (e.g., supply voltage). Similarly, the upper metal layer portion 508B and the back metal layer portion 512B provide routing from device 504 to Vss (e.g., ground voltage). Note that rails 514 and 516 and the connections to / from the rails are schematically shown in the illustrated embodiments, and the actual implementation of rails and connections to / from the rails may be done through various designs based on the desired functionality for the standard cell 500. Furthermore, although the upper via 507 and the rear via 510 are shown not to overlap vertically in Figure 5, various embodiments can be envisioned in which there is partial or complete overlap between the upper via and the rear via in the vertical direction.

[0048] As shown in Figure 5, the device 504 is connected to rails 514 and 516 using both the upper metal layer 508 and the back metal layer 512. Figure 6 shows a cross-sectional view of an embodiment of a standard cell 500 along the cutting line 6-6 shown in Figure 5. In the illustrated embodiment, the standard cell 500 includes a substrate 200 having a gate 502, a gate spacer 503, and a source / drain region 604 formed on the substrate. The source / drain region 604 is the source / drain region of the device 504. The source / drain region 604 may be, for example, a fin or nanosheet stack in a FinFET or NSH device. In a particular embodiment, the upper contact 506A is connected to the source / drain region 604A, and the upper contact 506B and upper via 507 connect the source / drain region 604B to the upper metal layer 508. In some embodiments, as described herein, the upper contact 506B and upper via 507 connect the source / drain region 604B to power routing (e.g., routing to rail 514 or rail 516) within the upper metal layer 508, and the upper contact 506A provides signal routing to the source / drain region 604A (e.g., via connected control signal routing within the upper metal layer 508). For example, in the embodiments shown in Figures 5 and 6, the upper contact 506B and upper via 507 connect the source / drain region 604B to the upper metal layer portion 508A for routing to rail 514 and Vdd. As shown in Figure 6, there are no connections (e.g., vias or contacts) between the source / drain region 604 and the back metal layer 512 along the path of the cutting line 6-6 in Figure 5.

[0049] Figure 7 shows a cross-sectional view of an embodiment of a standard cell 500 along the cutting line 7-7 shown in Figure 5. In the illustrated embodiment, the back via 510 and the back metal layer 512 are located beneath the source / drain region 604 of the device 504 (e.g., within the back layer of the device). In certain embodiments, the back via 510 is a embedded via that penetrates the substrate 200 for connecting the source / drain region 604B to the back metal layer 512. In various embodiments, as shown in Figure 7 and described herein, the back metal layer 512 is formed on or near the bottom surface of the substrate 200. In some embodiments, the back metal layer 512 is an embedded layer within the substrate 200 (e.g., the metal layer is embedded or embedded beneath the bottom surface of the substrate). Additional embodiments in which the back metal layer 512 is not located within the substrate 200 may be contemplated.

[0050] In certain embodiments, the rear via 510 connects the source / drain region 604B to power routing within the rear metal layer 512 (e.g., routing to rail 514 or rail 516). For example, in the embodiments shown in Figures 5 and 7, the rear via 510 connects the source / drain region 604B to the rear metal layer portion 512A for routing to rail 514 and Vdd. As shown in Figure 7, there are no vertical connections (e.g., vias) between the source / drain regions 604A, 604B and the upper metal layer 508 along the path of the cutting line 7-7 in Figure 5.

[0051] In various embodiments, as shown in Figures 5 to 7, the standard cell 500 includes power connections between the device 504 and rails 514 and 516 using connections both above and below the device within the standard cell (e.g., both the upper and back layers of the device). For example, rail 514 is connected to the source / drain region 604B via both upper vias 507 and upper metal layer portion 508A and back vias 510 and back metal layer portion 512A. Providing power connections both above and below the device 504 can reduce interfacial resistance between the diffusion region (e.g., source / drain region 604B) and the metal layer (e.g., upper vias 507 and back vias 510) in the standard cell 500. For example, interfacial resistance is reduced by increasing the connection area between the diffusion region and the metal layer using connections to rails 514 and 516 from both above and below the device 504, thereby reducing resistance in the path between the rails and the device. In some embodiments, the interfacial resistance in standard cell 500 is reduced to about half that of standard cell 100 or standard cell 300, because standard cell 500 doubles the number of power connections to rails 514 and 516.

[0052] Providing redundant power connections above and below the device 504 within the standard cell 300 may result in increased area costs compared to the standard cell 500 due to the connection above the device. However, reducing the interfacial resistance in the standard cell 500 improves its performance compared to the standard cell 300. For example, the standard cell 500 may have a performance improvement of approximately 5% or more compared to the standard cell 300. Furthermore, the standard cell 500 has even better performance than the standard cell 100 while having the same area cost. Therefore, the standard cell 500 can have improved performance without the need to increase the cell size or supply extra power to the cell.

[0053] In some embodiments, the properties of the metal in the upper via 507 and upper metal layer 508 versus the metal in the back via 510 and back metal layer 512 are used to control the properties of the power supply that provides power to the device 504. For example, the resistance of the metal in the upper via 507 and upper metal layer 508 can be characterized relative to the resistance of the metal in the back via 510 and back metal layer 512 to determine the relative proportion of power supplied through the upper and back metal layers. The power supply that provides power to the standard cell 500 can then be controlled using programming or modeling based on the relative proportion. In some embodiments, one or more tie cells can be coupled to the upper and back metal layers to link them together.

[0054] In some embodiments, the power supply may be connected to the upper and lower metal layers without programming or modeling, so that the power supply distributes power to the upper and lower metal layers based on their relative resistances. In such embodiments, the mismatch between the resistance in the upper and lower metal layers can be small. Small differences may be within acceptable limits so that programming or modeling of the power supply is not required. For example, the voltage difference across the upper and lower metal layers may be on the order of a few millivolts.

[0055] In some embodiments, a standard cell 500 may be implemented within multiple standard cells using via programming between cells. Figure 8 shows a cross-sectional view of one embodiment of a system having two standard cells 500 with via programming. System 800 includes a first standard cell 500A and a second standard cell 500B. Although two standard cells are shown, it should be understood that system 800 may include multiple alternating standard cells similar to the first standard cell 500A and the second standard cell 500B.

[0056] System 800 may include routing between two voltage sources Vdd1 and Vdd2 to a first standard cell 500A and a second standard cell 500B. In the illustrated embodiment, Vdd1 is routed to the back metal layer 512 in the first standard cell 500A, and Vdd2 is routed to the upper metal layer 508 in the second standard cell 500B. Via programming is implemented in System 800 to alternate the connections to Vdd1 and Vdd2 in the first standard cell 500A and the second standard cell 500B.

[0057] For example, as shown in Figure 8, in the first standard cell 500A, there is no connection (no contact vias) between the upper metal layer 508 (routed to Vdd2) and the source / drain regions 604A and 604B, but there is a connection between the back metal layer 512 (routed to Vdd1) and the source / drain region 604B using the back via 510. Conversely, in the second standard cell 500B, there is a connection via 507 between the upper metal layer 508 (routed to Vdd2) and the source / drain region 604B, but there is no connection between the back metal layer 512 (routed to Vdd1) and the source / drain regions 604A and 604B. Therefore, the first standard cell 500A receives Vdd1, and the second standard cell 500B receives Vdd2 based on programming determined by the presence or absence of contact vias in the standard cell.

[0058] The embodiments shown in Figures 5 to 8 provide reduced interfacial resistance for power connections by having connections both above and below device 504. Various embodiments may also be contemplated to potentially provide additional benefits for signal transmission within a cell (such as standard cell 500) by providing signal (e.g., control signal) connections for both the upper and lower gates of a transistor device (such as device 504). For example, providing additional signal connections or routing through the cell can reduce RC delays that typically arise from resistance in via connections in the upper layer of the cell.

[0059] However, providing signal connections to gates within the back metal layer (e.g., back via 510 connection to back metal layer 512) can be unreliable, difficult to implement, or expensive. For example, locating signal connections to gates within the back layer can cause parasitic problems, such as placing signal and power connections in close proximity, thereby reducing device reliability. Furthermore, forming signal connections to gates in the back layer may require a highly controlled process to allow for the close placement of signal and power connections, thereby increasing costs and reducing device yield. This disclosure aims to provide routing paths for signal connections within the back layer to reduce resistance when transmitting signals without requiring back layer connections to gates in close proximity to power connections. The disclosed technique can improve the performance of integrated circuit cells compared to previous cell layouts, such as those shown in Figures 1-4, by reducing RC delay within the cell.

[0060] Specific embodiments disclosed herein have three broad elements: 1) a first transistor and a second transistor arranged in the transistor region of an integrated circuit; 2) a via structure on the side of the first transistor opposite the second transistor; and 3) a control signal routed from the second transistor to the first transistor, entering the back metal layer from the second transistor, passing through the via structure to the upper metal layer, and passing through the upper metal layer to the gate of the first transistor. In certain embodiments, the control signal path passes under the first transistor in the back metal layer. In some embodiments, the control signal path passes between the signal output of the second transistor and the signal input of the first transistor.

[0061] In various embodiments, the via structure includes an inactive (e.g., "dummy") source / drain region and one or more vias connecting the back metal layer to the upper metal layer. In some embodiments, two or more via structures are implemented to transmit control signals between the back metal layer and the upper metal layer. Two or more via structures can transmit control signals in parallel between the back metal layer and the upper metal layer. The via structures can then be connected to each other (e.g., "short-circuited") within the metal layer to transmit control signals.

[0062] In short, the inventors have recognized that by using via structures from the connected transistor to the opposite side of the transistor, it is possible to provide routing connections for control signals through the back layer without providing additional gate connections in the back layer. The via structure may be, for example, an inactive (e.g., "dummy") transistor. Providing routing connections through the via structure beneath the transistor, through the back layer, provides a control signal path in addition to other paths to reduce RC delay in signal transmission. While the addition of such via structures may incur area costs, the improvement in the performance of the cell with control signals routed through the via structures may provide a substantial return in signal transmission that justifies the area costs.

[0063] Figure 9 shows a bottom view of one embodiment of cell 900, including both upper and lower power connections, along with lower signal routing connections. Cell 900 may be, for example, a standard cell or a custom circuit design cell. In the illustrated embodiment, cell 900 includes a gate 902 and a device 904. The gate 902 and device 904 may be similar to other embodiments of gates and devices described herein. In a particular embodiment, the gate 902 is a polyline formed from a polysilicon layer or a metal layer, and the device 904 is a transistor (e.g., a FinFET device, a nanosheet FET device, or a GAAFET device). Device 904 also includes an upper (source / drain) power contact 906, an upper via 907 to an upper metal layer 908, and a lower via 910 to a lower metal layer 912. The upper via 907 provides a power connection (e.g., Vdd / Vss connection) between the device 904 and the upper metal layer 908, while the back via 910 provides a power connection between the device and the back metal layer 912.

[0064] As described herein, the upper metal layer 908 and the back metal layer 912 may be coupled to a power rail to provide a power connection to the device 904. For example, the upper metal layer portion 908A and the back metal layer portion 912A may provide routing from the device 904 to Vdd (e.g., supply voltage), and the upper metal layer portion 908B and the back metal layer portion 912B may provide routing from the device 904 to Vss (e.g., ground voltage). For simplicity of the drawings, the power rail is not shown in the embodiment of cell 900 in Figure 9.

[0065] In certain embodiments, the back metal layer 912 includes a back metal layer portion 912C. The back metal layer portion 912C may be implemented to provide routing connections for control signals passing through the cell 900, as described herein. The back metal layer portion 912C may be in the same back metal layer as back metal layer portions 912A and 912B, or in a different back metal layer. In various embodiments, the back metal layer portion 912C includes a first back metal layer or a second back metal layer.

[0066] As shown in Figure 9, the back via 910 does not contact the back metal layer portion 912C to avoid short circuits between power and signal connections routed through the back metal layer 912. As described above, locating gate connections within the back metal layer 912 can be difficult, unreliable, and costly, considering the power connections within the back metal layer (e.g., the back via 910 and back metal layer portions 912A and 912B). Therefore, this disclosure intends to provide routing connections through the back metal layer portion 912C without providing connections through the back via 910 beneath the device 904 (e.g., within its vertical region). In various embodiments, as shown in Figures 10–13, a “dummy” cell may be located adjacent to cell 900 to provide routing for control signals.

[0067] Figure 10 shows a bottom view of layout 1000 according to several embodiments. In the illustrated embodiments, layout 1000 includes cell 1001. Cell 1001 includes an inactive ("dummy") gate 1002, and via structures 1010A, 1010B, and 1010C are arranged between the inactive gates to form an inactive ("dummy") device 1004. In various embodiments, cell 1001 may be located adjacent to active cells and gates (e.g., cell 900 and gate 902A shown in Figure 9). In certain embodiments, cell 1001 is a unique cell included adjacent to the end of an active cell (e.g., the end of a cell layout) or another signal endpoint in a cell layout. Cell 1001 includes paths for extensions of three back metal layer portions 912A, 912B, and 912C. In certain embodiments, the extension for the back metal layer portion 912C provides a routing path for control signals associated with the active cell (e.g., device 904). It should be understood that each of the metal layer portions 912A, 912B, and 912C may be arranged in a single back metal layer, different back metal layers, or a combination of back metal layers.

[0068] In certain embodiments, cell 1001 includes one or more via structures 1010. In the illustrated embodiment, cell 1001 includes three via structures 1010A, 1010B, and 1010C, but any number of via structures 1010 can be contemplated. As described herein, the via structures 1010 may include back vias 910, upper vias 907 (shown in Figure 11), and inactive (e.g., "dummy") and source / drain regions 1214 (shown in Figures 12 and 13) connecting the back metal layer portion 912C to the upper metal layer 908. The back vias 910A, 910B, and 910C provide a connection between the source / drain region of device 1004 (e.g., the source / drain region 1214 shown in Figures 12 and 13) and the back metal layer portion 912C.

[0069] Figure 11 shows a top view of layout 1000 according to several embodiments. In the illustrated embodiments, the via structure 1010 includes upper vias 907A, 907B, and 907C that connect the source / drain region of device 1004 (e.g., source / drain region 1214 shown in Figures 12 and 13) to the upper metal layer portion 908C. In some embodiments, the upper metal layer portion 908C includes multiple parts (e.g., paths). These multiple paths can be connected to each other (e.g., short-circuited) as schematically shown in Figure 11 to provide a connection between the upper via 907 and the active cell. For example, a gate via can connect the upper metal layer portion 908C to a gate in the active cell (e.g., gate 902 in Figure 9). In some embodiments, the upper metal layer portion 908C is located within a first metal layer in the upper metal layer 908, but other metal layers may be mounted.

[0070] In the embodiments shown in Figures 10 and 11, the upper metal layer portions 908A, 908B and the back metal layer portions 912A, 912B are not connected to any part of device 1004 within cell 1001. For example, there are no upper vias 907 or back vias 910 connecting the source / drain region within device 1004 (e.g., source / drain region 1214 shown in Figures 12 and 13) to the upper metal layer portions 908A, 908B or the back metal layer portions 912A, 912B. Without these connections, device 1004 is not provided with power connections, and device 1004 is an inactive (e.g., "dummy") device. When device 1004 is inactive, control signal paths (e.g., control signal paths 1220 shown in Figures 12 and 13) can pass through device 1004 without any interference from power signals.

[0071] Figure 12 shows a cross-sectional view of one embodiment of layout 1000 along the cutting line 12-12 in Figures 10 and 11, according to several embodiments. In the illustrated embodiment, the path (dotted line) of the control signal path 1200 is shown between the source / drain regions 1214A, 1214C and the active cell. The control signal path 1200 proceeds, for example, from the source / drain regions 1214A and 1214C, through contacts 906 and upper vias 907A and 907C to the upper metal layer portion 908C, and then it routes to the active cell. In the cross-section of cell 1001 shown in Figure 12, via structures 1010A and 1010C provide a path for the control signal path 1200 to the upper metal layer portion 908C above the back metal layer portion 912A (including power routing). The back vias 910A and 910C are also arranged along the cross-section shown in Figure 12. However, it should be noted that the back vias 910A and 910C within via structures 1010A and 1010C, respectively (as also shown in Figure 10), provide a connection path to the back metal layer portion 912C, not the back metal layer portion 912A. Therefore, in the embodiment shown in Figure 12, the control signal path 1200 has a path from source / drain regions 1214A and 1214C to back vias 910A and 910C, and then to the back metal layer portion 912C (which then routes to the active cell), but the back vias 910A and 910C are not connected to the back metal layer portion 912A. Thus, as shown in Figure 12, the control signal path 1200 has a path between the upper layer metal layer portion 908C and the back metal layer portion 912C, passing through both source / drain regions 1214A and 1214C.

[0072] Various embodiments of metal routing between the back vias 910A, 910C and the back metal layer portion 912C can be contemplated. The metal routing may include any combination of metal vias, metal wires, metal traces, etc., that provide a path / route between the two structures. For example, in one embodiment, the back vias 910A, 910C may extend vertically downward into the substrate 200 from source / drain regions 1214A, 1214C, respectively (as shown in Figure 12), and additional metal routing connects the back vias to the back metal layer portion 912C.

[0073] Figure 13 shows a cross-sectional view of one embodiment of layout 1000 along the cutting line 13-13 in Figures 10 and 11, according to several embodiments. In the cross-section of cell 1001 shown in Figure 13, via structure 1010B provides a path for the control signal path 1200 between the source / drain region 912C and the back metal layer portion 1214B. Similar to the cross-section in Figure 12, in the cross-section of Figure 13, the back metal layer portion 912B (e.g., power routing) is located beneath the transistor region 1230. However, the back via 910B within via structure 1010B (also shown in Figure 10) provides a connection path to the back metal layer portion 912C rather than the back metal layer portion 912B for the source / drain region 1214B. Thus, the control signal path 1200 proceeds from the source / drain region 1214B, through the back via 910B, to the back metal layer portion 912C (which then routes to the active cell). As described above, various embodiments of the metal routing between the bottom of the back via 910B and the back metal layer portion 912C can be considered. For example, in one embodiment, the back via 910B extends vertically into the substrate 200, and additional metal routing connects the back via to the back metal layer portion 912C.

[0074] Figure 14 shows a cross-sectional view of one embodiment of layout 1000 along the cutting line 14-14 of Figures 10 and 11, according to several embodiments. In the cross-section of cell 1001 shown in Figure 14, via structures 1010A, 1010B, and 1010C provide a path for the control signal path 1200 between the source / drain regions 1214A, 1214B, 1214C and the active cell via the back metal layer portion 912C. In the illustrated embodiment of the cross-section, the back metal layer portion 912C is located below the transistor region 1230 in device 1004. Thus, the back vias 910A, 910B, and 910C within via structures 1010A, 1010B, and 1010C provide direct downward connections into the back metal layer portion 912C for the source / drain regions 1214A, 1214B, and 1214C, respectively. Next, the control signal path 1200 goes from the source / drain regions 1214A, 1214B, and 1214C to the back metal layer portion 912C, and then to the active cell.

[0075] In the exemplary embodiments shown in Figures 12 to 14, device 1004 is formed within a transistor region 1230 of cell 1001. The transistor region 1230 typically includes structures mounted on the active layer of the device (such as adjacent active cells). For example, the transistor region 1230 may include a gate 1002, a gate spacer 1003, and a source / drain region 1214 found in the active layer of a transistor device. The source / drain region 1214 may be, for example, a doped region of device 1004 that forms fins or nanosheet stacks within a FinFET or NSH device.

[0076] As described above, in cell 1001, the gate 1002 and the source / drain region 1214 are not connected to any power supply, and therefore the transistor region 1230 of device 1004 can be considered an inactive (e.g., "dummy") transistor region. Because the transistor region 1230 of device 1004 is inactive, the source / drain region 1214 can be implemented within the control signal path 1200, as shown in Figures 12 to 14. Thus, as shown in the illustrated embodiment, the control signal path 1200 can provide a path between the source / drain region and the gate of an active cell, including a path through the back metal layer portion 912C, via structures 1010 (e.g., back via 910, source / drain region 1214, and via 907), and the upper metal layer portion 908C.

[0077] In a typical cell layout, routing from the output of an active cell device (e.g., device 904 shown in Figure 9 has an output at gate 902A) proceeds from the gate, through the upper metal layer 908, to the input of the source / drain region within the active cell device. As described herein, such routing can have high resistance, generating RC delay. However, the control signal path 1200 shown in Figures 12–14 is a path that involves the additional use of the back metal layer 912 by routing the control signal between the upper metal layer portion 908C and the back metal layer portion 912C via a structure within the cell 1001 (e.g., via structure 1010). Thus, in various embodiments, the via structure 1010 within the cell 1001 provides a path for the control signal on the opposite side of the active device (e.g., device 904) from other active devices.

[0078] In a particular embodiment, cell 1001 includes three via structures 1010A, 1010B, and 1010C. As described above, the three via structures 1010A, 1010B, and 1010C may be connected in parallel between the upper metal layer portion 908C and the back metal layer portion 912C, and the via structures are connected to each other (e.g., short-circuited) in the upper metal layer portion and the back metal layer portion. Thus, the control signal path 1200 can “split” (e.g., split) from the back metal layer portion 912C to the via structures 1010A, 1010B, and 1010C and extend in parallel through the via structures 1010A, 1010B, and 1010C. In the upper metal layer portion 908C, the control signal can then “recombine” (e.g., reconnect together) and connect to a gate in the active cell. Figures 10-14 show three via structures 1010A, 1010B, and 1010C, but note that the number of via structures within cell 1001 may be changed. For example, the number of via structures 1010 may be changed to balance area cost (due to the physical presence of the via structures) and performance (more via structures provide higher performance).

[0079] Running the control signal through the back metal layer 912 provides a low-resistance path (e.g., a "highway" path) for the control signal compared to routing the control signal only through the upper metal layer 908, which has relatively small metal structures (traces). Therefore, transmitting the control signal through the back metal layer 912 and the control signal path 1200 reduces the RC delay in the transmission of the control signal. It should be noted that the control signal may be routed through any back metal layer that provides a low-resistance path beneath device 904.

[0080] As shown in Figures 10 to 14, the control signal can be transmitted to the active device (e.g., device 904) along the control signal path 1200. The control signal path 1200 passes through the back metal layer (e.g., back metal layer portion 912C), which has low resistance, then passes through a plurality of via structures 1010 in parallel, and then reaches the upper metal layer (e.g., upper metal layer portion 908C). The combination of the low-resistance path in the back metal layer path and the parallel path through the via structures 1010 can provide a significant reduction in RC delay for transmitting the control signal to and from device 904, thereby improving the performance of the devices in cell layout 1000 compared to previous cell layouts.

[0081] One example where it may be useful to provide a control signal through both the upper and back metal layers is the implementation of layout 1000 in a bit cell erase process. In such an embodiment, the bit cell erase signal may be generated in device 904. Device 904 may be pre-charged to provide the bit cell erase signal. At lower interfacial resistances, the same driver power may drive the bit cell erase signal over a larger distance in the layout. For example, device 904 may be able to transmit the bit cell erase signal to a larger group of bit cells (e.g., 4-bit cells instead of 2-bit cells). As another example, an embodiment may be contemplated in which a control signal through both the upper and back metal layers to / from device 904 may be implemented to provide a differential structure embodiment in layout 1000. In such an embodiment, the signal may be routed in parallel to the upper and back metal layers, with the signal escaping from the upper side on one side of layout 1000 and from the back side on the other side of the layout. The signal may be routed in parallel so that both the upper and back metal layers see the same common mode. An additional cell layout that combines the control signal path 1200 with redundant power connections in the upper and lower metal layers may be intended to provide improved performance in both signal and power transmission compared to previous cell layouts.

[0082] The embodiments described above relate to utilizing the back metal layer to provide additional connections for power and / or control signals in an integrated circuit cell layout. Various embodiments of the implementation of these additional connections are also contemplated in this disclosure. For example, a standard memory array (e.g., SRAM array) design may be contemplated to utilize additional connections for power and / or control signals in the back metal layer to improve the power, performance, and area (PPA) metrics in the SRAM array. Current designs of SRAM arrays typically provide connections and routing for power or signals to transistors (or other structures) on top of transistors. Several embodiments may be contemplated having power connections in the back metal layer of an SRAM array (either alone or in combination with upper metal layer power connections), as described herein.

[0083] Providing power connections within the back metal layer of an SRAM array offers additional benefits for power transmission, but this disclosure recognizes that additional benefits can be achieved by locating several signal connection paths for bit lines and / or word lines within the back layer. For example, moving several signal connection paths for bit lines to the back layer may allow for a reduction in capacitance (capacitance) on the bit lines, which improves performance and power utilization in the SRAM array, while moving several signal connection paths for word lines to the back layer may improve power utilization in the SRAM array. Further improvements in area cost can also be achieved by locating bit lines or word lines in the back layer.

[0084] Certain embodiments disclosed herein have three broad elements: 1) a plurality of adjacent bit cells within an array; 2) a first bit line or a first pair of bit lines spanning alternating bit cells within the array; and 3) a second bit line or a second pair of bit lines spanning every other bit cell from the first bit line or the first pair of bit lines. In various embodiments, the first bit line is a metal wire located in a first metal layer on the upper side of the device (e.g., the front side or above the bit cells), and the second bit line is a metal wire located in a second metal layer on the back side of the device (e.g., below the bit cells). Alternating between first bit lines and second bit lines between adjacent bit cells within a memory array can significantly reduce capacitance within the memory array by increasing the isolation between different bit lines within the same metal layer. Reducing capacitance within a memory array can provide leverage for improving other parameters within the memory array, such as leakage, as described herein.

[0085] Another embodiment disclosed herein has three broad elements, namely: 1) a plurality of adjacent bit cells in an array; 2) a first word line spanning the bit cells in the array, which is a first word line being a first wire in a first metal layer located above the bit cells; and 3) a second word line spanning the bit cells in the array, which is a second word line being a second wire in a second metal layer located below the bit cells. In various embodiments, the first and second word lines connect to alternating bit cells in the array. For example, a memory array may have four adjacent bit cells, and both word lines may span the four bit cells. The first word line connects to the first and third bit cells, and the second word line connects to the second and fourth bit cells in the memory array.

[0086] Independent control of bit cells can be provided by alternating the connections between two separate word lines. For example, the first word line controls the toggle of the first and third bit cells, and the second word line controls the toggle of the second and fourth bit cells. Thus, instead of toggling all four bit cells, when a single bit is changed, only half of the bit cell needs to be toggled, thereby reducing dynamic power consumption in the memory array. Placing the wires for the word lines in the back metal layer can also provide an area cost advantage, as the two word lines can be placed in similar vertical areas (above / below the bit cells) through two separate metal layers (e.g., the upper metal layer and the back metal layer), thereby doubling the word line capacity without area cost.

[0087] In short, the inventors recognized that wiring in the back metal layer can be advantageously implemented in memory arrays (e.g., SRAM arrays). Utilizing wiring in the back metal layer for bit line and / or word line routing can provide various PPA improvements in memory arrays. For example, performance and power improvements can be provided by reducing bit line capacitance, which can be further leveraged for other improvements in memory arrays, including area reduction opportunities.

[0088] Figure 15 shows a top view of a memory array 1600 showing bit cells and bit lines according to several embodiments. In the illustrated embodiments, the memory array 1600 includes four bit cells, namely bit cell 1610A, bit cell 1510B, bit cell 1510C, and bit cell 1510D. Although four bit cells are shown in Figure 15, it should be understood that the memory array 1500 may contain any number of bit cells. In various embodiments, bit cells 1510A, 1510B, 1510C, and 1510D are arranged adjacent to each other within the memory array 1500 (e.g., adjacent to one another). For example, as shown in Figure 15, bit cells 1510A-D are arranged adjacent to each other perpendicularly (e.g., "stacked" vertically on top of each other).

[0089] In certain embodiments, the memory array 1500 includes pairs of bit lines that span each bit cell 1510. For example, in the illustrated embodiment, bit line 1520A spans bit cell 1510A, bit line 1520B spans bit cell 1510B, bit line 1520C spans bit cell 1510C, and bit line 1520D spans bit cell 1510D. Each pair of bit lines may be a complementary pair of bit lines (for example, one bit line is a positive bit line and the other is a negative bit line). In various embodiments, the bit lines 1520 extend perpendicular to the direction in which the bit cells 1510 are arranged adjacent to each other (for example, the direction in which bit cells 1510A-D are stacked in Figure 15). In certain embodiments, the bit lines 1520 are wires (e.g., metal paths, metal traces, metal structures, etc.) formed within the metal layer of the memory device.

[0090] In certain embodiments, bit lines 1520 (e.g., wires within a bit line) are connected to their respective bit cells 1510 by via connections 1530. For example, in the illustrated embodiment, bit line 1520A is connected to bit cell 1510A by via connection 1530A, bit line 1520B is connected to bit cell 1510B by via connection 1530B, bit line 1520C is connected to bit cell 1510C by via connection 1530C, and bit line 1520D is connected to bit cell 1510D by via connection 1530D. Note that although via connection 1530 is depicted as spanning a pair of bit lines in Figure 15, each wire within a pair of bit lines may have its own individual via connections. Therefore, via connections 1530A-D can each contain two or more via connections. Furthermore, in embodiments having multiple via connections 1530 within a single bit cell, the via connections may be aligned or offset within the bit cell as required by the design rules.

[0091] This disclosure intends to arrange pairs of different bit lines 1520 in different metal layers on the upper and back sides of bit cells 1510, as shown in Figure 15, in order to improve PPA compared to a typical SRAM array. In the illustrated embodiment, bit lines 1520A and 1520C are wires in the back metal layer of the memory array 1500 (e.g., the metal layer below the transistor regions of bit cells 1510A and 1510C). Conversely, bit lines 1520B and 1520D are wires in the upper metal layer of the memory array 1500 (e.g., the metal layer above the transistor regions of bit cells 1510B and 1510D). Thus, as shown in Figure 15, the bit lines are arranged alternately between the back and upper metal layers within adjacent bit cells. For example, bit line 1520A in bit cell 1510A is in the back metal layer, then bit line 1520B in bit cell 1510B switches to the upper metal layer, bit line 1520C in bit cell 1510C switches back to the back metal layer, and then bit line 1520D in bit cell 1510D switches back to the upper metal layer.

[0092] In various embodiments, the bit lines 1520 may be positioned in the upper or back metal layer using the techniques described herein. It should be noted that the bit lines 1520 can be positioned in the back metal layer without requiring gate connections, since the bit lines connect to the drains in the memory array 1500. Additional embodiments may be contemplated in which each pair of bit lines includes one bit line in the upper metal layer and one bit line in the back metal layer. In such embodiments, additional design considerations may be implemented to maintain symmetry between the bit lines in each pair of bit lines.

[0093] In some embodiments of the memory array, single-ended bit lines within bit cells may be intended. Figure 16 shows a top view of a memory array 1600 having single-ended bit lines within bit cells according to some embodiments. In the illustrated embodiments, the memory array 1600 includes bit cells 1610A-D, with a single bit line 1620A-D spanning the bit cells. Similar to the embodiment in Figure 15, the bit lines 1620A-D may be alternately arranged between the back metal layer and the upper metal layer between adjacent bit cells 1610A-D. Although four bit cells are shown in Figure 16, it should be understood that the memory array 1600 may contain any number of bit cells. In various embodiments, via connections 1630A-D provide connections between the bit lines 1620A-D and their respective bit cells 1610A-D.

[0094] In a typical SRAM array, bit lines are wires in a metal layer above the bit cell (e.g., the front side) (for example, bit lines are in the metal layer above the transistor region of the bit cell). However, placing bit lines within the same metal layer requires high shielding requirements between bit lines, which can increase bit line capacitance in the memory array and reduce the performance of the memory array.

[0095] In this disclosure, as shown in Figures 15 and 16, bit line capacitance in a memory array is reduced by alternating bit lines between the back and upper metal layers within adjacent bit cells. For example, alternating bit lines increases the isolation distance between bit lines (or pairs of bit lines) within the same metal layer. This increased isolation distance reduces the shielding requirements for the bit lines and thus reduces bit line capacitance. Reducing bit line capacitance can be further utilized in other properties of the memory array. For example, lower shielding requirements may reduce the area utilization by shielding structures, thereby increasing the area availability in the memory array for other structures. As another example, bit cells in a memory array can be slowed down along with reduced bit line capacitance while providing the same performance. Slowing down the bit cells can reduce leakage in the memory array.

[0096] Figure 17 shows a top view of a memory array 1700 showing bit cells and word lines according to several embodiments. In the illustrated embodiments, the memory array 1700 includes four bit cells, namely bit cell 1710A, bit cell 1710B, bit cell 1710C, and bit cell 1710D. Although four bit cells are shown in Figure 17, it should be understood that the memory array 1700 may contain any number of bit cells. In various embodiments, bit cells 1710A, 1710B, 1710C, and 1710D are arranged adjacent to each other within the memory array 1700 (e.g., adjacent to one another). For example, as shown in Figure 17, bit cells 1710A-D are arranged adjacent to each other perpendicularly (e.g., "stacked" vertically on top of each other).

[0097] In certain embodiments, the memory array 1700 includes a pair of parallel word lines, word line 1720A and word line 1720B, that extend across bit cells 1710A to D. Thus, word lines 1720A and 1720B can be considered to span the memory array 1700. In various embodiments, word lines 1720A and 1720B span the bit cells 1710A to D in the same direction in which the bit cells are arranged adjacent to each other (for example, in the vertical direction shown in Figure 17). Thus, word lines 1720A and 1720B span the memory array 1700 along their lengths and provide access to bit cells 1710A to D. In certain embodiments, word line 1720A is a wire in the back metal layer of the memory array 1700, and word line 1720B is a wire in the upper metal layer of the memory array. By placing word line 1720A on the back metal layer and word line 1720B on the upper metal layer, it becomes possible to place the two word lines on the same group of bit cells (e.g., bit cells 1710A-D) within the memory array 1700. Placing the two word lines on the same group of bit cells provides area utilization advantages, as will be explained below.

[0098] As shown in Figure 17, access (e.g., connection) to bit cells 1710A-D is provided by via connections 1730A-D. Via connection 1730 may be, for example, a metal via that penetrates an insulating layer placed between the transistor region containing bit cell 1710 and the metal layer containing word line 1720. In various embodiments, via connections 1730A-D selectively provide connections between bit cells 1710A-D and either word line 1720A or word line 1720B as the word line passes through the bit cells. In a particular embodiment, connections to bit cells 1710A-D are alternated between word lines 1720A and word line 1720B of adjacent bit cells by alternating the connections provided by via connections 1730A-D. For example, in the illustrated embodiment, via connection 1730A provides a connection between bit cell 1710A and word line 1720B, via connection 1730B then provides a connection between bit cell 1710B and word line 1720A, via connection 1730C then provides a connection between bit cell 1710C and word line 1720B, and via connection 1730D provides a connection between bit cell 1710D and word line 1720A. Thus, the connections from bit cells 1710B and 1710D to word line 1720A alternate with the connections from bit cells 1710A and 1710C to word line 1720B.

[0099] In a typical SRAM array, only a single word line in the upper layer is available for an array of adjacent bit cells. For example, because there is insufficient area to accommodate two parallel word lines spanning multiple vertical (as illustrated) bit cells, only a single word line can be implemented in the upper metal layer. With a single word line, when an instruction (e.g., a control signal) is provided to toggle a single bit cell, all bit cells along the word line receive the instruction to toggle. Since all bit cells are toggled, power consumption is unnecessarily increased compared to toggling only a selected number of bit cells.

[0100] In various embodiments, the word line 1720 is positioned in the upper or back metal layer using the techniques described herein. It should be noted that the word line 1720 positioned in the back metal layer typically requires a gate connection (e.g., to a path gate). Thus, embodiments may be contemplated in which the gate connection via the back layer described herein is implemented for the word line 1720.

[0101] In this disclosure, the arrangement of word lines in both the upper and lower metal layers may allow connections to bit cells to alternate between parallel word lines that simultaneously provide access to the same group of bit cells. For example, as shown in Figure 17, word line 1720A (in the lower metal layer) and word line 1720B (in the upper metal layer) have alternating connections to adjacent bit cells 1710 in the memory array 1700. Thus, a single word line (e.g., either word line 1720A or word line 1720B) can provide control signals to a reduced number of bit cells 1710 (e.g., half of the bit cells) in the memory array 1700. For example, when a control signal to toggle is transmitted via word line 1720A, only bit cells 1710A and 1710C are toggled, while bit cells 1710B and 1710D remain in their current state. Similarly, when a toggle control signal is transmitted via word line 1720B, only bit cells 1710B and 1710D are toggled, while bit cells 1710A and 1710C remain in their current state.

[0102] By reducing the number of bit cells toggled by a single control signal, the dynamic power consumption in memory array 1700 can be reduced compared to a memory array with a single word line. Providing reduced dynamic power consumption is also achieved at a lower area cost, as the word line count is doubled in the vertical region above the bit cell, instead of requiring an increase in the bit cell area to accommodate multiple word lines. The embodiment of the technique described in Figure 17 for doubling word lines can also be applied to other control signal lines implemented within integrated circuits such as memory arrays. For example, control signals such as bit line precharge signals, column selection signals, cross-connected PMOS structure signals are control signals that can utilize line doubling in the upper and back metal layers. Applying the disclosed technique to these control signals can further reduce power consumption, as these signals are full-power signals, unlike word line control signals.

[0103] Various embodiments of memory arrays that utilize the placement of both bit lines and word lines in the upper and back metal layers may also be considered. Figure 18 shows a top view of a memory array 1800 having both bit lines and word lines in the upper and back metal layers according to several embodiments. In the illustrated embodiment, the memory array 1800 includes four bit cells, namely bit cell 1810A, bit cell 1810B, bit cell 1810C, and bit cell 1810D. Although four bit cells are shown in Figure 18, it should be understood that the memory array 1800 may contain any number of bit cells. In various embodiments, bit cells 1810A, 1810B, 1810C, and 1810D are arranged adjacent to each other within the memory array 1800 (e.g., adjacent to one another). For example, as shown in Figure 18, bit cells 1810A-D are arranged adjacent to each other perpendicularly (e.g., "stacked" vertically on top of each other).

[0104] The illustrated embodiment of memory array 1800 essentially includes the bit lines of memory array 1500 shown in Figure 15, which overlap with the word lines of memory array 1700 shown in Figure 17. Thus, memory array 1800 includes bit lines 1820A spanning bit cell 1810A, bit lines 1820B spanning bit cell 1810B, bit lines 1820C spanning bit cell 1810C, and bit lines 1820D spanning bit cell 1810D. Memory array 1800 further includes word lines 1830A and 1830B spanning bit cells 1810A to D.

[0105] As described in the earlier embodiments, bit lines 1820A-D may include bit line pairs in either the upper metal layer or the back metal layer. For example, in the illustrated embodiment, bit lines 1820A and 1820C are in the back metal layer, and bit lines 1820B and 1820D are in the upper metal layer. Similarly, word line 1830A may be in the back metal layer, and word line 1830B may be in the upper metal layer. Via connections 1840A-D then provide alternating connections from bit cells 1810A-D to word lines 1830A and 1830B, and via connections 1850A-D provide alternating connections between bit lines 1820A-D and bit cells 1810A-D, as described herein.

[0106] Although the bit line 1820 and word line 1830 are shown intersecting each other and are described as being in the “back (or top) metal layer”, it should be understood that the bit line and word line may be mounted in different metal layers in both the top and back layers. For example, the bit line 1820A may be mounted in a first metal layer within the back metal layer, and the word line 1830A may be mounted in a second metal layer within the back metal layer. Additional embodiments may be conceived to accommodate spacing between lines, with the bit line and word line being routed through multiple metal layers. The embodiment of the memory array 1800 shown in Figure 18 can benefit from the various advantages described herein relating to having both the bit line and word line in the back and top metal layers simultaneously.

[0107] In various embodiments, word lines in both the upper and lower metal layers may be implemented in larger cells of the memory array (e.g., “megacells”) to improve area utilization in such cells. Figure 19 shows a top view of a larger memory megacell replacing two smaller memory megacells according to several embodiments. In the illustrated embodiments, megacells 1910A and 1910B are combined into a single megacell, megacell 1900. Megacell 1910A includes memory array banks 1912A and 1912B separated by bit-line logic circuits 1916A, and word-line logic circuits 1914A are located adjacent to the memory array banks and bit-line logic circuits. Memory array banks 1912A and 1912B may include any of the various memory cells or memory arrays disclosed herein, in addition to other intended embodiments of memory cells and memory arrays. The bit line logic circuit 1914A may include a sensing amplifier or other logic for reading data from memory array banks 1912A and 1912B. The word line logic circuit 1916A may include word line decoder logic, word line selection logic, or multiplexer logic for interacting with word lines in memory array banks 1912A and 1912B.

[0108] In various embodiments, the megacell 1910A also includes a global input / output (I / O) circuit 1918A and a global control circuit 1920A. The global I / O circuit 1918A may include, for example, a write driver or a sense amplifier. The global control circuit 1920A may include, for example, a clock or decoder logic. The megacell 1910B may be similar to the megacell 1910A by including a memory array bank 1912C, a memory array bank 1912D, a bit line logic circuit 1914B, a word line logic circuit 1916B, a global input / output (I / O) circuit 1918B, and a global control circuit 1920B.

[0109] As indicated by the arrows in Figure 19, megacells 1910A and 1910B can be combined to form megacell 1900. Megacell 1900 includes memory array banks 1912A-D having a single instance of bit-line logic circuit 1914, word-line logic circuit 1916, global input / output (I / O) circuit 1918, and global control circuit 1920. Thus, megacell 1900 may have a reduced area cost compared to the combination of megacells 1910A and 1910B.

[0110] The megacell 1900 can be formed by mounting word lines on both the upper and lower metal layers. For example, in the illustrated embodiment, the megacell 1900 includes word lines 1930A and 1930B for connection to memory array banks 1912A and 1912C, respectively. Similar word lines may be provided to memory array banks 1912B and 1912D.

[0111] In certain embodiments, word line 1930A is located in the upper metal layer and word line 1930B is located in the back metal layer. As shown in Figure 19, the distance that word line 1930B must travel to connect to a memory cell in memory array bank 1912C is longer than the distance that word line 1930A must travel to connect to a memory cell in memory array bank 1912A. Due to this longer distance, word line 1930B can be located in the back metal layer, as the back metal layer typically has metal wiring with lower resistance than the upper metal layer. Using the low-resistance back metal layer for word line 1930B also eliminates the need for repeaters that may be required for upper metal layer word lines connecting to memory array bank 1912C or memory array bank 1912D. Thus, megacell 1900 offers better area utilization, as well as better performance and power metrics, compared to the combination of megacells 1910A and 1910B.

[0112] In various embodiments, wide memory megacells, which may have a large area cost, can be converted to taller and narrower memory megacells to reduce area requirements. Figure 20 shows a top view of a tall memory megacell replacing a wide memory megacell according to several embodiments. In the illustrated embodiments, megacell 2000 is a wide memory megacell. Megacell 2000 includes memory array banks 2012A, 2012B, 2012C, and 2012D. Memory array banks 2012A and 2012B are separated by a bit-line logic circuit 2014A and connected to the bit-line logic circuit 2014A, while memory array banks 2012C and 2012D are separated by a bit-line logic circuit 2014B and connected to the bit-line logic circuit 2014B.

[0113] Megacell 2000 includes a word line logic circuit 2016 (integrated with each of memory array banks 2012A-D), a global I / O circuit 2018, and a single instance of the global control circuit 2020. As shown in Figure 20, megacell 2000 may be converted to megacell 2050. Megacell 2050 may have a structure similar to memory array 1800 shown in Figure 18, having memory array banks 2012A-D and a single instance of the bit line logic circuit 2014, word line logic circuit 2016, global I / O circuit 2018, and global control circuit 2020.

[0114] The conversion to the megacell 2050 can be provided, similar to the memory array 1800, by implementing word lines on both the upper and lower metal layers. For example, in the illustrated embodiment, the megacell 2050 includes word line 2030A in the upper metal layer for connection to memory array bank 2012A and word line 2030B in the lower metal layer for connection to memory array bank 2012C. Thus, the megacell 2050 offers better area utilization, as well as better performance and power metrics, compared to the megacell 2000. Further area savings are also observed in the megacell 2050, where the width of the word line logic circuit 2016 is reduced compared to the megacell 2000.

[0115] Based on this disclosure of bit line mounting configurations in both the upper and lower metal layers, various embodiments of hierarchical bit line layouts can also be conceived. Figure 21 shows a top view of a memory array with hierarchical bit lines according to several embodiments. In the illustrated embodiments, the memory array 2100 is a memory array having bit lines that span bit cells 2110 in two upper metal layers. For example, bit line 2120A may be in the first metal layer, and bit line 2120B may be in the second metal layer.

[0116] Hierarchical routing of bit lines can be implemented by jumping from bit line 2120A to bit line 2120B in the transition between bit cell bank 2130A and bit cell bank 2130B, as shown in Figure 21. Bit cells 2110 within bit cell bank 2130 can share resources (such as sensing amplifiers) to reduce bit line capacitance for large data caches (e.g., caches with 512 word lines). Resource sharing can also reduce the number of local I / O connections required within memory array 2100.

[0117] By adding bit line routing to the back metal layer, bit line capacitance can be further reduced. For example, memory array 2150 includes three bit lines 2170A, 2170B, and 2170C that span bit cell 2160. Bit line 2170A is in the first metal layer within the back metal layer, bit line 2170B is in the first metal layer, and bit line 2170C is in the second metal layer within the upper metal layer. Thus, three bit cell banks 2180A, 2180B, and 2180C can be generated by the hierarchy of bit lines 2170A, 2170B, and 2170C. Exemplary computer system

[0118] Referring next to Figure 22, a block diagram of one embodiment of system 2200 is shown, which can incorporate and / or utilize the methods and mechanisms described herein. In the illustrated embodiment, system 2200 includes at least one instance of system-on-chip (SoC) 2206, which may include multiple types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other methods, a communication fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors within SoC 2206 include multiple execution lanes and similar instruction issue queues. In various embodiments, SoC 2206 is coupled to external memory 2202, peripherals 2204, and a power supply 2208.

[0119] A power supply 2208 is also provided, which supplies a supply voltage to the SoC 2206 and one or more supply voltages to the memory 2202 and / or peripheral devices 2204. In various embodiments, the power supply 2208 represents a battery (e.g., a rechargeable battery for a smartphone, laptop, tablet computer, or other device). In some embodiments, two or more instances of the SoC 2206 are included (and two or more external memories 2202 are also included).

[0120] Memory 2202 refers to any type of memory, including dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3, and / or low-power versions of SDRAM such as LPDDR2), RAMBUS DRAM (RDRAM), and static RAM (SRAM). One or more memory devices are connected to a circuit board to form memory modules such as single in-line memory modules (SIMMs) and dual in-line memory modules (DIMMs). Alternatively, the devices are mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0121] The peripheral device 2204 may include any desired circuit configuration depending on the type of system 2200. For example, in one embodiment, the peripheral device 2204 includes devices for various wireless communications such as Wi-Fi, Bluetooth, cellular, and global positioning systems. In some embodiments, the peripheral device 2204 may also include additional storage, including RAM storage, solid-state storage, or disk storage. The peripheral device 2204 may also include user interface devices such as a display screen including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, and a speaker.

[0122] As illustrated, System 2200 is shown to be applicable to a wide range of areas. For example, System 2200 may be used as part of the chips, circuits, components, etc., of a desktop computer 2210, a laptop computer 2220, a tablet computer 2230, a cellular or mobile phone 2240, or a television 2250 (or a set-top box connected to a television). A smartwatch and a health monitoring device 2260 are also illustrated. In some embodiments, the smartwatch may include a variety of general-purpose computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device may monitor the user's vital signs, track the user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any of the health monitoring-related functions. Other wearable devices, such as devices worn around the neck, implantable devices in the human body, and glasses designed to provide augmented and / or virtual reality experiences, are also intended.

[0123] System 2200 may be further used as part of one or more cloud-based services 2270. For example, the aforementioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 2200 may be used in one or more devices in a home 2280 other than those described above. For example, appliances in a home may monitor and detect conditions of note. For example, various devices in a home (e.g., refrigerators, cooling systems, etc.) may monitor the status of the devices and alert the homeowner (or repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in the home and automate the adjustment of the heating / cooling system based on the homeowner's response history to various conditions. Figure 22 also shows the application of System 2200 to various modes of transport 2290. For example, System 2200 may be used in control systems and / or entertainment systems for aircraft, trains, buses, rental vehicles, private cars, ships ranging from privately owned boats to cruise ships, and scooters (rented or owned). In various cases, System 2200 can be used to provide automatic guidance (e.g., autonomous vehicles), general system control, and other methods. Many other embodiments of these are possible and contemplated. Note that the devices and applications illustrated in Figure 22 are illustrative and not intended to limit. Other devices are possible and contemplated. ***

[0124] This disclosure includes references to “one embodiment” or a group of “embodiments” (e.g., “several embodiments” or “various embodiments”). Embodiments are different implementations or examples of the disclosed concept. References to “one embodiment,” “one embodiment,” “a particular embodiment,” etc., do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, and modifications or substitutions within the spirit or scope of this disclosure are intended.

[0125] This disclosure may discuss the potential benefits that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily demonstrate any or all of the potential benefits. Whether a benefit is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation within the claims may not exhibit some or all of any disclosed benefits. For example, a particular implementation may include other circuits outside the scope of this disclosure that, together with one of the disclosed embodiments, negate or reduce one or more of the disclosed benefits. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation technique or tool) may also negate or reduce the disclosed benefits. Even assuming skilled execution, the realization of benefits may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, the inputs supplied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on certain occasions, and as a result, the benefits of the solution may not be realized. Given the existence of possible external factors of this disclosure, it is expressly intended that any potential benefits described herein should not be construed as limitations on claims that must be satisfied to demonstrate infringement. Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvements available to designers who have an interest in this disclosure. The acceptable description of such benefits (e.g., the statement that a particular benefit "may occur") is not intended to convey any doubt as to whether such benefits can actually be realized, but rather to acknowledge the technical reality that the realization of such benefits often depends on additional factors.

[0126] Unless otherwise specified, the embodiments are non-limiting. That is, even if only a single embodiment describes a particular feature, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure. The disclosed embodiments are intended to be illustrative, not limiting, unless there is a statement to the contrary in this disclosure. The foregoing is intended to enable claims that cover not only the disclosed embodiments but also alternatives, modifications, and equivalents that would be obvious to a person skilled in the art who would benefit from this disclosure.

[0127] For example, the features of this application can be combined in any preferred manner. Therefore, new claims can be formulated for any such combination of features during the examination of this application (or an application claiming priority to this application). In particular, referring to the attached claims, features from dependent claims can be combined with features from other dependent claims, including claims dependent on other independent claims, as appropriate. Similarly, features from each independent claim can be combined as appropriate.

[0128] Accordingly, each of the attached dependent claims may be constructed to depend on a single other claim, but additional dependencies are also contemplated. Any combination of features in the dependent claims that are consistent with this disclosure is contemplated and may be claimed in this application or another application. In summary, the combinations are not limited to those specifically enumerated in the attached claims.

[0129] Where appropriate, claims prepared in one format or legal type (e.g., apparatus) are intended to also support corresponding claims in another format or legal type (e.g., method). ***

[0130] As this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The following paragraphs, and the definitions provided through this disclosure, are hereby publicly noted as being used in interpreting the claims made pursuant to this disclosure.

[0131] References to singular items (i.e., nouns or noun phrases preceded by "a," "an," or "the") are intended to mean "one or more" unless explicitly stated in the context. Therefore, references to "items" in the claims do not, without context, preclude additional instances of an item. "Multiple" items refer to a set of two or more items.

[0132] In this specification, the word "may" is used in an allowable sense (i.e., possible, feasible) and not in an obligatory sense (i.e., not required).

[0133] The terms and forms "comprising" and "including" are open-ended and mean "to include, but not to limit."

[0134] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless otherwise explicitly stated in the context. Thus, the enumeration of “x or y” is equivalent to “x or y, or both,” and therefore includes 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase “either x or y, but not both” clarifies that “or” is used in an exclusive sense.

[0135] The enumerations "w, x, y, z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities, including single elements up to the total number of elements in the set. For example, in the set [w, x, y, z], these expressions cover any single element in the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0136] In this disclosure, various “labels” may precede nouns or noun phrases. Unless otherwise explicitly stated in the context, the various labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different examples of the feature. Furthermore, when applied to features, the labels “first,” “second,” and “third” do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0137] As used herein, the phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision; that is, the decision may be based on the specified factor alone, or on the specified factor and other unspecified factors. Consider the phrase "determine A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover even one embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0138] The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not preclude the possibility that additional factors may influence, or otherwise trigger, the effect, either in conjunction with or independently of a specific factor. That is, the effect may depend on these factors alone, or on the specified factor and other unspecified factors. Consider the phrase “perform A in response to B.” This phrase means that B is a factor that triggers the performance of A, or a specific outcome with respect to A. This phrase does not preclude the performance of A from also being in response to other factors, such as C. This phrase also does not preclude the performance of A from being in response to both B and C. This phrase is intended to include an embodiment in which A is performed solely in response to B. As used herein, the phrase “in response to” is synonymous with the phrase “in response to at least partially.” Similarly, the phrase “in response to” is synonymous with the phrase “in at least partially.” ***

[0139] Within this disclosure, various entities (which may be referred to as "units," "circuits," or other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The expression “configured to perform one or more tasks” is used herein to refer to structures (i.e., physical things). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks while in operation. A structure may be said to be “configured” to perform some task even when it is not currently in operation. Thus, entities described or explained as “configured” to perform some task refer to physical things such as devices, circuits, systems having a processor unit and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0140] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. Even if not specifically stated, it is understood that those entities are "configured" to perform those tasks / operations.

[0141] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After proper programming, the FPGA can then be said to be "configured" to perform a particular function.

[0142] For the purposes of a U.S. patent application based on this disclosure, any claim that states a structure is “configured” to perform one or more tasks is not expressly intended to invoke Section 112(f) of the U.S. Patent Act with respect to that claim element. If an applicant wishes to invoke Section 112(f) during the examination process of a U.S. patent application based on this disclosure, it would use “means for” performing the function to describe the claim element.

[0143] This disclosure may describe various “circuits.” These circuits or “circuit configurations” constitute hardware that includes various types of circuit elements, such as combinational logic, clock memory devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), and programmable logic arrays. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuit configurations may include digital components, analog components, or a combination of both, as needed. Certain types of circuits may be generally referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), function units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit configurations.

[0144] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoder unit” may be described as performing the function of “processing the opcode of an instruction and routing the instruction to one or more of several functional units,” meaning that the decoder unit is “configured” to perform this function. The detail of this function is sufficient to imply to a person skilled in the art of computer technology a set of possible structures of the circuit.

[0145] In various embodiments, as described in the previous paragraph, circuits, units, and other elements defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to each other, and the way they interact, form the microarchitecture definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation form of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementation forms can be derived, and all of its implementation forms belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art presented with the microarchitecture definition provided pursuant to this disclosure can implement the structure by coding the circuit / unit / component description in a hardware description language (HDL) such as Verilog or VHDL using ordinary art, without excessive experimentation. The HDL description is often expressed in a form that appears to be functional. However, to a person skilled in the art, this HDL description is a method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions can take the form of operation-level code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable, in contrast to operation-level code), or structure code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry, generating a mask, and ultimately manufacturing the integrated circuit. Some hardware circuits or parts thereof can also be custom designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuits. The integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, and inductors), as well as interconnects between transistors and circuit elements.In some embodiments, multiple integrated circuits connected integrally can be implemented to realize the hardware circuit, and / or, in some embodiments, separate elements can be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented on an FPGA. This decoupling between the design of this group of circuits and the subsequent low-level implementation of these circuits generally leads to scenarios where the circuit or logic designer does not specify any particular set of structures for the low-level implementation form, other than a description of how the circuit is configured, because this process is performed at different stages of the circuit implementation process.

[0146] The fact that the same specifications of a circuit can be implemented using many different low-level combinations of circuit elements results in a multitude of equivalent structures for that circuit. As mentioned above, these low-level circuit implementation forms can vary depending on changes in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. Often, the choice made by different design tools or methods to generate these different implementation forms can be arbitrary.

[0147] Furthermore, in a given embodiment, a single implementation of a specific functional specification of a circuit typically involves a large number of devices (e.g., millions of transistors). Therefore, given this sheer volume of information, it is impractical to fully enumerate the low-level structures used to implement a single embodiment, let alone a vast number of equivalent possible implementations. For this reason, this disclosure describes the circuit structure using functional omissions commonly used in the industry.

Claims

1. It is a device, circuit board and A transistor having a gate region, a source region, and a drain region positioned above the substrate in a vertical dimension perpendicular to the substrate, A first metal layer positioned above the transistor in the aforementioned vertical dimension, A second metal layer positioned below the transistor in the aforementioned vertical dimension, A first rail connected to both the first metal layer and the second metal layer, The present invention comprises a second rail connected to both the first metal layer and the second metal layer, The apparatus wherein at least one of the source region and the drain region is connected to at least one of the first rail and the second rail via connections to both the first metal layer and the second metal layer.

2. The apparatus according to claim 1, wherein the first metal layer is disposed on the upper side of the substrate.

3. The apparatus according to claim 1, wherein the second metal layer is disposed on the back side of the substrate.

4. The apparatus according to claim 1, wherein the first rail and the second rail are power rails connected to one or more power sources.

5. The apparatus according to claim 1, wherein the first rail and the second rail are signal rails for the source region and the drain region.

6. The apparatus according to claim 1, wherein the source region is connected to the first rail via connections to both the first metal layer and the second metal layer, and the drain region is connected to the second rail via connections to both the first metal layer and the second metal layer, respectively.

7. The apparatus according to claim 6, further comprising: at least one via connecting the source region to the first metal layer; and at least one via connecting the source region to the second metal layer.

8. The apparatus according to claim 6, further comprising: at least one via connecting the drain region to the first metal layer; and at least one via connecting the drain region to the second metal layer.

9. The apparatus according to claim 1, further comprising at least one via connecting the gate region to at least one of the first metal layer and the second metal layer.

10. A non-temporary computer-readable storage medium that stores multiple instructions, wherein, when the multiple instructions are executed, they generate an integrated circuit device, and the integrated circuit device is circuit board and A transistor having a gate region, a source region, and a drain region positioned above the substrate in a vertical dimension perpendicular to the substrate, A first metal layer positioned above the transistor in the aforementioned vertical dimension, A second metal layer positioned below the transistor in the aforementioned vertical dimension, A first rail connected to both the first metal layer and the second metal layer, The present invention comprises a second rail connected to both the first metal layer and the second metal layer, The source region is connected to the first rail via connections to both the first metal layer and the second metal layer, A non-temporary computer-readable storage medium, wherein the drain region is connected to the second rail via connections to both the first metal layer and the second metal layer, respectively.

11. The non-temporary computer-readable storage medium according to claim 10, wherein the source region receives a first portion of the current from a power source that supplies a supply voltage through the first metal layer, and receives a second portion of the current from the power source that supplies the supply voltage through the second metal layer.

12. The non-temporary computer-readable storage medium according to claim 11, wherein the first portion of the current and the second portion of the current are controlled based on the resistance of the first metal layer and the second metal layer.

13. The non-temporary computer-readable storage medium according to claim 10, wherein the first metal layer includes a power routing connected to the first rail and a ground routing connected to the second rail, the source region being connected to the power routing in the first metal layer and the drain region being connected to the ground routing in the first metal layer.

14. The non-temporary computer-readable storage medium according to claim 10, wherein the second metal layer includes a power routing connected to the first rail and a ground routing connected to the second rail, the source region being connected to the power routing in the second metal layer and the drain region being connected to the ground routing in the second metal layer.

15. An integrated circuit device, circuit board and A transistor having a gate region, a source region, and a drain region, A first metal layer positioned vertically above the transistor toward the upper side of the substrate, the first metal layer having power routing and ground routing, A second metal layer positioned vertically below the transistor toward the back side of the substrate, the second metal layer having power routing and ground routing, A first contact between the power routing within the first metal layer and the source region, A second contact between the ground routing and the drain region within the first metal layer, A third contact between the power routing within the second metal layer and the source region, An integrated circuit device comprising: a fourth contact between the ground routing and the drain region within the second metal layer.

16. The device according to claim 15, wherein the power routing and ground routing within the first metal layer are connected to a power source.

17. The device according to claim 16, wherein the power routing and ground routing within the second metal layer are connected to the power supply.

18. The device according to claim 17, wherein the source region is configured to receive a first portion of the current from the power source through the power routing in the first metal layer, and the source region is configured to receive a second portion of the current from the power source through the power routing in the second metal layer.

19. The device according to claim 15, wherein the first contact and the second contact are located in a first insulating layer vertically above the transistor, and the third contact and the fourth contact are located in a second insulating layer vertically below the transistor.

20. The device according to claim 15, wherein the gate region is connected to at least one of the first metal layer and the second metal layer using vias that penetrate the insulating layer on the transistor.

21. It is a device, A first transistor formed within the transistor region of an integrated circuit, A first metal layer is positioned above the transistor region in a vertical dimension perpendicular to the transistor region, A second metal layer is positioned below the transistor region in the aforementioned vertical dimension, A first wire is placed in the first metal layer and connected to the signal input of the first transistor, A second wire disposed within the second metal layer, the second wire passing under the first transistor in the vertical dimension and from the first side of the first transistor to the second side of the first transistor in the horizontal dimension perpendicular to the vertical dimension, A device comprising: a control signal routed to the signal input of the first transistor, wherein the control signal is routed from the second side of the first transistor through the second wire to the first side of the first transistor, then routed from the second wire to the first wire, and routed to the signal input of the first transistor.

22. The apparatus according to claim 21, further comprising a power rail connected to a third wire in the first metal layer and a fourth wire in the second metal layer, wherein the first transistor is connected to the power rail via the third wire and the fourth wire.

23. The apparatus according to claim 21, further comprising a second transistor formed within the transistor region, wherein the first transistor and the second transistor are separated in the horizontal dimension.

24. The apparatus according to claim 23, wherein the control signal is routed between the signal output of the second transistor and the signal input of the first transistor.

25. The apparatus according to claim 21, further comprising at least one via structure for connecting the first wire to the second wire.

26. The apparatus according to claim 25, wherein the at least one via structure includes at least one inactive doped region within the transistor region.

27. The apparatus according to claim 21, wherein the first metal layer is arranged on the upper side of the transistor region and the second metal layer is arranged on the back side of the transistor region.

28. The apparatus according to claim 21, wherein the control signal is routed below the first transistor in the vertical dimension.

29. The apparatus according to claim 21, further comprising at least one via between the first wire and the first transistor.

30. It is a device, A first transistor formed within the transistor region of an integrated circuit, A first metal layer is positioned above the transistor region in a vertical dimension perpendicular to the transistor region, A second metal layer is positioned below the transistor region in the aforementioned vertical dimension, A first wire is placed in the first metal layer and connected to the signal input of the first transistor, A second wire disposed within the second metal layer, the second wire passing under the first transistor in the vertical dimension and from the first side of the first transistor to the second side of the first transistor in the horizontal dimension perpendicular to the vertical dimension, A via structure for connecting the first wire to the second wire, the via structure being located on the first side of the first transistor, A device comprising: a control signal routed to the signal input of the first transistor, wherein the control signal is routed to the signal input of the first transistor through the second wire, through the at least one via structure, and through the first wire.

31. The apparatus according to claim 30, further comprising a second transistor formed within the transistor region, wherein the control signal is routed between the signal output of the second transistor and the signal input of the first transistor.

32. The apparatus according to claim 30, wherein the at least one via structure includes at least one doped region within the transistor region and one or more via connections between the first wire and the second wire.

33. The apparatus according to claim 30, wherein the at least one via structure includes two or more via structures connected in parallel between the first wire and the second wire.

34. The apparatus according to claim 33, wherein the two or more via structures are connected to each other within the first metal layer.

35. The apparatus according to claim 30, wherein the at least one via structure is located at the end of the apparatus.

36. It is a device, The transistor region of an integrated circuit, A first transistor having a first gate region, a first source region, and a first drain region arranged in the transistor region, A second transistor having a second gate region, a second source region, and a second drain region arranged in the transistor region, and positioned on the first side of the first transistor in a horizontal dimension parallel to the transistor region, A first metal layer is positioned above the transistor region in a vertical dimension perpendicular to the transistor region, A second metal layer is positioned below the transistor region in the aforementioned vertical dimension, A first connection between the first gate region and the first wire disposed in the first metal layer, A second connection between the second gate region and the second wire disposed in the second metal layer, At least one via structure connecting the first wire to the second wire, the at least one via structure located on the second side of the first transistor in the horizontal dimension, A device comprising: a control signal routed from the second gate region to the first gate region, the control signal proceeding from the second gate region to the second wire via the second connection, from the second wire to the at least one via structure, from the at least one via structure to the first wire, and from the first wire to the first gate region via the first connection.

37. The apparatus according to claim 36, wherein the first source region and the first drain region are connected to additional wiring in the first metal layer and the second metal layer, and the second source region and the second drain region are connected to additional wiring in the first metal layer and the second metal layer.

38. The apparatus according to claim 36, wherein the at least one via structure includes at least one doped region within the transistor region and one or more via connections between the first wire and the second wire.

39. The apparatus according to claim 36, wherein the at least one via structure includes two or more via structures connected in parallel between the first wire and the second wire.

40. The apparatus according to claim 36, wherein the second connection includes at least one via between the second wire and the second transistor.

41. A memory device, A plurality of bit cells, wherein the bit cells are arranged adjacent to each other, and the plurality of bit cells include a first bit cell adjacent to a second bit cell, A first metal layer positioned above the plurality of bit cells in a vertical dimension perpendicular to the plurality of bit cells, A second metal layer positioned below the plurality of bit cells in the vertical dimension perpendicular to the plurality of bit cells, A first bit line spanning the first bit cell, wherein the first bit line includes a wire disposed within the first metal layer, and the wire disposed within the first metal layer is connected to the first bit cell. A memory device comprising: a second bit line spanning the second bit cell, wherein the second bit line includes a wire disposed within the second metal layer, and the wire disposed within the second metal layer is connected to the second bit cell.

42. The apparatus according to claim 41, wherein the first bit wire includes an additional wire disposed in the first metal layer, and the wire disposed in the first metal layer and the additional wire disposed in the first metal layer are configured as a complementary pair.

43. The apparatus according to claim 41, wherein the second bit wire includes an additional wire disposed in the second metal layer, and the wire disposed in the second metal layer and the additional wire disposed in the second metal layer are configured as a complementary pair.

44. A third bit cell adjacent to the second bit cell in the plurality of bit cells, which is on the opposite side of the second bit cell from the perspective of the first bit cell, A third bit line spanning the third bit cell, wherein the third bit line includes an additional wire disposed within the first metal layer, and the additional wire disposed within the first metal layer is connected to the third bit cell. The apparatus according to claim 41, further comprising the following:

45. A fourth bit cell adjacent to the third bit cell in the plurality of bit cells, which is on the opposite side of the third bit cell from the second bit cell, A fourth bit line spanning the fourth bit cell, wherein the fourth bit line includes an additional wire disposed within the second metal layer, and the additional wire disposed within the second metal layer connects to the fourth bit cell. The apparatus according to claim 44, further comprising the following:

46. The first bit line and the second bit line span the plurality of bit cells in the first direction, and the device, A first word line that spans the plurality of bit cells in a second direction, wherein the second direction is perpendicular to the first direction, and the first word line includes an additional wire disposed within the first metal layer, The apparatus according to claim 41, further comprising: a second word line extending across the plurality of bit cells in the second direction, the second word line including an additional wire disposed within the second metal layer.

47. The apparatus according to claim 46, wherein the first word line is connected to the second bit cell, and the second word line is connected to the first bit cell.

48. The apparatus according to claim 41, wherein the first bit line is parallel to the second bit line.

49. The apparatus according to claim 41, wherein the bit cells are arranged adjacent to each other in a first direction, and the first bit line and the second bit line span the plurality of bit cells in a second direction perpendicular to the first direction.

50. A memory device, A plurality of bit cells, wherein the bit cells are arranged adjacent to each other, and the plurality of bit cells include a first bit cell adjacent to a second bit cell, A first metal layer positioned above the plurality of bit cells in a vertical dimension perpendicular to the plurality of bit cells, A second metal layer positioned below the plurality of bit cells in the vertical dimension perpendicular to the plurality of bit cells, A first word line spanning the plurality of bit cells, wherein the first word line includes a wire disposed within the first metal layer, and the wire disposed within the first metal layer connects to the first bit cell, A memory device comprising: a second word line spanning the plurality of bit cells, wherein the second word line includes a wire disposed within the second metal layer, and the wire disposed within the second metal layer is connected to the second bit cell.

51. The apparatus according to claim 50, further comprising a third bit cell adjacent to the second bit cell in the plurality of bit cells, wherein the third bit cell is on the opposite side of the second bit cell as seen from the first bit cell, and the wire disposed in the first metal layer is connected to the third bit cell.

52. The apparatus according to claim 51, further comprising a fourth bit cell adjacent to the third bit cell in the plurality of bit cells, wherein the fourth bit cell is on the opposite side of the third bit cell as seen from the second bit cell, and the wire disposed in the second metal layer is connected to the fourth bit cell.

53. The apparatus according to claim 50, wherein the bit cells are arranged adjacent to each other in a first direction, and the first word line and the second word line span across the plurality of bit cells in the first direction.

54. The first word line and the second word line span the plurality of bit cells in the first direction, and the device, A first bit line that spans the first bit cell in a second direction, wherein the second direction is perpendicular to the first direction, and the first bit line includes an additional wire disposed within the first metal layer, The apparatus according to claim 50, further comprising: a second bit line extending in the second direction to the second bit cell, the second bit line including an additional second wire disposed within the second metal layer.

55. The apparatus according to claim 50, further comprising a word line logic cell connected to the first word line and the second word line, wherein the word line logic cell is configured to provide separate control signals to the first word line and the second word line.

56. It is a system, The transistor region of an integrated circuit, A first metal layer is positioned above the transistor region in a vertical dimension perpendicular to the transistor region, A second metal layer is disposed below the transistor region in the vertical dimension perpendicular to the transistor region, Word line logic circuits and A first bank of memory cells arranged adjacent to the word line logic circuit, From the word line logic circuit, a second bank of memory cells is located adjacent to the first bank on the opposite side of the first bank, A first word line extending from the word line logic circuit into the memory cell in the first bank, the first word line including a wire disposed in the first metal layer, the wire disposed in the first metal layer connecting to the memory cell in the first bank, A system comprising: a second word line extending from the word line logic circuit into the memory cell in the second bank, the second word line passing through the memory cell in the first bank and including a wire disposed in the second metal layer, the wire disposed in the second metal layer connecting to the memory cell in the second bank.

57. The system according to claim 56, further comprising a bit line logic circuit adjacent to the first bank and the second bank and spanning the length of the first bank and the second bank.

58. A third bank of memory cells is arranged adjacent to the word line logic circuit, The word line logic circuit further comprises a fourth bank of memory cells located adjacent to the third bank on the opposite side of the third bank, The third bank and the fourth bank are adjacent to the bit line logic circuit on the opposite side of the first bank and the second bank from the bit line logic circuit. The system according to claim 57.

59. A third word line extending from the word line logic circuit into the memory cell in the third bank, which is a third wire disposed within the first metal layer and connected to the memory cell in the third bank, A fourth word line extending from the word line logic circuit into the memory cell in the fourth bank, passing through the memory cell in the third bank, and being a fourth wire disposed within the second metal layer, and connecting to the memory cell in the fourth bank, The system according to claim 58, further comprising the following:

60. The system according to claim 56, further comprising a global control logic circuit connected to the first bank and the second bank of memory cells, wherein the global control logic circuit includes one or more clocks and one or more decoders.

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