Photoelectric conversion devices and equipment

Abstract

This technology offers advantages in suppressing the multiplier increase. [Solution] A photoelectric conversion device is provided on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the photoelectric conversion device comprises: a first region of a first conductivity type that constitutes a part of the first main surface and is connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type that is located away from the first region; a third region of a second conductivity type opposite to the first conductivity type that is located closer to the second main surface than the first and second regions; and a fourth region located between the first and second regions, wherein the second and third regions function as an avalanche photodiode, and the first and second regions are configured to be electrically conductive through the fourth region.

Description

[Technical Field]

[0001] This invention relates to a photoelectric conversion device and apparatus. [Background technology]

[0002] A single-photon avalanche diode (SPAD) is known as a photodetector capable of detecting weak light at the single-photon level by utilizing avalanche (electron avalanche) multiplication. Patent document 1 shows a photodetector having pixels that include an avalanche photodiode (APD) functioning as a SPAD. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-064086 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Let's consider the charge multiplication factor in an APD. In a SPAD, generally, a voltage is applied between the cathode and anode of the APD, which is the breakdown voltage Vbd plus an excess bias Vex. Avalanche breakdown is detected by the change (decrease) in the cathode potential when an avalanche current flows. If the cathode capacitance of the APD is Cc and the change in cathode potential when avalanche breakdown occurs is ΔV, then the amount of charge discharged from the cathode due to avalanche breakdown is expressed as Cc × ΔV. If the unit charge is qe, then the number of electron-hole pairs produced in one avalanche breakdown, i.e., the carrier multiplication factor, is expressed as Cc × ΔV / qe. Since the charge multiplication factor and the carrier multiplication factor are the same, we will simply refer to them as multiplication factors below. The cathode capacitance Cc has a large capacitive component due to the wiring pattern connected to the cathode and the detection circuit for detecting avalanche breakdown, for example, around 8 fF. Furthermore, if the change in cathode potential ΔV at which avalanche breakdown is detected is set to ΔV = 2.4V, which is about the same as the excess bias Vex, the amplification factor becomes 120,000. While a high amplification factor makes it possible to detect weak light at the single-photon level, it also presents the following challenges.

[0005] The numerous carriers generated by avalanche breakdown flow between the anode and cathode to which the breakdown voltage Vbd is applied. Therefore, a large current flows due to the incidence of a single photon, consuming a significant amount of energy. As more pixels are arranged and the number of incident photons increases, the energy consumption increases.

[0006] The present invention aims to provide a technology that is advantageous in suppressing the magnification ratio. [Means for solving the problem]

[0007] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device in which a photoelectric conversion unit is disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the photoelectric conversion unit includes a first region of a first conductivity type that constitutes a part of the first main surface and is connected to a detection circuit for detecting avalanche breakdown, a second region of the first conductivity type disposed away from the first region, a third region of a second conductivity type opposite to the first conductivity type disposed closer to the second main surface than the first region and the second region, and a fourth region disposed between the first region and the second region, and the second region and the third region function as an avalanche photodiode, and the first region and the second region are configured to be electrically connected through the fourth region.

Effects of the Invention

[0008] According to the present invention, a technique advantageous for suppressing the multiplication factor can be provided.

Brief Description of the Drawings

[0009] [Figure 1] A diagram showing a configuration example of the photoelectric conversion device of the present embodiment. [Figure 2] A block diagram showing a configuration example of a pixel of the photoelectric conversion device of FIG. 1. [Figure 3] A diagram showing an operation example of a pixel of the photoelectric conversion device of FIG. 2. [Figure 4] A diagram showing an operation example of a pixel of the photoelectric conversion device of FIG. 2. [Figure 5] A plan view showing a configuration example of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 6] A cross-sectional view showing a configuration example of an APD and a PD of FIG. 5. [Figure 7] A diagram showing an equivalent circuit diagram and an operation example of a pixel of FIG. 5. [Figure 8] A plan view showing a configuration example of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 9] A cross-sectional view showing a configuration example of an APD and a PD of FIG. 5. [Figure 10]A plan view showing an example of the configuration of the APD and PD pixels of the photoelectric converter in Figure 1. [Figure 11] Figure 10 is a cross-sectional view showing an example of the configuration of APD and PD. [Figure 12] Figure 11 shows a cross-sectional view illustrating modified APD and PD. [Figure 13] Figure 1 is a cross-sectional view showing an example of the configuration of the APD and PD pixels in the photoelectric converter. [Figure 14] Figure 1 is a cross-sectional view showing an example of the configuration of the APD and PD pixels in the photoelectric converter. [Figure 15] Figure 1 is a cross-sectional view showing an example of the configuration of the APD and PD pixels in the photoelectric converter. [Figure 16] Figure 15 shows a part of the pixel manufacturing method. [Figure 17] Figure 1 is a cross-sectional view showing an example of the configuration of the APD and PD pixels in the photoelectric converter. [Figure 18] Figure 17 shows a part of the pixel manufacturing method. [Figure 19] This figure shows the distribution of impurity ions in the depth direction of the semiconductor substrate in pixel regions 204, 238, and 239 of Figure 17. [Figure 20] Figure 1 shows an equivalent circuit diagram illustrating an example of the pixel configuration of the photoelectric converter. [Figure 21] A plan view showing an example of the configuration of the APD and PD pixels of the photoelectric converter in Figure 1. [Figure 22] Figure 21 is a cross-sectional view showing an example of the configuration of APD and PD. [Figure 23] Figure 21 shows the equivalent circuit diagram and operation example of a pixel. [Figure 24] Figure 1 shows an equivalent circuit diagram illustrating an example of the pixel configuration of the photoelectric converter. [Figure 25] Figure 24 shows an example of pixel operation. [Figure 26] This figure shows an example of the configuration of a device incorporating the photoelectric conversion device of this embodiment. [Modes for carrying out the invention]

[0010] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0011] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to Figures 1 to 26. The following embodiments are all examples of the present disclosure and do not limit the invention as defined in the claims. In the following embodiments, the signal charge carrier is electrons, and a Single Photon Avalanche Diode (SPAD) that detects changes in cathode potential due to avalanche current is described. Therefore, the semiconductor region of the first conductivity type, which has charges of the same polarity as the signal charge as majority carriers, is an N-type semiconductor region, and the semiconductor region of the second conductivity type, which is opposite to the first conductivity type, is a P-type semiconductor region. However, holes may be the signal charge carrier, or a configuration in which changes in anode potential are detected. In this case, the semiconductor region of the first conductivity type, which has charges of the same polarity as the signal charge as majority carriers, is a P-type semiconductor region, and the semiconductor region of the second conductivity type, which is opposite to the first conductivity type, is an N-type semiconductor region.

[0012] First, using Figure 1, a photoelectric converter applicable to the embodiments of this disclosure will be described based on general SPAD operation. Figure 1 is a block diagram showing an example configuration of the photoelectric converter 100 of this embodiment. The photoelectric converter 100 includes a pixel array 101, a control pulse generation circuit 115, a horizontal scanning circuit 111, a readout circuit 112, a vertical scanning circuit 110, a signal line 113, and drive lines 213 and 214. The pixel array 101 has a plurality of pixels 104 arranged in a matrix. Each pixel 104 may be configured to include a photoelectric conversion unit 102 including an avalanche photodiode (APD) and a signal processing circuit 103. The photoelectric conversion unit 102 converts light into an electrical signal. The signal processing circuit 103 outputs the converted electrical signal to the readout circuit 112.

[0013] The vertical scanning circuit 110 receives control pulses supplied from the control pulse generation circuit 115 and supplies control pulses to the pixels 104. Logic circuits such as shift registers and address decoders may be used in the vertical scanning circuit 110.

[0014] The signals output from the photoelectric conversion unit 102 of each pixel 104 are processed by the signal processing circuit 103. The signal processing circuit 103 is equipped with, for example, a counter and memory, and digital values ​​are stored in the memory.

[0015] The horizontal scanning circuit 111 inputs control pulses to the signal processing circuit 103 to sequentially select each column in order to read the signal from the memory where the digital signals of the pixels 104 are stored. For the selected column, the signal is output to the signal line 113 from the signal processing circuit 103 of the pixels selected by the vertical scanning circuit 110. The signal output to the signal line 113 is then output via the output circuit 114 to a recording device, signal processing device, or other device located outside the photoelectric converter 100.

[0016] In the configuration shown in Figure 1, pixels 104 are arranged in two dimensions in the pixel array 101. However, the configuration is not limited to this, and pixels 104 may be arranged in one dimension in the pixel array 101. The function of the signal processing circuit 103 does not necessarily need to be provided one for each pixel 104; for example, a single signal processing circuit 103 may be shared by multiple pixels 104, and signal processing may be performed sequentially.

[0017] Figure 2 is a block diagram showing an example configuration of one pixel 104 as shown in Figure 1. Using Figure 2 and Figures 3(a), 3(b), 4(a), and 4(b) described later, the basic configuration and operation of the pixel 104 including the APD will first be explained. Next, the detailed configuration of the pixel 104 in this embodiment will be explained using Figures 5 and onward.

[0018] As shown in Figure 2, an APD201 is placed in the photoelectric conversion unit 102 of the pixel 104. The APD201 generates charge pairs corresponding to the incident light through photoelectric conversion. A potential VL is supplied to the anode of the APD201. In addition, a potential VH, which is higher than the potential VL supplied to the anode, is supplied to the cathode of the APD201. As a result, a reverse bias voltage is supplied between the anode and cathode such that the APD201 performs avalanche multiplication. By supplying such a voltage, the charge generated by the incident light undergoes avalanche multiplication, and an avalanche current is generated. For simplicity, in the following explanation, we will assume VL = -Vbd and VH = Vex. Here, Vbd is the breakdown voltage of the APD201, and Vex is the excess voltage. Typically, VL is around -20V to -30V, and VH is around 2V to 3V.

[0019] As shown in Figure 2, the signal processing circuit 103 of pixel 104 may include a quench element 202, a waveform shaping circuit 210, a counter circuit 211, and a selection circuit 212. However, it is not limited to these, and the signal processing circuit 103 may also include other signal processing circuits.

[0020] The quench element 202 is connected to the supply line that supplies potential VH and to the APD201. The quench element 202 has the function of converting the change in avalanche current generated in the APD201 into a voltage signal. When the signal is multiplied by avalanche multiplication, the quench element 202 functions as a load circuit (quench circuit) and suppresses the voltage supplied to the APD201, thereby suppressing avalanche multiplication (quench operation).

[0021] The waveform shaping circuit 210 shapes the cathode potential change of the APD201 obtained during photon detection and outputs a pulse signal. As a result, the waveform shaping circuit 210 functions as a detection circuit that detects avalanche breakdown occurring in the APD201. For example, an inverter circuit may be used as the waveform shaping circuit 210. A configuration example with one inverter as the waveform shaping circuit 210 is conceivable. However, it is not limited to this, and a circuit in which multiple inverters are connected in series may be used as the waveform shaping circuit 210. In addition, other circuits that have a waveform shaping effect may be used as the waveform shaping circuit 210.

[0022] The counter circuit 211 counts the number of pulse signals output from the waveform shaping circuit 210 and stores the counted value. The value held in the counter circuit 211 is reset when a reset control pulse is supplied from the vertical scanning circuit 110 shown in Figure 1 via the drive line 213.

[0023] The selection circuit 212 receives selection control pulses from the vertical scanning circuit 110 shown in Figure 1 via the drive line 214, which switches the electrical connection between the counter circuit 211 and the signal line 113. The selection circuit 212 may include, for example, a buffer circuit for outputting a signal.

[0024] A switching element such as a transistor may be placed between the quench element 202 and the APD201, or between the photoelectric conversion unit 102 and the signal processing circuit 103, to switch the electrical connection. Similarly, the supply of potentials such as VH and VL to the photoelectric conversion unit 102 may be electrically switched using a switching element such as a transistor.

[0025] In the configuration shown in Figure 2, a counter circuit 211 is used in the signal processing circuit 103. However, the configuration is not limited to this. Instead of the counter circuit 211, a photoelectric converter 100 may be used to acquire the timing of the pulse signal output from the waveform shaping circuit 210 by using a time-to-digital converter (TDC) and memory. In this case, the generation timing of the pulse signal output from the waveform shaping circuit 210 is converted into a digital signal by the TDC. The TDC is supplied with a control pulse pREF from the vertical scanning circuit 110 via a drive line (which may be the same as drive lines 213 and 214) to measure the timing at which the pulse signal is output. The TDC acquires a digital signal with the input timing of the signal output from the pixel 104 via the waveform shaping circuit 210 as a relative time, using the control pulse pREF as a reference.

[0026] Figures 3(a) and 3(b) schematically illustrate the relationship between the operation of the APD201 and the output signal. Figure 3(a) is an excerpt of the APD201, quench element 202, and waveform shaping circuit 210 shown in Figure 2. Here, the input side of the waveform shaping circuit 210 is denoted as nodeA and the output side as nodeB. Figure 3(b) shows the potential changes at nodeA and nodeB.

[0027] From time t0 to time t1, a potential difference (voltage) of potential VH - potential VL is applied to APD201. When a photon is incident on APD201 at time t1, avalanche breakdown occurs in APD201, an avalanche multiplication current flows through the quench element 202, and the potential of nodeA drops. As the amount of potential drop increases further and the potential difference applied to APD201 decreases, the avalanche breakdown in APD201 stops, as shown at time t2, and the potential level of nodeA stops dropping below a certain value. This potential at which avalanche breakdown stops is approximately 0V, that is, the potential at which the voltage applied to APD201 is approximately Vbd. Subsequently, between time t2 and time t3, a current flows through nodeA to compensate for the potential drop from potential VL, and at time t3, nodeA settles to its original potential level. At this time, any portion of the output waveform at nodeA that exceeds a certain threshold is reshaped by the waveform shaping circuit 210 and output as a signal to nodeB.

[0028] Here, the quench element 202 and the waveform shaping circuit 210 may be formed on the same semiconductor substrate as the APD 201. However, it is not limited to this, and the chip on which the APD 201 is located and the chip on which the quench element 202 and the waveform shaping circuit 210 are located may be formed separately and stacked. For example, as shown by the dotted line in Figure 2, the chip (semiconductor substrate) on which the photoelectric conversion unit 102 is located and the chip (semiconductor substrate) on which the signal processing circuit 103 is located may be formed separately and stacked.

[0029] Figures 4(a) and 4(b) schematically illustrate the relationship between the operation of the APD201 and the output signal, which differs from the configuration shown in Figures 3(a) and 3(b). Figure 4(a) is an equivalent circuit diagram corresponding to Figure 3(a), but a P-channel (P-type) MOS (MIS) transistor 203 is used instead of the quench element 202. Figure 4(b) shows the potential changes at nodeA, nodeB, and nodeC in Figure 4(a). NodeA and nodeB are the input and output nodes, respectively, of the waveform shaping circuit 210, as in Figure 3(a). NodeC is the node connected to the gate electrode of transistor 203.

[0030] Transistor 203 is a switch for resetting the potential of node A to potential VH, and is controlled by the potential of node C. When the potential of node C, as shown in Figure 4(b), is high, transistor 203 is in the off state (non-conductive state, hereafter sometimes referred to as OFF). When the potential of node C is low, transistor 203 is in the on state (conductive state, hereafter sometimes referred to as ON). A periodic pulse is input to node C, and a part of it is shown in Figure 4(b). The operation shown in Figure 4(b) will be explained below.

[0031] First, at time t0, the potential of nodeA is reset to potential VH by transistor 203. Then, when transistor 203 is turned OFF, the potential of nodeA becomes floating at potential VH.

[0032] Assume that a photon is incident on APD201 at time t1. When avalanche breakdown occurs in APD201 due to the incident photon, the potential of nodeA decreases due to the avalanche current, and the avalanche breakdown stops at time t2. The potential of nodeA remains low and in a floating state, but when a pulse to reset nodeA is input to nodeC at time t3, the potential of nodeA is reset again to potential VH. Therefore, nodeB on the output side of the waveform shaping circuit 210 generates an avalanche breakdown detection pulse that is High from the time when the potential of nodeA reaches the judgment threshold between time t1 and time t2 until time t3.

[0033] In the operation shown in Figure 4(b), consider the case where a photon is incident between time t1 and time t3, that is, when the next photon is incident while the potential of nodeA remains low. In this case, APD201 cannot cause further avalanche breakdown for the second and subsequent photons incident between the first photon and time t3. Therefore, even if multiple photons are incident between time t1 and time t3, the number of avalanche breakdown detections in the waveform shaping circuit 210 will be 1. Also, for example, in the operation shown in Figure 4(b), if no photons are incident between time t0 and time t3, the potential of nodeA remains at potential VH, and the potential of nodeB remains at a low level. In other words, the number of avalanche breakdown detections is 0.

[0034] In the operation described using Figure 4(b), a distinction is made between whether there were zero or one or more photon incidences to APD201 during one cycle of the reset pulse input to nodeC. Therefore, if multiple photons are incident during one cycle of the reset pulse input to nodeC, a signal detection loss occurs. On the other hand, if photons are incident one after another without interruption, in the operation described using Figure 3(b), avalanche breakdown does not stop in APD201, and avalanche current continues to flow, resulting in a so-called pile-up state. In the pile-up state, the potential of nodeA remains low, so a detection pulse is not generated by the waveform shaping circuit 210, and current flows (unnecessarily) in APD201. Therefore, pile-up can be a major problem in SPAD operation in terms of power consumption.

[0035] In addition to the continuous flow of current due to pile-up, the following issues may exist in SPAD operation. These issues may arise from the large multiplication factor in SPAD operation, as mentioned above.

[0036] One problem is emission crosstalk. In the APD201, a large number of carriers are generated by the incidence of a photon. It is known that some of the generated carrier pairs cause emission through recombination. In a pixel array 101 having multiple pixels 104 (photoelectric conversion units 102), if avalanche breakdown occurs due to a photon incident on a certain pixel 104, secondary photons emitted from that pixel 104 may be incident on surrounding pixels 104, potentially becoming false signals. This is called emission crosstalk. For example, as mentioned above, if the amplification factor is 120,000 and we assume that 0.01% of the 120,000 generated carrier pairs produced by the incidence of one photon recombine, then 12 secondary photons that cause emission crosstalk will be generated.

[0037] The next problem concerns the change in dark current. Carriers generated by avalanche multiplication are accelerated in high-electric-field areas, becoming so-called hot carriers. Some of these hot carriers are trapped at the interface near the cathode of the APD201, changing the state of the interface. In the APD described in Patent Document 1, the area around the cathode is depleted, and many dark current carriers are generated from this interface. However, the electric field strength around the cathode is relatively low, and only a small portion of the carriers generated at the interface cause avalanche generation. These avalanche-causing interface-generated carriers appear as the dark current of the SPAD. When the state of the interface changes due to the capture of hot carriers, the carrier generation rate at the interface changes, and as a result, the dark current value changes. This change occurs as the SPAD continues to be used, which can lead to problems such as the initial dark current correction becoming ineffective.

[0038] Furthermore, as mentioned above, energy consumption increases as the number of signal photons increases. For example, if Vbd = 25V, it is estimated that the incidence of one photon generates 120,000 carriers and consumes about 0.5 pJ of energy. When many pixels are arranged and the number of incident photons increases, energy consumption increases. This can place a heavy load on the power supply system of the photoelectric converter 100 that operates the SPAD.

[0039] As mentioned above, the capacitance component is large due to the wiring pattern connected to the cathode of the APD201 and detection circuits such as the waveform shaping circuit 210 used to detect avalanche breakdown, resulting in a large avalanche multiplication factor. This can cause the aforementioned problems of light emission crosstalk, changes in dark current, and power consumption. If the junction capacitance of the diode at the cathode of the APD201 becomes large, the problem can become even more serious. The junction capacitance of the diode at the cathode of the APD201 is a capacitance component separate from the capacitance caused by the wiring pattern connected to the cathode of the APD201 and detection circuits such as the waveform shaping circuit 210 used to detect avalanche breakdown.

[0040] In the pile-up conditions that can occur in the operation shown in Figure 3(b), the aforementioned problems can become particularly pronounced. The operation shown in Figure 4(b) has the significant advantage of not causing such pile-ups. Signal detection loss may occur if multiple photons are incident during one cycle of the reset pulse input to nodeC, but SPAD is advantageous for photon detection in situations with few photon incidents. In situations with few photon incidents, it is unlikely that multiple photons will be incident during one cycle of the reset pulse. Therefore, it is considered that there will be almost no signal detection loss in such situations. However, problems such as emission crosstalk, changes in dark current, and power consumption due to large amplification factors can still exist in the operation shown in Figure 4(b).

[0041] The following describes in detail the photoelectric converter 100 of this disclosure, which suppresses light emission crosstalk, dark current changes, and power consumption, respectively, based on the operation shown in Figure 4(b). However, each embodiment of this disclosure is also applicable to the operation shown in Figure 3(b).

[0042] (First Embodiment) Figure 5 is a plan view of the photoelectric conversion unit 102 arranged in the pixel 104 in the first embodiment of the present disclosure. Figure 6 is a cross-sectional view of the photoelectric conversion unit 102 between A and B shown in Figure 5. Figure 5 is a plan view of the main surface 251 (first main surface) of the semiconductor substrate 250 shown in Figure 6.

[0043] The photoelectric conversion unit 102 of the pixel 104 arranged in the photoelectric conversion device 100 is formed on a semiconductor substrate 250 having a main surface 251 and a main surface 252 (second main surface) opposite to the main surface 251. In the configuration shown in Figures 5 and 6, the photoelectric conversion unit 102 includes region 204 (first region), region 206 (second region), region 208 (third region), and region 207 (fourth region).

[0044] Region 204 is a high-impurity concentration N-type conductive region that constitutes a part of the main surface 251 of the semiconductor substrate 250. Region 204 is connected to a detection circuit (for example, the waveform shaping circuit 210 described above) for detecting avalanche breakdown via a connection pattern 205. Although the connection pattern 205 does not constitute a part of the main surface 251, it is shown in Figure 5 to make the connection position between region 204 and the connection pattern 205 easier to understand. Region 206 is a high-impurity concentration N-type conductive region located away from region 204. As shown in Figure 6, region 206 may constitute a part of the main surface 251 of the semiconductor substrate 250. Unlike region 204, region 206 is not directly connected to the connection pattern 205 that leads to the detection circuit. Region 206 is connected to the connection pattern 205 via regions 207 and 204, as will be described later. Region 208 is a P-type conductive region, opposite to the N-type, located closer to the main surface 252 of the semiconductor substrate 250 than regions 204 and 206.

[0045] Region 204 may be the cathode of a photodiode (PD) containing a PN junction formed by region 204 and region 208, and region 208 may be the anode of the PD containing region 204 and region 208. Similarly, region 206 may be the cathode of an APD containing a PN junction formed by region 206 and region 208, and region 208 may be the anode of the APD containing region 206 and region 208. As shown in Figure 6, region 208 may be formed between regions 204, 206 and the main surface 252 of the semiconductor substrate 250 (below regions 204, 206 in the drawing) and extend over almost the entire surface of one pixel 104 (photoelectric conversion unit 102). As shown in Figure 6, in cross-sectional view, region 208 extends from one region 230 to the other region 230.

[0046] Region 207 is located between region 204 and region 206. Regions 204 and 206 are configured to be electrically conductive through region 207. It is preferable that region 207 has a lower impurity concentration than regions 204 and 206. In the configuration shown in Figures 5 and 6, region 207 is a low-impurity concentration N-type region that functions as a resistor connecting region 204 and region 206.

[0047] As shown in Figure 6, the photoelectric conversion unit 102 may further include regions 209, 230, 231, and 190. Region 209 is a P-type region formed to constitute the main surface 252 of the semiconductor substrate 250. Region 230 is a P-type region formed at the boundary of each pixel 104 (photoelectric conversion unit 102) to separate them from one another. Region 231 (the fifth region) is a photoelectric conversion region, a P-type or N-type region with a lower impurity concentration than regions 204 and 206, located between region 208 and the main surface 252 (region 209) of the semiconductor substrate 250. Region 190 is a region located between regions 204, 207, 206 and region 208 in the region surrounded by the main surface 251 of the semiconductor substrate 250, regions 208 and 230. Region 190 is a P-type or N-type region with lower impurity concentrations than regions 204 and 206. Regions 190 and 231 may be regions with lower impurity concentrations than regions 208, 209, and 230.

[0048] In the configuration shown in Figures 5 and 6, when light is incident on the photoelectric conversion unit 102 during the operation of the photoelectric conversion device 100, the PN junction including regions 206 and 208 functions as the APD201 described above and undergoes avalanche breakdown. On the other hand, the PN junction including regions 204 and 208 does not function as the APD201 described above and does not undergo avalanche breakdown in principle. For this reason, the PN junction including regions 204 and 208 may be referred to as the parasitic PD232 below.

[0049] To allow regions 206 and 208 to function as APD201, and to prevent regions 204 and 208 from functioning as APD201, the distance D1 between region 206 and region 208 is shorter than the distance D2 between region 204 and region 208, as shown in Figure 6. Therefore, during operation, a higher electric field is generated in the PN junction formed by region 206 and region 208 than in the PN junction formed by region 204 and region 208. As a result, a depletion region is formed in the region of region 208 that overlaps with region 206 in the orthogonal projection onto the main surface 251 of the semiconductor substrate 250. Charge generated in region 231 by the incidence of light flows into region 206 through this depletion region, causing avalanche breakdown. Region 190 is basically depleted during operation. Therefore, electrical conduction between region 204 and region 206 occurs mainly through the N-type region 207, which functions as a resistor. Furthermore, the impurity concentration of the first conductivity type in region 204 may be lower than that of the first conductivity type in region 206. This makes it less likely for avalanche breakdown to occur in regions 204 and 208.

[0050] In this embodiment, photons incident on region 231 may be incident from the main surface 251 of the semiconductor substrate 250 or from the main surface 252. Here, it is assumed that the photons are incident from the main surface 252 of the semiconductor substrate 250. In other words, the photoelectric converter 100 is a so-called back-surface incident type photoelectric converter. Furthermore, the signal processing circuit 103, including the waveform shaping circuit 210, is formed on a separate substrate that is connected to the semiconductor substrate 250 on which region 231 and APD201 are arranged via a connection pattern 205.

[0051] Figures 7(a) and 7(b) are diagrams illustrating the SPAD operation of this embodiment. Figure 7(a) shows an equivalent circuit diagram of part of the photoelectric conversion unit 102 and the signal processing circuit 103, and Figure 7(b) shows the potential changes of nodes A to D during SPAD operation. Nodes A to C are in the same positions as shown in Figure 4(a). Node D is the cathode of APD201, in other words, the potential of region 206. Node A is the potential of region 204, which is the cathode of parasitic PD232, assuming that the wiring resistance of connection pattern 205 can be ignored.

[0052] First, at time t0, transistor 203 resets the potential of nodeA and the potential of nodeD via region 207 to potential VH. Transistor 203 functions as a reset circuit to reset the potentials of regions 204 and 206 to a predetermined potential (potential VH) according to the reset pulse input to nodeC. Subsequently, when transistor 203 is turned OFF, the potentials of nodeA and nodeD become floating at potential VH.

[0053] Next, at time t1, photons are incident on the photoelectric conversion unit 102, and when avalanche breakdown occurs in APD201, the potential of nodeD decreases due to the avalanche current. At this time, the potential of nodeA also decreases due to the current flowing through region 207, but it cannot keep up with the change in the potential of nodeD, so the decrease in potential is slow. At time t2, when the avalanche breakdown stops, current flows through region 207 so that nodeA and nodeD become the same potential. In this process, the potential of nodeA exceeds the threshold of the waveform shaping circuit 210, and a pulse is generated at nodeB that detects avalanche breakdown in APD201.

[0054] In the above operation, an avalanche current flows from time t1 to time t2. Here, the configuration in which APD201 is directly connected to the waveform shaping circuit 210, as shown in Figure 4(a), is called the comparative example configuration. In the potential change shown in Figure 7(b), the potential of nodeD drops to the potential at which avalanche breakdown stops, similar to the operation shown in Figure 4(b) in the comparative example configuration. On the other hand, the potential of nodeA, to which a large capacitance component is added due to the connection pattern 205 and the waveform shaping circuit 210 (detection circuit), cannot follow the change in the potential of nodeD because region 207 functions as a resistor, and the potential change at time t2 is small. Therefore, if the capacitance component of the parasitic PD232 added to the comparative example configuration is sufficiently small compared to the other capacitance components added to nodeA, the discharge charge amount of nodeA is kept small compared to the operation of the comparative example configuration. As a result, the amplification factor of avalanche breakdown occurring in APD201 is suppressed compared to the comparative example configuration.

[0055] Here, we will provide a quantitative explanation. As a condition, we assume that the size of pixel 104 is several μm square, for example, 5 μm square. In that case, the diameters of regions 204 and 206 will be, for example, about 1 μm. Region 204, which constitutes the parasitic PD232, may be smaller than region 206. Under these conditions, the capacitance of the PN junction of region 206 is approximately 0.8 fF, the additional capacitance (parasitic capacitance) from the connection pattern 205 to the input of the waveform shaping circuit 210 is approximately 7.2 fF, and the capacitance of the PN junction of region 204 is approximately 0.6 fF. In this embodiment, the capacitance due to the presence of region 204 is increased compared to the configuration of the comparative example. However, it can be seen that the capacitance component due to region 204 is sufficiently smaller than the capacitance component due to the connection pattern 205 and the waveform shaping circuit 210 from the connection pattern 205 to the input of the waveform shaping circuit 210.

[0056] Next, we consider what resistance value should be set in region 207, which functions as a resistor, to effectively suppress the carrier amplification factor. Here, the resistance in region 207 is not necessarily ohmic resistance. The resistance value of region 207 is obtained by V1 / I1, where V1 is the potential difference between region 204 and region 206, and I1 is the current flowing through region 207.

[0057] First, let's assume that the drop in cathode (region 206) potential of APD201 when avalanche breakdown occurs is 2.4V. In this case, the avalanche current depends on the characteristics of APD201, but under the above conditions, it is approximately 50μA. Therefore, in region 206, which has a capacitance of 0.8fF, the time it takes for the potential to drop by 2.4V is approximately 40ps. At this time, in order for the potential of region 204 not to follow the potential change of region 206, the product of the resistance value of region 207 and the capacitance value of region 206, the so-called CR time constant, must be approximately 40ps or more. Under the above conditions, since the capacitance of region 206 is 0.8fF, it is calculated that the resistance value of region 207 must be approximately 50kΩ or more. In reality, it is conceivable that the conditions may change to some extent. For example, if the avalanche current is 100 μA, the time it takes for the potential of region 206 to drop by 2.4 V is 20 ps, ​​requiring a resistance of approximately 25 kΩ in region 207. Also, if the drop in cathode (region 206) potential when avalanche breakdown occurs is approximately 1.9 V, then a resistance of approximately 20 kΩ in region 207 is required. Therefore, it is preferable for region 207 to function as a resistor of 20 kΩ or more. Considering the junction capacitance of region 206 and the amount of avalanche current, it is considered that the effect of suppressing the multiplication factor cannot be expected unless the resistance of region 207 is at least approximately 20 kΩ.

[0058] On the other hand, the larger the resistance value of region 207, the greater the effect of suppressing the amplification factor. However, if the resistance value of region 207 is too large, the response time from when avalanche breakdown actually begins until it is detected becomes long. For example, if the period of the pulse input to nodeC is 20 μs, if the response time is not sufficiently shorter than the pulse period, a loss in detecting avalanche breakdown will occur. Therefore, if the required response time is 0.2 μs or less, the above time constant is 0.2 μs or less, and the upper limit of the resistance value of region 207 is estimated to be 250 MΩ. In general, it is difficult to form a resistance of several hundred MΩ within the pixel 104 (semiconductor substrate 250). Therefore, in the design of the actual pixel 104 (photoelectric conversion unit 102), the lower limit of the resistance value of region 207 is important.

[0059] As mentioned above, when avalanche breakdown occurs, the amplification factor decreases, and the magnitude of the potential change (potential drop) at nodeA also decreases. Therefore, the threshold value for determining avalanche breakdown in the waveform shaping circuit 210 needs to be set to a value corresponding to the amplification factor that has changed due to the placement of the parasitic PD232.

[0060] The embodiment described above can be summarized using Figures 5 to 7(a) and 7(b). The addition of the parasitic PD232 compared to the comparative example configuration adds capacitance to nodeA from the PN junction in region 204, which is a disadvantage from the viewpoint of suppressing the multiplication factor when avalanche breakdown occurs. However, the capacitance component of the PN junction in region 204 is sufficiently small compared to the capacitance component caused by the connection pattern 205 and the waveform shaping circuit 210. Therefore, it does not have a significant impact on the multiplication factor. On the other hand, the resistance value of region 207 can be set to an appropriate value to prevent electrical conduction between nodeA and nodeD to the desired extent. This makes it possible to significantly reduce the amount of charge discharged from nodeA when avalanche breakdown occurs compared to the SPAD operation of the comparative example configuration. In other words, the configuration of this embodiment suppresses the carrier multiplication factor when avalanche breakdown occurs, and is effective against three problems: emission crosstalk, changes in dark current, and power consumption when many photons are incident.

[0061] Here, the configurations of the parasitic PD232, APD201, and region 207 are not limited to those shown in Figures 5 and 6. For example, as shown in Figure 8, region 207 does not necessarily connect region 204 and region 206 via the shortest path, but may connect them via a bypass path. A region 207 laid out in a bypass manner increases the distance between region 204 and region 206, making it easier to increase the resistance value.

[0062] Furthermore, for example, in the configuration shown in Figure 9, the region 206 for constituting the APD201 has a two-tiered configuration consisting of region 206a and region 206b. Of region 206, region 206a is a shallow N-type region in contact with the main surface 251 of the semiconductor substrate 250, just like region 204. Of region 206, region 206b is an N-type region that is formed at a deeper location (closer to the main surface 252 of the semiconductor substrate 250) than region 206a and is continuous with region 206a.

[0063] Regions 204 and 206 shown in Figure 6 are both single-layer structures with different depths, and therefore can be formed by processes using different masks. On the other hand, region 206a of region 206 shown in Figure 9 can be formed using the same mask. Therefore, the planar positional relationship between region 204 and region 206 (region 206a) on the main surface 251 of the semiconductor substrate 250 is formed with a constant positional relationship, independent of mask misalignment. This leads to the stable formation of the resistance value of region 207, which is an electrical conduction connecting region 204 and region 206. Region 206b of region 206 is formed using a different mask than the mask used to form regions 204 and 206a. Even in this case, only the position of the depletion region of the P-type region 208 is determined, and the mask misalignment of region 206b relative to region 206a does not significantly affect the characteristics. The configurations shown in Figures 8 and 9 may be used in combination. By applying the configurations shown in Figures 8 and 9, SPAD operation with suppressed magnification and stabilized characteristics can be achieved. In other words, it can contribute to further improvement of the characteristics of the photoelectric converter 100.

[0064] Furthermore, in the configurations shown in Figures 6 and 9, by positioning region 206 closer to the main surface 252 of the semiconductor substrate 250 than region 204, the distance between region 206 and region 208 is made shorter than the distance between region 204 and region 208. However, this is not the only option. For example, region 204 and region 206 may have the same shape, and the portion of region 208 that overlaps with region 206 may have a step that brings it closer to region 206. For example, region 204 and region 206 may be formed using the same mask. On the other hand, region 208 may comprise a uniform region as shown in Figures 6 and 9, and a region that is continuous with the uniform region and approaches region 206 in the region that overlaps with region 206 in the orthogonal projection onto the main surface 251 of the semiconductor substrate 250. This also enables the suppressed multiplier SPAD operation combining APD201 and parasitic PD232 as described above. Furthermore, since regions 204 and 206 can be formed using a single mask, the SPAD operation characteristics can be stabilized, similar to the configuration shown in Figure 9.

[0065] Furthermore, the outer edges of each region, such as regions 204, 206, and 208, may be areas where the impurity concentration is 1 / 10 of the highest concentration within that region. Alternatively, for example, the outer edges of each region, such as regions 204, 206, and 208, may be areas where the impurity concentration is 1 / 100 of the highest concentration within that region. Furthermore, for example, the outer edges of each region, such as regions 204, 206, and 208, may be continuous with the highest impurity concentration within that region, with an impurity concentration of 1 × 10⁻⁶. 16 It may also be the part that becomes [this]. Furthermore, for each region, if adjacent regions have different conductivity types, the outer edge of each region may be the part where the conductivity type changes.

[0066] (Second Embodiment) Next, a photoelectric conversion device 100 according to a second embodiment of the present disclosure will be described. Figure 10 is a plan view of the photoelectric conversion unit 102 arranged in the pixel 104 in this embodiment. Figure 11 is a cross-sectional view of the photoelectric conversion unit 102 between A and B shown in Figure 10. Figure 10 is a plan view of the main surface 251 of the semiconductor substrate 250 shown in Figure 11. The equivalent circuit of this embodiment shown in Figures 10 and 11 may be the same as the circuit of the first embodiment described above using Figures 5 to 9, as shown in Figure 7(a), and the operation may also be the same.

[0067] In this embodiment, as shown in Figure 11, regions 204 and 206 have a stacked structure in the depth direction. More specifically, region 206 is located between region 204 and region 208. Here, the depth direction is the direction from the main surface 251 to the main surface 252 of the semiconductor substrate 250. Hereafter, it may be said that the depth increases as one approaches the main surface 252 from the main surface 251.

[0068] APD201 is composed of regions 206 and 208. A low concentration of P-type or N-type impurities is introduced into region 207. Regardless of the conductivity type of the impurities, a low-density N-type conductive electron layer is formed in region 207 during operation, and it acts as a resistor connecting region 204 and region 206. When region 207 is effectively an N-type region, the operation of region 207 is the same as in the first embodiment described above. Here, the "effective" conductivity type refers to the conductivity type with the higher impurity concentration when P-type and N-type impurities are present together, and the difference in concentration is the effective concentration. In the embodiments described above and the embodiments described below, the conductivity type of each region can be the effective conductivity type.

[0069] The following describes the case where region 207 is effectively a P-type region, but its majority carriers are electrons. If region 207, which is effectively a P-type impurity region, is neutral or completely depleted during operation, then electrical conduction between region 204 and region 206 is broken, and region 206 of APD201 remains in a floating state. Therefore, information about the occurrence of avalanche breakdown in APD201 is not transmitted, and it does not function as a SPAD. On the other hand, if the depth and impurity concentration of the P-type region 207 are appropriate, the majority carriers of region 207 can be electrons with low density, and region 207 can function as a resistor between region 204 and region 206. Specifically, the Debye length of the P-type region 207 should be approximately the same as the depth of region 207. This allows the majority carriers of region 207 to be electrons with low density.

[0070] Regions 204 and 206 are high-density N-type regions with a high density of electrons as majority carriers. The pseudo-Fermi levels of regions 204 and 206 do not change in such a way that the majority carriers become holes in the P-type region 207. This is because the limit on the change in the pseudo-Fermi level is determined by the Debye length. Therefore, in the P-type region 207, although the density is low, electrons become the majority carriers, and region 207 can act as a resistor. A lower density electron layer is easier to achieve when region 207 is a moderately concentrated P-type region than when region 207 is an N-type region. Therefore, region 207 is more likely to function as a higher-resistance region. Compared to the configurations described using Figures 5 to 9, the configuration shown in Figure 11 allows for a shorter distance between regions 204 and 206. Therefore, a higher resistance per unit length of region 207 may be required than in the above configurations.

[0071] As explained above, when region 207 acts as a resistor and exhibits a desired resistance value, the amplification factor when avalanche breakdown occurs can be suppressed compared to the comparative example SPAD by the same operating principle as the first embodiment described with reference to Figures 5 to 9. As a result, even in the configurations shown in Figures 10 and 11, the problems of light emission crosstalk, dark current changes, and power consumption caused by a large amplification factor can be improved.

[0072] Furthermore, as shown in Figures 10 and 11, in the orthogonal projection onto the main surface 251 of the semiconductor substrate 250, regions 204 and 206 are arranged to overlap each other. Therefore, compared to the plan view in Figure 5, the area occupied by regions 204 and 206 is reduced. This makes it easier to apply when reducing the size of the pixel 104 (photoelectric conversion unit 102). Moreover, the three layers of regions 204, 206, and 207 can be formed using the same mask. This reduces the likelihood of characteristic variations due to mask misalignment in regions 204, 206, and 207, and further reduces manufacturing costs.

[0073] Figure 12 shows a modified version of the configuration shown in Figure 11. In the configuration shown in Figure 12, region 233 (the sixth region) is a P-type region, in which an effective P-type impurity concentration is introduced such that it is essentially depleted during operation. Region 207 has approximately the same depth as region 233 and is a region in which N-type or P-type impurities are introduced, locally formed in the central part of regions 204 and 206 in the orthogonal projection onto the main surface 251 of the semiconductor substrate 250. As described above, region 207 is a region in which electrons become majority carriers at a low density during operation. Therefore, if region 207 is P-type, its effective impurity concentration is lower than that of region 233.

[0074] In the configurations shown in Figures 11 and 12, region 207 becomes an electrical conduction path between region 204 and region 206. In the configuration shown in Figure 12, region 207 has a smaller cross-sectional area perpendicular to the direction of current flow than in the configuration shown in Figure 11, making it easier to obtain a larger resistance value. Regions 204, 206, and 233 can be formed using the same mask. In the configuration shown in Figure 12, region 207 may have N-type impurities further introduced into region 233 using a different mask than the one used to form regions 204, 206, and 233. This makes region 207 effectively an N-type region, or a P-type region with a lower effective impurity concentration than region 233. Alternatively, the same mask used to form region 207 and the connection pattern 205 may be used. The N-type impurities when forming region 206 will essentially have a distribution that is spread in the depth direction in the central part. Therefore, depending on the design of the distribution of each impurity concentration, when regions 204, 206, and 233 are formed using the same mask, region 207 may also be formed locally at the same time.

[0075] In the configuration of this embodiment, in the orthogonal projection onto the main surface 251 of the semiconductor substrate 250, regions 204 and 206 are arranged to overlap each other. In this case, region 206 may be arranged to be contained within region 204, or region 204 may be arranged to be contained within region 206.

[0076] In the configuration of this embodiment, as in the configuration shown in the first embodiment described above, the carrier amplification factor when avalanche breakdown occurs can be suppressed. This improves the aforementioned problems of light emission crosstalk, dark current changes, and power consumption. Furthermore, even when the size of pixel 104 is reduced, the configuration of this embodiment, in which regions 204, 207, and 206 overlap, can be effectively applied. Moreover, the configuration in which regions 204, 207, and 206 overlap can reduce characteristic variations while suppressing an increase in the manufacturing process.

[0077] (Third embodiment) Next, a photoelectric converter 100 of the third embodiment of this disclosure will be described using Figure 13. Figure 13 is a cross-sectional view of the photoelectric converter 102 arranged in the pixel 104 in this embodiment. The photoelectric converter 100 in this embodiment differs from the modified example of the second embodiment shown in Figure 12 in that the photoelectric converter 102 has a region 232. Except for this point and the points described below, it is substantially the same as the second embodiment and may be omitted from the description. The circuit diagram and SPAD operation in this embodiment are also the same as the operation described in Figures 5, 7(a), and 7(b), etc.

[0078] In this embodiment, region 232 is connected to a detection circuit for detecting avalanche breakdown via a connection pattern 205. Region 232 is a high-impurity concentration N-type conductive region that constitutes a part of the main surface 251 of the semiconductor substrate 250. Region 232 is ohmic-connected to region 204 and the connection pattern 205. The N-type impurity concentration in region 232 is higher than that of region 204. In a plan view, region 204 is arranged to surround region 232.

[0079] In a plan view, region 207 is positioned to overlap with the connection pattern 205. In this case, it is possible to form region 207 using the through-holes after the process of forming the through-holes for the connection pattern 205, and N-type impurities may be introduced to a depth similar to that of region 233. On the other hand, in this case, the resistance value of region 207 may be affected by region 232. To reduce the influence on the resistance value, as shown in Figure 14, region 207 and the connection pattern 205 may be positioned so that they do not overlap in a plan view.

[0080] The appropriate impurity concentrations for each region are described below. Note that the impurity concentration referred to here is the effective impurity concentration, which is the difference in impurity concentration when P-type and N-type impurities are present together. Furthermore, the impurity concentrations shown below are examples, and the regions described in each embodiment are not limited to the range of impurity concentrations shown below.

[0081] For example, the impurity concentration in region 204 is preferably in the range of 1×10 15 ~1×10 20 cm -3 . The impurity concentration in region 206 is preferably in the range of 5×10 16 ~2×10 18 cm -3 . By setting the impurity concentration in region 206 to be not less than a predetermined value, it becomes easier for it to function as part of APD 201. By setting the impurity concentration in region 206 to be not more than a predetermined value, it becomes easier to electrically separate it from region 204. The impurity concentration in region 208 is preferably in the range of 2×10 16 ~2×10 17 cm -3 . By setting the impurity concentration in region 208 to be not less than a predetermined value, it becomes easier for it to function as part of APD 201. By setting the impurity concentration in region 208 to be not more than a predetermined value, it becomes easier to deplete vertically through a part of it during operation. The impurity concentration in region 233 is determined by the distance between region 204 and region 206 and the impurity distribution in these two regions. Therefore, although it varies depending on the conditions, for example, it is preferably in the range of 2×10 -3 ~2×10 16 cm 18 -3 . Regions 209 and 230 are preferably, for example, in the range of 5×10 -3 ~2×10 16 cm 18 -3 . Region 232 is preferably, for example, in the range of 1×10 -3 ~1×10 19 cm 20 -3 . Region 207 may be either P-type or N-type as described above. Region 207, for example, has N-type impurities introduced into a part of region 233, for example, with an impurity concentration of 5×10 -3 cm 16 -3The following P-type or N-type regions form a conductive path. During operation, region 233 becomes depleted, but within the depleted region 233, the portion of region 207 becomes a low potential for electrons and acts as an electron conductive path. Note that if the semiconductor substrate before ion implantation is P-type, even without introducing P-type impurity ions to form region 233, a portion of the semiconductor substrate located between region 204 and region 206 may become a P-type region 233.

[0082] Furthermore, although the impurity concentrations in region 204 and region 232 are varied in Figure 13, region 204 may be formed with an impurity concentration similar to that of region 232, and no impurities may be introduced into the region corresponding to region 232. Alternatively, region 207 may be formed naturally during the formation of region 232 due to the depth-direction tailing of the N-type impurity distribution.

[0083] In the configuration of this embodiment, as with the configurations shown in the first and second embodiments described above, the carrier amplification factor when avalanche breakdown occurs can be suppressed. This improves the aforementioned problems of light emission crosstalk, dark current changes, and power consumption. Furthermore, the presence of region 232 allows the configuration of this embodiment, in which regions 204, 207, and 206 overlap, to be effectively applied even when the size of the pixel 104 is reduced. Moreover, the configuration in which regions 204, 207, and 206 overlap can reduce characteristic variations while suppressing an increase in the manufacturing process.

[0084] (Fourth Embodiment) Next, a photoelectric converter 100 of the fourth embodiment of this disclosure will be described using Figure 15. Figure 15 is a cross-sectional view of the photoelectric converter 102 arranged in the pixel 104 in this embodiment. The photoelectric converter 100 in this embodiment differs from the third embodiment shown in Figure 13 in that the region 233 has a donut shape with a hollowed-out center in plan view. Except for this point and the points described below, it is substantially the same as the third embodiment and may be omitted from the description. The circuit diagram and SPAD operation in this embodiment are also the same as the operation described in Figures 5, 7(a), and 7(b), etc.

[0085] Figure 16 shows a method for forming region 233 of the photoelectric conversion unit 102 arranged in pixel 104 in this embodiment. In the figure, a resist 240 is arranged on the semiconductor substrate. The resist 240 is used when forming regions 204, 206, and 233. P-type impurity ions 241 are ions used to form region 233.

[0086] Following a standard semiconductor manufacturing process, a resist is applied to the entire surface of the semiconductor substrate, and then the resist in the areas overlapping regions 204 and 206 in a plan view is partially etched away. Next, by shallowly implanting N-type impurity ions, region 204 corresponding to the first cathode is formed, and by implanting N-type impurity ions to a predetermined depth, region 206 corresponding to the second cathode is formed. Furthermore, as shown in Figure 16, by implanting P-type impurity ions 241 obliquely to the interface of the semiconductor substrate and rotating it relative to the semiconductor substrate, a donut-shaped region 233 is formed. The hollowed-out portion is a P-type semiconductor or an N-type semiconductor with a low impurity concentration. By controlling the impurity concentration of region 190, the impurity concentration of region 233, and the diameter of the hollowed-out portion, a desired region 207 can be formed.

[0087] To introduce N-type impurities into region 233 and form a region 207 with a low impurity concentration of either P-type or N-type impurities, the amount of N-type impurities introduced per unit area must be approximately equal to the amount of P-type impurities in region 233. For example, if the P-type impurity concentration in region 233 is 1 × 10⁻⁶ 17 / cm 3 Therefore, the N-type impurities introduced to form region 207 are 1.1 × 10⁻⁶ 17 / cm 3 Therefore, 1 × 10 16 / cm 3 An N-type region 207 with a concentration of 1 × 10 is formed. 16 / cm 3 In the N-type region 207, there are 2.1 × 10⁻¹⁰ units of both P-type and N-type combined. 17 / cm 3 The following impurity ions are introduced. If region 207 is a cube with a side length of 0.3 μm, then region 207 contains 1.1 × 10⁻¹⁰ 17 ×(0.3×10 -4 ) cubed, that is, there are 2970 N-type impurity ions. Similarly, there are 2700 P-type impurity ions. The effective number of N-type impurity ions is (2970 - 2700), which is 270. These numbers are averages, and in reality, the number varies. Statistics teaches that the standard deviation of the variation is the square root of the average number. In this case, the variation in the total number of P-type and N-type impurity ions is the square root of (2970 + 2700), which is approximately 75. In other words, for an effective number of N-type impurity ions of an average of 270, the standard deviation of the variation is 75. Therefore, the concentration is 1 × 10⁻⁶ 16 / cm 3 Even though it's an N-type carrier guide, if we express the variability in terms of standard deviation, it's 1 ± 0.28 × 10⁻¹⁰. 16 / cm 3This results in very large variations. The cause of this large variation is, as mentioned above, the presence of a large number of P-type impurity ions and a large number of N-type impurity ions in region 207. If there is a large variation in region 207 among many pixels, that is, if the resistance value of region 207 differs greatly from pixel to pixel, the effectiveness of the present invention will decrease in actual operation. However, according to this embodiment, the hollowed-out central portion of region 233, which becomes region 207, contains only a small number of impurities. Applying the values ​​from the example above, there are only an average of 270 N-type impurity ions in region 207. The standard deviation of this variation is approximately 16, which is the square root of 270, and is significantly reduced from the standard deviation of 75 in the example above. Therefore, according to this embodiment, the characteristic variation among many pixels is small, and, similar to the first to third embodiments, improvements are achieved in three problems: light emission crosstalk, changes in dark current, and power consumption when many photons are incident.

[0088] (Fifth embodiment) Next, a photoelectric converter 100 of the fifth embodiment of this disclosure will be described using Figure 17. Figure 17 is a cross-sectional view of the photoelectric converter 102 arranged in the pixel 104 in this embodiment. The photoelectric converter 100 in this embodiment differs from the third embodiment shown in Figure 13 in that it includes regions 238 and 239. Except for this point and the points described below, it is substantially the same as the third embodiment and may be omitted from the description. The circuit diagram and SPAD operation in this embodiment are also the same as the operation described in Figures 5, 7(a), and 7(b), etc.

[0089] Region 238 is a P-shaped region formed over a wider area in plan view, surrounding region 233, at a depth similar to that of region 233 in cross-sectional view. Region 239 is an N-shaped region formed over a wider area in plan view, surrounding region 206, at a depth similar to that of region 206 in cross-sectional view. Regions 233 and 206 overlap with region 204 in plan view, and regions 238 and 239 overlap with region 204 in plan view. The following explanation assumes the shapes described above, but is not limited to these shapes.

[0090] Region 207 can be formed by introducing N-type impurities into a portion of region 233. However, in this case, as described in the fourth embodiment, if the impurity concentration in region 233 is high, a problem may arise in which the properties of region 207 vary greatly. To reduce this large variation in properties, it is necessary to reduce the concentration of P-type impurities in region 233. However, it can be difficult to reduce the concentration of P-type impurities in region 233 without variation.

[0091] Figure 16 shows how P-type impurity ions are obliquely implanted into the semiconductor substrate to form a donut-shaped region 233 after regions 204 and 206 have been formed in the opening portion of the resist 240. However, accurately forming a donut shape is not easy, and basically, P-type impurity ions are implanted almost perpendicularly into the semiconductor substrate to form a uniform region 233. When forming regions 204 and 206, a considerable concentration of N-type impurity layers is deposited between these two regions, that is, in the region where region 233 should be formed. Therefore, in order to form region 233, which is superior to this N-type impurity and electrically separates regions 204 and 206, a situation may arise where a larger amount of P-type impurity must be introduced. The cause of this problem arises when forming region 206. Generally, when impurity ions are implanted, a certain distribution is created in the depth direction of the semiconductor substrate, so when forming region 206, a certain N-type impurity distribution is created on the shallower side of that peak, but this problem arises from a different mechanism.

[0092] Generally, in the formation of semiconductor devices, the process of forming a desired opening in the resist and then implanting impurity ions into the semiconductor substrate is repeated. Basically, only impurity ions that enter the resist opening are selectively introduced into the semiconductor substrate. However, when the opening area is small and the energy of impurity ion implantation is increased for device formation in deep areas, the phenomenon of some of the impurity ions implanted in the resist entering the opening becomes significant. That is, relatively high-energy ions implanted in the resist move through the resist in the depth direction while gradually losing kinetic energy. Since these impurity ions undergo random motion in the plane direction, impurity ions implanted particularly close to the resist opening may come out of the resist opening and enter the semiconductor substrate at the opening. Such impurity ions have lost some kinetic energy by the time they come out of the resist opening and generally accumulate on the shallower side than the desired depth. Such unwanted impurity ions are generated in large numbers near the boundary of the resist opening. When the resist opening area is large, such unwanted impurity ions only affect the area near the resist opening boundary, but when the opening area is small, such unwanted impurity ions practically enter throughout the entire resist opening.

[0093] When implanting N-type impurity ions to form region 206, the situation described above occurs, and unwanted N-type impurity ions, transmitted via the resist, deposit in a shallower area than the depth to which region 206 is formed, i.e., in the region where region 233 should be formed. Therefore, more P-type impurity ions are required for the formation of region 233. A large number of P-type and N-type impurity ions will be mixed in the region 207 formation area, which may lead to large variations in the properties of region 207 as described in the fourth embodiment. A method that can easily reduce such large variations in the properties of region 207 will be described below.

[0094] In this embodiment, the impurity concentration in region 206 is reduced, thereby lowering the amount of N-type ions implanted when forming region 206. Unwanted N-type impurity ions entering the region where region 233 is formed also decrease in proportion to the amount implanted. On the other hand, since region 206, which corresponds to the second cathode, plays a role in forming the APD with region 208, a certain minimum impurity concentration is necessary. Therefore, region 239, which has a planarly larger area than region 206, is given part of the role of forming region 206. N-type impurity ions are implanted under almost the same energy conditions as the implantation of N-type impurity ions for the formation of region 206 to form region 239. This makes it possible to reduce the amount of N-type impurity ions required to form region 206.

[0095] For example, the amount of N-type impurity ions required per unit area in region 206 is 1 × 10⁻⁶ 13 / cm 2 Let's assume that the amount of N-type impurity ions implanted during the formation of region 206 is 6 × 10 12 / cm 2 The amount of N-type impurities implanted during the formation of region 239 is 4 × 10 12 / cm 2 Therefore, combining both, the required amount of N-type impurity ions introduced into region 206 is 1 × 10⁻⁶. 13 / cm 2 This is because, during the formation of region 239, the influence of unwanted N-type impurity ions via the resist remains near the boundary of region 239 and hardly penetrates into region 233. Therefore, by forming region 206 together with region 239, the amount of unwanted N-type impurity ions that penetrate into region 233 can be reduced. This reduces the amount of P-type impurity ions introduced to form region 233, in other words, the amount of N-type impurity ions introduced to form region 207. Consequently, the variation in the characteristics of region 207 can be reduced. During operation, it is preferable that regions of region 239 other than region 206 are depleted. Otherwise, the PN junction capacity of region 206 increases, and the original purpose of the present invention, which is to reduce the carrier multiplication factor during avalanche generation, will be at least partially undermined.

[0096] Figure 18 is a pixel cross-sectional view of the process for forming regions 238 and 239 shown in Figure 17. After ion implantation of regions 204, 206, and 233, the process shown in Figure 18 is performed without a thermal process. In the figure, a resist 242 with an opening for the region to be formed in region 238 is placed on the semiconductor substrate. The direction of implantation of P-type impurity ions 243 for forming region 238 is also shown. After forming region 238, N-type impurity ion implantation for forming region 239 is performed using the same resist 242.

[0097] Generally, it is known that when impurity ions are implanted parallel to the crystal axis of a semiconductor substrate, the ions undergo channeling and penetrate deeper than the desired depth in the semiconductor substrate. Typically, the direction perpendicular to the surface of the semiconductor substrate is also the direction of the crystal axis, so channeling occurs when impurity ions are implanted perpendicular to the surface of the semiconductor substrate. On the other hand, in semiconductor regions where impurity ions are introduced at high concentrations, the crystal structure is partially disrupted and partially amorphous. Therefore, even if impurity ions are implanted into the amorphous region, channeling is suppressed because the crystal axis is disrupted.

[0098] In the process shown in Figure 18, ion implantation has already been performed in regions 204, 206, and 233, and in particular, approximately 1 × 10⁻¹⁶ ions have been implanted in region 204. 18 cm -3Assuming that the above high concentration of impurity ions has been introduced and this region is amorphous, when P-type impurity ions are injected to form region 238 in this state, channeling is suppressed in region 204 when viewed in plan, while channeling occurs in the other regions. In the regions where channeling occurs, the P-type impurity ions penetrate deeply and reach region 239 to some extent. Therefore, the effective N-type impurity concentration in region 239 in this region decreases, making it more susceptible to depletion. On the other hand, in the regions 204 and 206 when viewed in plan, the proportion of P-type impurity ions that reach the depth of region 206 is smaller, and the effective N-type impurity concentration in region 206 does not decrease as much. Therefore, the method for forming region 238 shown in Figure 18 selectively reduces the N-type impurity concentration in regions 239 other than the regions 204 and 206 when viewed in plan, making it possible for this region to be depleted during operation.

[0099] Figure 19 shows the depth distribution of impurity ions in regions 204, 238, and 239. Of the two impurity ion distributions in region 238, the solid line represents the distribution in regions 204 and 206 on the planar layout. The dotted line represents the distribution in the remaining area, showing that the distribution extends significantly to region 239.

[0100] The concentration of P-type impurities in region 233 is determined by the sum of the P-type impurity implantation in the process shown in Figure 16 and the P-type impurity implantation in the process shown in Figure 18, although the P-type impurity implantation in the process shown in Figure 16 may be omitted. Furthermore, the implantation of N-type impurity ions in regions 206 and 239 may be performed at an oblique angle, slightly offset from the vertical axis direction of the semiconductor substrate surface, in order to suppress channeling. Doing so improves the APD characteristics formed in regions 206 and 208, and increases the overlap of impurity distributions with region 238 in regions 239 other than region 206, making depletion more likely during actual operation.

[0101] After the formation of region 238 and region 239, as shown in Figure 18, are completed, region 207 is formed. The formation of region 207 may be carried out in the same process as region 232, or in a separate process. If it is a separate process, region 207 and region 232 may be positioned in a non-overlapping location in a plan view, as shown in Figure 14. It is also possible to avoid forming region 232 by making the N-type impurity concentration in region 204 very high. Alternatively, region 207 may be formed simultaneously by forming region 232 to a slightly deeper depth.

[0102] In the configuration of this embodiment, as in the configurations shown in the first to fifth embodiments described above, the carrier multiplication factor when avalanche breakdown occurs can be suppressed. Furthermore, according to this embodiment, while suppressing characteristic variations, effects can be achieved on three problems: emission crosstalk, changes in dark current, and power consumption during multiple photon incidence.

[0103] (Sixth Embodiment) Next, the SPAD operation of the sixth embodiment of this disclosure will be described using Figure 20. Figure 20 is an equivalent circuit diagram of a part of the photoelectric conversion unit 102 and the signal processing circuit 103. Compared with the equivalent circuit shown in Figure 7(a), the configuration shown in Figure 20 has an additional transistor 234. Transistor 234 is an N-type MOS transistor. The gate electrode of transistor 234 is connected to nodeB. When nodeB becomes High, transistor 234 turns ON and sets the potentials of nodeA and nodeD to a potential level such that the APD201 does not undergo avalanche breakdown. In other words, transistor 234 functions as a setting circuit that sets the potentials of regions 204 and 206 to a potential in the photoelectric conversion unit 102 that does not undergo avalanche breakdown when the waveform shaping circuit 210 (detection circuit) detects avalanche breakdown. In the configuration shown in Figure 20, when transistor 234 turns ON, the potentials of regions 204 and 206 become 0V, which is the ground level.

[0104] In the first to fifth embodiments described above, as shown in Figure 7(b), the amplification factor when avalanche breakdown occurs is suppressed, resulting in the potentials of nodeA and nodeD remaining high even after avalanche breakdown occurs. Therefore, if more photons are incident in this state, further avalanche breakdown may occur, and the potentials of nodeA and nodeD may become even lower due to discharge by the avalanche current. In that case, nodeB is already at a high level due to the first photon incident, and the state of nodeB does not change with the second and subsequent photon incidents. In other words, avalanche breakdown caused by the second and subsequent photon incidents is not detected as a signal, resulting in the generation of useless electron-hole pairs.

[0105] Therefore, in the circuit shown in Figure 20, transistor 234 is provided. If avalanche breakdown occurs due to the incidence of one photon during one period of the periodic reset pulse input to nodeC, the signal from nodeB emitted by the waveform shaping circuit 210 becomes high level, indicating that avalanche breakdown has been detected. As a result, transistor 234 turns ON, and nodeA and nodeD become ground level. Consequently, even if subsequent photons are incident before the next reset pulse is input to nodeC, avalanche breakdown will not occur in APD201. In other words, the occurrence of avalanche breakdown is kept to the absolute minimum.

[0106] Here, this embodiment is effective when transistor 203 operates as a reset circuit for resetting the potentials of region 204 (node ​​A) and region 206 (node ​​D) to predetermined potentials. When node A and node D are reset by transistor 234 (transistor 234 is ON), no electron-Hall pairs are generated in APD201. Furthermore, the reset by transistor 234 is a potential difference discharge of about 2V to ground level. Therefore, the electrical energy required is far less than the potential difference discharge of about 20-30V to a large negative potential VL that occurs when avalanche breakdown occurs.

[0107] As described above, according to this embodiment, in addition to suppressing the carrier multiplication factor when avalanche breakdown occurs, it is possible to prevent the occurrence of unnecessary avalanche breakdown within one cycle of the reset pulse periodically input to nodeC. Therefore, this embodiment has an even greater improvement effect on the problems of light emission crosstalk, dark current changes, and power consumption compared to the first to fifth embodiments described above.

[0108] (Seventh Embodiment) Next, a photoelectric conversion device 100 according to the seventh embodiment of this disclosure will be described using Figures 21 to 23(a) and 23(b). Figure 21 is a plan view of the photoelectric conversion unit 102 arranged in the pixel 104 in this embodiment. Figure 22 is a cross-sectional view of the photoelectric conversion unit 102 between A and B shown in Figure 21. Figure 21 is a plan view of the main surface 251 of the semiconductor substrate 250 shown in Figure 22. Figure 23(a) shows an equivalent circuit diagram of part of the photoelectric conversion unit 102 and the signal processing circuit 103, and Figure 23(b) shows the potential changes of nodes A to E during SPAD operation. Nodes A to D are in the same positions as shown in Figure 7(a). Node E is a node connected to the gate electrode 235 of the transistor 237, which will be described later.

[0109] In the configuration shown in Figures 21 and 22, region 206 can constitute a part of the main surface 251 of the semiconductor substrate 250. Furthermore, the photoelectric conversion unit 102 further includes a transistor 237 that causes regions 204 and 206 to function as source regions or drain regions, respectively, and region 207 to function as a channel region. Transistor 237 is an N-type MOS transistor. Transistor 237 includes a gate electrode 235 and a gate insulating film 236 disposed between the gate electrode 235 and the main surface 251 of the semiconductor substrate 250. Since region 190 is basically depleted during operation, the formation or non-formation of the channel region (region 207) directly beneath the gate electrode 235 is determined by controlling the potential of the gate electrode 235. As a result, the conduction between region 204 and region 206 is controlled by transistor 237. As shown in the equivalent circuit diagram of Figure 23(a), transistor 237 will be positioned between nodeD, which is connected to the cathode of APD201, and nodeA, which is connected to the cathode of parasitic PD232.

[0110] Next, the SPAD operation of this embodiment will be explained using Figure 23(b). A pulse that periodically turns on transistor 237 is input to nodeE, which is connected to the gate electrode 235 of transistor 237. As a result, transistor 237 conducts at a predetermined period. In addition, a reset pulse is input to nodeC at the same period as nodeE. As a result, transistor 203, which functions as a reset circuit for resetting the potentials of regions 204 and 206 to a predetermined potential (potential VH), resets the potentials of regions 204 and 206 at the same period as transistor 237.

[0111] At time t0, the reset of nodeA and nodeD is completed. While transistor 237 is conducting due to a pulse input to nodeE, a reset pulse is input to nodeC, turning transistor 203 ON. This initiates the reset, resetting the potential of not only region 204 (nodeA) but also region 206 (nodeD). Next, transistor 237 turns OFF, followed by transistor 203. As a result, nodeA and nodeD enter a floating state at potential VH.

[0112] When a photon is incident at time t1, avalanche breakdown occurs at APD201, and the potential of region 206 (nodeD) drops to near ground level, stopping avalanche multiplication. At this time, nodeD has a small discharge capacitance, so its carrier multiplication factor is small. At time t2, nodeD remains in a floating state at the potential where avalanche multiplication has stopped.

[0113] Next, at time t3, nodeE becomes high and transistor 237 turns ON. As a result, nodeA and nodeD conduct, and a potential change occurs so that nodeA and nodeD are at the same potential. The potential of nodeA decreases and the potential of nodeD increases, but since the capacitance added to nodeA is large and the capacitance added to nodeD is small, the potential change of nodeA is small. The waveform shaping circuit 210 (detection circuit) detects avalanche breakdown according to the potential of nodeA (region 204) when transistor 237 conducts. Therefore, by setting the judgment threshold of the waveform shaping circuit 210 to an appropriate value so that even a small potential change of nodeA can be detected, avalanche breakdown in APD201 is detected.

[0114] At time t4, when the potential of nodeC goes low and transistor 203 turns ON, nodeA and nodeD are reset again. Then, at time t5, when the potential of nodeC goes high, the system returns to the state at time t0.

[0115] In this embodiment, the carrier amplification factor when avalanche breakdown occurs can potentially be kept even smaller compared to the first to fifth embodiments. In the configurations shown in the first to fifth embodiments, nodeA and nodeD always have a certain degree of electrical conduction through the region 207 which functions as a resistor. Therefore, when avalanche breakdown occurs in APD201, a certain amount of discharge occurs in nodeA, which has a large capacitance. On the other hand, in this embodiment, the electrical conduction between nodeA and nodeD can be almost completely disconnected while transistor 237 is OFF and the channel region is not generated. Therefore, when avalanche breakdown occurs in APD201, only discharge occurs in nodeD, which has a small loaded capacitance.

[0116] Furthermore, consider the case where multiple photons are incident during one reset cycle by transistor 203 (reset circuit). Even in this case, in this embodiment, the potential of node D is sufficiently lowered to approximately ground level by the avalanche breakdown caused by the first incident photon. Therefore, avalanche breakdown does not occur due to the incident of the second and subsequent photons. Consequently, in this embodiment, it is not necessary to include transistor 234 as shown in the third embodiment.

[0117] As described above, this embodiment can further suppress the carrier amplification factor when avalanche breakdown occurs compared to the embodiments described above. Therefore, this embodiment exhibits even greater improvement effects on the three problems mentioned above: luminescence crosstalk, changes in dark current, and power consumption.

[0118] (Eighth embodiment) Next, a photoelectric converter 100 according to the eighth embodiment of the present disclosure will be described. This embodiment can be considered a modification of the seventh embodiment described above, and, similar to the configuration shown in Figures 21 and 22 described above, the APD201 and the parasitic PD232 are connected by a transistor 237. On the other hand, in this embodiment, as shown in Figure 24, a comparator 220 is used instead of the waveform shaping circuit 210 as a detection circuit for detecting avalanche breakdown. Node A is connected to the - input terminal of the comparator 220, and node F is connected to the + input terminal.

[0119] Next, the SPAD operation in this embodiment will be explained using Figure 25. In this embodiment, during a single signal detection operation (operation between two consecutive reset pulses input to nodeC), the SPAD responds to the incidence of multiple photons, counts the number of incident photons, and performs signal processing.

[0120] As shown in Figure 25, in this embodiment as well, similar to the seventh embodiment described above, pulses are periodically input to nodeE, and transistor 237 conducts at a predetermined period. On the other hand, unlike the seventh embodiment, nodeC does not receive a reset pulse at the same period as nodeE, but rather receives a reset pulse that resets the potentials of regions 204 and 206 each time the transistor conducts a predetermined number of times. In the example shown in Figure 25, one reset pulse is input to nodeC for every four pulse inputs to nodeE. The relationship between the reset pulse input to nodeC and the pulse input to nodeE when a reset pulse is input to nodeC may be the same as the relationship shown in Figure 23(b).

[0121] During the one cycle in which a reset pulse is input to nodeC, pulses that cause transistor 237 to conduct multiple times are periodically input to nodeE. In the example shown in Figure 25, photons are incident at times t1, t2, and t3. These are the first, third, and fourth periods of the four periods in which pulses are input to nodeE during the one cycle in which a reset pulse is input to nodeC. Even if an avalanche breakdown occurs at APD201 due to the incident photons, the input pulse to nodeE causes transistor 237 to conduct, and the potential of nodeD (region 206) rises. Therefore, three avalanche breakdowns occur at APD201 corresponding to each of the three incident photons, and each time transistor 237 turns ON, the potential of nodeA drops by an amount equivalent to the total discharge amount in the three avalanche breakdowns. The potential of nodeA from time t4 to time t5 is the potential that has dropped by an amount equivalent to the total discharge amount in the three avalanche breakdowns. The capacitance added to APD201 (region 206) is small, and the discharge amount per avalanche breakdown is small. Therefore, this embodiment utilizes the fact that multiple avalanche breakdowns can occur in APD201 even if nodeA (and nodeD) are not reset to potential VH.

[0122] In Figure 25, nodeF and nodeB are shown in a magnified view from time t4 to time t5. NodeF, connected to the + input terminal of comparator 220, receives stepped potentials V0, V1, V2, V3, and V4, respectively. Vn (n=0, 1, 2, 3, 4) is the potential corresponding to the number of avalanche breakdowns that occurred during one cycle of the reset pulse input to nodeC. The values ​​are set such that when a Vn such that n≧k is input to nodeF for k avalanche breakdowns, nodeB, corresponding to the output of comparator 220, inverts from High to Low.

[0123] Since comparator 220 generally has a constant current flowing through it during operation, it may be configured to operate only during the period from time t4 to time t5. Alternatively, the potential of nodeB can be set to High during current-off periods other than from time t4 to time t5. Such a comparator circuit configuration is quite common, so details are omitted.

[0124] In the example shown in Figure 25, nodeB inverts at time t6 when nodeF becomes V3. Therefore, the number of times avalanche breakdown occurs is determined to be 3. In this way, the comparator 220 (detection circuit) generates a multi-level signal corresponding to the potential of nodeA before transistor 237 conducts for a predetermined number of times and before transistor 203 (reset circuit) resets the potentials of nodeA and nodeD. This makes it possible to count the number of times multiple avalanche breakdowns occur due to the incidence of multiple photons in a single signal detection operation (operation between two consecutive reset pulses input to nodeC).

[0125] This embodiment is not limited to the configuration shown in Figure 24. There may be circuit configurations in which no steady current flows during the operation of the comparator 220. Also, there may be cases where the connection between the parasitic PD232 and APD201 functions as a region 207, as in the first and second embodiments. When region 207 functions as a resistor, a configuration can be considered in which an N-type transistor is placed between the - input terminal of the comparator 220 and node A, with the source region connected to node A and the drain region connected to the - input terminal, and the gate electrode is kept at a constant potential. Using the saturation region operation of this transistor, discharge is performed from the drain region by avalanche breakdown occurring in APD201. As long as the saturation region operation is maintained, a potential change equivalent to the total discharge charge amount due to multiple avalanche currents occurs in the drain region. The comparator 220 can detect this potential change in the drain region and count the number of avalanche breakdowns that have occurred.

[0126] Here, the count of comparator 220 does not necessarily have to match the actual number of avalanche breakdowns that occurred. It is sufficient to have a circuit that converts the analog quantity, the total discharge charge amount generated by multiple avalanche breakdowns, into a digital quantity. For example, a digital signal "1" may correspond to "2.5" avalanche breakdowns in APD201. In other words, the conversion gain of digital signal / actual number of avalanche breakdowns may take a value other than 1. By setting a small conversion gain, a small digital signal can represent a large number of avalanche breakdowns.

[0127] Furthermore, for example, instead of the comparator 220, a circuit equivalent to a source follower may be connected to nodeA. In that case, the circuit connected to nodeA may have a configuration that performs AD conversion on the source follower output, similar to that used in a so-called CMOS sensor readout circuit.

[0128] As explained using Figure 2, in general, in SPADs, the number of avalanche breakdown occurrences in each pixel 104 is added using the counter circuit 211, and the maximum count is determined by the number of bits in the counter circuit 211. Since the size of pixel 104 is limited, the number of bits that can be formed in the counter is also limited. Therefore, by reducing the conversion gain between the digital signal and the actual number of avalanche breakdowns, it is possible to accommodate a larger number of photons. In other words, the saturation signal of pixel 104 can be increased. Reducing such a conversion gain can be particularly effective when the number of photons is high.

[0129] As described above, this embodiment, like the seventh embodiment described above, can suppress the carrier amplification factor when avalanche breakdown occurs. In other words, this embodiment exhibits an improvement effect on the three problems mentioned above: emission crosstalk, dark current changes, and power consumption. Furthermore, compared to the seventh embodiment, the reset pulse input to nodeC can be made shorter in period. As a result, it becomes possible to reduce the power consumption required for the drive pulse (reset pulse). Moreover, as described above, it becomes possible to increase the pixel saturation signal.

[0130] Herein, an example of the application of the photoelectric converter 100 according to the above embodiment will be described below. Figure 26 is a schematic diagram of a device EQP equipped with the photoelectric converter 100. As shown in Figure 26, the photoelectric converter 100 is housed in a semiconductor package PKG. The package PKG may include a substrate on which the photoelectric converter 100 is fixed, a lid such as glass facing the photoelectric converter 100, and conductive connecting members such as bonding wires or bumps that connect terminals provided on the substrate and terminals provided on the photoelectric converter 100. The device EQP may further include at least one of a control device CTRL, a processing device PRCS, a display device DSPL, and a storage device MMRY.

[0131] The optical system OPT forms an image on the pixel array 101 and can be, for example, a lens, shutter, or mirror. The control device CTRL controls the operation of the photoelectric converter 100 and can be, for example, a semiconductor device such as an ASIC. The processing unit PRCS processes the signals output from the photoelectric converter 100 and can be a semiconductor device such as a CPU or ASIC. The display device DSPL displays the data obtained from the photoelectric converter 100 and can be an EL display device or a liquid crystal display device. The memory device MMRY stores the data obtained from the photoelectric converter 100 and is a magnetic device or a semiconductor device. The memory device MMRY can be a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN may have moving parts or propulsion parts such as a motor or engine. The mechanical device MCHN also drives the components of the optical system OPT for, for example, zooming, focusing, and shutter operation. The EQP device displays data output from the photoelectric converter 100 on the display device DSPL, or transmits it externally using a communication device (not shown) provided by the EQP device. For this reason, the EQP device may also be equipped with a storage device MMRY and a processing device PRCS.

[0132] The EQP device incorporating the photoelectric converter 100 can be applied to surveillance cameras, on-board cameras mounted on transportation equipment such as automobiles, railway vehicles, ships, aircraft, and industrial robots. In addition, the EQP device incorporating the photoelectric converter 100 can be applied not only to transportation equipment but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0133] The EQP device is suitable for electronic devices such as information terminals with imaging capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, surveillance cameras). In the case of cameras, the EQP device can also be transportation equipment such as vehicles, ships, and aircraft. As transportation equipment, the EQP device is suitable for transporting the photoelectric converter 100 or for assisting and / or automating driving (operation) through its imaging function. The processing device for assisting and / or automating driving (operation) can process information obtained from the photoelectric converter 100 to operate the mechanical device as a moving device. Alternatively, the EQP device may be medical equipment such as endoscopes, measuring instruments such as distance sensors, analytical instruments such as electron microscopes, office equipment such as photocopiers, or industrial equipment such as robots.

[0134] According to the embodiments described above, a technology advantageous for suppressing the amplification factor can be provided. Therefore, if the photoelectric conversion device according to this embodiment is used in an EQP (Equipment Equipment), the value of the equipment can also be improved.

[0135] The disclosures herein include the following photoelectric conversion devices and equipment.

[0136] (Item 1) A photoelectric conversion device comprising a photoelectric conversion unit disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The aforementioned photoelectric conversion unit is A first region of a first conductivity type, which constitutes a part of the first main surface and is connected to a detection circuit for detecting avalanche breakdown, A second region of the first conductivity type, which is located away from the first region, A third region of a second conductivity type opposite to the first conductivity type, located closer to the second main surface than the first and second regions, A fourth region is located between the first region and the second region, The second and third regions function as an avalanche photodiode. A photoelectric conversion device characterized in that the first region and the second region are configured to be electrically conductive through the fourth region.

[0137] (Item 2) The photoelectric conversion device according to item 1, characterized in that the first region and the third region do not function as an avalanche photodiode.

[0138] (Item 3) The photoelectric conversion device according to item 1 or 2, characterized in that the distance between the second region and the third region is shorter than the distance between the first region and the third region.

[0139] (Item 4) A photoelectric conversion device comprising a photoelectric conversion unit disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The aforementioned photoelectric conversion unit is A first region of a first conductivity type, which constitutes a part of the first main surface and is connected to a detection circuit for detecting avalanche breakdown, A second region of the first conductivity type, which is located away from the first region, A third region of a second conductivity type opposite to the first conductivity type, located closer to the second main surface than the first and second regions, A fourth region is provided which connects the first region and the second region, A photoelectric conversion device characterized in that the distance between the second region and the third region is shorter than the distance between the first region and the third region.

[0140] (Item 5) The photoelectric conversion device according to any one of items 1 to 4, characterized in that the fourth region has a lower impurity concentration than the first and second regions.

[0141] (Item 6) The photoelectric conversion unit further includes a fifth region between the third region and the second main surface, in which the impurity concentration is lower than that of the first and second regions. A photoelectric conversion device according to any one of items 1 to 5, characterized in that the charge generated in the fifth region by the incidence of light flows into the second region through a depletion region formed in the third region that overlaps with the second region in the orthogonal projection onto the first principal surface.

[0142] (Item 7) The photoelectric conversion device according to any one of items 1 to 6, characterized in that the fourth region includes the region of the first conductivity type.

[0143] (Item 8) The photoelectric conversion device according to item 7, characterized in that the fourth region functions as a resistor connecting the first region and the second region.

[0144] (Item 9) The photoelectric conversion device according to item 8, characterized in that the fourth region functions as a resistor of 20 kΩ or more.

[0145] (Item 10) The photoelectric conversion device according to any one of items 1 to 9, characterized in that the second region constitutes a part of the first main surface.

[0146] (Item 11) The photoelectric conversion device according to any one of items 1 to 9, characterized in that the second region is located between the first region and the third region.

[0147] (Item 12) The photoelectric conversion device according to any one of items 1 to 11, further comprising a setting circuit that, when the detection circuit detects avalanche breakdown, sets the potentials of the first region and the second region to a potential at which avalanche breakdown does not occur in the photoelectric conversion unit.

[0148] (Item 13) A photoelectric converter according to any one of items 1 to 12, further comprising a reset circuit for resetting the potentials of the first region and the second region to a predetermined potential.

[0149] (Item 14) The second region constitutes a part of the first main surface, The photoelectric conversion unit further comprises transistors that cause the first and second regions to function as source regions or drain regions, respectively, and the fourth region to function as a channel region. A photoelectric conversion device according to any one of items 1 to 6, characterized in that the conduction between the first region and the second region is controlled by the transistor.

[0150] (Item 15) The system further includes a reset circuit for resetting the potentials of the first and second regions to predetermined potentials. The transistor conducts at a predetermined period, The photoelectric conversion device according to item 14, characterized in that the reset circuit resets the potentials of the first region and the second region with the same period as the transistor.

[0151] (Item 16) The photoelectric conversion device according to item 15, characterized in that the detection circuit detects avalanche breakdown in accordance with the potential of the first region when the transistor conducts.

[0152] (Item 17) The system further includes a reset circuit for resetting the potentials of the first and second regions to predetermined potentials. The transistor conducts at a predetermined period, The photoelectric conversion device according to item 14, characterized in that the reset circuit resets the potentials of the first region and the second region each time the transistor conducts a predetermined number of times.

[0153] (Item 18) The photoelectric converter according to item 17, characterized in that the detection circuit generates a digital signal corresponding to the potential of the first region before the transistor conducts for a predetermined number of times and the reset circuit resets the potentials of the first region and the second region.

[0154] (Item 19) The photoelectric converter according to any one of items 15 to 18, characterized in that the reset circuit starts the reset while the transistor is conducting.

[0155] (Item 20) The photoelectric conversion device according to item 11, characterized in that it includes at least a region in which the first region and the second region overlap in a plan view, and has a sixth region of the second conductivity type located at a depth between the first region and the second region.

[0156] (Item 21) The photoelectric conversion device according to item 20, characterized in that the fourth region is surrounded by the sixth region in a plan view, has substantially the same depth as the sixth region, and has an impurity concentration of the second conductivity type or the first conductivity type that is lower than the impurity concentration of the sixth region. (Item 22) A photoelectric converter described in any one of items 1 through 21, A processing device that processes the signal output from the aforementioned photoelectric converter, A device characterized by being equipped with the following features.

[0157] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0158] 100 Photoelectric converter 102 Photoelectric conversion unit 204,206,207,208 area 201 APD 250 semiconductor substrates 251,252 Main surface

Claims

1. A photoelectric conversion device comprising a photoelectric conversion unit arranged on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The aforementioned photoelectric conversion unit is A first region of a first conductivity type, which constitutes a part of the first main surface and is connected to a detection circuit for detecting avalanche breakdown, A second region of the first conductivity type, which is located away from the first region, A third region of a second conductivity type opposite to the first conductivity type, located closer to the second main surface than the first and second regions, A fourth region is disposed between the first region and the second region, The second region and the third region function as an avalanche photodiode. A photoelectric conversion device characterized in that the first region and the second region are configured to be electrically conductive through the fourth region.

2. The photoelectric conversion apparatus according to claim 1, characterized in that the fourth region has a lower impurity concentration than the first and second regions.

3. The photoelectric conversion device according to claim 1, characterized in that the first region and the third region do not function as an avalanche photodiode.

4. The photoelectric conversion device according to claim 1, characterized in that the distance between the second region and the third region is shorter than the distance between the first region and the third region.

5. A photoelectric conversion device comprising a photoelectric conversion unit arranged on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The aforementioned photoelectric conversion unit is A first region of a first conductivity type, which constitutes a part of the first main surface and is connected to a detection circuit for detecting avalanche breakdown, A second region of the first conductivity type, which is located away from the first region, A third region of a second conductivity type opposite to the first conductivity type, located closer to the second main surface than the first and second regions, A fourth region is provided which connects the first region and the second region, A photoelectric conversion device characterized in that the distance between the second region and the third region is shorter than the distance between the first region and the third region.

6. The photoelectric conversion apparatus according to claim 5, characterized in that the fourth region has a lower impurity concentration than the first and second regions.

7. The photoelectric conversion unit further comprises a fifth region between the third region and the second main surface, the fifth region having a lower impurity concentration than the first and second regions. The photoelectric conversion device according to claim 1, characterized in that the charge generated in the fifth region by the incidence of light flows into the second region through a depletion region formed in the third region that overlaps with the second region in the orthogonal projection onto the first principal surface.

8. The photoelectric conversion device according to claim 1, characterized in that the fourth region includes the region of the first conductivity type.

9. The photoelectric conversion device according to claim 8, characterized in that the fourth region functions as a resistor connecting the first region and the second region.

10. The photoelectric conversion device according to claim 9, characterized in that the fourth region functions as a resistor of 20 kΩ or more.

11. The photoelectric conversion device according to claim 1, characterized in that the second region constitutes a part of the first main surface.

12. The photoelectric conversion device according to claim 1, characterized in that the second region is located between the first region and the third region.

13. The photoelectric conversion device according to claim 1, further comprising a setting circuit that, when the detection circuit detects avalanche breakdown, sets the potentials of the first region and the second region to a potential at which avalanche breakdown does not occur in the photoelectric conversion unit.

14. The photoelectric converter according to claim 1, further comprising a reset circuit for resetting the potentials of the first region and the second region to a predetermined potential.

15. The second region constitutes a part of the first main surface, The photoelectric conversion unit further comprises transistors that cause the first and second regions to function as source regions or drain regions, respectively, and the fourth region to function as a channel region. The photoelectric conversion device according to claim 1, characterized in that the conduction between the first region and the second region is controlled by the transistor.

16. The system further includes a reset circuit for resetting the potentials of the first and second regions to predetermined potentials. The transistor conducts at a predetermined period, The photoelectric conversion device according to claim 15, characterized in that the reset circuit resets the potentials of the first region and the second region with the same period as the transistor.

17. The photoelectric conversion device according to claim 16, characterized in that the detection circuit detects avalanche breakdown according to the potential of the first region when the transistor conducts.

18. The system further includes a reset circuit for resetting the potentials of the first and second regions to predetermined potentials. The transistor conducts at a predetermined period, The photoelectric conversion device according to claim 15, characterized in that the reset circuit resets the potentials of the first region and the second region each time the transistor conducts for a predetermined number of times.

19. The photoelectric converter according to claim 18, characterized in that the detection circuit generates a digital signal corresponding to the potential of the first region before the transistor conducts for a predetermined number of times and the reset circuit resets the potentials of the first region and the second region.

20. The photoelectric converter according to claim 16, characterized in that the reset circuit starts the reset while the transistor is conducting.

21. The photoelectric conversion device according to claim 12, characterized in that it includes at least a region in which the first region and the second region overlap in a plan view, and has a sixth region of the second conductivity type disposed at a depth between the first region and the second region.

22. The photoelectric conversion device according to claim 21, characterized in that the fourth region is surrounded by the sixth region in a plan view, has substantially the same depth as the sixth region, and has an impurity concentration of the second conductivity type or the first conductivity type that is lower than the impurity concentration of the sixth region.

23. A photoelectric conversion device according to any one of claims 1 to 22, A processing device that processes the signal output from the aforementioned photoelectric converter, A device characterized by being equipped with the following features.

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