Semiconductor equipment

Abstract

To provide a semiconductor device that enhances the effect of expanding the active region while suppressing the occurrence of cracks in the main electrode that affect the device characteristics. [Solution] The active region 45 of the semiconductor substrate 41 has a main region 451 and an extended region 452. The main region is arranged alongside the pad 44 in the Y direction. The extended region is a region with a smaller area than the main region, and in the Y direction it is connected to the pad-side edge of the main region, and in the X direction it is arranged alongside the pad. The protective film 56 has an opening 561 that overlaps with the emitter electrode 42. The opening is provided continuously across the main region and the extended region. In the opening, the radius of curvature of the inner corner 56C2, which is a corner that is convex inward from the active region, is larger than the radius of curvature of the outer corner 56C1, which is a corner that is convex outward from the active region.

Description

Technical Field

[0001] The disclosure in this specification relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device in which main electrodes are arranged on both surfaces of a semiconductor substrate. The description of the prior art document is incorporated herein by reference as an explanation of the technical elements in this specification.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, the active region where elements are formed extends outside the lower part of the terminal. Then, when the switching element in the extended region outside and the switching element in the region below the terminal are turned on, the elements are provided such that the current density in the extended region becomes lower than the current density in the region below the terminal. Thus, the current density in the extended region is low. From the above viewpoints or other viewpoints not mentioned, further improvement of the semiconductor device is required.

[0005] One disclosed object is to provide a semiconductor device capable of enhancing the effect of active region expansion. Another disclosed object is to provide a semiconductor device capable of suppressing the generation of cracks that affect element characteristics in the main electrode while enhancing the effect of active region expansion.

Means for Solving the Problems

[0006] The semiconductor device disclosed herein is A semiconductor substrate (41) having an active region (45) which is the formation region of a vertical element, and an outer peripheral region (46) that surrounds the active region in a plan view in the thickness direction of the substrate, A first main electrode (42) is arranged on the active region on one surface of the semiconductor substrate and is electrically connected to the vertical element, A second main electrode (43) is positioned on the back surface opposite to one side in the thickness direction of the plate and is electrically connected to the vertical element, A signal electrode, comprising a pad (44) arranged on the outer peripheral region on one surface, A protective film (56) is arranged on one surface and has an opening (561) that overlaps with the first main electrode in a plan view, Equipped with, The active region comprises a main region (451) positioned alongside the pad in a first direction perpendicular to the thickness direction, and an extended region (452) which is smaller in area than the main region in a plan view, is connected to the pad-side end of the main region in the first direction, and is positioned alongside the pad in a second direction perpendicular to the thickness direction and the first direction. The opening is, It is continuously provided across the main area and the extended area, In a plan view, the radius of curvature of the inner corner (56C2), which is located at the connection point between the main region and the extended region and is convex inward from the active region, is greater than the radius of curvature of the outer corner (56C1), which is located independently in either the main region or the extended region and is convex outward from the active region. It includes a conductive member (80) connected to the first main electrode, The conductive member has a planar shape corresponding to the opening in a predetermined range in the thickness direction from the end face on the first main electrode side, In the conductive member, the radius of curvature of the corner portion (80C2) corresponding to the inner corner portion is greater than or equal to the radius of curvature of the inner corner portion.

[0007] According to the disclosed semiconductor device, the openings in the protective film expand in proportion to the expansion of the active area. Heat from the expanded area can be dissipated upward through the openings. Therefore, the effect of expanding the active area can be enhanced.

[0008] Stress concentrates at the corners of the opening, which can cause cracks to form in the first main electrode, starting from the corners. In this case, the cracks propagate from the apex of the corner outward from the convexity. To enhance the effect of expanding the active region, the opening of the disclosed semiconductor device has an outer corner and an inner corner. In the case of the outer corner, even if a crack occurs, it propagates outward from the convexity, i.e., outward from the active region. In the case of the inner corner, if a crack occurs, it propagates outward from the convexity, i.e., inward from the active region. However, in the disclosed semiconductor device, the radius of curvature of the inner corner is increased, which can suppress the occurrence of cracks. Thus, it is possible to enhance the effect of expanding the active region while suppressing the occurrence of cracks in the first main electrode that affect the device characteristics.

[0009] The various embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference numerals in parentheses in this section are illustrative in their correspondence with the embodiments described later and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows a schematic configuration of a vehicle drive system to which the semiconductor device according to the first embodiment is applied. [Figure 2] This is a plan view showing a semiconductor device according to the first embodiment. [Figure 3] This is a cross-sectional view along line III-III in Figure 2. [Figure 4] A planar view showing a semiconductor device. [Figure 5] This is a cross-sectional view along the VV line in Figure 4. [Figure 6] This is a plan view showing the openings in the protective film. [Figure 7] This is a diagram showing a modified example. [Figure 8]It is a diagram showing a modified example. [Figure 9] In the semiconductor device according to the second embodiment, it is a plan view showing a semiconductor element. [Figure 10] It is a diagram showing the relationship of the inner corner part. [Figure 11] In the semiconductor device according to the third embodiment, it is a plan view showing a semiconductor element. [Figure 12] It is a cross-sectional view taken along line XII-XII of FIG. 11. [Figure 13] In the semiconductor device according to the fourth embodiment, it is a plan view showing a semiconductor element. [Figure 14] It is a cross-sectional view taken along line XIV-XIV of FIG. 13. [Figure 15] In the semiconductor device according to the fifth embodiment, it is a plan view showing a semiconductor element.

Modes for Carrying Out the Invention

[0011] Hereinafter, a plurality of embodiments will be described based on the drawings. In each embodiment, the same reference numerals may be given to corresponding components, and redundant explanations may be omitted. When only a part of the configuration is described in each embodiment, the configuration of other embodiments described previously can be applied to the other parts of the said configuration. Also, not only the combinations of configurations explicitly shown in the description of each embodiment, but also the configurations of a plurality of embodiments can be partially combined with each other as long as there is no problem with the combination, even if not explicitly shown.

[0012] The semiconductor device of this embodiment is applied, for example, to a power conversion device of a moving body having a rotating electric machine as a drive source. The moving body is, for example, an electric vehicle (BEV), a hybrid vehicle (HEV), a plug-in hybrid vehicle (PHEV), or other electric vehicles, a flying body such as an electric vertical take-off and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine. Hereinafter, an example applied to a vehicle will be described.

[0013] (First Embodiment) First, based on Figure 1, we will explain the general configuration of the vehicle's drive system.

[0014] <Vehicle drive system> As shown in Figure 1, the vehicle's drive system 1 includes a DC power supply 2, a motor generator 3, and a power converter 4.

[0015] The DC power supply 2 is a DC voltage source composed of rechargeable secondary batteries. These secondary batteries are, for example, lithium-ion batteries or nickel-metal hydride batteries. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as the vehicle's driving source, i.e., an electric motor. During regeneration, the motor generator 3 functions as a generator. The power converter 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0016] <Power converter> Next, the circuit configuration of the power converter 4 will be described based on Figure 1. The power converter 4 is equipped with a power conversion circuit. As shown in Figure 1, the power converter 4 is equipped with a smoothing capacitor 5 and an inverter 6 which is a power conversion circuit.

[0017] The smoothing capacitor 5 primarily smooths the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the P line 7, which is the high-potential power line, and the N line 8, which is the low-potential power line. The P line 7 is connected to the positive terminal of the DC power supply 2, and the N line 8 is connected to the negative terminal of the DC power supply 2. The positive terminal of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. Similarly, the negative terminal is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0018] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage to a three-phase AC voltage according to switching control by a control circuit (not shown) and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to the rotational force from the wheels to a DC voltage according to switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0019] The inverter 6 is configured with three phase upper and lower arm circuits 9. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via the output line 10. The inverter 6 has six arms. At least a portion of each of the P line 7, N line 8, and output line 10 is made up of conductive material such as a busbar.

[0020] Each arm is composed of an insulated-gate bipolar transistor 11 (hereinafter referred to as IGBT11), which is a switching element, and a freewheeling diode 12. In this embodiment, an n-channel type IGBT11 is used. The diode 12 is connected in antiparallel to the corresponding IGBT11. In the upper arm 9H, the collector of the IGBT11 is connected to the P line 7. In the lower arm 9L, the emitter of the IGBT11 is connected to the N line 8. The emitter of the IGBT11 in the upper arm 9H and the collector of the IGBT11 in the lower arm 9L are interconnected. The anode of the diode 12 is connected to the emitter of the corresponding IGBT11, and the cathode is connected to the collector.

[0021] The power converter 4 may further include a converter as a power conversion circuit. The converter is a DC-DC converter circuit that converts a DC voltage to a DC voltage of a different value. The converter is placed between the DC power supply 2 and the smoothing capacitor 5. The converter is configured, for example, with a reactor and the above-described up-and-down arm circuit 9. With this configuration, step-up and step-down voltage conversion is possible. The power converter 4 may also include a filter capacitor to remove power supply noise from the DC power supply 2. The filter capacitor is placed between the DC power supply 2 and the converter.

[0022] The power converter 4 may include a drive circuit for the switching elements that make up the inverter 6, etc. The drive circuit supplies a drive voltage to the gate of the corresponding arm's IGBT 11 based on a drive command from the control circuit. The drive circuit drives the corresponding IGBT 11, i.e., turns it on or off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0023] The power converter 4 may include a control circuit for the switching element. The control circuit generates a drive command to operate the IGBT 11 and outputs it to the drive circuit. The control circuit generates the drive command based on a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. Examples of various sensors include a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the windings 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs a PWM signal as a drive command. The control circuit is configured to include, for example, a processor and memory. ECU is an abbreviation for Electronic Control Unit. PWM is an abbreviation for Pulse Width Modulation.

[0024] <Semiconductor device> Next, semiconductor devices to which semiconductor elements are applied will be described based on Figures 2 and 3. Figure 2 is a plan view showing a semiconductor device. Figure 2 is a top view plan view of a semiconductor device. Figure 3 is a cross-sectional view along line III-III in Figure 2. In Figure 3, the structure of the semiconductor element is illustrated in a simplified manner.

[0025] In the following, the thickness direction of the semiconductor substrate is defined as the Z direction. The direction perpendicular to the Z direction is defined as the X direction. The direction perpendicular to both the Z and X directions is defined as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is defined as the planar shape. Furthermore, the view from the Z direction is simply referred to as the planar view.

[0026] As shown in Figures 2 and 3, the semiconductor device 20 comprises a encapsulant 30, a semiconductor element 40, wiring members 70, 70, a conductive spacer 80, and an external connection terminal 90. The semiconductor device 20 constitutes one of the arms described above. Thus, two semiconductor devices 20 constitute one phase of the upper and lower arm circuit 9.

[0027] The encapsulant 30 encapsulates a portion of the other elements that constitute the semiconductor device 20. The remaining parts of the other elements are exposed outside the encapsulant 30. The encapsulant 30 is made of, for example, a resin. An example of a resin is an epoxy resin. The encapsulant 30 is molded from the resin by, for example, a transfer molding method. Such a encapsulant 30 may be referred to as a resin encapsulant, molded resin, or resin molded body. The encapsulant 30 may also be formed using, for example, a gel. The gel is filled (placed) in, for example, the opposing regions of a pair of wiring members 70, 70.

[0028] As shown in Figure 2, the sealant 30 has a substantially rectangular shape in plan. The sealant 30 has an outer surface, which is one side 30a and a back surface 30b. The back surface 30b is the surface opposite to the one side 30a in the Z direction. The one side 30a and the back surface 30b are, for example, flat surfaces. The sealant 30 has sides that are continuous with the one side 30a and the back surface 30b. The sides include two sides 30c and 30d from which the external connection terminal 90 protrudes. The side 30d is the surface opposite to the side 30c in the X direction.

[0029] The semiconductor element 40 comprises a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44. The semiconductor element 40 is sometimes referred to as a semiconductor chip. The semiconductor substrate 41 is made of materials such as silicon (Si) or a wide-bandgap semiconductor with a wider bandgap than silicon, and a vertical element is formed from it. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0030] The vertical element is configured to conduct the main current in the thickness direction, i.e., the Z direction, of the semiconductor substrate 41 (semiconductor element 40). In this embodiment, the vertical element consists of an IGBT 11 and a diode 12 that constitute a single arm. The vertical element is an IGBT with the diode 12 connected in antiparallel, i.e., an RC (Reverse Conducting) IGBT. The vertical element is a heating element that generates heat when current is passed through it. A gate electrode (not shown) is formed on the semiconductor substrate 41. The gate electrode has, for example, a trench structure.

[0031] The semiconductor substrate 41 has a front surface 41a and a back surface 41b on which the main electrodes are provided. Front surface 41a is the surface of the semiconductor substrate 41 that faces the front surface 30a of the encapsulant 30. Back surface 41b is the surface opposite to front surface 41a in the thickness direction. One of the main electrodes, the emitter electrode 42, is located on front surface 41a of the semiconductor substrate 41. The other main electrode, the collector electrode 43, is located on back surface 41b of the semiconductor substrate 41. The emitter electrode 42 corresponds to the first main electrode, and the collector electrode 43 corresponds to the second main electrode.

[0032] When the IGBT 11 is turned on, a current (main current) flows between the main electrodes, that is, between the emitter electrode 42 and the collector electrode 43. The emitter electrode 42 also serves as the anode electrode of the diode 12. The collector electrode 43 also serves as the cathode electrode of the diode 12. The collector electrode 43 is formed over almost the entire back surface 41b of the semiconductor substrate 41. The emitter electrode 42 is formed on a portion of one side 41a of the semiconductor substrate 41.

[0033] The pad 44 is a signal electrode. The pad 44 is formed on one surface 41a of the semiconductor substrate 41 in a region different from the region where the emitter electrode 42 is formed. In the Y direction, the pad 44 is formed at the end opposite to the region where the emitter electrode 42 is formed. The pad 44 is provided alongside the emitter electrode 42 in the Y direction. The pad 44 includes at least a pad for the gate electrode. Details of the semiconductor element 40 will be described later.

[0034] The wiring member 60 is electrically connected to the emitter electrode 42 and provides a wiring function. Similarly, the wiring member 70 is electrically connected to the collector electrode 43 and provides a wiring function. The wiring members 60 and 70 are arranged so as to sandwich the semiconductor element 40 in the Z direction. The wiring members 60 and 70 are arranged so that at least a portion of them faces each other in the Z direction. In a plan view, the wiring members 60 and 70 enclose the semiconductor element 40. The wiring member 60 corresponds to the first wiring member, and the wiring member 70 corresponds to the second wiring member.

[0035] The wiring members 60 and 70 provide a heat dissipation function to dissipate the heat generated by the semiconductor element 40. The wiring members 60 and 70 are sometimes referred to as heat sinks or heat dissipation plates. In this embodiment, the wiring members 60 and 70 are metal plates made of a metal with good conductivity, such as Cu or a Cu alloy. The metal plates are provided, for example, as part of a lead frame. Instead of metal plates, a substrate in which a metal body is placed on the surface of an insulating substrate may be used. The wiring members 60 and 70 may have a plating film of Ni or Au on their surface.

[0036] The wiring member 60 has an opposing surface 60a, which is the side facing the semiconductor element 40, and a back surface 60b, which is the side opposite to the opposing surface 60a. Similarly, the wiring member 70 also has an opposing surface 70a and a back surface 70b. The wiring members 60 and 70 are, for example, roughly rectangular in shape. The back surfaces 60b and 70b of the wiring members 60 and 70, respectively, are exposed from the encapsulant 30. The back surfaces 60b and 70b are sometimes referred to as heat dissipation surfaces or exposed surfaces. The back surface 60b of the wiring member 60 is roughly flush with one surface 30a of the encapsulant 30. The back surface 70b of the wiring member 70 is roughly flush with the back surface 30b of the encapsulant 30.

[0037] The conductive spacer 80 is interposed between the semiconductor element 40 and the wiring member 60. The conductive spacer 80 is connected to the emitter electrode 42. The conductive spacer 80 is connected to the wiring member 60. The conductive spacer 80 provides a spacer function to ensure a predetermined distance between the semiconductor element 40 and the wiring member 60. For example, the conductive spacer 80 ensures height for electrically connecting the corresponding signal terminal 93 to the pad 44 of the semiconductor element 40. The conductive spacer 80 is located in the middle of the electrical and thermal conduction paths between the emitter electrode 42 of the semiconductor element 40 and the wiring member 60, and provides wiring and heat dissipation functions.

[0038] The conductive spacer 80 contains a metallic material with good electrical and thermal conductivity, such as Cu. The conductive spacer 80 may have a plating film on its surface. The conductive spacer 80 is sometimes referred to as a terminal, terminal block, or metal block. The semiconductor device 20 has the same number of conductive spacers 80 as the semiconductor elements 40. The conductive spacers 80 are individually connected to the semiconductor elements 40. The conductive spacer 80 is, for example, a columnar body. In a plan view, the conductive spacer 80 has a shape corresponding to the opening 561, which will be described later. The conductive spacer 80 is approximately the same size as or slightly smaller than the opening 561. The conductive spacer 80 is positioned directly above the main region 451 and directly above the extended region 452, which will be described later.

[0039] The external connection terminal 90 is a terminal for electrically connecting the semiconductor device 20 to an external device. The external connection terminal 90 is formed using a metal material with good conductivity, such as copper. The external connection terminal 90 is, for example, a plate. The external connection terminal 90 is sometimes referred to as a lead. The external connection terminal 90 comprises main terminals 91 and 92 and a signal terminal 93. The main terminals 91 and 92 are external connection terminals 90 that are electrically connected to the main electrodes of the semiconductor element 40.

[0040] The main terminal 91 is electrically connected to the emitter electrode 42. The main terminal 91 is sometimes referred to as the emitter terminal. The main terminal 91 is connected to the emitter electrode 42 via the wiring member 60. The main terminal 91 is connected to one end of the wiring member 60 in the Y direction. The thickness of the main terminal 91 is thinner than that of the wiring member 60. The main terminal 91 is connected to the wiring member 60, for example, so as to be substantially flush with the opposing surface 60a. The main terminal 91 may be connected to the wiring member 60 by being provided integrally with it, or it may be provided as a separate member and connected by joining.

[0041] In this embodiment, the main terminal 91 is provided integrally with the wiring member 60 as part of the lead frame. The main terminal 91 extends from the wiring member 60 in the Y direction and protrudes to the outside from the side surface 30c of the sealant 30. The main terminal 91 has a bent portion in the middle of the part covered by the sealant 30 and protrudes from near the center in the Z direction on the side surface 30c.

[0042] The main terminal 92 is electrically connected to the collector electrode 43. The main terminal 92 is sometimes referred to as the collector terminal. The main terminal 92 is connected to the collector electrode 43 via the wiring member 70. The main terminal 92 is connected to one end of the wiring member 70 in the Y direction. The thickness of the main terminal 92 is thinner than that of the wiring member 70. The main terminal 92 is connected to the wiring member 70, for example, so as to be substantially flush with the opposing surface 70a. The main terminal 92 may be connected to the wiring member 70 by being provided integrally with it, or it may be provided as a separate member and connected by joining.

[0043] In this embodiment, the main terminal 92 is provided integrally with the wiring member 70 as part of a lead frame separate from the main terminal 91. The main terminal 92 extends from the wiring member 70 in the Y direction and protrudes to the outside from the same side surface 30c as the main terminal 91. The main terminal 92 also has a bent portion in the middle of the part covered by the sealant 30 and protrudes from near the center in the Z direction on the side surface 30c. The two main terminals 91 and 92 are arranged side by side in the X direction with their sides facing each other.

[0044] The signal terminals 93 are electrically connected to the pads 44 of the semiconductor element 40. In this embodiment, they are electrically connected via bonding wires 100. The signal terminals 93 extend in the Y direction and protrude outward from the side surface 30d of the encapsulant 30. Side surface 30d is the side opposite to side surface 30c in the Y direction. The semiconductor device 20 of this embodiment has five signal terminals 93 corresponding to the pads 44. The signal terminals 93 are configured on a lead frame common to, for example, the wiring member 70 and the main terminal 92. Multiple signal terminals 93 are electrically isolated from each other by cutting tie bars (not shown).

[0045] The emitter electrode 42 of the semiconductor element 40 is joined to the conductive spacer 80 via bonding material 101. The conductive spacer 80 is joined to the wiring member 60 via bonding material 102. The collector electrode 43 of the semiconductor element 40 is joined to the wiring member 70 via bonding material 103. Bonding materials 101 to 103 are conductive bonding materials. For example, solder can be used as bonding materials 101 to 103. An example of solder is a multi-component lead-free solder containing Cu, Ni, etc., in addition to Sn. Instead of solder, a sintered bonding material such as sintered silver may be used. Bonding materials 101 to 103 may be made of the same material as each other, or they may be made of different materials. In this embodiment, solder is used as bonding materials 101, 102, and 103.

[0046] As described above, in the semiconductor device 20, the semiconductor element 40 that constitutes one arm is sealed by the sealing body 30. The sealing body 30 integrally seals the semiconductor element 40, a part of the wiring member 60, a part of the wiring member 70, the conductive spacer 80, and a part of the external connection terminal 90.

[0047] In the Z direction, the semiconductor element 40 is positioned between the wiring members 60 and 70. The semiconductor element 40 is sandwiched between the opposing wiring members 60 and 70. The semiconductor device 20 has a double-sided heat dissipation structure. The semiconductor device 20 can efficiently dissipate the heat from the semiconductor element 40 to both sides in the Z direction. The back surface 60b of the wiring member 60 is substantially flush with one surface 30a of the encapsulant 30. The back surface 70b of the wiring member 70 is substantially flush with the back surface 30b of the encapsulant 30. Since the back surfaces 60b and 70b are exposed surfaces, heat dissipation can be enhanced.

[0048] <Semiconductor elements> Next, the semiconductor device 40 will be described based on Figures 4 and 5. Figure 4 is a plan view showing one side of the semiconductor device 40. For convenience, the active region, including the IGBT region and the diode region, is shown with a solid line in Figure 4. The emitter electrode 42 and protective film are omitted. Figure 5 is a cross-sectional view along the VV line in Figure 4.

[0049] As shown in Figure 4, the semiconductor substrate 41 has a roughly rectangular shape. The semiconductor substrate 41 has an active region 45. The active region 45 is the region for forming vertical elements. The active region 45 is sometimes referred to as the main region, main cell region, cell region, element region, or element formation region.

[0050] The active region 45 has a main region 451 and an extended region 452. The main region 451 is aligned with the pad 44 in the Y direction. The extended region 452 is a region with a smaller area than the main region 451 in a plan view. Area refers to the area along the XY plane. The extended region 452 is connected to the end of the main region 451 on the pad 44 side in the Y direction. The extended region 452 is a region that extends from the main region 451 in the Y direction. The extended region 452 is aligned with the pad 44 in the X direction. The extended region 452 is a region next to the pad. The Y direction corresponds to the first direction, and the X direction corresponds to the second direction.

[0051] As an example, in this embodiment, the active region 45 has two extended regions 452. In the X direction, one of the extended regions 452 is connected to the vicinity of one end of the main region 451, and the other extended region 452 is connected to the vicinity of the other end of the main region 451. A pad 44 is positioned between the two extended regions 452. The active region 45 has a planar shape that is roughly U-shaped or roughly C-shaped.

[0052] The active region 45 of the RC-IGBT includes an IGBT region 45i, which is the IGBT formation region, and a diode region 45d, which is the diode formation region. The IGBT region 45i and the diode region 45d are arranged alternately in the Y direction. Multiple cells (unit structures) are provided in the active region 45. Multiple cells are connected in parallel to each other to form an RC-IGBT. As an example, the IGBT region 45i and the diode region 45d are arranged alternately at a predetermined pitch across the main region 451 and the extended region 452.

[0053] The semiconductor substrate 41 has an outer peripheral region 46 that surrounds the active region 45. In a plan view, the outer peripheral region 46 is the region outside the outer peripheral edge of the active region 45. Although not shown in the figures, a pressure-resistant structure such as a guard ring is formed in the outer peripheral region 46.

[0054] As shown in Figure 5, the semiconductor substrate 41 has a collector region 47, a cathode region 48, a buffer region 49, a drift region 50, a base region 51, and an emitter region 52. The semiconductor substrate 41 is formed by creating each semiconductor region through methods such as ion implantation of impurities. The semiconductor region is sometimes referred to as a semiconductor layer or a diffusion layer.

[0055] The collector region 47 is formed on the surface layer of the back surface 41b of the semiconductor substrate 41. The collector region 47 is a p-conductivity type (p+) semiconductor region with a higher impurity concentration than the base region 51. The cathode region 48 is also formed on the surface layer of the back surface 41b. The cathode region 48 is an n-conductivity type (n+) semiconductor region with a higher impurity concentration than the drift region 50. The cathode region 48 is provided alongside the collector region 47 in the XY plane. The collector region 47 is provided in the IGBT region 45i, and the cathode region 48 is provided in the diode region 45d. The cathode region 48 is provided alternately with the collector region 47 in the Y direction.

[0056] The buffer region 49 is formed on the surface opposite to the back surface 41b in the collector region 47 and the cathode region 48. The buffer region 49 is formed between the collector region 47 and the cathode region 48 and the drift region 50. The buffer region 49 is an n-conductivity type semiconductor region (n) with a lower impurity concentration than the cathode region 48 and a higher impurity concentration than the drift region 50. By providing the buffer region 49, it is possible to suppress the depletion layer from spreading towards the collector region 47.

[0057] The drift region 50 is formed on the surface of the buffer region 49 opposite to the surface on the collector region 47 side. The drift region 50 is an n-conductivity semiconductor region with a lower impurity concentration than the buffer region 49.

[0058] The base region 51 is formed on the surface opposite to the buffer region 49 side in the drift region 50. The base region 51 is a p-conductivity (p) semiconductor region with a lower impurity concentration than the collector region 47. The base region 51 is mainly located in the active region 45 of the semiconductor substrate 41. The base region 51 is formed on the surface layer of one side 41a of the semiconductor substrate 41. The base region 51 is sometimes referred to as the channel region. If the n-conductivity type is the first conductivity type, then the p-conductivity type is the second conductivity type.

[0059] The emitter region 52 is located on the surface layer on the side 41a within the base region 51. The emitter region 52 is an n-conductivity (n+) semiconductor region with a higher impurity concentration than the drift region 50. The emitter region 52 is formed in the IGBT region 45i of the active region 45. Within the IGBT region 45i, the emitter region 52 is located in contact with the side surface of the trench 53, which will be described later.

[0060] Trenches 53 are formed in the semiconductor substrate 41 having the above configuration. The trenches 53 are formed from one surface 41a to a predetermined depth. The trenches 53 penetrate the base region 51. The tip of the trench 53 reaches the drift region 50. Multiple trenches 53 are formed in the active region 45 of the semiconductor substrate 41. Each trench 53 extends in the X direction. Multiple trenches 53 are arranged at approximately equal intervals in the Y direction, forming a stripe pattern in plan view. The trenches 53 define cells. Each cell contains one trench 53, and multiple cells are arranged side by side in the Y direction.

[0061] A gate insulating film 54 is formed on the wall surface of the trench 53. A gate electrode 55 is formed on the surface of the gate insulating film 54 so as to fill the trench 53. The gate electrode 55 penetrates the base region 51 and reaches the drift region 50. Multiple gate electrodes 55 are formed in the active region 45 of the semiconductor substrate 41. Each gate electrode 55 extends in the X direction. The multiple gate electrodes 55 are arranged at approximately equal intervals in the Y direction, forming a stripe shape in a plan view.

[0062] An emitter electrode 42 is formed on one surface 41a of the semiconductor substrate 41. The emitter electrode 42 is mainly formed on the active region 45. The emitter electrode 42 is electrically connected to the emitter region 52 and the base region 51. The emitter electrode 42 is electrically isolated from the gate electrode 55. The emitter electrode 42 may also be electrically connected to the base region 51 via a base contact region. The base contact region is provided on the surface layer on the side of the one surface 41a within the base region 51. The base contact region is provided adjacent to the emitter region 52. The base contact region is a p-conductivity type (p+) semiconductor region with a higher impurity concentration than the base region 51.

[0063] Pads 44, which are signal electrodes, are also formed on one surface 41a of the semiconductor substrate 41. The pads 44 are arranged on the outer peripheral region 46. The semiconductor element 40 of this embodiment has five pads 44. Specifically, there is a pad for the gate electrode, a pad for the Kelvin emitter that detects the emitter potential of the IGBT 11, a pad for current sensing, a pad for the anode potential of the thermosensitive diode (thermosensitive element) that detects the temperature of the semiconductor element 40, and a pad for the cathode potential of the thermosensitive diode (thermosensitive element). The pad 44 for the Kelvin emitter is electrically connected to the emitter electrode 42. The other pads 44 are electrically isolated from the emitter electrode 42. The five pads 44 are formed together on one end in the Y direction and arranged in the X direction on the semiconductor substrate 41, which is approximately rectangular in shape. The five pads 44 are located near the center of the edge of the semiconductor substrate 41 along the X direction.

[0064] The semiconductor element 40 has a protective film 56 disposed on one surface 41a of the semiconductor substrate 41. The protective film 56 is an insulating film provided on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral edge of the emitter electrode 42. For example, polyimide or silicon nitride can be used as the material for the protective film 56. The protective film 56 has an opening 561 that defines the bonding region between the emitter electrode 42 and the bonding material 101. The opening 561 is a through hole that penetrates the protective film 56 in the Z direction. The opening 561 is provided so as to overlap with the emitter electrode 42 in a plan view. Similarly, the protective film 56 has an opening (not shown) that defines the bonding region at the pad 44.

[0065] The emitter electrode 42 has an exposed portion 421 that is exposed through the opening 561 of the protective film 56 and provides a bonding area. The exposed portion 421 forms a bonding area with the bonding material 101. In plan view, the outer contour of the exposed portion 421 matches the outer contour of the opening 561. The exposed portion 421 is located on the active area 45. The emitter electrode 42 has a multilayer structure. The emitter electrode 42 has a base electrode 422 and a connecting electrode 423. The pad 44 has a similar configuration to the emitter electrode 42.

[0066] The base electrode 422 is a metal layer formed adjacent to the semiconductor substrate 41 in the multilayer emitter electrode 42. The base electrode 422 is sometimes referred to as the lower electrode, lower layer electrode, wiring electrode, or first metal layer. The base electrode 422 is connected to one surface 41a of the semiconductor substrate 41. The base electrode 422 is formed using a material mainly composed of Al (aluminum), for example. In this embodiment, an Al alloy such as AlSi or AlSiCu is used as the material.

[0067] The base electrode 422 extends over the outer peripheral region 46 while encompassing the active region 45 in a plan view. The base electrode 422 is connected to the emitter region 52 and the base region 51. In a plan view, the base electrode 422 has a peripheral edge 422a surrounding the exposed portion 421. The peripheral edge 422a is the portion of the base electrode 422 that overlaps with the protective film 56. The protective film 56 is arranged on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral edge 422a of the base electrode 422.

[0068] The connecting electrode 423 is laminated on the base electrode 422 for purposes such as improving bonding strength with the bonding material 101 and improving wettability to the bonding material 101. The connecting electrode 423 is also referred to as the upper base electrode, upper electrode, upper layer electrode, or second metal layer. The connecting electrode 423 includes at least one metal layer. The metal layer constituting the connecting electrode 423 includes, for example, Ni, Pd, Au, Pt, or Ag.

[0069] The connecting electrode 423 in this embodiment includes at least a nickel (Ni) layer. Ni is harder than the Al alloy that constitutes the base electrode 422. A gold (Au) layer may be further provided on the Ni layer. The Au layer, for example, suppresses oxidation of the Ni layer and improves wettability with the solder, which is the bonding material 101. Since Au diffuses into the solder during soldering, the Au layer exists before soldering and does not exist after soldering.

[0070] The connecting electrode 423 is stacked on the base electrode 422 and exposed through the opening 561. As an example, in this embodiment, the connecting electrode 423 is positioned on the base electrode 422 within the opening 561. The outer peripheral end of the connecting electrode 423 is in contact with, for example, the wall surface of the protective film 56 that defines the opening 561. The exposed portion 421 of the emitter electrode 42 is composed of the portion of the base electrode 422 that overlaps with the opening 561 in a plan view, and the connecting electrode 423.

[0071] A collector electrode 43 is formed on the back surface 41b of the semiconductor substrate 41. The collector electrode 43 is formed over almost the entire surface of the back surface 41b. The collector electrode 43 is electrically connected to the collector region 47 and the cathode region 48.

[0072] In the semiconductor device 40 described above, an IGBT structure is formed in each cell of the IGBT region 45i. The IGBT structure includes a collector region 47, a buffer region 49, a drift region 50, a base region 51, an emitter region 52, and a gate electrode 55. In addition, a diode structure is formed in each cell of the diode region 45d. The diode structure includes a cathode region 48, a buffer region 49, a drift region 50, and a base region 51 that functions as an anode.

[0073] A guard ring 57 is formed in the outer peripheral region 46 of the semiconductor substrate 41. By providing the guard ring 57, when a high voltage is applied to the IGBT region 45i, the depletion layer extending from the base region 51 is extended in a direction along one surface 41a, thereby mitigating the electric field strength. In other words, the breakdown voltage of the semiconductor element 40 can be increased. The guard ring 57 is provided so as to surround the active region 45. The number of guard rings 57 is not particularly limited. At least one or more is sufficient. In the example shown in Figure 6, one of the guard rings 57 is provided adjacent to the edge of the base region 51. Another guard ring 57 is provided at a position away from the inner guard ring 57.

[0074] <Opening in the protective film> Next, the opening 561 of the protective film 56 will be described based on Figure 6. Figure 6 is a plan view showing one side of the semiconductor element 40. For convenience, the active region is shown with a dashed line in Figure 6. The dotted line in the figure indicates the boundary between the main region 451 and the extended region 452. The outer edge of the exposed portion 421 of the emitter electrode 42, that is, the end (opening) of the opening 561 of the protective film 56, is shown with a solid line.

[0075] As shown in Figure 6, the opening 561 of the protective film 56 is continuously provided across the main region 451 and the extended region 452 of the active region 45. In plan view, the opening 561 has multiple corners. These multiple corners include an outer corner 561C1 and an inner corner 561C2.

[0076] The outer corner portion 561C1 is a corner portion that protrudes outward from the active region 45. The outer corner portion 561C1 is present in both the main region 451 and the extended region 452. The outer corner portion 561C1 is not continuously provided across the main region 451 and the extended region 452, but is located independently in either the main region 451 or the extended region 452. A portion of the outer corner portion 561C1 is located independently in the main region 451. Another portion of the outer corner portion 561C1 is located independently in the extended region 452. The semiconductor element 40 of this embodiment has six outer corner portions 561C1. Specifically, the main region 451 has two outer corner portions 561C1. Each of the extended regions 452 has two outer corner portions 561C1.

[0077] The inner corner portion 561C2 is a corner portion that protrudes inward from the active region 45. The inner corner portion 561C2 is located at the connection between the main region 451 and the extended region 452. The inner corner portion 561C2 is continuously provided across the main region 451 and the extended region 452. The semiconductor element 40 has two inner corner portions 561C2.

[0078] The radii of curvature of the outer corners 561C1 are approximately equal to each other. The radius of curvature of the outer corners 561C1 is greater than the radius of curvature of the corresponding outer corner of the active region 45. The radii of curvature of the inner corners 561C2 are approximately equal to each other. The radius of curvature of the inner corners 561C2 is greater than the radius of curvature of the corresponding inner corner of the active region 45. The radius of curvature of the inner corners 561C2 is greater than the radius of curvature of the outer corners 561C1.

[0079] <Summary of the First Embodiment> As described above, in this embodiment, the active region 45 has a main region 451 and an extended region 452. In other words, the active region 45 is expanded to the area next to the pad 44. In addition, the opening 561 of the protective film 56 is expanded in accordance with the expansion of the active region 45. This allows heat from the extended region 452 to escape upward through the opening 561. Specifically, heat can be escaped from the portion directly above the extended region 452 in the exposed portion 421 of the emitter electrode 42 to the conductive spacer 80 and, consequently, the wiring member 60 via the bonding material 101. Of course, heat can also be escaped from the portion directly above the main region 451 in the exposed portion 421 of the emitter electrode 42 to the conductive spacer 80 and, consequently, the wiring member 60 via the bonding material 101.

[0080] Therefore, it is possible to suppress the temperature of the extended region 452 from rising higher than the temperature of the main region 451. In other words, it is possible to suppress the need to turn off the IGBT due to a temperature rise in the extended region 452. It is possible to suppress the situation where it becomes impossible to supply any more current to the semiconductor device 20 even though the main region 451 has not become very hot, and a large current can be supplied to the semiconductor device 20 until the main region 451 becomes hot. As a result, the effect of expanding the active region can be enhanced. With the above configuration, it is possible to suppress the temperature rise of the entire active region 45 at the timing when the IGBT is operated and a large current is supplied to the motor generator 3, for example, during thermal point operations such as climbing a hill or overtaking.

[0081] Stress concentrates at the corners of the opening 561, which can cause cracks to form in the emitter electrode 42, starting from the corners. In this case, the cracks propagate from the apex of the corner outwards. As described above, in the semiconductor device 20 of this embodiment, the openings 561 of the protective film 56 are continuously provided across the main region 451 and the expanded region 452 in order to enhance the effect of expanding the active region. As a result, the opening 561 has an outer corner portion 561C1 and an inner corner portion 561C2.

[0082] In the case of the outer corner 561C1, even if a crack occurs, it propagates to the outside of the active region 45, i.e., the outer peripheral region 46. Therefore, even if a crack occurs in the emitter electrode 42, it has almost no effect on the device characteristics. In the case of the inner corner 561C2, if a crack occurs, it propagates to the outside of the convex, i.e., to the inside of the active region 45. However, since the radius of curvature of the inner corner 561C2 is larger than the radius of curvature of the outer corner 561C1, stress is less likely to concentrate in the inner corner 561C2. Therefore, it is possible to suppress the occurrence of cracks originating from the inner corner 561C2. In other words, it is possible to suppress the occurrence of cracks in the emitter electrode 42 that would affect the device characteristics.

[0083] Based on the above, the semiconductor device 20 of this embodiment can enhance the effect of expanding the active region while suppressing the occurrence of cracks that affect the device characteristics.

[0084] The extended region 452 is located next to the pad 44 in the X direction. This allows for the effective use of the empty space next to the pad 44, making it possible to expand the active region 45 without changing the area of ​​the semiconductor substrate 41, i.e., the chip area.

[0085] <Variation> The arrangement of the pads 44 and the active region 45 is not limited to the example described above. For example, as shown in Figure 7, the pads 44 may be arranged together on one end in the X direction. Figure 7 corresponds to Figure 6. The active region 45 has only one extension region 452. The extension region 452 is positioned off-center in the X direction, opposite to the pads 44.

[0086] In the example shown in Figure 7, the semiconductor element 40 (aperture 561) has five outer corners 561C1 and one inner corner 561C2. Specifically, the main region 451 has three outer corners 561C1, and the extended region 452 has two outer corners 561C1.

[0087] The number of pads 44 is not limited to the example described above. The semiconductor element 40 has at least one pad 44. For example, as shown in Figure 8, it may have only one pad 44. The pad 44 is a pad for the gate electrode 55. Figure 8 corresponds to Figure 6. Compared to the example shown in Figure 6, the area of ​​the extended region 452 is larger because there are fewer pads 44. In this configuration as well, the semiconductor element 40 has six outer corners 561C1 and two inner corners 561C2, similar to Figure 6.

[0088] In the examples shown in Figures 7 and 8, the radius of curvature of the inner corner 561C2 is larger than the radius of curvature of the outer corner 561C1. Therefore, it is possible to enhance the effect of expanding the active region while suppressing the occurrence of cracks that affect the element characteristics.

[0089] (Second Embodiment) This embodiment is a modification based on the prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the corners of the conductive spacer 80 were not specifically mentioned. Instead, the corners of the conductive spacer 80 may also be made to satisfy the predetermined relationship.

[0090] Figure 9 shows an example of a semiconductor element 40 in the semiconductor device 20 according to this embodiment. Figure 9 also shows a conductive spacer 80, which is a conductive member connected to the emitter electrode 42. The semiconductor element 40 shown in Figure 9 has the same configuration as in the prior embodiment (see Figure 6).

[0091] The conductive spacer 80 has a planar shape corresponding to the opening 561 in a predetermined range in the Z direction from the end face on the emitter electrode 42 side. The predetermined range may be the entire length in the Z direction or a part thereof. The conductive spacer 80 in this embodiment is a columnar body having a shape corresponding to the opening 561 in a plan view, similar to the prior embodiment. The conductive spacer 80 is a columnar body that is roughly U-shaped (C-shaped). The conductive spacer 80 is slightly smaller than the opening 561.

[0092] The conductive spacer 80 is continuously provided across the main region 451 and the extended region 452 of the active region 45. In plan view, the conductive spacer 80 has multiple corners. These multiple corners include an outer corner 80C1 and an inner corner 80C2.

[0093] The outer corner portion 80C1 is a corner portion that protrudes outward from the active region 45. The outer corner portion 80C1 is a corner portion that corresponds to the outer corner portion 561C1. A portion of the outer corner portion 80C1 is located independently in the main region 451. Another portion of the outer corner portion 80C1 is located independently in the extended region 452. The semiconductor element 40 of this embodiment has six outer corner portions 80C1. Specifically, the main region 451 has two outer corner portions 80C1. Each of the extended regions 452 has two outer corner portions 80C1.

[0094] The inner corner portion 80C2 is a corner portion that protrudes inward from the active region 45. The inner corner portion 80C2 is located at the connection between the main region 451 and the extended region 452. In a plan view, the inner corner portion 80C2 is continuously provided across the main region 451 and the extended region 452. The semiconductor element 40 has two inner corner portions 80C2.

[0095] The radii of curvature of the outer corners 80C1 are approximately equal to each other. The radius of curvature of the outer corners 80C1 is greater than the radius of curvature of the corresponding outer corner of the active region 45 and is greater than or equal to the radius of curvature of the outer corner 561C1 of the corresponding opening 561. The radii of curvature of the inner corners 80C2 are approximately equal to each other. The radius of curvature of the inner corners 80C2 is greater than the radius of curvature of the corresponding inner corner of the active region 45 and is greater than or equal to the radius of curvature of the corresponding inner corner 561C2. The radius of curvature of the inner corners 80C2 may be greater than the radius of curvature of the corresponding inner corner 561C2, or it may be equal to the radius of curvature of the inner corner 561C2. The other configurations of the semiconductor device 20 are the same as those described in the prior embodiment.

[0096] <Summary of the second embodiment> Figure 10 shows the relationship between the active region, the opening 561, and the inner corner of the conductive spacer 80. Figure 10 is an enlarged plan view of the area near the inner corner. In Figure 10(a), the radius of curvature of the inner corner 80C2 is smaller than the radius of curvature of the inner corner 561C2. In this configuration, the distance between the vertex of the inner corner of the active region 45 and the vertex of the inner corner 80C2 is L1.

[0097] In Figure 10(b), as shown in Figure 9, the radius of curvature of the interior angle 80C2 is set to be greater than or equal to the radius of curvature of the interior angle 561C2. In this configuration, the distance between the vertex of the interior angle of the active region 45 and the vertex of the interior angle 80C2 is L2. Distance L2 is shorter than distance L1.

[0098] In this embodiment, the radius of curvature of the inner corner portion 80C2 of the conductive spacer 80 is greater than or equal to the radius of curvature of the inner corner portion 561C2. By satisfying this relationship, the distance between the vertex of the inner corner portion of the active region 45 and the vertex of the inner corner portion 80C2 can be shortened compared to a configuration that does not satisfy this relationship. In other words, the area of ​​the exposed portion 421 of the active region 45 in which the conductive spacer 80 is not directly located can be made smaller (narrower). Therefore, in addition to the effects described in the prior embodiment, localized heat generation can be suppressed.

[0099] The configuration described in this embodiment is not limited to combinations with the configuration shown in Figure 6. For example, combinations with the configurations shown in Figures 7 and 8 are also possible.

[0100] (Third embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the configuration of the active region 45 was common to the main region 451 and the extended region 452. Alternatively, the main region 451 and the extended region 452 may have different configurations.

[0101] Figure 11 shows an example of a semiconductor element 40 in the semiconductor device 20 according to this embodiment. In Figure 11, as in Figure 4, the active region 45, which includes the IGBT region 45i and the diode region 45d, is shown by a solid line. The emitter electrode 42 is omitted, and the edge of the opening 561 of the protective film 56 is shown by a dashed line. Figure 12 is a cross-sectional view taken along the line XII-XII in Figure 11.

[0102] As shown in Figures 11 and 12, the main region 451 has IGBT structures (IGBTs) and diode structures formed within it. In the main region 451, the IGBT regions 45i and diode regions 45d are arranged alternately at a predetermined pitch in the Y direction, which is the direction in which the trenches 53 are aligned. In the main region 451, the area of ​​each IGBT region 45i is larger than the area of ​​each diode region 45d. In other words, the number of cells in each IGBT region 45i is greater than the number of cells in each diode region 45d.

[0103] On the other hand, the extended region 452 does not have an IGBT region 45i. Only the diode structure (diode) is formed in the extended region 452. The entire extended region 452 is the diode region 45d.

[0104] Other configurations are the same as in the previous embodiment (see, for example, Figures 4 and 6). For example, the radius of curvature of the inner corner 561C2 of the opening 561 is greater than the radius of curvature of the outer corner 561C1.

[0105] <Summary of the third embodiment> According to this embodiment, as in the prior embodiment, the opening 561 of the protective film 56 is enlarged in accordance with the enlargement of the active region 45. This allows heat from the expanded region 452 to escape upward through the opening 561. In addition, the ratio of the diode region 45d in the expanded region 452 is increased compared to the ratio of the diode region 45d in the main region 451. The amount of heat generated by the diode structure is smaller than that of the IGBT structure. By increasing the ratio of the diode region 45d in the expanded region 452, it is possible to suppress the temperature of the expanded region 452 from rising higher than the temperature of the main region 451.

[0106] Therefore, it is possible to effectively suppress the need to turn off the IGBT due to a temperature rise in the expanded region 452. In other words, the effect of expanding the active region can be further enhanced. Similar to the prior embodiment, since the radius of curvature of the inner corner portion 561C2 is larger than the radius of curvature of the outer corner portion 561C1, it is possible to suppress the occurrence of cracks in the emitter electrode 42 that affect the element characteristics.

[0107] Furthermore, although the proportion of the IGBT region 45i is increased in the main region 451, the temperature rise is suppressed by heat dissipation through the opening 561 (exposed portion 421). This suppresses the decrease in the short-circuit withstand capability of the IGBT due to the temperature rise. In addition, by increasing the proportion of the diode region 45d in the extended region 452, the area of ​​the diode region 45d in the entire active region 45 is secured. This reduces the current density during diode operation and suppresses the occurrence of electromigration.

[0108] In this embodiment, only the diode region 45d is provided in the extended region 452. As described above, the amount of heat generated by the diode structure is smaller than that of the IGBT structure, so it is possible to more effectively suppress the temperature of the extended region 452 from rising higher than the temperature of the main region 451.

[0109] The configuration of this embodiment can be combined with any of the configurations of the first embodiment, the second embodiment, or any of the modified embodiments.

[0110] (Fourth Embodiment) This embodiment is a modification based on the prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, only the diode region 45d was provided in the extended region 452. Alternatively, an IGBT region 45i may be provided in the extended region 452, while having a different configuration from the main region 451.

[0111] In the extended region 452, the arrangement of the IGBT region 45i is not particularly limited. In a configuration in which the extended region 452 includes the IGBT region 45i, it is sufficient that the ratio of diode region 45d in the extended region 452 is higher than the ratio of diode region 45d in the main region 451. In the extended region 452, for example, IGBT region 45i and diode region 45d may be arranged alternately.

[0112] Figure 13 shows an example of a semiconductor element 40 in the semiconductor device 20 according to this embodiment. Figure 13 is a plan view corresponding to Figure 11. In Figure 13, as in Figure 11, the ends of the opening 561 are shown with dashed lines, and the active region 45, which includes the IGBT region 45i and the diode region 45d, is shown with solid lines. Figure 14 is a cross-sectional view along the line XIV-XIV in Figure 13.

[0113] In the examples shown in Figures 13 and 14, the extended region 452 is provided with a diode region 45d and an IGBT region 45i. In the extended region 452, the IGBT region 45i is located at the end on the outer peripheral region 46 side. That is, the IGBT region 45i is located at the end adjacent to the outer peripheral region 46, rather than at the end at the boundary with the main region 451 in the extended region 452. The IGBT region 45i is located at the end of the extended region 452 facing the guard ring 57. Trench 53 (not shown) is arranged in parallel in the Y direction, as in the previous embodiment. In this embodiment, the IGBT region 45i is located at the end of the extended region 452 in the Y direction, that is, at the end of the active region 45.

[0114] Other configurations are the same as those described in the previous embodiment (see, for example, Figures 4 and 6). For example, the radius of curvature of the inner corner 561C2 of the opening 561 is larger than the radius of curvature of the outer corner 561C1.

[0115] <Summary of the fourth embodiment> When the diode is forward-biased, the guard ring 57 is at the same potential as the base region 51. Therefore, holes are supplied to the drift region 50 from the guard ring 57, which is a p-type semiconductor.

[0116] In this embodiment, an IGBT region 45i is provided at the end of the extended region 452. The diode region 45d is moved further away from the guard ring 57 by the amount of the IGBT region 45i provided at the end. As a result, when the diode region 45d is forward biased, it is possible to suppress the accumulation of a large amount of holes in the drift region 50 near the boundary between the extended region 452 and the outer peripheral region 46. Therefore, when the diode region 45d is switched to reverse bias, it is possible to suppress the inflow of a large amount of holes into the base region 51 which functions as an anode, that is, the occurrence of local current concentration. Thus, the recovery withstand capability of the diode can be improved. According to this embodiment, the effect of expanding the active region can be further enhanced while improving the recovery withstand capability. In addition, as with the prior embodiment, it is possible to suppress the occurrence of cracks that affect the element characteristics.

[0117] As shown in Figure 13, in this embodiment, an IGBT region 45i is also provided at the end of the active region 45 opposite to the pad 44 in the Y direction. This also improves the recovery withstand capability of the diode. Furthermore, in the X direction, the end of the diode region 45d is located inward from the end of the IGBT region 45i. This also improves the recovery withstand capability of the diode. In this way, the recovery withstand capability of the diode can also be improved in the main region 451. Note that the prior embodiment has a similar configuration, as shown in Figure 4 and others. Therefore, the above-described effects can be achieved.

[0118] An example has been shown in which an IGBT region 45i is provided at the Y-direction end of the extended region 452, but this is not limited to this. For example, an IGBT region 45i may be provided at the end opposite to the pad 44 in the X-direction. IGBT regions 45i may also be provided at both the Y-direction end and the X-direction end.

[0119] The breakdown voltage structure of the outer peripheral region 46 is not limited to the guard ring 57 described above. Any structure including a p-type semiconductor region that is at the same potential as the base region 51 when the diode is forward biased is acceptable. For example, a RESURF structure may be adopted. In this case, the p-type semiconductor region is formed on the surface of the drift region 50 in the outer peripheral region 46. This semiconductor region extends outward from the base region 51. Even in such a RESURF structure, by providing an IGBT region 45i at the end of the extended region 452, the recovery withstand capability can be improved while enhancing the effect of expanding the active region. RESURF is an abbreviation for Reduced Surface electric field.

[0120] The configuration of this embodiment can be combined with any of the configurations of the first embodiment, the second embodiment, or any of the modified embodiments.

[0121] (Fifth embodiment) This embodiment is a modification based on the prior embodiment, and the description of the prior embodiment can be incorporated by reference. In the prior embodiment, the position of the temperature-sensitive diode for detecting the temperature of the semiconductor element 40 was not specifically mentioned. Instead, the temperature-sensitive diode may be provided at a predetermined position.

[0122] Figure 15 shows an example of a semiconductor element 40 in the semiconductor device 20 according to this embodiment. Figure 15 is a plan view corresponding to Figure 11. In Figure 15, as in Figure 11, the ends of the opening 561 are shown with dashed lines, and the active region 45, which includes the IGBT region 45i and the diode region 45d, is shown with solid lines.

[0123] As shown in Figure 15, the multiple pads 44 are arranged together on one end in the X direction, similar to the configuration shown in Figure 7. The multiple pads 44 are unevenly distributed in the X direction. The extension region 452 is located at the end opposite to the pad 44 arrangement area in the X direction. The active region 45 includes only one extension region 452. The active region 45, including the extension region 452, has a roughly L-shape in plan.

[0124] The semiconductor element 40 has a temperature-sensitive diode 58. The temperature-sensitive diode 58 is composed of, for example, impurity-doped polysilicon and an aluminum-based wiring material, and is provided on one surface 41a of the semiconductor substrate 41. The temperature-sensitive diode 58 is not located in a position that overlaps with the active region 45 in a plan view, but is provided between the pad 44 and the extended region 452 in the X direction. The anode of the temperature-sensitive diode 58 is electrically connected to the anode pad 44, and the cathode is electrically connected to the cathode pad 44. The other configurations are the same as those described in the prior embodiment (see, for example, Figures 4 and 7).

[0125] <Summary of the Fifth Embodiment> In this embodiment, the temperature-sensitive diode 58 is located outside the active region 45. This increases the area of ​​the exposed portion 421 of the emitter electrode 42, thereby improving heat dissipation. In other words, even if the ratio of the IGBT region 45i in the main region 451 is increased, the generated heat can be efficiently dissipated.

[0126] In this embodiment, the temperature-sensitive diode 58 is provided between the pad 44 and the extended region 452. In other words, the temperature-sensitive diode 58 is provided in the vicinity of the extended region 452. The temperature in the vicinity of the extended region 452 is relatively high. Therefore, the temperature of the semiconductor element 40 can be detected even while the temperature-sensitive diode 58 is provided outside the active region 45. In addition, the wiring connecting the temperature-sensitive diode 58 and the pad 44 can be shortened.

[0127] The configuration of this embodiment can be combined with any of the configurations of the first embodiment, second embodiment, third embodiment, fourth embodiment, or modified version. For example, in a configuration in which the temperature-sensitive diode 58 is provided near the center of the edge of the pad 44, the temperature-sensitive diode 58 may be provided between the pad 44 and the extended region 452.

[0128] The arrangement of the temperature-sensing diode 58 is not limited to the examples described above. The temperature-sensing diode 58 may be placed in a position that overlaps with the active region 45, for example, the main region 451. As an example, in a configuration in which the pads 44 are arranged off-center on one end in the X direction and the extended region 452 is provided on the other end, the temperature-sensing diode 58 may be placed in a position that overlaps with the main region 451.

[0129] (Other embodiments) The disclosures in this specification and drawings are not limited to the exemplary embodiments. The disclosures include the exemplary embodiments and variations thereof by those skilled in the art. For example, the disclosures are not limited to combinations of parts and / or elements shown in the embodiments. The disclosures are implementable in a variety of combinations. The disclosures may have additional parts that can be added to the embodiments. The disclosures include those in which parts and / or elements of the embodiments have been omitted. The disclosures include substitutions or combinations of parts and / or elements between one embodiment and another. The scope of the disclosed technical areas is not limited to the descriptions of the embodiments. Some of the scope of the disclosed technical areas are indicated by the claims and should be understood to include all modifications within the meaning and scope equivalent to the claims.

[0130] The disclosures in the specification and drawings are not limited by the claims. The disclosures in the specification and drawings encompass the technical ideas described in the claims and extend to a wider and more diverse range of technical ideas than those described in the claims. Therefore, a variety of technical ideas can be extracted from the disclosures in the specification and drawings without being bound by the claims.

[0131] When an element or layer is referred to as “on top of,” “connected to,” “connected to,” or “joined,” it may be directly on top of, connected to, connected to, or joined to another element or layer, and there may also be an intervening element or layer. In contrast, when an element is referred to as “directly on top of,” “directly connected to,” “directly connected to,” or “directly joined to” another element or layer, there is no intervening element or layer. Other words used to describe relationships between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between,” “adjacent” vs. “directly adjacent,” etc.). As used in this specification, the term “and / or” includes any combination with respect to one or more of the enumerated items relating to the relationship, and all combinations thereof.

[0132] Spatially relative terms such as "inside," "outside," "back," "below," "low," "above," and "high" are used here to facilitate descriptions of the relationship between one element or feature and other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, if the device in the drawing is turned upside down, an element described as "below" or "directly below" another element or feature will be oriented "above" the other element or feature. Thus, the term "below" can encompass both up and down orientations. The device may also be oriented in other directions (it may be rotated 90 degrees or in other directions), and the spatially relative descriptors used in this specification will be interpreted accordingly.

[0133] The vehicle's drive system 1 is not limited to the configuration described above. For example, although an example with one motor generator 3 has been shown, it is not limited to this. It may have multiple motor generators. The power conversion device 4 is shown as having an inverter 6 as a power conversion unit, but it is not limited to this. For example, it may have a configuration with multiple inverters. It may have a configuration with at least one inverter and a converter. It may have only a converter.

[0134] The configuration of the semiconductor device 20 is not limited to the example described above. The semiconductor device 20 only needs to include at least semiconductor elements 40.

[0135] An example of an RC-IGBT was shown as a vertical element configured in the active region 45 of the semiconductor substrate 41, but it is not limited to this. The diode may be externally mounted. The IGBT and the diode may be on separate chips.

[0136] The switching element is not limited to IGBT11. For example, a MOSFET may be used. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0137] The diagram shows an example in which the back surfaces 60b, 70b of the wiring members 60, 70 are exposed from the sealant 30, but is not limited to this. At least one of the back surfaces 60b, 70b may be covered by the sealant 30. At least one of the back surfaces 60b, 70b may be covered by an insulating member (not shown) separate from the sealant 30. The diagram shows an example in which the semiconductor device 20 includes a sealant 30, but is not limited to this. The semiconductor device may also be configured without a sealant 30.

[0138] Instead of the conductive spacer 80, a protrusion may be provided on the wiring member 60. In this case, the wiring member 60 corresponds to the conductive member.

[0139] While an example of a double-sided heat dissipation structure has been shown for the semiconductor device 20, it is not limited to this. It can also be applied to a single-sided heat dissipation structure. For example, the collector electrode 43 is connected to a heat sink or a metal body of the substrate, and the emitter electrode 42 is connected to a lead. In this case, the lead corresponds to a conductive member.

[0140] Although an example has been shown in which the semiconductor device 20 has only one semiconductor element 40 that constitutes one arm, it is not limited to this. The semiconductor device 20 may have multiple semiconductor elements 40 that constitute one arm. That is, multiple semiconductor elements 40 may be connected in parallel to each other to constitute one arm. Also, the semiconductor device 20 may have multiple semiconductor elements 40 that constitute one phase of the upper and lower arm circuit 9. It may also have multiple semiconductor elements 40 that constitute multiple phases of the upper and lower arm circuit 9.

[0141] The arrangement of the trenches 53 (gate electrodes 55) is not limited to the stripe pattern described above. The arrangement of the IGBT region 45i and the diode region 45d is not limited to the alternating arrangement in the Y direction described above.

[0142] The active region 45 may be divided into multiple parts. The active region 45 may be divided into two parts, for example, in the X direction. Gate runners (gate wiring), not shown, are placed between the active regions 45. The gate runners electrically connect the gate electrode 55 and the pad 44 for the gate electrode. The technical concepts that can be understood from the embodiments and modifications described so far are described below as an addendum. <Note 1> A semiconductor substrate (41) having an active region (45) which is a region for forming vertical elements, and an outer peripheral region (46) that surrounds the active region in a plan view in the thickness direction of the substrate, A first main electrode (42) is arranged on the active region on one surface of the semiconductor substrate and is electrically connected to the vertical element, A second main electrode (43) is arranged on the back surface opposite to the aforementioned one surface in the thickness direction of the plate and is electrically connected to the vertical element, A signal electrode, comprising a pad (44) arranged on the outer peripheral region on one surface, A protective film (56) is arranged on the aforementioned surface and has an opening (561) that overlaps with the first main electrode in the plan view, Equipped with, The active region comprises a main region (451) arranged alongside the pad in a first direction perpendicular to the thickness direction of the plate, and an extended region (452) which is smaller in area than the main region in a plan view, is connected to the pad-side end of the main region in the first direction, and is arranged alongside the pad in a second direction perpendicular to the thickness direction and the first direction. The aforementioned opening is It is provided continuously across the main region and the extended region, A semiconductor device wherein, in the plan view, the radius of curvature of an inner corner (56C2), which is located at the connection between the main region and the extended region and is a corner that is convex inward of the active region, is greater than the radius of curvature of an outer corner (56C1), which is located independently in the main region or the extended region and is a corner that is convex outward of the active region. <Note 2> The device comprises a conductive member (80) connected to the first main electrode, The conductive member has a planar shape corresponding to the opening in a predetermined range in the thickness direction from the end face on the first main electrode side, The semiconductor device according to Appendix 1, wherein the radius of curvature of the corner portion (80C2) corresponding to the inner corner portion in the conductive member is greater than or equal to the radius of curvature of the inner corner portion. [Explanation of symbols]

[0143] 1…Drive system, 2…DC power supply, 3…Motor generator, 4…Power converter, 5…Smoothing capacitor, 6…Inverter, 7…P line, 8…N line, 9…Upper and lower arm circuit, 9H…Upper arm, 9L…Lower arm, 10…Output line, 11…IGBT, 12…Diode, 20…Semiconductor device, 30…Encapsulation, 30a…One side, 30b…Back side, 30c, 30d…Side, 40…Semiconductor element, 1…Semiconductor substrate, 41a…One side, 41b…Back side, 42…Emitter electrode, 421…Exposed area, 422…Underlay electrode, 422a…Peripheral area, 423…Connecting electrode, 43…Collector electrode, 44…Pad, 45…Active area, 45i…IGBT area, 45d…Diode area, 451 ...Main region, 452...Extended region, 46...Outer region, 47...Collector region, 48...Cathode region, 49...Buffer region, 50...Drift region, 51...Base region, 52...Emitter region, 53...Trench, 54...Gate insulating film, 55...Gate electrode, 56...Protective film, 561...Opening, 56C1...Outer corner, 56C2...Inner corner, 57...Guard ring, 58...Temperature-sensitive diode, 60...Wiring material, 60a...Opposite surface, 60b...Back surface, 70...Wiring material, 70a...Opposite surface, 70b...Back surface, 80...Conductive spacer, 80C1...Outer corner, 80C2...Inner corner, 90...External connection terminal, 91, 92...Main terminal, 93...Signal terminal, 100...Bonding wire, 101, 102, 103...Bonding material

Claims

[Claim 1] A semiconductor substrate (41) having an active region (45) which is a region for forming vertical elements, and an outer peripheral region (46) that surrounds the active region in a plan view in the thickness direction of the substrate, A first main electrode (42) is arranged on the active region on one surface of the semiconductor substrate and is electrically connected to the vertical element, A second main electrode (43) is arranged on the back surface opposite to the one surface in the thickness direction of the plate and is electrically connected to the vertical element, A signal electrode, comprising a pad (44) arranged on the outer peripheral region on one surface, A protective film (56) is arranged on the aforementioned surface and has an opening (561) that overlaps with the first main electrode in the plan view, Equipped with, The active region comprises a main region (451) arranged alongside the pad in a first direction perpendicular to the thickness direction of the plate, and an extended region (452) which is smaller in area than the main region in a plan view, is connected to the pad-side end of the main region in the first direction, and is arranged alongside the pad in a second direction perpendicular to the thickness direction and the first direction. The aforementioned opening is It is provided continuously across the main region and the extended region, In the plan view, the radius of curvature of the inner corner (56C2), which is located at the connection between the main region and the extended region and is a corner that is convex inward of the active region, is greater than the radius of curvature of the outer corner (56C1), which is located independently in the main region or the extended region and is a corner that is convex outward of the active region. The device comprises a conductive member (80) connected to the first main electrode, The conductive member has a planar shape corresponding to the opening in a predetermined range in the thickness direction from the end face on the first main electrode side, A semiconductor device in which the radius of curvature of the corner portion (80C2) corresponding to the inner corner portion in the conductive member is greater than or equal to the radius of curvature of the inner corner portion.

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