Semiconductor equipment

Abstract

To provide a semiconductor device with reduced parasitic capacitance. [Solution] The transistor 10 has a first insulating layer 110 on a substrate 100, a first oxide semiconductor layer 121 on the first insulating layer, a second oxide semiconductor layer 122 on the first oxide semiconductor layer, a source electrode layer 130 and a drain electrode layer 140 on the second oxide semiconductor layer, a second insulating layer 170 on the first insulating layer, the source electrode layer and the drain electrode layer, a third insulating layer 175 on the second insulating layer, a third oxide semiconductor layer 123 on the second oxide semiconductor layer, a gate insulating layer 150 on the third oxide semiconductor layer and a gate electrode layer 160 on the gate insulating layer, wherein the second insulating layer is an oxygen barrier layer and has a region in contact with the sides of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer and the drain electrode layer, and the third oxide semiconductor layer has a region in contact with the sides of the second oxide semiconductor layer, the source electrode layer and the drain electrode layer.

Description

[Technical Field]

[0001] This invention relates to a product, a method, or a method of manufacturing; or to a process, a machine , relating to manufacture or composition of matter. In particular The present invention relates to, for example, semiconductor devices, display devices, light-emitting devices, energy storage devices, imaging devices, and the like. The present invention relates to a driving method or a method for manufacturing the same. In particular, one aspect of the present invention relates to a semiconductor device Or, regarding the method of its manufacture.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to the general term. Transistors and semiconductor circuits are forms of semiconductor devices. Also, memory devices, Display devices and electronic equipment may include semiconductor devices. [Background technology]

[0003] A technology that constructs transistors using semiconductor films formed on substrates with insulating surfaces is attracting attention. It is being considered. The transistor in question is used in integrated circuits (ICs) and image display devices (display devices), etc. It is widely applied in electronic devices. Silicon is used as a semiconductor thin film applicable to transistors. While condensate semiconductor materials are widely known, oxide semiconductors are attracting attention as another material. Yes, they are.

[0004] For example, indium (In), gallium (Ga), and as the active layer of a transistor. A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. Yes, they are. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2006-165528 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] As semiconductor devices are miniaturized, parasitic capacitance near transistors becomes a major problem.

[0007] In transistor operation, near the channel (for example, between the source electrode and the drain electrode) If raw capacitance is present, time is required for the parasitic capacitance to charge, affecting the transistor's response. This can reduce performance and, consequently, the responsiveness of semiconductor devices.

[0008] Furthermore, the various processes involved in forming transistors (especially thin-film deposition and processing) are constantly evolving with increasing miniaturization. Controlling this is becoming increasingly difficult, as variations in the manufacturing process affect transistor characteristics, and furthermore... This can have a significant impact on reliability.

[0009] Furthermore, with miniaturization, pattern formation becomes difficult due to the resolution limit of the exposure equipment, etc. Problems have arisen in the manufacturing of the inverters, and the costs associated with capital investment are becoming enormous.

[0010] Therefore, one aspect of the present invention aims to reduce parasitic capacitance near a transistor. One of the objectives is to provide a semiconductor device with good electrical characteristics. Alternatively, one of the objectives is to provide highly reliable semiconductor devices. This provides a method for manufacturing a transistor or semiconductor device that can form patterns below the resolution limit. One of the objectives is to perform the following actions in the manufacturing process of transistors or semiconductor devices. One of the objectives is to reduce variations in properties caused by the acid. Alternatively, an acid with low oxygen deficiency. One of the objectives is to provide a semiconductor device having a synthetic semiconductor layer. Alternatively, a simple process One of the objectives is to provide a semiconductor device that can be formed in a certain time. Alternatively, oxidation The objective is to provide a semiconductor device with a configuration that can reduce interface states near the semiconductor layer. One of the objectives is to provide low-power semiconductor devices. Another objective is to provide a new manufacturing method for semiconductor devices that reduces development costs. Alternatively, one of the objectives is to provide novel semiconductor devices, etc. One of the objectives is to provide a method for manufacturing a device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention comprises a first insulating layer, a first oxide semiconductor layer on the first insulating layer, and a first A second oxide semiconductor layer on the oxide semiconductor layer, and a source electrode layer on the second oxide semiconductor layer and drain electrode layer, first insulating layer, source electrode layer, and second on drain electrode layer An insulating layer, a third insulating layer on the second insulating layer, and a third oxide semiconductor layer on the second oxide semiconductor layer A conductive layer, a gate insulating layer on a third oxide semiconductor layer, and a gate insulating layer on the gate insulating layer The second insulating layer is an oxygen barrier layer, comprising the first oxide semiconductor layer and the second oxide It has a region in contact with the side surfaces of the material semiconductor layer, the source electrode layer and the drain electrode layer, and a third oxidation The semiconductor layer consists of a second oxide semiconductor layer, a source electrode layer, a drain electrode layer, and a second insulating layer. The semiconductor device is characterized by having a region that is in contact with the side surface of a third insulating layer.

[0013] Another aspect of the present invention comprises a first insulating layer, a first oxide semiconductor layer on the first insulating layer, and A second oxide semiconductor layer on the first oxide semiconductor layer, and a source electrode on the second oxide semiconductor layer. A first electrode having a region in contact with the side surface of a second oxide semiconductor layer and a drain electrode layer The electrode layer and the second conductive layer, the first insulating layer, the source electrode layer, and the drain electrode layer The insulating layer 2, the third insulating layer on the second insulating layer, and the third oxide on the second oxide semiconductor layer A monocrystalline semiconductor layer, a gate insulating layer on a third oxide semiconductor layer, and a gate electrode on the gate insulating layer. The first electrode layer and the second electrode have a second insulating layer which is an oxygen barrier layer. The layer is in contact with the second insulating layer on its side, and the third oxide semiconductor layer is in contact with the first insulating layer, 1 oxide semiconductor layer, 2 oxide semiconductor layer, source electrode layer, drain electrode layer, 2 insulating A semiconductor device characterized by having a border layer and a region in contact with the side surface of a third insulating layer. be.

[0014] Another aspect of the present invention comprises a first insulating layer, a first oxide semiconductor layer on the first insulating layer, and A second oxide semiconductor layer on the first oxide semiconductor layer, and a source electrode on the second oxide semiconductor layer. The layers and drain electrode layer, the first insulating layer, the source electrode layer, and the drain electrode layer The insulating layer 2, the third insulating layer on the second insulating layer, and the source electrode layer and drain electrode layer and a fourth insulating layer formed in contact with the sides of the second insulating layer and the third insulating layer. And, a third oxide semiconductor layer on the second oxide semiconductor layer, and a gate on the third oxide semiconductor layer The device has a gate insulating layer and a gate electrode layer on the gate insulating layer, and the second insulating layer is an oxygen barrier layer. The first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain The third oxide semiconductor layer has a region in contact with the side surface of the electrode layer, and the third oxide semiconductor layer has a region in contact with the first insulating layer and the first oxide Oxide semiconductor layer, second oxide semiconductor layer, source electrode layer, drain electrode layer, and fourth insulating This semiconductor device is characterized by having a region that is in contact with the side surface of the marginal layer.

[0015] Furthermore, it is preferable to use an aluminum oxide layer as the second insulating layer.

[0016] Another aspect of the present invention comprises a first conductive layer, a first insulating layer on the first conductive layer, and a first insulating A first oxide semiconductor layer on a layer, a second oxide semiconductor layer on the first oxide semiconductor layer, and Source electrode layer and drain electrode layer on oxide semiconductor layer 2, first insulating layer, source electrode A second insulating layer on the electrode layer and drain electrode layer, a third insulating layer on the second insulating layer, and A third oxide semiconductor layer on the second oxide semiconductor layer, and a gate insulating layer on the third oxide semiconductor layer. A layer, a gate electrode layer on the gate insulating layer, a third insulating layer, a third oxide semiconductor layer, and a gate The device comprises an insulating layer and a fourth insulating layer on the gate electrode layer, wherein the second insulating layer is an oxygen barrier. A layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode layer, and a drain The third oxide semiconductor layer is in contact with the side surface of the in electrode layer, and the third oxide semiconductor layer is in contact with the first insulating layer and the first oxide semiconductor layer Body layer, second oxide semiconductor layer, source electrode layer, drain electrode layer, second insulating layer, third insulating layer The fourth insulating layer is characterized by having a region in contact with the side surface of the edge layer, and being an oxygen barrier layer. This is a semiconductor device.

[0017] Furthermore, it is preferable to use an aluminum oxide film as the second and fourth insulating layers. It's nice.

[0018] Another aspect of the present invention involves forming a first insulating layer and a first oxide semiconductor film on the first insulating layer. A first oxide semiconductor film is formed, a second oxide semiconductor film is formed on the first oxide semiconductor film, and a first heat treatment is performed. The first conductive film is formed on the second oxide semiconductor film, and the first mask and the first conductive film are formed. The film is used to etch a portion of the first oxide semiconductor film and the second oxide semiconductor film. By doing so, a first oxide semiconductor layer and a second oxide semiconductor layer are formed in an island-like manner, and the first A second insulating layer is formed on the insulating layer and the first conductive film, and when forming the second insulating layer, the first A mixed layer of an insulating layer and a second insulating film is formed, and at the same time, acid is introduced into the mixed layer or the first insulating layer. An element is added, a second heat treatment is performed, oxygen is diffused into the second oxide semiconductor layer, and the second A third insulating film is formed on the insulating layer, and the third insulating layer is subjected to a planarization treatment to form the third insulating layer. Then, using the second mask, the third insulating layer and the second insulating layer are selectively etched, Using the mask and the second insulating layer, the first conductive film is selectively etched. This forms a source electrode layer and a drain electrode layer, and a third insulating layer and a second oxide layer. A third oxide semiconductor film is formed on the conductive layer, and a fourth insulating film is formed on the third oxide semiconductor film. Forming a second conductive film on the fourth insulating film, the second conductive film, the third insulating film, and the By performing a chemical mechanical polishing treatment on the oxide semiconductor film 3, the third oxide semiconductor layer, A method for manufacturing a semiconductor device, characterized by forming a gate insulating layer and a gate electrode layer. be.

[0019] Another aspect of the present invention involves forming a first insulating layer and a first oxide semiconductor film on the first insulating layer. A first oxide semiconductor film is formed, a second oxide semiconductor film is formed on the first oxide semiconductor film, and a first heat treatment is performed. The first conductive film is formed on the second oxide semiconductor film, and the first mask and the first conductive film are formed. The first oxide semiconductor film and the second oxide semiconductor film are selectively etched using a film. By doing so, a first oxide semiconductor layer and a second oxide semiconductor layer are formed in an island-like manner, and the first A second insulating film is formed on the insulating layer and the first conductive film, and when the second insulating film is formed, the first insulating layer A mixed layer of the margin layer and the second insulating film is formed, and oxygen is added to the mixed layer or the first insulating layer. A second heat treatment is performed to diffuse oxygen into the second oxide semiconductor layer, and the second oxide semiconductor The oxygen vacancies in the layer are reduced, a third insulating film is formed on the second insulating film, and the third insulating film is laid flat. After flattening, the third insulating film and a portion of the second insulating film are removed using a second mask. By chipping, a third insulating layer and a second insulating layer are formed, and the first conductive layer and the third A fourth insulating film is formed on the insulating layer, and anisotropic etching is performed to create the second insulating layer, A fourth insulating layer is formed in contact with the side surface of the third insulating layer, and the fourth insulating layer is used as a mask. Then, by etching a portion of the first conductive film, the source electrode and drain electrode Forming a third insulating layer and a second oxide semiconductor layer, and forming a third oxide semiconductor film on the third insulating layer and the second oxide semiconductor layer. A fifth insulating film is formed on the third oxide semiconductor film, and a second conductive film is formed on the fifth insulating film. The second conductive film, the third insulating film, and the third oxide semiconductor film are subjected to chemical mechanical polishing. By doing so, a third oxide semiconductor layer, a gate insulating layer, and a gate electrode layer are formed. This is a method for manufacturing a semiconductor device characterized by the following:

[0020] Furthermore, it is preferable to form the second insulating film using oxygen gas by sputtering. stomach.

[0021] Furthermore, the second insulating film is made using the sputtering method with an aluminum oxide target. It is preferable to form it on a silicon oxide film under conditions where oxygen is present at a concentration of 50% by volume or more.

[0022] Furthermore, it is preferable to perform the second heat treatment at a temperature of 300°C to 450°C.

[0023] Furthermore, the configuration can consist of a semiconductor device, a microphone, a speaker, and a housing. [Effects of the Invention]

[0024] By using one aspect of the present invention, it is possible to reduce parasitic capacitance near the transistor. Alternatively, it is possible to provide a semiconductor device with good electrical characteristics. Alternatively, high reliability A semiconductor device can be provided. Alternatively, a pattern formation below the resolution limit of the exposure device can be achieved. A method for manufacturing a transistor or semiconductor device that enables this can be provided. Or, Reducing variations in the characteristics of transistors or semiconductor devices due to the manufacturing process. It is possible. Alternatively, it is possible to provide a semiconductor device having an oxide semiconductor layer with few oxygen vacancies. Yes, it is possible. Or, it is possible to provide a semiconductor device that can be formed using a simple process. Alternatively, a semiconductor device can be provided with a configuration that can reduce interface states near the oxide semiconductor layer. It can be provided. Or, a low-power semiconductor device can be provided. Also, We can provide a new method for manufacturing semiconductor devices that reduces development costs. Or, a new semiconductor device We can provide conductive devices and the like, or a method for manufacturing the above-mentioned semiconductor device. It is possible.

[0025] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. Furthermore, other effects are... This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings Furthermore, it is possible to extract other effects from the descriptions in the claims and other documents. [Brief explanation of the drawing]

[0026] [Figure 1] Top view and cross-sectional view illustrating a transistor. [Figure 2] Top view and cross-sectional view illustrating a transistor. [Figure 3] Top view and cross-sectional view illustrating a transistor. [Figure 4] Band diagram of an oxide semiconductor layer. Magnified cross-sectional view of a transistor. [Figure 5] ALD film formation principle. [Figure 6] ALD device overview diagram. [Figure 7] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 8] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 9] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 10] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 11] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 12] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 13] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 14] Top view and cross-sectional view illustrating a transistor. [Figure 15] Top view and cross-sectional view illustrating a transistor. [Figure 16] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 17] Top view and cross-sectional view illustrating a transistor. [Figure 18] Top view and cross-sectional view illustrating a transistor. [Figure 19] Top view and cross-sectional view illustrating a transistor. [Figure 20] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 21] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 22] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 23] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 24] High-resolution TEM image with Cs correction in cross-section of CAAC-OS, and schematic cross-sectional diagram of CAAC-OS. [Figure 25] High-resolution TEM image with Cs correction in the plane of CAAC-OS. [Figure 26] A diagram illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors. [Figure 27] A figure showing the electron diffraction pattern of CAAC-OS. [Figure 28] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 29] Cross-sectional view and circuit diagram of a semiconductor device. [Figure 30] Cross-sectional view and circuit diagram of a semiconductor device. [Figure 31] A plan view showing the imaging device. [Figure 32] A plan view showing the pixels of an imaging device. [Figure 33] A cross-sectional view showing the imaging device. [Figure 34] A cross-sectional view showing the imaging device. [Figure 35] A diagram illustrating an example of RF tag configuration. [Figure 36] A diagram illustrating an example of a CPU configuration. [Figure 37] Circuit diagram of a memory element. [Figure 38] A diagram illustrating an example of a display device configuration and a circuit diagram of a pixel. [Figure 39] A diagram illustrating the display module. [Figure 40] A perspective view showing the cross-sectional structure of a package using a lead frame type interposer. [Figure 41] A diagram illustrating electronic devices. [Figure 42] A diagram illustrating electronic devices. [Figure 43] A diagram illustrating electronic devices. [Figure 44] A diagram illustrating electronic devices. [Modes for carrying out the invention]

[0027] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0028] For example, in this specification, etc., if it is explicitly stated that X and Y are connected The cases are when X and Y are electrically connected and when X and Y are functionally connected. The cases disclosed in this specification, etc., include the case where X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the diagram or text. In addition to the connection relationships shown in the diagram or text, other connections may also be included as described in the diagram or text. do.

[0029] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0030] One example of a case where X and Y are directly connected is when an electrical connection between X and Y is possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. If the diode, display element, light-emitting element, load, etc. are not connected between X and Y and elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitors). Without the need for elements such as components, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. This is the case when X and Y are connected.

[0031] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between them. Furthermore, if X and Y are electrically connected, X and This includes cases where Y is directly connected to it.

[0032] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected. When X and Y are functionally connected, the situation is different from when X and Y are directly connected. This includes cases where and are electrically connected.

[0033] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y and When they are electrically connected (i.e., when there is another element or circuit between X and Y) (when connected) and when X and Y are functionally connected (i.e., X and Y are connected) (When functionally connected with another circuit in between) and when X and Y are directly connected In the case of (that is, when X and Y are connected without another element or circuit in between) and However, this shall be as disclosed in this specification, etc. That is, explicitly stated that they are electrically connected. If it is explicitly stated that it is connected, then Similar information is disclosed in this specification, etc.

[0034] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or via (In short), electrically connected to X, the drain (or second terminal, etc.) of the transistor is connected to Z. If Y is electrically connected via (or without) 2, or if the transistor source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are directly connected, with the transistor's drain (or second terminal, etc.) directly connected to a portion of Z2. If it is connected to and another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0035] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and X is the source (or the X terminal) of the transistor. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope.

[0036] Alternatively, another way to express it is, for example, "the source (or first terminal, etc.) of the transistor." It is electrically connected to X via at least a first connection path, and the first connection path is It does not have a second connection path, and the second connection path is via a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor. The path between ( and ), and the above first connection path is a path via Z1, and the transit The drain (or second terminal, etc.) of the terminal is electrically connected to Y via at least a third connection path. They are connected in a manner, and the third connection path does not have the second connection path, and the third The connection path is the path via Z2. This can be expressed as "The transition The source of the starter (or the first terminal, etc.) is connected via Z1 through at least the first connection path. And, electrically connected to X, the first connection path does not have a second connection path. The second connection path described above has a connection path via a transistor, and the drain of the transistor (or a second terminal, etc.) is connected to Y via Z2 by at least a third connection path. It is expressed as, "They are electrically connected, and the third connection path does not have the second connection path." It is possible. Or, "the source (or first terminal, etc.) of the transistor is less Both are electrically connected to X via Z1 through the first electrical path, and the first electrical The target path does not have a second electrical path, and the second electrical path is the transistor From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor It is an electrical path, and the drain (or second terminal, etc.) of the transistor is at least third The electrical path is electrically connected to Y via Z2, and the third electrical path is , it does not have a fourth electrical path, and the fourth electrical path is the drain of the transistor The electrical pulse from (or the second terminal, etc.) to the source (or the first terminal, etc.) of the transistor It can be expressed as "It is S." Using similar methods of expression as these examples, the circuit configuration By defining the connection path in the transistor, the source (or first terminal) To distinguish between the drain (or second terminal, etc.) and the second terminal, and to determine the technical scope. It is possible.

[0037] Note that these methods of expression are just examples and are not limited to these methods. Here, X Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0038] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will perform the function of the wiring, and It possesses the functions of both components of the electrode's function. Therefore, the electrode in this specification A conductive connection is a situation where a single conductive film combines the functions of multiple components. Combined forms are also included in that category.

[0039] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be modified in various ways. It will be easily understood by those skilled in the art to obtain this. Therefore, the present invention is as shown in the embodiments below. The description is not to be interpreted as being limited to the stated content. The same reference numeral is used in common across different drawings for parts that are identical or have similar functions. I will omit the explanation of that repetition.

[0040] <Notes regarding descriptions of drawings> In this specification, terms indicating placement, such as "above" and "below," refer to the positional relationship between components. These are used for convenience in explaining with reference to the drawings. Also, the positional relationships between the components are as follows: It changes appropriately depending on the direction in which the configuration is described. Therefore, the words described in the specification It is not limited and can be appropriately rephrased depending on the situation.

[0041] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and are in direct contact. It does not limit the meaning to what is being done. For example, if the expression is "electrode B on insulating layer A", It is not necessary for electrode B to be in direct contact with insulating layer A, but rather between insulating layer A and electrode B. This does not exclude those that include other components.

[0042] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where the temperature is in a certain condition. Therefore, it also includes cases where the temperature is between -5° and 5°. A "row" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" means two This refers to a state in which two straight lines are arranged at an angle between 60° and 120°.

[0043] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0044] Furthermore, in the drawings, the size, layer thickness, or area is shown at an arbitrary size for the sake of explanation. Therefore, it is not necessarily limited to that scale. Furthermore, the drawings are intended to be clear. This is a schematic representation and is not limited to the shapes or values ​​shown in the drawings.

[0045] Furthermore, in drawings, such as top views (also called plan views or layout drawings) and perspective views, To ensure clarity in the drawings, some components may be omitted from the description.

[0046] Furthermore, "identical" means that they may have the same area or the same shape. Due to the manufacturing process, it is possible that the shapes may not be exactly the same, even if they are nearly identical. This can be rephrased as saying they are identical.

[0047] <Notes regarding paraphrasable descriptions> In this specification and other documents, when describing the connection relationships of transistors, one of the source and drain This is referred to as "either the source or the drain" (or the first electrode, or the first terminal), and the source and The other side of the drain is referred to as "the other side of the source or drain" (or the second electrode, or the second terminal). It is noted that the source and drain of a transistor are related to the structure or operation of the transistor. This is because it varies depending on the conditions, etc. Regarding the terminology for the source and drain of a transistor... This can be appropriately rephrased as source (drain) terminal or source (drain) electrode, depending on the situation. It is possible to obtain it.

[0048] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0049] Furthermore, in this specification, the term "transistor" includes a gate, a drain, and a source. It is an element having at least three terminals. And, drain (drain terminal, drain A channel between the region (or drain electrode) and the source (source terminal, source region, or source electrode). It has a channel region, and current can be passed through the drain, channel region and source. It is something that can be worn.

[0050] Here, the source and drain vary depending on the transistor's structure or operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are not called source or drain. Let's refer to one of the source and drain as the first electrode, and the other of the source and drain as the second electrode. It may be written as such.

[0051] The ordinal numbers "1st," "2nd," and "3rd" used in this specification are intended to avoid confusion of constituent elements. This is added to avoid any misunderstanding and does not mean that the number is limited.

[0052] Furthermore, in this specification, the substrate of the display panel may be, for example, FPC (Flexible Printed Circuit). (Tracked Circuits) or TCP (Tape Carrier Pack) Items with ge) etc. attached, or COG (Chip On Glass) on the substrate In some cases, devices in which ICs (integrated circuits) are directly mounted are called display devices.

[0053] Furthermore, the words "membrane" and "layer" can be used interchangeably depending on the context or situation. Therefore, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive film." In some cases, it may be possible to change the term to "insulating film". Alternatively, for example, the term "insulating film" may be used. In some cases, it may be possible to change the term to "insulating layer."

[0054] <Notes regarding the definition of terms> The following sections will explain the definitions of each term used in this specification.

[0055] In this specification, when the terms "trench" or "groove" are used, they refer to a narrow, band-shaped recess. To say.

[0056] Furthermore, in this specification, when silicon oxide nitride is shown as the film, for example, SiOxNy and It may be stated. In this case, x and y may be natural numbers or numbers with decimal points. That's good too.

[0057] <About the connection> In this specification, "A and B are connected" means that A and B are not directly connected. This also includes things that are electrically connected. Here, A and B are electrically connected "Continued" means that there is an object between A and B that has some kind of electrical effect. This refers to a device that enables the exchange of electrical signals between A and B.

[0058] Note that these methods of expression are just examples and are not limited to these methods. Here, X Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0059] Furthermore, the content described in one embodiment (even a part of it) may vary depending on the form of its implementation. Other content (even partial content) described in the voice, and / or one or more other facts The content described in the form of implementation (even if only a part of it) may be applied, combined, or replaced. It is possible to perform tasks such as drawing.

[0060] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content stated, or the content stated using the text described in the specification.

[0061] Furthermore, a diagram (even a partial one) described in one embodiment may refer to another part of that diagram. Further figures (even partial ones) described in that embodiment, and / or one or more In the diagram (or even just a part of it) described in another embodiment of the number, by combining them... This allows for the creation of even more diagrams.

[0062] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention and a method for manufacturing the same are described using drawings. explain.

[0063] Figures 1(A), 1(B), and 1(C) are top views of a transistor 10 according to one embodiment of the present invention. These are cross-sectional views. Figure 1(A) is a top view, and Figure 1(B) is a cross-sectional view of the dashed line shown in Figure 1(A). Figure 1(C) is a cross-sectional view between A1 and A2, and Figure 1(A) is a cross-sectional view between A3 and A4. Note that in Figure 1(A), the diagram is For clarity, some elements have been enlarged, reduced, or omitted in the illustration. Also, dashed lines are used. The direction from A1 to A2 is referred to as the channel length direction, and the direction from the dashed line A3 to A4 is referred to as the channel width direction. There are cases where this is the case.

[0064] The transistor 10 consists of a substrate 100, an insulating layer 110, an oxide semiconductor layer 121, and an oxide Semiconductor layer 122, oxide semiconductor layer 123, source electrode layer 130, drain electrode layer 1 40, gate insulating layer 150, gate electrode layer 160, insulating layer 170, insulating layer 175 The insulating layer 110 is formed on the substrate 100. The oxide semiconductor layer 121 is The oxide semiconductor layer 122 is formed on the insulating layer 110. The oxide semiconductor layer 122 is formed on the oxide semiconductor layer 121. The source electrode layer 130 and the drain electrode layer 140 are located on the oxide semiconductor layer 122. It is formed on and electrically connects to the oxide semiconductor layer 122. The insulating layer 170 is formed on the insulating layer 110. A source electrode layer 130 and a drain electrode layer 140 are formed on top of an oxide semiconductor layer 121 and an acid The insulating layer 175 is in contact with the side surface of the ion semiconductor layer 122. The insulating layer 175 is formed on the insulating layer 170, and the side surface It is in contact with the oxide semiconductor layer 123 in that part. The oxide semiconductor layer 123 is in contact with the oxide semiconductor layer 1 It is formed on 22. Also, the oxide semiconductor layer 123 is on the side of the insulating layer 170, insulating layer 175 It is in contact with the side surface of the source electrode layer 130 and the side surface of the drain electrode layer 140. The insulating layer 150 is formed on the oxide semiconductor layer 123. The gate electrode layer 160 is formed on the gate It is formed on the insulating layer 150.

[0065] Note that in Figure 1(B), the gate electrode layer 160 is shown as a single layer, but the gate will be described later. The electrode layer 161 and the gate electrode layer 162 may be stacked. (Included in transistor 10) The edges of the oxide semiconductor layer 123 and the gate insulating layer 150 are located further apart from the gate electrode layer 160. It is located on the outside. Furthermore, the structure described above consists of an oxide semiconductor layer 122 and an oxide semiconductor layer. Because the body layer 123, the source electrode layer 130, and the drain electrode layer 140 are in contact, During operation of the inverter 10, oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer It has the characteristic of having a high heat dissipation effect against heat generated within the conductive layer 123.

[0066] Furthermore, when the transistor 10 deposits the second insulating film which will become the insulating layer 170, the insulating layer 1 The interface with 10 contains the material for the insulating layer 110 and the material for the second insulating film, and also the material used when forming the second insulating film. A mixed layer containing gases such as [unclear] is formed, and oxygen (excess oxygen) is present in the mixed layer or insulating layer 110. A substance called exO is added. Further heat treatment removes the oxygen from the oxide semiconductor layer. It diffuses to 121 and oxide semiconductor layer 122, oxide semiconductor layer 121, oxide semiconductor The oxygen can be used to replenish the oxygen deficiency present in layer 122. This allows for the supply of oxygen to the oxygen deficiency present in layer 122. Transistor characteristics (e.g., threshold, reliability, etc.) can be improved.

[0067] The excess oxygen added during the formation of the second insulating film is, for example, by a sputtering method. During film deposition, the applied voltage, power, plasma, or substrate temperature can affect oxygen radiation. It exists in various states, such as calcium, oxygen ions, or oxygen atoms. At this time, the excess oxygen This is a state that has more energy than the stable state, and penetrates into the insulating layer 110. It is possible.

[0068] Furthermore, the method of adding oxygen is not limited to the method described above, and the insulating layer 110 may be added during film formation. It may contain excess oxygen, and after film formation, another method (e.g., ion implantation, ion plasma) may be used. Methods such as immersion may also be used.

[0069] As shown in the cross-sectional view of Figure 1(C)A3-A4, transistor 10 is located in the channel width direction. Then, the gate electrode layer 160 is connected to the oxide semiconductor layer 121 via the gate insulating layer 150. The conductive layer 122 faces the side surface of the oxide semiconductor layer 123. That is, the electrode gate layer 160 is facing the electrode. When pressure is applied, oxide semiconductor layer 121, oxide semiconductor layer 122, oxide semiconductor layer 12 3 is surrounded by the electric field of the gate electrode layer 160 in the channel width direction. Gate electrode layer 16 The structure of a transistor in which a semiconductor layer is surrounded by an electric field of 0 is called a surrounded channel. This is called an nel (s-channel) structure. Also, transistor 10 uses grooves to form a cell. Because gate electrodes, source electrodes, and drain electrodes can be formed in a fuselage, position It offers excellent alignment precision, making it possible to easily fabricate tiny transistors. A structure like this is a self-aligned s-channel FET (Self Align s -channel FET, SA s-channel FET) structure, or trench Gate s-channel FET (Trench gate s-channel FET) ET), or TGSA FET (Trench Gate Self Align) structure Manufacturing, or GLSA FET (Gate Last Self Align FET) Call.

[0070] Here, oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 are combined When combined with an oxide semiconductor layer 120, the SA s-channel structure transistor In this configuration, channels are formed throughout the entire (bulk) oxide semiconductor layer 120 when it is in the ON state. Therefore, the ON current increases. On the other hand, in the OFF state, the oxide semiconductor layer 120 is formed By depleting the entire channel region, the off-current can be further reduced.

[0071] As a result, the groove 174 has an oxide semiconductor layer 123, a gate insulating layer 150, and a gate electrode layer. When forming 160, the embedding ability of each film can be improved, and the transistor 10 It can be easily manufactured.

[0072] Furthermore, because transistor 10 has a TGSA structure, the gate electrode and source electrode are connected. Alternatively, it reduces the parasitic capacitance that occurs between the gate electrode and the drain electrode, and the cutoff frequency of transistor 10. This improves the wavenumber characteristics and makes it possible to enable a high-speed response for transistor 10.

[0073] Note that the position of the upper surface of the source electrode layer 130 or the drain electrode layer 140 is the gate electrode layer It can be lower than the base of 160, the same as it, or higher.

[0074] Furthermore, the transistor 10 may have a linear groove 174 as shown in Figure 2(A). As shown in the transistor diagram 2(B), the upper surface of the gate electrode layer 160 is lower than the upper surface of the insulating layer 175. It may also be located below. Also, transistor 10 has an insulating film 150a as shown in Figure 2(C). Furthermore, the third oxide semiconductor film 123a does not need to be planarized. Also, transistor As shown in Figure 3(A), the edges of the source electrode layer 130 and the drain electrode layer are acidic. The material may have a shape that is shorter than the ion semiconductor layer 122, or it may have a shape that is longer than the material semiconductor layer 122.

[0075] <Regarding channel length> Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. The region where the gate electrode overlaps with the part of the semiconductor through which current flows when the zistor is ON. , or the source (source region or source electrode) in the region where the channel is formed This refers to the distance between the drain (drain region or drain electrode) and the other element. In a zista, the channel length is not necessarily the same across all regions. That is, one channel The channel length of a transistor may not be fixed to a single value. Therefore, in this specification... The channel length is one of the following values ​​in the region where the channel is formed: maximum value, minimum value. Alternatively, use the average value.

[0076] <Regarding channel width> Channel width refers to, for example, the channel width of a semiconductor (or transistor) when it is in the ON state. This refers to the length of the region where the current-carrying part and the gate electrode overlap. In a channel, the channel width is not necessarily the same across all regions. That is, in a channel, The channel width of an inverter may not be fixed to a single value. Therefore, in this specification, The channel width is any one value, maximum value, or minimum value within the region where the channel is formed. The result will be the average value.

[0077] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is shown in the top view of the transistor. The apparent channel width shown in [the relevant section] becomes larger, and its effect can no longer be ignored. In some cases, such as in transistors with a fine and three-dimensional structure, the upper surface of the semiconductor may be The ratio of channel regions formed on the side surface of the semiconductor to the ratio of channel regions formed In some cases, the apparent channel width shown in the top view may become larger. However, the effective channel width actually formed is larger.

[0078] By the way, in transistors with a three-dimensional structure, the effective channel width is measured Estimation can be difficult in some cases. For example, estimating the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If this information is not precisely known, it is difficult to accurately measure the effective channel width.

[0079] <SCWについて> Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. The apparent channel width in a region is called the "enclosure channel width (SCW: Surround)". It is sometimes referred to as "ded Channel Width." Also, in this specification, simply When "channel width" is mentioned, it refers to the enclosed channel width or the apparent channel width. In some cases, the term "channel width" may refer to the effective channel width. It can refer to channel width. Other terms include channel length, channel width, effective channel width, and apparent width. The channel width and enclosure channel width are determined by acquiring cross-sectional TEM images and then viewing those images. The value can be determined by analysis, etc.

[0080] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine this. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The values ​​may differ from those obtained when calculating using the channel width.

[0081] <Improved performance through miniaturization> Miniaturization of transistors is essential for highly integrating semiconductor devices. It is known that miniaturization degrades the electrical characteristics of transistors, and the channel width shrinks. Reducing the ON current decreases the ON current.

[0082] For example, in the transistor according to one aspect of the present invention shown in Figure 1, as described above, the channel is shaped A third oxide semiconductor layer 123 is formed so as to cover the oxide semiconductor layer 122. Therefore, the channel forming layer and the gate insulating layer are not in contact. This can suppress the scattering of carriers that occurs at the interface between the stratified layer and the gate insulating layer, and transistor The on-current can be increased.

[0083] Furthermore, in a transistor according to one aspect of the present invention, the channel of the oxide semiconductor layer 122 Because the gate electrode layer 160 is formed so as to electrically surround the width direction of the flank, the oxide For semiconductor layer 1223, in addition to the gate electric field from the vertical direction, there is also a gate electric field from the lateral direction. An electric field is applied. That is, a gate electric field is applied to the entire oxide semiconductor layer. As a result, the current flows throughout the oxide semiconductor layer 122, further increasing the on-current. It can be done.

[0084] Furthermore, in one aspect of the present invention, the transistor has an oxide semiconductor layer 123 and an oxide semiconductor layer 121 By forming it on the oxide semiconductor layer 122, it has the effect of making it difficult for interface states to form, and oxide By placing the semiconductor layer 122 in an intermediate position, the influence of impurities from above and below can be eliminated. It also has the effect of improving the on-current of the transistor as described above. This allows for stabilization of the threshold voltage and reduction of the S value (subthreshold value). Therefore, Icut (current when gate voltage VG is 0V) can be reduced, and power consumption This can reduce the threshold voltage of the transistor. This can improve the long-term reliability of semiconductor devices.

[0085] In this embodiment, an oxide semiconductor layer 120 is used in the channel, etc. Although an example has been shown, the embodiments of the present invention are not limited thereto. For example, Depending on the channel, its vicinity, the source region, the drain region, etc., it may be used in some cases or situations. Accordingly, silicon (including strained silicon), germanium, silicon germanium, silicon carbide Cone, gallium arsenide, aluminum gallium arsenide, indium phosphate, gallium nitride, organic It may be formed from a material containing semiconductors, etc.

[0086] <Transistor Configuration> The transistor configuration of this embodiment is shown below.

[0087] Circuit board 100 The substrate 100 may be, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. It can also be used. In addition, single-crystal semiconductor substrates made of silicon or silicon carbide, multi-bonded Crystal semiconductor substrate, compound semiconductor substrate made of silicon germanium, SOI (Semico It is also possible to use a circuit board (inductor on insulator), etc. A substrate on which semiconductor elements are provided may also be used. The substrate 100 is not merely a support material, but also has other devices such as transistors formed on it. A substrate may also be used. In this case, the gate electrode layer 160 and source electrode layer 13 of the transistor 0, and one of the drain electrode layers 140 are electrically connected to the other devices mentioned above. That's fine.

[0088] Furthermore, a flexible substrate may be used as the substrate 100. One method for creating a transistor is to fabricate a transistor on a non-flexible substrate, and then... Another method involves peeling it off and transferring it to a flexible substrate, substrate 100. In that case, the non-flexible It is preferable to provide a release layer between the substrate and the transistor. The substrate 100 is made of woven fibers. A sheet, film, or foil containing the material may also be used. Furthermore, the substrate 100 may be stretchable. It is also possible to return the substrate 100 to its original shape when bending or pulling is stopped. It may have a quality. Or it may have the property of not returning to its original shape. Thickness of substrate 100 For example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and further Preferably, the thickness is 15 μm or more and 300 μm or less. When the substrate 100 is thinned, the semiconductor device It can be lightened. Also, by making the substrate 100 thinner, in the case of having flexibility even when using glass or the like, or having the property of returning to the original shape when bending or pulling is stopped. There may be a case. Therefore, the impact applied to the semiconductor device on the substrate 100 due to dropping or the like can be alleviated. That is, a robust semiconductor device can be provided.

[0089] As the substrate 100 which is a flexible substrate, for example, metal, alloy, resin, glass, or their fibers and the like can be used. The substrate 100 which is a flexible substrate preferably has less deformation due to the environment as the linear expansion rate is lower. As the substrate 100 which is a flexible substrate, for example, a material having a linear expansion rate of 1 × 10 / K or less, 5 × 10 / K or less, or 1 × 10 / K or less may be used. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, -3 -5 -5

[0090] 《Insulating layer 110》 The insulating layer 110 has the role of preventing the diffusion of impurities from the substrate 100, and can also play the role of supplying oxygen to the oxide semiconductor layer 120. Therefore, the insulating layer 110 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, by the TDS method, the oxygen release amount in terms of oxygen atoms is 1.0 19 atoms / cm 3The membrane is defined as described above. Note that the membrane during the above TDS analysis The surface temperature range is 100°C to 700°C, or 100°C to 500°C. This is preferable. Also, as described above, if the substrate 100 is a substrate on which other devices are formed The insulating layer 110 also functions as an interlayer insulating film. In that case, the surface becomes flat. Sea urchins are processed using methods such as CMP (Chemical Mechanical Polishing). It is preferable to perform a flattening treatment.

[0091] Oxide semiconductor layers 121, 122, 123 The oxide semiconductor layer 122 is an oxide semiconductor film containing In or Zn, and is typically, In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M -Zn oxide (where M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd ) exists.

[0092] Used as oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 Oxide semiconductors that can be used contain at least indium (In) or zinc (Zn). It is preferable that it contains both In and Zn. To reduce variations in the electrical characteristics of semiconductor transistors, stabilizers are used along with them. It is preferable to include a riser.

[0093] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Examples include aluminum (Al) or zirconium (Zr). Also, other stabilizers... These are lanthanides: lanthanum (La), cerium (Ce), and praseodymium (P). r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Examples include rhodium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). .

[0094] Furthermore, when the oxide semiconductor layer 123 is an In-M-Zn oxide, the ratio of In and M atoms Preferably, In is 25 atomic% or more, M is less than 75 atomic%, and further Preferably, In is 34 atomic% or more and M is less than 66 atomic%.

[0095] The content of indium, gallium, etc. in the oxide semiconductor layer 123 is determined by time-of-flight secondary ions. Mass spectrometry (TOF-SIMS), X-ray electron spectroscopy (XPS), ICP mass spectrometry (IC This can be compared using P-MS.

[0096] The oxide semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more. More preferably, it is 3eV or more, which reduces the off-current of transistor 10. can.

[0097] The thickness of the oxide semiconductor layer 122 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 10 The wavelength should be 0 nm or less, and more preferably 3 nm to 50 nm.

[0098] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 constitute the oxide semiconductor layer 122. It is an oxide semiconductor film composed of one or more elements. Therefore, the oxide semiconductor layer 12 At the interface between 2 and the oxide semiconductor layer 122 and the oxide semiconductor layer 124, interfacial scattering occurs. It is less likely to occur. Therefore, since the movement of carriers is not inhibited at this interface, the field-effect mobility of the transistor 10 is increased.

[0099] The oxide semiconductor layers 121 and 123 typically include In-Ga oxide, In -Zn oxide, In-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-M-Z n oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), and the energy level of the lower end of the conduction band is closer to the vacuum level than that of the oxide semiconductor layer 122. Typically, the difference between the energy of the lower end of the conduction band of the oxide semiconductor layers 121 and 123 and the energy of the lower end of the conduction band of the oxide semiconductor layer 122 is 0.05 eV or more, 0.0 7 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less, 1 eV or less, 0 .5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the oxide semiconductor layers 121 and 123 and the electron affinity of the oxide semiconductor layer 122 is 0.05 e V or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Note that the electron affinity indicates the difference between the vacuum level and the energy of the lower end of the conduction band.

[0100] When the oxide semiconductor layers 121 and 123 have Al, Ti, Ga, Y, Zr, S n, La, Ce, Mg, or Nd at an atomic ratio higher than that of In, the following effects may be obtained. (1) The energy gap of the oxide semiconductor layers 121, 122, and oxide semiconductor layer 124 is increased. (2) The oxide semiconductor layers 121, acid ​(3) Reduce the electron affinity of the ionized semiconductor layer 123. (4) Shield against external impurities. 4) Compared to the oxide semiconductor layer 122, the insulating properties are higher. (5) Al, Ti, Ga, Y Zr, Sn, La, Ce, Mg, or Nd are metallic elements that have a strong bonding force with oxygen. Therefore, Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd are more effective than In. Having a specific atomic ratio makes oxygen deficiency less likely to occur.

[0101] Furthermore, the oxide semiconductor layer 121 and oxide semiconductor layer 123 are compared with the oxide semiconductor layer 122. Because it has high insulating properties, it has the same function as a gate insulating layer.

[0102] When oxide semiconductor layer 121 and oxide semiconductor layer 123 are In-M-Zn oxide, Zn The atomic ratio of In and M, excluding O, is preferably such that In is 50 atoms. % or less, M is 50 atomic% or more, and more preferably In is 25 atomic% or less Below, M is assumed to be 75% or higher.

[0103] Furthermore, oxide semiconductor layer 121 and oxide semiconductor layer 123 are made of In-M-Zn oxide (where M is Al In the case of oxide semiconductors (Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), Compared to layer 122, the M(Al) contained in oxide semiconductor layer 121 and oxide semiconductor layer 123 The atomic ratio of Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd is high, In terms of appearance, compared to the atoms contained in the oxide semiconductor layer 123, the preferred amount is 1.5 times or more. The atomic ratio is at least twice, and more preferably at least three times higher. The element represented by M above is Because it binds more strongly to oxygen than indium, oxygen vacancies form in the oxide semiconductor layer 121, oxide semiconductor It has the function of suppressing the occurrence of oxidation in the conductive layer 123. That is, oxide semiconductor layer 121, oxide The material semiconductor layer 123 is an oxide semiconductor film that is less prone to oxygen vacancies than the oxide semiconductor layer 122. be.

[0104] Furthermore, the oxide semiconductor layer 122 is more than oxide semiconductor layer 121 and oxide semiconductor layer 123. It is good to increase the s orbital content. In oxide semiconductors, the s orbitals of heavy metals are the main carriers. It contributes to conduction, and by increasing the In content, more s orbitals overlap. Therefore, oxides with a composition where In is greater than M are acids with a composition where In is equal to or less than M. Compared to oxides, it has higher mobility. Therefore, the oxide semiconductor layer 122 contains indium. By using a large amount of oxide, it is possible to realize transistors with high field-effect mobility. Cut.

[0105] Furthermore, the oxide semiconductor layer 122 is made of In-M-Zn oxide (where M is Al, Ti, Ga, Y, Z). In the case of r, Sn, La, Ce, Mg, or Nd, the oxide semiconductor layer 122 is formed. In the target used for this purpose, the atomic ratio of metal elements is In:M:Zn=x1:y1:z If we set it to 1, then x1 / y1 is between 1 / 3 and 6, and furthermore, between 1 and 6, and z1 / y1 is preferably between 1 / 3 and 6, and more preferably between 1 and 6. By setting y1 to between 1 and 6, the oxide semiconductor layer 122 is made CAAC-OS (CA xis Aligned Crystalline Oxide Semiconductor (tor) film formation becomes easier. Typical examples of atomic ratios of target metal elements include: In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, 2:1:1.5, 2: Examples include 1:2.3, 2:1:3, 3:1:2, 4:2:3, 4:2:4.1, etc.

[0106] Furthermore, oxide semiconductor layer 121 and oxide semiconductor layer 123 are made of In-M-Zn oxide (where M is A For oxide semiconductors (l, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), In a target used to deposit a body layer 121 and an oxide semiconductor layer 123, the metal element If the ratio of the number of atoms in the primary atoms is In:M:Zn=x2:y2:z2, then x2 / y2 <x1 / y1で Preferably, z2 / y2 is between 1 / 3 and 6, and more preferably between 1 and 6. Furthermore, by setting z2 / y2 to between 1 and 6, the oxide semiconductor layer 121 and the oxide semiconductor The CAAC-OS film is more easily formed as layer 123. Typical examples of ratios include In:M:Zn = 1:3:2, 1:3:4, 1:3:6, 1:3: 8, 1:4:4, 1:4:5, 1:4:6, 1:4:7, 1:4:8, 1:5:5, 1: Examples include 5:6, 1:5:7, 1:5:8, 1:6:8, 1:6:4, 1:9:6, etc.

[0107] Furthermore, the atomic ratios of oxide semiconductor layer 121 and oxide semiconductor layer 123 are, respectively, considered to be within the margin of error. This includes a variation of plus or minus 40% in the above atomic ratio.

[0108] Furthermore, the oxide semiconductor layer 123 is made of metal oxides, such as aluminum oxide (AlOx), acid Gallium oxide (GaOx), hafnium oxide (HfOx), silicon oxide (SiOx), acid It can also be replaced with germanium oxide (GeOx) or zirconia oxide (ZrOx). Furthermore, the metal oxide can also be present on the oxide semiconductor layer 123.

[0109] Furthermore, the atomic ratio is not limited to these, and an appropriate atomic ratio can be used depending on the required semiconductor properties. You should use this.

[0110] Furthermore, oxide semiconductor layer 121 and oxide semiconductor layer 123 may have the same composition. For example, oxide The target used in the sputtering method is defined as the monocrystalline semiconductor layer 121 and the oxide semiconductor layer 123. The atomic ratio of the metal elements is In:Ga:Zn = 1:3:2, 1:3:4, or 1:4:5 In-Ga-Zn oxide may also be used.

[0111] Alternatively, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 may have different compositions. For example, , as the oxide semiconductor layer 121, atoms of the target metal element used in the sputtering method Using an In-Ga-Zn oxide with a numerical ratio of In:Ga:Zn = 1:3:4, an oxide semiconductor layer Assuming 123, the atomic ratio of the target metal elements is In:Ga:Zn=1:3:2. Ga-Zn oxide may also be used.

[0112] The thicknesses of oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 are: It is preferable that the wavelength be between 3 nm and 100 nm, or between 3 nm and 50 nm.

[0113] Here, the thickness of the oxide semiconductor layer 122 is at least compared to the oxide semiconductor layer 121. It may be formed thinly, the same thickness, or thickly. For example, oxide semi Increasing the thickness of the conductive layer 122 can increase the on-current of the transistor. The oxide semiconductor layer 121 loses its effect of suppressing the formation of interface states in the oxide semiconductor layer 122. It is sufficient if the thickness is not excessive. For example, the thickness of the oxide semiconductor layer 122 is the oxide semiconductor layer For a thickness of 121, if it is greater than 1, or more than 2, or more than 4, or 6 It can be more than doubled. Also, when it is not necessary to increase the on-current of the transistor The thickness of the oxide semiconductor layer 121 may be greater than or equal to the thickness of the oxide semiconductor layer 122. For example, If the insulating layer 110 or the insulating layer 175 contains an excess of oxygen, the acid may be removed by heat treatment. The element diffuses, and the amount of oxygen vacancies contained in the oxide semiconductor layer 122 can be reduced, The electrical characteristics of the device can be stabilized.

[0114] Furthermore, the oxide semiconductor layer 123, like the oxide semiconductor layer 121, is similar to the oxide semiconductor layer 122. The thickness should be such that the effect of suppressing the formation of interface states is not lost. For example, oxide semiconductor The thickness should be the same as or less than that of the conductive layer 121. If the oxide semiconductor layer 123 is thick... , the electric field formed by the gate electrode layer 160 (or gate electrode layer 161, gate electrode layer 162) Because it may become difficult for the oxide semiconductor layer 122 to reach it, the oxide semiconductor layer 123 is thin. It is preferable to form it. For example, the oxide semiconductor layer 123 is the thickness of the oxide semiconductor layer 122. It should be made thinner than this. However, this is not the only option; the thickness of the oxide semiconductor layer 123 is determined by the gate isolation. Considering the voltage rating of the 150mm margin layer, you should set it appropriately according to the voltage used to drive the transistor. stomach.

[0115] Oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123, respectively If the composition is different, the interface is... Observation is performed using an Electron Microscope. There are cases where this is possible.

[0116] <Regarding Hydrogen Concentration> The hydrogen contained in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 reacts with the oxygen bonded to the metal atoms to form water, and at the same time, oxygen vacancies are formed in the lattice (or the part where oxygen has desorbed). When hydrogen enters these oxygen vacancies, electrons that are carriers may be generated. Also, part of the hydrogen may bond with the oxygen bonded to the metal atoms to generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics.

[0117] For this reason, it is preferable that hydrogen is reduced as much as possible together with oxygen vacancies at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each of their interfaces. For example, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123 , and each of their interfaces is 1×10 atoms / cm 16 or more and 2×10 3 atoms / cm 20 or less, preferably 1×10 3 atoms / cm 16 or more and 5×10 3 atoms / cm 19 or less, more preferably 1× 3 10 10 16 atoms / cm 3 or more and 1×10 19 atoms / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or more and 5×10 18 atoms / cm 3 ​​​​The following This is desirable. As a result, transistor 10 has an electrical characteristic in which the threshold voltage is positive ( It can have a characteristic also known as the Marie-off characteristic.

[0118] <Regarding carbon and silicon concentrations> Furthermore, oxide semiconductor layer 121, oxide semiconductor layer 122, oxide semiconductor layer 123, and so At each interface, if silicon or carbon, which are among the Group 14 elements, are present, an oxide is formed. Oxygen vacancies in semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 The amount increases, and an n-type region is formed. Therefore, the oxide semiconductor layer 121, oxide semiconductor Body layer 122, oxide semiconductor layer 123, and silicon and carbon at their respective interfaces. It is desirable to reduce the elementary concentration. For example, oxide semiconductor layer 121, oxide semiconductor layer 1 22, oxide semiconductor layer 123, oxide semiconductor layer 124, and S at their respective interfaces The concentrations of silicon and carbon obtained by IMS are 1 × 10⁻⁶. 16 atoms / cm 3 The above 1 ×10 19 atoms / cm 3 The following is preferably 1 × 10 16 atoms / cm 3 The above 5 ×10 18 atoms / cm 3 More preferably 1 × 10 16 atoms / cm 3 The above 2 x 10 18 atoms / cm 3 The following is preferable. As a result, the transition TA10 has an electrical characteristic (also called a normally-off characteristic) in which the threshold voltage is positive. do.

[0119] <Regarding the concentration of alkali metals> Furthermore, alkali metals and alkaline earth metals generate carriers when they bond with oxide semiconductors. This can occur, and the transistor's off-current may increase. Therefore, acid Oxide semiconductor layer 121, oxide semiconductor layer 122, oxide semiconductor layer 123, and each It is preferable to reduce the concentration of alkali metals or alkaline earth metals at the interface. For example, oxide semiconductor layer 121, oxide semiconductor layer 122, oxide semiconductor layer 123, and At each interface, alkali metals or aluminum obtained by secondary ion mass spectrometry The concentration of potassium earth metals is 1 × 10⁻⁶ 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 It is desirable to do the following. This will allow transistor 10 to It can have electrical characteristics where the value voltage is positive (also called normally-off characteristics). ru.

[0120] <Regarding nitrogen concentration> Furthermore, oxide semiconductor layer 121, oxide semiconductor layer 122, oxide semiconductor layer 123, and so When nitrogen is present at each interface, electrons, which act as carriers, are generated, increasing the carrier density. And an n-type region is formed. As a result, using an oxide semiconductor containing nitrogen Transistors tend to exhibit normally-on characteristics. Therefore, oxide semiconductor layer 121, oxide Nitrogen is formed in the monocrystalline semiconductor layer 122, the oxide semiconductor layer 123, and at their respective interfaces. It is preferable that the amount is reduced as much as possible, for example, oxide semiconductor layer 121, oxide semiconductor layer 1 22, oxide semiconductor layer 123, and nitrogen obtained by SIMS at each interface. The elementary cardinality is 1 × 10⁻⁶ 15 atoms / cm3 The above 5 x 10 19 atoms / cm 3 below, Preferably 1 × 10 15 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 below, Better 1 × 10 15 atoms / cm 3 The above 1 x 10 18 atoms / cm 3 Below Below, more preferably 1 × 10 15 atoms / cm 3 The above 5 x 10 17 ate / c m 3 The following is preferable. This allows transistor 10 to have a threshold voltage of plastic It can have electrical characteristics that result in a "normally off" state (also known as a normally-off characteristic).

[0121] <About carrier density> Impurities in oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 By reducing the oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer The carrier density of 123 can be reduced. Therefore, the oxide semiconductor layer 121, The monocrystalline semiconductor layer 122 and the oxide semiconductor layer 123 have a carrier density of 1 × 10⁻¹⁶ 15 pcs / c m 3 The following is preferably 1 × 10 13 pieces / cm 3 More preferably 8 × 10 11 pieces / cm 3 Less than 1 × 10 11 pieces / cm 3 Less than 1 × 10 10 pieces / cm 3 It is less than 1 × 10 -9 pieces / cm 3 That concludes this section.

[0122] Oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 are By using oxide semiconductor films with low pure substance concentration and low defect level density, even better electrical performance can be achieved. Transistors with specific characteristics can be fabricated. Here, the impurity concentration is low and defects are present. A low energy level density (low oxygen deficiency) is referred to as high-purity intrinsic or substantially high-purity intrinsic. Oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic have few carrier sources. Therefore, the carrier density can be lowered in the oxide semiconductor film. A transistor in which a channel region is formed has electrical characteristics where the threshold voltage is positive (no Also known as the Marie-off property.) It is prone to becoming high-purity intrinsic or substantially high-purity intrinsic. Oxide semiconductor films, having a low defect level density, can also have a low trap level density. There is. Also, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic have an off-current. It is extremely small, and the voltage between the source electrode and the drain electrode (drain voltage) is between 1V and 10V. Within the range, the off-current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1 × 10 -13 A characteristic of A or less can be obtained. Therefore, channeling the oxide semiconductor film Transistors in which a region is formed exhibit small fluctuations in electrical characteristics and are highly reliable. It may sometimes become "ta".

[0123] Furthermore, as mentioned above, a transient using a highly purified oxide semiconductor film in the channel formation region The off-current of the sta is extremely small. For example, if the voltage between the source and drain is 0.1V, 5 When set to V or approximately 10V, the off-current normalized by the transistor's channel width. This makes it possible to reduce the voltage to several yA / μm to several zA / μm.

[0124] The oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 are, for example, Non-single-crystal structures are also acceptable. Examples of non-single-crystal structures include CAAC-OS, which will be discussed later, and polycrystalline structures. This includes microcrystalline or amorphous structures. In non-single-crystal structures, amorphous structures are the most defective. CAAC-OS has a high level density, while CAAC-OS has the lowest defect level density.

[0125] The oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 are, for example, A microcrystalline structure is also acceptable. A microcrystalline oxide semiconductor layer 121, an oxide semiconductor layer 122, and The oxide semiconductor layer 123 contains, for example, microcrystals with a size of 1 nm to less than 10 nm in the film. Includes. Or, oxide films and oxide semiconductor films with a microcrystalline structure, for example, 1n in the amorphous phase. It is a multiphase structure having crystalline portions between m and less than 10 nm.

[0126] The oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 are, for example, An amorphous structure is also acceptable. An amorphous oxide semiconductor layer 121, an oxide semiconductor layer 122, Furthermore, the oxide semiconductor layer 123, for example, has a disordered atomic arrangement and does not contain crystalline components. Alternatively, an amorphous oxide film may, for example, have a completely amorphous structure and lack crystalline parts. .

[0127] Furthermore, oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 are A mixed film having regions of two or more structures: CAAC-OS, a microcrystalline structure, and an amorphous structure. It may be present. As a mixed film, for example, a region with an amorphous structure and a region with a microcrystalline structure, CA There is a monolayer structure having an AC-OS region. Alternatively, as a mixed film, for example, amorphous There is a layered structure consisting of a structural region, a microcrystalline structure region, and a CAAC-OS region.

[0128] Furthermore, oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 are, For example, it may have a single crystal structure.

[0129] Compared to oxide semiconductor layer 122, the oxide semiconductor film is less prone to oxygen vacancies. By providing contact with the top and bottom of 122, oxygen vacancies in the oxide semiconductor layer 122 are reduced. This is possible. In addition, the oxide semiconductor layer 122 is composed of metal elements that make up the oxide semiconductor layer 122. Because it is in contact with oxide semiconductor layer 121 and oxide semiconductor layer 123 which have one or more elements, The interface between semiconductor layer 121 and oxide semiconductor layer 122, and the oxide semiconductor layer 122 and oxide semiconductor The interface state density at the interface with layer 123 is extremely low. For example, oxygen is added to the insulating layer 110. After addition, by heat treatment, the oxygen passes through the oxide semiconductor layer 121 to the oxide semiconductor Oxygen moves to layer 122, but at this time, oxygen is less likely to be captured at the interface level, and efficiency It is often possible to move oxygen contained in the oxide semiconductor layer 121 to the oxide semiconductor layer 122. This is possible. As a result, it is possible to reduce the oxygen vacancies contained in the oxide semiconductor layer 122. There is. Also, since oxygen is added to the oxide semiconductor layer 121, the oxide semiconductor layer 121 It is possible to reduce oxygen vacancies. That is, at least the localization of the oxide semiconductor layer 122 The density can be reduced.

[0130] Furthermore, the oxide semiconductor layer 122 contains insulating films with different constituent elements (for example, silicon oxide film). When in contact with the gate insulating layer, an interface state is formed, and this interface state forms a channel. This can happen. In such cases, a second transistor with a different threshold voltage appears, and the transistor The apparent threshold voltage of an inverter can fluctuate. However, oxide semiconductors... Oxide semiconductor layer 121 and oxide semiconductor layer containing one or more metal elements that constitute layer 122 Since 123 is in contact with the oxide semiconductor layer 122, the oxide semiconductor layer 121 and the oxide semiconductor layer 1 Interface states are formed at the interface of 22 and at the interface between the oxide semiconductor layer 123 and the oxide semiconductor layer 122. It will become more difficult to achieve.

[0131] Furthermore, oxide semiconductor layer 121 and oxide semiconductor layer 123 are connected to the insulating layer 110 and the gate, respectively. The constituent elements of the insulating layer 150 are mixed into the oxide semiconductor layer 122, and an impurity-induced energy level is formed. It also functions as a barrier film to suppress penetration.

[0132] For example, an insulating film containing silicon may be used as the insulating layer 110 or the gate insulating layer 150. In this case, the silicon in the gate insulating layer 150, or the insulating layer 110 and the gate insulating layer 150 Carbon that may be mixed in enters the oxide semiconductor layer 121 or oxide semiconductor layer 123 at the interface. Impurities such as silicon and carbon can be present in the oxide semiconductor layer 1. When it enters 22, it forms an impurity level, and the impurity level acts as a donor, generating electrons, thus n It can sometimes be standardized.

[0133] However, the thickness of the oxide semiconductor layer 121 and oxide semiconductor layer 123 is greater than a few nanometers. If impurities such as silicon and carbon that have been mixed in do not reach the oxide semiconductor layer 122. Therefore, the influence of impurity levels is reduced.

[0134] Therefore, by providing oxide semiconductor layer 121 and oxide semiconductor layer 123, the transient This can reduce variations in electrical characteristics such as threshold voltage.

[0135] Furthermore, the gate insulating layer 150 and the oxide semiconductor layer 122 are in contact, and a channel is formed at their interface. If this occurs, interfacial scattering will occur at the interface, and the field-effect mobility of the transistor will decrease. However, the oxide semiconductor layer 122 contains one or more metal elements. 21. Since the oxide semiconductor layer 123 is provided in contact with the oxide semiconductor layer 122, At the interface between the conductive layer 122 and the oxide semiconductor layer 121 and oxide semiconductor layer 123, carriers are dispersed. This reduces the likelihood of disturbances and allows for a higher field-effect mobility of the transistor.

[0136] In this embodiment, the amount of oxygen vacancies in the oxide semiconductor layer 122, and furthermore, the oxide semiconductor layer By reducing the amount of oxygen vacancies in the oxide semiconductor layer 121 and oxide semiconductor layer 123 that are in contact with 122. This makes it possible to reduce the localized energy level density of the oxide semiconductor layer 122. As a result, the transistor 10 shown in this embodiment exhibits low threshold voltage fluctuation and high reliability. It can have excellent characteristics. Furthermore, the transistor 10 shown in this embodiment has excellent electrical properties. It possesses certain characteristics.

[0137] Furthermore, silicon-containing insulating films are often used as the gate insulating layer of transistors. Therefore, for the reasons stated above, the region that becomes the channel of the oxide semiconductor layer is a transient in one aspect of the present invention. It can be said that a structure that does not come into contact with the gate insulating layer, like a sta, is preferable. When a channel is formed at the interface between the insulating layer and the oxide semiconductor layer, carrier scattering occurs at the interface. This can occur, and the field-effect mobility of the transistor may decrease. From this perspective as well It is preferable to keep the region that forms the channel of the oxide semiconductor layer separate from the gate insulating layer. .

[0138] Therefore, oxide semiconductor layer 120 is made of oxide semiconductor layer 121, oxide semiconductor layer 122, acid By using a stacked structure of oxide semiconductor layers 123, channels are formed in the oxide semiconductor layer 123. This allows for the formation of transistors with high field-effect mobility and stable electrical characteristics. It is possible.

[0139] Note that oxide semiconductors do not necessarily need to be made of three layers; they can be single-layer, double-layer, quadruple-layer, or even five-layer. The above configuration is also acceptable. When a single layer is used, the oxide semiconductor layer 122 shown in this embodiment is used. You can use a layer that corresponds to that.

[0140] <Band Diagram> Now, let's explain the band diagram. For ease of understanding, the band diagram shows the insulating layer 110. Oxide semiconductor layer 121, oxide semiconductor layer 122, oxide semiconductor layer 123, and gate insulation This shows the energy (Ec) at the lower end of the conduction band in marginal layer 150.

[0141] As shown in Figures 4(A) and 4(B), oxide semiconductor layer 121, oxide semiconductor layer 122, In the oxide semiconductor layer 123, the energy at the lower edge of the conduction band changes continuously. This is because The elements constituting oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 are This can be understood from the fact that oxygen molecules diffuse easily to each other due to their commonality. Therefore, oxidation The material semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 are layers of films with different compositions. Although it is a layered structure, it can also be described as having continuous physical properties.

[0142] Oxide semiconductor films stacked with a common main component are not simply stacked layers but are connected in a continuous manner. (Here, in particular, a U-shaped well in which the energy at the lower end of the conduction band changes continuously between each layer.) The fabrication process is carried out so that a U-shaped well structure is formed. That is, at the interface of each layer. To ensure that there are no impurities that form defect levels such as trap centers or recombination centers. This forms a layered structure. If impurities are present between the layers of the stacked multilayer film, energy The continuity of the energy band is lost, and carriers disappear at the interface due to trapping or recombination. It ends up happening.

[0143] Note that in Figure 4(B), the Ec values ​​of oxide semiconductor layer 121 and oxide semiconductor layer 123 are similar. I have shown one example, but each case may be different.

[0144] From Figures 4(B) and 4(C), the oxide semiconductor layer 122 becomes a well, and transient In step 10, it can be seen that a channel is formed in the oxide semiconductor layer 122. A U-shaped well in which the energy at the bottom of the conduction band changes continuously, with the oxide semiconductor layer 122 at the bottom. The channel in the door structure can also be called an embedded channel.

[0145] Furthermore, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are insulated from an insulating film such as a silicon oxide film. Near the interface with the film, trap levels can form due to impurities and defects. Due to the presence of the body layer 121 and the oxide semiconductor layer 123, the oxide semiconductor layer 122 and the trough The top level can be kept away. However, if the oxide semiconductor layer 121 or the oxide semiconductor When the energy difference between the Ec of body layer 123 and the Ec of oxide semiconductor layer 122 is small, oxidation Electrons in the semiconductor layer 122 may exceed the energy difference and reach the trap level. The electrons that become the negative charge are trapped in the trap level, creating a negative solid at the insulating film interface. A constant charge is generated, causing the transistor's threshold voltage to shift in the positive direction. Furthermore, In long-term storage tests of transistors, traps are not fixed, causing fluctuations in characteristics. There are concerns.

[0146] Therefore, in order to reduce the fluctuation of the transistor threshold voltage, the oxide semiconductor layer 121 , and the energy difference between the Ec of the oxide semiconductor layer 123 and the oxide semiconductor layer 122 It is necessary to provide such a feature. The respective energy difference is preferably 0.1 eV or more. A voltage of 0.2 eV or higher is more preferable.

[0147] Furthermore, the oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 contain crystals. It is preferable that the part is included. In particular, using a crystal oriented along the c axis makes it safer for transistors. It is possible to impart specific electrical characteristics.

[0148] Furthermore, in the band diagram shown in Figure 4(B), if the oxide semiconductor layer 123 is not provided, Between the semiconductor layer 123 and the gate insulating layer 150 is an In-Ga oxide (for example, with an atomic ratio of You may use an In-Ga oxide with an In:Ga ratio of 7:93, or gallium oxide. It may also be provided. In-Ga oxide may be provided between the insulating layer 150, or gallium oxide may be provided. That's fine.

[0149] The oxide semiconductor layer 122 is more electrically charged than the oxide semiconductor layer 121 and the oxide semiconductor layer 123. An oxide with high affinity for its offspring is used. For example, as the oxide semiconductor layer 122, an oxide semiconductor The electron affinity is 0.07 eV to 1.3 eV greater than that of layer 121 and oxide semiconductor layer 123. Preferably, 0.1 eV to 0.7 eV, and more preferably 0.2 eV to 0.4 eV. Oxides with an eV of less than or equal to a certain value can be used.

[0150] The transistor shown in this embodiment uses one or more metal elements to constitute the oxide semiconductor layer 122. Because it contains oxide semiconductor layer 121 and oxide semiconductor layer 123, The interface between the conductive layer 121 and the oxide semiconductor layer 122, and the interface between the oxide semiconductor layer 123 and the oxide semiconductor layer It becomes difficult to form interface states at the interface with the conductive layer 122. Therefore, the oxide semiconductor layer 121, acid By providing the semiconductor layer 123, the electrical characteristics of the transistor, such as the threshold voltage, are improved. It can reduce variability and fluctuations.

[0151] Source electrode layer 130, drain electrode layer 140 The source electrode layer 130 and the drain electrode layer 140 contain copper (Cu), tungsten (W), and mo Ribdenum (Mo), Gold (Au), Aluminum (Al), Manganese (Mn), Titanium (T) i) Tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn) Iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (I r), a material consisting of strontium (Sr), an element, or an alloy, or a material mainly composed of these. A single or multilayer conductive layer containing compounds such as oxygen, nitrogen, fluorine, and silicon. It is preferable to do so. For example, when stacking, the lower side that is in contact with the oxide semiconductor layer 122 The conductive layer (for example, the source electrode layer 131 and drain electrode layer 141 shown in Figure 15) is oxygen and It has a material that is easy to bond, and the upper conductive layer (for example, the source electrode layer 132 shown in Figure 15, The rain electrode layer 142) can have a material with strong oxidation resistance. Furthermore, it can have heat resistance and conductivity. It is preferable to use high-melting-point materials such as tungsten or molybdenum that can achieve both electrical and functional properties. Furthermore, it is preferable to form it with a low-resistance conductive material such as aluminum or copper. -When a Mn alloy is used, manganese oxide is formed at the interface with the oxygen-containing insulator, It is preferable because it has the function of suppressing the diffusion of Cu.

[0152] Furthermore, when a conductive material that readily combines with oxygen is brought into contact with an oxide semiconductor layer, in the oxide semiconductor layer A phenomenon occurs where oxygen diffuses towards the conductive material side, which readily combines with oxygen. - Oxygen deficiency occurs in the region in contact with the electrode layer or drain electrode layer, resulting in a small amount of oxygen in the film. The hydrogen contained in the region enters the oxygen vacancy, causing that region to become significantly n-type. Therefore, the n-type region is made to act as the source or drain of the transistor. It is possible.

[0153] For example, a laminated structure using W as the lower conductive layer and Pt as the upper conductive layer This process makes the contacted oxide semiconductor n-type while simultaneously providing conductivity through contact with the insulating layer 170. This can suppress oxidation of the electrolytic layer.

[0154] Gate insulating layer 150 The gate insulating layer 150 contains oxygen (O), nitrogen (N), fluorine (F), and aluminum (Al ), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge ), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd) It may contain hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide. (SiOx), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy) Silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx) ), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (La Ox), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide ( An insulating film containing one or more types of TaOx can be used. Also, the gate insulating layer 150 is The materials may be laminated. In addition, the gate insulating layer 150 may contain lanthanum (La), nitrogen, It may contain impurities such as zirconium (Zr).

[0155] Furthermore, an example of the laminated structure of the gate insulating layer 150 will be described. The gate insulating layer 150 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide. , and preferably containing silicon oxide or silicon oxide nitride.

[0156] Hafnium oxide has a higher dielectric constant compared to silicon oxide and silicon oxide nitride. Therefore Therefore, the physical film thickness can be made larger than the equivalent oxide film thickness, so the equivalent oxide film thickness can be 10 nm or less. Even when the size is set to below 5nm or less, the leakage current due to tunnel current can be reduced. Yes, it is possible. In other words, it is possible to realize a transistor with a small off-current. Furthermore, the crystal structure Hafnium oxide with an amorphous structure has a higher dielectric constant compared to hafnium oxide with an amorphous structure. It is equipped with. Therefore, in order to make a transistor with a small off-current, it has a crystal structure. It is preferable to use hafnium oxide. Examples of crystal structures include monoclinic and cubic systems. Examples include the above. However, one aspect of the present invention is not limited to these.

[0157] Incidentally, the surface of hafnium oxide having a crystalline structure has interface states due to defects. This may occur. The interface level may function as a trap center. Therefore, When hafnium oxide is placed in close proximity to the channel region of a transistor, the interface levels Therefore, the electrical characteristics of the transistor may deteriorate. To reduce the influence of the interface state, To achieve this, another film is placed between the transistor's channel region and the hafnium oxide. It is sometimes preferable to separate them from each other by doing so. This membrane has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or an oxide semiconductor. It may also be a film included in the conductive film. That is, the film having a buffering function may be silicon oxide. Silicon oxide nitride, oxide semiconductors, etc., can be used. The film contains, for example, a semiconductor with a larger energy gap than the semiconductor that forms the channel region. Alternatively, an insulator may be used. Or, a film having a buffering function may have, for example, a channel region. A semiconductor or insulator with lower electron affinity than the semiconductor is used. Alternatively, a semiconductor with a buffering function is used. For example, the film may have a semiconductor with a higher ionization energy than the semiconductor that forms the channel region. Use a conductor or an insulator.

[0158] On the other hand, the interface state (trap) on the surface of hafnium oxide having the above-described crystal structure By trapping charge at the center, the threshold voltage of the transistor can be controlled. There is a combination. In order to keep the charge stable, for example, the channel region and the hafny oxide If you place an insulator with a larger energy gap than hafnium oxide between the um and the other material... Alternatively, if a semiconductor or insulator with a lower electron affinity than hafnium oxide is placed in the environment, Good. Alternatively, for films with buffering properties, a higher ionization energy than hafnium oxide is used. A semiconductor or insulator can be placed. By using such an insulator, the interface state This makes it less likely for trapped charges to be released, and allows the charge to be retained for a long period of time. can.

[0159] Examples of such insulators include silicon oxide and silicon oxide-nitride. In order to trap charge in the interface state within the insulating layer 150, the gate charge must be removed from the oxide semiconductor film. The electrons should be moved toward the polar layer 160. A specific example would be at a high temperature (for example) Under temperatures between 125°C and 450°C (typically between 150°C and 300°C), the gate electric current is used. The potential of the polar layer 160 is higher than the potential of the source electrode layer 130 and the drain electrode layer 140. You just need to maintain it for more than one second, or more typically, more than one minute.

[0160] In this way, a desired amount of electrons is trapped in the interface state such as the gate insulating layer 150. The threshold voltage shifts to the positive side. The voltage of the gate electrode layer 160, or the applied voltage... By adjusting the timing, the amount of electrons captured (the amount of variation in the threshold voltage) can be controlled. This is possible. Furthermore, if charge can be captured, within the gate insulating layer 150 It is not necessary. A laminated film with a similar structure may be used for other insulating layers.

[0161] 《Gate Entry Layer 160》 The gate electrode layer 160 may contain, for example, aluminum (Al), titanium (Ti), or chromium (C). r), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium Nium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (T) a) and conductive films such as tungsten (W) can be used. The pole layer 160 can be stacked. For example, as shown in Figure 15, gate electrode layer 16 2 may use the above material, or the gate electrode layer 161 and gate electrode layer 163 may use the above material A conductive film containing nitrogen, such as a nitride, may also be used.

[0162] Insulating layer 170 The insulating layer 170 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), and Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), i Zirconium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), HAF It can contain elements such as nium (Hf), tantalum (Ta), and titanium (Ti). For example... Aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (Si Silicon oxide (Ox), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), nitride Silicon (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaO) An insulating film containing one or more of x) can be used. Furthermore, the insulating layer 170 is a laminate of the above materials. That's fine.

[0163] The insulating layer 170 preferably contains an aluminum oxide film. The aluminum oxide film is It has a barrier effect that prevents both hydrogen, water and other impurities, as well as oxygen, from passing through the membrane. Therefore, the aluminum oxide film is used during the transistor fabrication process and during production. After manufacturing, oxidation of impurities such as hydrogen and moisture, which can cause variations in the electrical characteristics of transistors. To prevent contamination of the material semiconductor layer 121 and the oxide semiconductor layer 122, and to prevent the presence of oxides of oxygen, which are the main component material. Prevention of emission from semiconductor layer 121 and oxide semiconductor layer 122, and prevention of oxygen leakage from insulating layer 110 It is suitable for use as a protective film that has the effect of preventing the release of essential substances.

[0164] Furthermore, it is preferable that the insulating layer 170 be a film that has oxygen supply capacity. When forming the second insulating film, a mixed layer is formed, and acid is added to the mixed layer or insulating layer 110. An element is added, and through subsequent heat treatment, oxygen diffuses into the oxide semiconductor, It can replenish oxygen in the body to address oxygen deficiencies, and its transistor characteristics (e.g., threshold) It can improve things like reliability.

[0165] Furthermore, there may be other insulating layers above or below the insulating layer 170. For example, an oxidizing layer Magnesium, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, acid Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, Using an insulating film containing one or more neodymium oxide, hafnium oxide, and tantalum oxide Yes, it's possible. Oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Hafnium (H) f) It can contain tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide Aluminum (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), acid Silicon nitride (SiOxNy), silicon oxide nitride (SiNxOy), silicon nitride ( SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide Um (YOx), Zirconium Oxide (ZrOx), Lanthanum Oxide (LaOx), Neo Oxide 1 type: dm (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx) An insulating film containing the above can be used. Furthermore, even if the insulating layer 170 is made up of the above materials Good. The insulating layer 170 preferably has more oxygen than the stoichiometric composition. Oxygen released from the marginal layer passes through the gate insulating layer 150 to the channel of the oxide semiconductor layer 120. Because it can diffuse into the channel formation region, oxygen deficiencies formed in the channel formation region Oxygen can be supplied to it. Therefore, stable transistor electrical characteristics can be obtained. It is possible.

[0166] 《Insulating layer 175》 The insulating layer 175 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), and Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), i Zirconium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), HAF It can contain elements such as nium (Hf), tantalum (Ta), and titanium (Ti). For example... Magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxide nitride (Si Silicon oxide (SiNxOx), silicon nitride (SiNxOx), silicon nitride (SiNx), gallium oxide Um (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), oxide Zirconium (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), acid Hafnium oxide (HfOx) and tantalum oxide (TaOx), aluminum oxide (AlOx) An insulating film containing one or more of x) can be used. In addition, the insulating layer 175 is a laminate of the above materials. It is also preferable that the insulating layer has more oxygen than the stoichiometric composition. .

[0167] Alternatively, the insulating layer 175 may be made of a low dielectric constant material (low-k material). For example, silicon oxide (SiOF) with a few percent of fluorine (F) introduced, and silicon oxide (SiOF) with a few percent of carbon (C) introduced. Silicon oxide (SiOC), fluorinated silicate glass (FSG), organic silicate glass Lass (OSG), silsesquioxane hydrogenate (HSQ), methylsilsesquioxane (M SQ), organic polymers, polyimides, fluororesins (polytetrafluoroethylene, etc.), f It can be formed using amorphous carbon with added ions, etc. Insulating layer 175 Furthermore, by using a low-k material, the capacitance related to transistor 10 can be further reduced. It is possible.

[0168] <Transistor manufacturing method> Next, the method for manufacturing the semiconductor device of this embodiment will be described with reference to Figures 5 to 13. Note that any parts that overlap with the parts described above in the transistor configuration will be omitted. Furthermore, the A1-A2 direction shown in Figures 7 to 13 is the channel shown in Figures 1(A) and 1(B). It is sometimes referred to as the longitudinal direction. Also, the A3-A4 direction shown in Figures 7 to 13 is the same as in Figure 1(A ) and the channel width direction shown in Figure 1(C) may also be referred to as the channel width direction.

[0169] In this embodiment, each layer constituting the transistor (insulating layer, oxide semiconductor layer, conductive layer These include sputtering, chemical vapor deposition (CVD), vacuum deposition, and pulsed laser deposition. It can be formed using the PLD (Plant Loading) method. Alternatively, it can be formed by coating or printing methods. This can be done. The film deposition methods include sputtering and plasma chemical vapor deposition (PECVD). The ) method is typical, but the thermal CVD method can also be used. An example of the thermal CVD method is MOCVD (organic vapor deposition). You may also use methods such as metal chemical deposition (MLD) or ALD (atomic layer deposition).

[0170] <Thermal CVD method> Thermal CVD is a film deposition method that does not use plasma, so defects are generated by plasma damage. It has the advantage of not being affected.

[0171] Furthermore, in the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the contents of the chamber are processed By using atmospheric pressure or reduced pressure, the reaction is carried out near or on the substrate, causing the deposit to be deposited on the substrate. Film deposition may be performed.

[0172] Furthermore, thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. Various films such as metal films, semiconductor films, and inorganic insulating films can be formed, for example, In -When forming a Ga-Zn-O film, trimethylindium, trimethylgallium, And dimethylzinc can be used. The chemical formula for trimethylindium is I It is n(CH3)3. Also, the chemical formula for trimethylgallium is Ga(CH3)3. ; Also, the chemical formula of dimethylzinc is Zn(CH3)2. Further, these combinations are not limited thereto, and triethylgallium (chemical formula Ga(C2H5 )3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5 )2) can be used instead of dimethylzinc.

[0173] <ALD Method> In a film-forming apparatus using a conventional CVD method, one or more raw material gases (precursors) for the reaction are simultaneously supplied to the chamber during film formation. In a film-forming apparatus using the ALD method, the precursors for the reaction are sequentially introduced into the chamber, and film formation is performed by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of precursors are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced after the first precursor so that the multiple types of precursors do not mix, and then the second precursor is introduced. Also, instead of introducing an inert gas, after exhausting the first precursor by vacuum evacuation, the second precursor can be introduced.

[0174] Figures 5(A), (B), (C), and (D) show the film-forming process of the ALD method. The first precursor 6 01 is adsorbed on the surface of the substrate (see Figure 5(A)), and the first single layer is formed (see Figure 5(B ). At this time, metal atoms and the like contained in the precursor can bind to the hydroxyl groups present on the substrate surface. Alkyl groups such as methyl groups and ethyl groups may be bonded to the metal atoms. After exhausting the first precursor 601, the second precursor 602 introduced reacts (see Figure 5(C)), and the second single layer is laminated on the first single layer to form a thin film. (See Figure 5(D)). For example, if an oxidizing agent is included as the second precursor. A metal atom or an alkyl group bonded to a metal atom present in the first precursor, and an oxidizing agent. A chemical reaction occurs between them, forming an oxide film. Also, a second precursor If a gas containing hydrogen is used, a metal film can be formed by a reduction reaction.

[0175] The ALD method is a film deposition method based on surface chemical reactions, in which a precursor is adsorbed onto the surface to be deposited. Further formation occurs due to the action of a self-stopping mechanism. For example, trimethylaluminum The eel precursor reacts with the hydroxyl groups (OH groups) present on the surface of the film to be deposited. At this time, heat Because only surface reactions occur, the precursor comes into contact with the film surface and absorbs thermal energy. Metal atoms and the like in the precursor can be adsorbed onto the surface of the film to be deposited via this. Casa has a high vapor pressure, is thermally stable and does not self-decompose in the pre-deposition stage, and does not form on the substrate. It has characteristics such as rapid chemical adsorption. Also, since the precursor is introduced as a gas, If the precursors introduced to each other have enough time to diffuse, then high aspect Even in areas with uneven surface characteristics, a film can be formed with good coverage.

[0176] Furthermore, in the ALD method, the gas introduction sequence is controlled, and multiple passes are made until the desired thickness is achieved. By repeating the process, a thin film with excellent step coverage can be formed. The thickness of the thin film can be repeated. Because it can be adjusted by the number of times, precise film thickness adjustment is possible. Also, exhaust capacity By increasing the force, the film deposition rate can be increased, and furthermore, the impurity concentration in the film can be reduced. It is possible.

[0177] Furthermore, ALD methods include thermal ALD (thermal ALD) and plasma ALD ( There is the plasma ALD method. In the thermal ALD method, thermal energy is used to react the precursor. The plasma ALD method is a method that carries out the precursor reaction in a radical state. ru.

[0178] The ALD method allows for the precise deposition of extremely thin films. It can also be used for surface coating on surfaces with uneven surfaces. The rate is high, and the membrane density is high.

[0179] <Plasma ALD> Furthermore, by depositing films using the plasma ALD method, it is possible to achieve results that are superior to the thermal ALD method (thermal ALD method). This enables film deposition at even lower temperatures. For example, the plasma ALD method can be used even below 100°C. It is possible to deposit films without reducing the deposition rate. In addition, in the plasma ALD method, N2 is used Because radicalization can be performed by a rasma, not only oxides but also nitrides can be deposited. It is possible.

[0180] Furthermore, plasma ALD can enhance the oxidizing power of the oxidizing agent. This allows for ALD When forming a film, the precursor remains in the film, or organic compounds detached from the precursor. It can reduce the amount of carbon, chlorine, hydrogen, etc. in the membrane, thus reducing impurities. It is possible to have a film with a low concentration of substances.

[0181] Furthermore, when performing plasma ALD, radical species are generated, and ICP (Inductive) Plasma (vely coupled plasma) is kept away from the substrate. It can also generate plasma damage to the substrate or the film on which the protective film is formed. It can suppress the effect.

[0182] As described above, by using the plasma ALD method, the process temperature can be lowered and the surface coverage rate can be increased compared to other film-forming methods, and the film can be formed. This can suppress the intrusion of water and hydrogen from the outside. Therefore, the reliability of transistor characteristics can be improved.

[0183] <Description of the ALD apparatus> Fig. 6(A) shows an example of a film-forming apparatus using the ALD method. The film-forming apparatus using the ALD method includes a film-forming chamber (chamber 1701), a raw material supply section 1711a, a raw material supply section 1711b, high-speed valves 1712a and 1712b which are flow controllers, a raw material inlet 1713 a, a raw material inlet 1713b, a raw material outlet 1714, and an exhaust device 1715. The raw material inlets 1713a and 1713b installed in the chamber 1701 are connected to the raw material supply sections 1711a and 1711b respectively through supply pipes and valves, and the raw material outlet 1714 is connected to the exhaust device 1715 through a discharge pipe, a valve, and a pressure regulator.

[0184] Inside the chamber, there is a substrate holder 1716 equipped with a heater, and a film-forming substrate 1700 is placed on the substrate holder.

[0185] In the raw material supply sections 1711a and 1711b, raw material gas is formed from solid raw materials or liquid raw materials by means of vaporizers and heating means. Alternatively, the raw material supply sections 1711a and 1711b may be configured to supply gaseous raw material gas.

[0186] Although an example of providing two raw material supply sections 1711a and 1711b is shown, ​​​​​​There are no particular limitations, and three or more may be provided. Also, high-speed valve 1712a, high-speed valve 17 12b can be precisely controlled by time, supplying either the source gas or the inert gas. The configuration is as follows. High-speed valves 1712a and 1712b are flow controllers for the raw material gas. Furthermore, it can also be described as a flow controller for inert gases.

[0187] In the film deposition apparatus shown in Figure 6(A), the substrate to be deposited 1700 is loaded onto the substrate holder 1716. After sealing the chamber 1701, the substrate holder 1716 is heated by a heater to deposit the film. The substrate 1700 is heated to a desired temperature (for example, 100°C or higher or 150°C or higher), and the source gas is added. The supply of, exhaust by exhaust device 1715, supply of inert gas, and exhaust by exhaust device 1715 A thin film is formed on the substrate surface by repeatedly exhaling air.

[0188] In the film deposition apparatus shown in Figure 6(A), raw material is prepared in raw material supply section 1711a and raw material supply section 1711b. By appropriately selecting raw materials (such as volatile organometallic compounds), hafnium (Hf), A type selected from aluminum (Al), tantalum (Ta), zirconium (Zr), etc. To form an insulating layer composed of oxides (including composite oxides) containing the above elements. This can be done. Specifically, an insulating layer composed of hafnium oxide and aluminum oxide An insulating layer comprising, an insulating layer comprising hafnium silicate, or aluminum Insulating layers and the like, composed of nium silicate, can be formed. The raw materials (volatile organometallic compounds, etc.) to be prepared in the feeding section 1711a and the raw material supply section 1711b By selecting appropriately, metal layers such as tungsten layers and titanium layers, and titanium nitride layers, etc. Thin films, such as nitride layers, can also be deposited.

[0189] For example, when forming a hafnium oxide layer using a film deposition apparatus that utilizes the ALD method, the solvent and a liquid containing hafnium precursor compounds (such as hafnium alkoxide or tetrakisdimethyl A raw material gas obtained by vaporizing hafnium amides (such as amide hafnium (TDMAH)) and an acid Two types of gases, ozone (O3), are used as nitrifying agents. In this case, the raw material supply unit 1711a or The first raw material gas supplied is TDMAH, and the second raw material supplied from the raw material supply unit 1711b is TDMAH. The raw material gas is ozone. The chemical formula for tetrakisdimethylamidehafnium is Hf It is [N(CH3)2]4. Other materials include tetrakis(ethylmethylamine). Examples include hafnium. Furthermore, nitrogen has the function of eliminating charge trapping levels. Therefore, by using nitrogen as the raw material gas, a hafnium oxide film with a low charge trapping level density can be formed. It is possible.

[0190] For example, when forming an aluminum oxide layer using a film deposition apparatus that utilizes the ALD method, A raw material gas is obtained by vaporizing a liquid (such as TMA) containing a medium and an aluminum precursor compound, and oxidation Two types of gas, H2O, are used as the agent. In this case, they are supplied from the raw material supply unit 1711a. The first raw material gas is TMA, and the second raw material gas supplied from the raw material supply unit 1711b is H It becomes 2O. The chemical formula for trimethylaluminum is Al(CH3)3. Also, Other material liquids include tris(dimethylamide)aluminum and triisobutylaluminum. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) Examples include (T).

[0191] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Rolodisilane is adsorbed onto the film-forming surface, and chlorine contained in the adsorbed material is removed, causing an oxidizing gas (O2) A radical (nitrous oxide) is supplied and reacted with the adsorbed material.

[0192] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 A tungsten film is formed by simultaneously introducing gas and H2 gas. Note that B2H6 gas can be used instead. SiH4 gas may also be used.

[0193] For example, oxide semiconductor films, such as In-Ga-Zn-O, can be deposited using an ALD (Advanced Laser Deposition) system. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. An O layer is formed, and then Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gas are simultaneously introduced to form a ZnO layer. Oh, the order of these layers is not limited to this example. Also, by mixing these gases, In-Ga-O Layers of mixed compounds such as In-Zn-O layers and Ga-Zn-O layers may be formed. Alternatively, you can use H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas. However, it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas... In (C2H5)3 gas may be used instead. Alternatively, G may be used instead of Ga (CH3)3 gas. a(C2H5)3 gas may be used. Alternatively, Zn(CH3)2 gas may be used.

[0194] Multi-chamber film deposition system Furthermore, a multi-chamber manufacturing apparatus having at least one film deposition apparatus as shown in Figure 6(A) An example is shown in Figure 6(B).

[0195] The manufacturing apparatus shown in Figure 6(B) can continuously deposit laminated films without exposure to the atmosphere. This aims to prevent the inclusion of impurities and improve throughput.

[0196] The manufacturing apparatus shown in Figure 6(B) consists of a loading chamber 1702, a conveying chamber 1720, a pre-processing chamber 1703, It has at least a deposition chamber 1701 and an unloading chamber 1706. The chambers of the manufacturing equipment (including the loading chamber, processing chamber, transport chamber, film deposition chamber, unloading chamber, etc.) To prevent moisture from adhering, etc., an inert gas (such as nitrogen gas) with a controlled dew point is filled in. It is preferable to leave it as is, and preferably maintain reduced pressure.

[0197] Furthermore, chambers 1704 and 1705 utilize the same ALD method as chamber 1701. It may be a film deposition apparatus, or a film deposition apparatus that utilizes plasma CVD, or spa It may be a film deposition apparatus utilizing the taring method, or a metal-organic vapor deposition (MOCVD) apparatus. The tal Organic Chemical Vapor Deposition method It may also be used as a film deposition apparatus.

[0198] For example, Chamber 1704 is a film deposition apparatus that utilizes the plasma CVD method, The following is an example of a film deposition apparatus using the MOCVD method, designated as -1705, for the deposition of a multilayer film. show.

[0199] Figure 6(B) shows an example where the top view of the transport chamber 1720 is hexagonal, but depending on the number of layers of the laminated film... Furthermore, it may be used as a manufacturing apparatus with even more polygons, connected to a larger number of chambers. Furthermore, although the top surface shape of the substrate is shown as a rectangle in Figure 6(B), it is not particularly limited. Although Figure 6(B) shows an example of a single-wafer deposition process, there is also a batch deposition process where multiple substrates are deposited at once. It can also be used as a device.

[0200] <Formation of insulating layer 110> First, an insulating layer 110 is deposited on the substrate 100. The insulating layer 110 is deposited using plasma CVD, thermal By CVD (MOCVD, ALD) or sputtering, for example, aluminum oxide nium, magnesium oxide, silicon oxide, silicon nitride oxide, gallium oxide, gel oxide Manium, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hazel oxide Oxide insulating films such as nitrium and tantalum oxide, silicon nitride, silicon oxide nitride, nitrogen Aluminum oxide, aluminum nitride, or other nitride insulating films, or mixtures thereof It can be formed using the above materials. Alternatively, it may be a laminate of the above materials, and at least after acid The upper layer of the stack that is in contact with the first oxide semiconductor film which becomes the oxide semiconductor layer 121 is the oxide semiconductor layer 1 It is preferable to form it with a material that contains excess oxygen, which can serve as a source of oxygen for 22.

[0201] For example, silicon oxide nitride with a thickness of 100 nm can be used as the insulating layer 110 by plasma CVD. A membrane can be used.

[0202] Next, a heat treatment may be performed to remove water, hydrogen, etc. contained in the insulating layer 110. As a result, it is possible to reduce the concentration of water, hydrogen, etc. contained in the insulating layer 110, and heat treatment This reduces the amount of water, hydrogen, etc., that diffuses into the first oxide semiconductor film that is formed later. It is possible.

[0203] <Formation of the first oxide semiconductor film and the second oxide semiconductor film> Next, a first oxide semiconductor film, which will later become the oxide semiconductor layer 121, is placed on the insulating layer 110, and then A second oxide semiconductor film, which will become the oxide semiconductor layer 122, is formed. The second oxide semiconductor film is formed by methods such as sputtering, MOCVD, or PLD. This can be done, and it is more preferable to form it using the sputtering method. As for the sputtering method, RF sputtering Sputtering, DC sputtering, AC sputtering, etc. can be used. In this context, opposing target method (opposing electrode method, vapor phase sputtering method, VDSP (Vapo Formed by the Deposition Spattering method. This reduces plasma damage during film deposition.

[0204] For example, when forming a first oxide semiconductor film by sputtering, in the sputtering apparatus Each chamber is designed to remove as much water and other impurities as possible from the oxide semiconductor. High vacuum is achieved using an adsorption-type vacuum pump such as an IO pump (5 × 10 -7 Pa~1 ×10 -4 It is possible to achieve temperatures up to approximately Pa, and the substrate to which the film is deposited should be heated to 100°C or higher, preferably. It is preferable that it can be heated to 400°C or higher. Alternatively, a turbomolecular pump and a cold turbo... By combining the parts, the exhaust system prevents gases containing carbon components and moisture from flowing back into the chamber. It is preferable to do so. Also, combining a turbomolecular pump and a cryopump A different exhaust system may be used.

[0205] To obtain high-purity intrinsic oxide semiconductors, not only is the chamber evacuated to a high vacuum, but spa It is also necessary to increase the purity of the sputtering gas. The oxygen gas and argon gas used as sputtering gas are The dew point is -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. By using highly purified gas, the amount of moisture and other substances incorporated into the oxide semiconductor film can be minimized. It can be prevented.

[0206] Sputtering gases include noble gases (typically argon), oxygen, and mixtures of noble gases and oxygen. Use the appropriate gas. In the case of a mixture of noble gas and oxygen, the oxygen gas should be used relative to the noble gas. It is preferable to increase the S ratio.

[0207] Furthermore, when forming an oxide semiconductor film, for example, using the sputtering method, the substrate temperature The temperature is 150°C to 750°C, preferably 150°C to 450°C, and more preferably By depositing an oxide semiconductor film at a temperature between 200°C and 420°C, CAAC-OS is produced. It can form a film.

[0208] The first oxide semiconductor film is constructed such that its electron affinity is lower than that of the second oxide semiconductor film. You can choose the price.

[0209] Furthermore, the second oxide semiconductor film is more efficient than the first oxide semiconductor film and the third oxide semiconductor film. It may have a high s-orbital content. In oxide semiconductors, the s-orbitals of heavy metals are mainly capsulated. It contributes to rear conduction, and by increasing the In content, more s orbitals overlap. Therefore, oxides in which In is more abundant than Ga have a composition in which In is equal to or less abundant than Ga. Compared to other oxides, it has higher mobility. Therefore, indium oxide semiconductor layer 122 By using oxides with a high content of [the substance], it is possible to realize transistors with high mobility. ru.

[0210] Furthermore, in the first oxide semiconductor film and the second oxide semiconductor film, for example, by sputtering When forming a film, a multi-chamber sputtering system is used to form the first oxide semiconductor The film and the second oxide semiconductor film can be continuously deposited without exposure to the atmosphere. In total, extraneous impurities get trapped at the interface between the first oxide semiconductor film and the second oxide semiconductor film. This can suppress the process and reduce the number of interface states. As a result, The electrical characteristics of the zista can be stabilized, particularly in reliability testing.

[0211] Furthermore, in the first oxide semiconductor film to which oxygen is added, during the addition of oxygen, If there is damage, the oxide semiconductor layer 122 becomes the main conductive path. This allows the oxide semiconductor layer 123 to be moved away from the damaged area, and as a result the transistor It can stabilize the electrical characteristics, particularly in reliability testing.

[0212] For example, as the first oxide semiconductor film, In:Ga:Zn=1 is obtained by sputtering. Using a 3:4 (atomic ratio) target, an oxide semiconductor film with a thickness of 20 nm was deposited. It is possible to produce a second oxide semiconductor film by sputtering. A 15 nm thick oxide film was deposited using a Ga:Zn=1:1:1 (atomic ratio) target. A semiconductor film can be used.

[0213] Furthermore, the second acid is formed by heat treatment after the formation of the first oxide semiconductor film and the second oxide semiconductor film. This can reduce the amount of oxygen vacancy in the ionized semiconductor film.

[0214] Next, a first heat treatment is performed to transfer some of the oxygen to the second oxide semiconductor film, and the second This can reduce oxygen vacancies in oxide semiconductor films. The second oxidation with reduced oxygen vacancies... The first oxide semiconductor film is made into a second oxide semiconductor film. Also, at this time, the acid of the first oxide semiconductor film The number of defects can also be reduced. In addition, the first heat treatment adds oxygen to the first Hydrogen, water, etc. contained in the oxide semiconductor film and the second oxide semiconductor film can be removed. This results in the first oxide semiconductor film and the second oxide semiconductor film with added oxygen. The amount of impurities can be reduced.

[0215] The temperature of the first heat treatment is 250°C or higher and below the substrate strain point, preferably 300°C or higher and 650°C. The temperature should be below ℃, and more preferably between 350℃ and 550℃.

[0216] The first heat treatment involves using noble gases such as helium, neon, argon, xenon, and krypton, Alternatively, the process may be carried out in an inert gas atmosphere containing nitrogen. Or, after heating in an inert gas atmosphere, oxygen Atmosphere or dry air (with a dew point of -80°C or lower, preferably -100°C or lower, preferably - Heating may be performed in an air atmosphere below 120°C, or under reduced pressure. In addition to the dry air mentioned above, it is preferable that the inert gas and oxygen gas do not contain hydrogen, water, etc. In particular, the dew point is preferably -80°C or lower, and more preferably -100°C or lower. Processing time will range from 3 minutes to 24 hours.

[0217] Furthermore, in the first heat treatment, instead of an electric furnace, heat transfer from a heat source such as a resistance heating element is used. A device that heats the object to be processed by conduction or thermal radiation may be used. For example, GRTA( Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Ra RTA (Rapid Thermal Anneal) devices, etc. Anneal) equipment can be used. LRTA equipment uses halogen lamps and metal Halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps The light (electromagnetic waves) emitted from lamps such as high-pressure mercury lamps heats the object being processed. The GRTA apparatus is a device that performs a first heat treatment using high-temperature gas. For high-temperature gases, noble gases such as argon, or inert gases such as nitrogen, are used. .

[0218] The first heat treatment forms oxide semiconductor layer 121 and oxide semiconductor layer 122, which will be described later. It can be done after etching.

[0219] For example, after heat treatment at 450°C for 1 hour in a nitrogen atmosphere, then in an oxygen atmosphere... It can then be subjected to a heat treatment at 450°C for 1 hour.

[0220] Through the above process, oxygen vacancies in the oxide semiconductor film are reduced, as well as impurities such as hydrogen and water. It is possible to form an oxide semiconductor film with reduced localized energy level density. Cut.

[0221] <Formation of the first conductive film> Next, the first source electrode layer 130 and drain electrode layer 140 are formed on the oxide semiconductor layer 123. A conductive film is formed. The first conductive film is formed by sputtering, chemical vapor deposition (CVD) ( Metallic organochemical deposition (MOCVD), metal chemical vapor deposition, atomic layer deposition (ALD) This includes plasma chemical vapor deposition (PECVD), evaporation methods, and pulsed laser deposition. It can be formed using methods such as the (PLD) method.

[0222] The material for the first conductive film is copper (Cu), tungsten (W), molybdenum (Mo), and gold (A). u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt ( Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S) A conductive material consisting of the material r), an alloy, or a compound having these materials as its main component. It is preferable to have a single layer or stacked film. For example, when stacked, the oxide semiconductor layer 1 The lower conductive layer in contact with 22 has a material that readily bonds with oxygen, and the upper conductive layer has an oxidation-resistant material. It is possible to have a material with strong properties. In addition, tungsten (W) can achieve both heat resistance and conductivity. It is preferable to use high-melting-point materials such as aluminum or molybdenum (Mo). It is preferable to form it with a low-resistance conductive material such as (Al) or copper (Cu). Furthermore, Cu -When a Mn alloy is used, a film containing manganese oxide is formed at the interface with an oxygen-containing insulator, and acid Manganese oxide is preferable because it has the function of suppressing the diffusion of Cu.

[0223] For example, a tungsten film with a thickness of 20 to 100 nm is subjected to a first conductive process by sputtering. It can be formed as a membrane.

[0224] Furthermore, the conductive layer 130b, which is formed by processing the first conductive film in a later step, is in this subsequent step In this case, it has the function of a hard mask, as well as the functions of a source electrode layer and a drain electrode layer. This eliminates the need for additional film deposition steps, thus shortening the semiconductor manufacturing process. .

[0225] <Formation of oxide semiconductor layer 121 and oxide semiconductor layer 122> Next, a resist mask is formed by a lithography process, and using this resist mask, The first conductive film is selectively etched to form a conductive layer 130b. Subsequently, the conductive layer 13 After removing the resist on 0b, the conductive layer 130b is used as a hard mask for the second oxide semiconductor. The film and the first oxide semiconductor film are selectively etched, and the oxide semiconductor layer 122 and acid The ionized semiconductor layer 121 can be formed in an island-like manner (see Figure 7). Note that the etching method Dry etching can be used as a method. Furthermore, the conductive layer 130b is hardened. By using it as a mask and etching the oxide semiconductor layer, the etching process is more efficient compared to a resist mask. This can reduce the edge roughness of the oxide semiconductor layer after chipping.

[0226] For example, methane gas and argon gas are used as etching gases, and the resist mask and The first oxide semiconductor film and the second oxide semiconductor film are selectively etched using a hard mask. By doing so, oxide semiconductor layer 121 and oxide semiconductor layer 122 can be formed. ru.

[0227] <Deposition of the second insulating film> Next, a second insulating film is formed on the insulating layer 110 and the conductive layer 130b.

[0228] The second and third insulating films are produced by plasma CVD, thermal CVD (MOCVD, ALD) By methods such as the (method) or sputtering method, for example, aluminum oxide (SiOx), magnesium oxide Cium (MgOx), silicon oxide (SiOx), silicon oxide nitride (SiOxNy), Gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx) ), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdO x) Oxide insulating films such as hafnium oxide (HfOx) and tantalum oxide (TaOx). Silicon nitride (SiNx), silicon oxide nitride (SiNxOy), aluminum nitride ( Nitride insulating films such as AlNx, aluminum nitride oxide (AlNxOy), or these It can be formed using a mixture of materials. Alternatively, it may be formed by laminating the above materials.

[0229] Furthermore, as the second insulating film, an aluminum oxide film is formed by sputtering. This is desirable. Also, using aluminum oxide as a target for sputtering is preferable. This is desirable. Furthermore, it is desirable to have oxygen gas as the gas used during film formation.

[0230] When the aluminum oxide film is formed, a mixed layer 171 is formed at the interface with the insulating layer 110. ru.

[0231] For example, the oxygen gas used during the deposition of the second insulating film is applied during the deposition by the sputtering method. Due to the influence of the applied voltage, power, plasma, substrate temperature, etc., oxygen radicals, oxygen ions, Oxygen atoms and other elements exist in various states, and some states have higher energy levels compared to their stable states. At this time, oxygen (excess oxygen, called exO) 172 is mixed into the insulating layer 110, or It is added to layer 171 (see Figure 8).

[0232] Next, a second heat treatment may be performed. Typically, the second heat treatment is performed at a temperature of 150°C or higher. Below the plate strain point, preferably 250°C to 500°C, more preferably 300°C to 45°C The temperature can be set to 0°C or below. This heat treatment is performed on the insulating layer 110 and the mixed layer. The oxygen 172 diffuses and moves to the oxide semiconductor layer 122, and within the oxide semiconductor layer 122 It can replenish oxygen to compensate for existing oxygen deficiencies (see Figure 9).

[0233] For example, using the sputtering method, with an aluminum oxide (AlOx) target, A second insulating film is formed by incorporating 50% by volume of oxygen gas as the gas used during sputtering. This can be done. The thickness can be 20 nm to 40 nm. Also, a second heating treatment In theory, it can be treated at 400°C for 1 hour under an oxygen atmosphere.

[0234] <Oxygen addition> Furthermore, in fabricating transistor 10, the above method is not the only option, and the addition of oxygen may also be used. This may be done separately. The oxygen addition process may be performed on the insulating layer 110, or the first This may also be performed on an oxide semiconductor film, or a third oxide semiconductor film 123a described later. The oxygen can be an oxygen radical, an oxygen atom, an oxygen atom ion, or an oxygen molecular ion. Use one or more units. Methods for adding oxygen include ion doping and ion implantation. Methods include plasma immersion ion implantation, etc.

[0235] Furthermore, when using ion implantation as a method for adding oxygen, even if oxygen atomic ions are used... Yes, or you may use oxygen molecular ions. When oxygen molecular ions are used, the added film will Damage can be reduced. Oxygen molecular ions are added to the film surface to which the oxygen is added. It is separated and added as oxygen atom ions. Because energy is used, when oxygen molecular ions are added to the membrane to which the oxygen is added The energy per oxygen atom ion in is the energy of the oxygen atom ion when the oxygen is added. The effect is lower compared to when added to a membrane. Therefore, it reduces damage to the membrane to which the oxygen is added. It can be reduced.

[0236] Furthermore, when implanting oxygen molecular ions, compared to when implanting oxygen atomic ions, the acid The energy per elementary atom ion is low. Therefore, it is implanted using oxygen molecular ions. This makes it possible to increase the acceleration voltage and thus increase throughput. Furthermore, by using oxygen molecular ions for implantation, compared to the case using oxygen atomic ions, It is possible to halve the dose required to add the same amount of oxygen atoms and ions. As a result, it is possible to increase the throughput of the manufacturing process.

[0237] Furthermore, when adding oxygen to the membrane to which the oxygen is added, the oxygen source in the membrane to which the oxygen is added Using conditions such that the peak of the concentration profile of the child ions is located, the oxygen is added. It is preferable to add oxygen to the membrane. As a result, compared to when oxygen atomic ions are implanted... In general, this reduces the acceleration voltage during injection, thereby reducing damage to the membrane to which the oxygen is added. It is possible to do so. That is, the amount of defects in the membrane to which the oxygen is added can be reduced. It is possible to suppress fluctuations in the electrical characteristics of the transistor. As a result, when the oxygen is added... This reduces damage to the film being treated and suppresses fluctuations in the transistor's electrical characteristics. It can be controlled.

[0238] Furthermore, a plasma is generated in an oxygen-containing atmosphere, and the film to which the oxygen is added is exposed to the plasma. By plasma immersion ion implantation, oxygen is added to the film to which the oxygen is added. This is also acceptable. As an oxygen-containing atmosphere, oxygen, ozone, nitrous oxide, nitrogen dioxide, and other acids are also acceptable. There is an atmosphere containing chemical gases. This occurs when a bias is applied to the substrate 100 side. By exposing the film to which the oxygen is added to the plasma, the oxygen is added to the film. It is possible and preferable to increase the amount added. An example of a device for performing such plasma processing. One example is the ashing device.

[0239] For example, if the acceleration voltage is 5kV and the dose is 1 × 10⁻¹⁰ 16 / cm 2 The oxygen molecular ions It can be added to the first oxide semiconductor film by on-implantation.

[0240] By combining the above steps and subsequent heat treatment, the oxide semiconductor layer 122 is processed as follows: The amount of oxygen deficiency can be reduced. Note that the membrane with added oxygen is different from the membrane before oxygen was added. Compared to the other membrane, the membrane density is lower.

[0241] <Deposition of the third insulating film> Next, a third insulating film is deposited on the second insulating film. The third insulating film is deposited by plasma CVD. Thermal CVD (MOCVD, ALD), sputtering, or spin coating methods, etc. For example, aluminum oxide (SiOx), magnesium oxide (MgOx), and sulfite oxide. Silicon oxide (SiOx), silicon nitride (SiOxNy), gallium oxide (GaOx), Germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (Zr Ox), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (Hf Ox) and oxide insulating films such as tantalum oxide (TaOx), silicon nitride (SiNx) Silicon nitride (SiNxOy), aluminum nitride (AlNx), aluminum nitride Formed using nitride insulating films such as nium (AlNxOy), or mixtures thereof. This is possible. Alternatively, the above materials may be laminated.

[0242] Alternatively, the third insulating film may be made of a low-dielectric constant material (low-k material). For example, silicon oxide (SiOF) with a few percent of fluorine (F) introduced, and silicon oxide (SiOF) with a few percent of carbon (C) introduced. Silicon oxide (SiOC), fluorinated silicate glass (FSG), organic silicate glass Lass (OSG), silsesquioxane hydrogenate (HSQ), methylsilsesquioxane (M SQ), organic polymers, fluororesins (polytetrafluoroethylene), polyimide, fluorine It can be formed using amorphous carbon with added elements, etc.

[0243] The second heat treatment may be performed after the formation of the third insulating film.

[0244] <Planarization of the third insulating film> Next, the third insulating film is planarized to form the insulating layer 175b. The planarization process is C MP (Chemical Mechanical Polishing) method, dry edge This can be done using methods such as the chipping method and the reflow method. Alternatively, flattening can be performed using the CMP method. In this case, by introducing a film with a different composition from the third insulating film on the third insulating film, C The thickness of the insulating layer 175 on the substrate surface after MP processing can be made uniform.

[0245] The second heat treatment may be performed after the third insulating film has been planarized.

[0246] <Formation of grooves, and formation of source electrode layer 130 and gate insulating layer 150> Next, a resist mask 176 is formed on the insulating layer 175b by a lithography process (Figure (See 10). Note that the organic film is applied to the insulating layer 175b, or on the resist. The lithography process may be performed after coating with an organic film. The organic film may contain propylene glycol. It contains methyl monomethyl ether, ethyl lactate, etc., and has an anti-reflective coating (BA) during exposure. Function as RC (Bottom Anti-reflective Coating) In addition to having these properties, it also has effects such as improving the adhesion between the resist and the film, and improving resolution. can.

[0247] Furthermore, when forming transistors with extremely short channel lengths, at least the source electrode layer 130, in the region that divides the conductive layer 130b which becomes the drain electrode layer 140, electron beam Resist mask processing using methods suitable for fine line processing, such as immersion lithography, EUV lithography, etc. The process involves performing the following steps, and then etching the area using an etching process. When forming a resist mask with light, a positive-type resist is used as the resist mask. If this is the case, the exposure area can be minimized, and throughput can be improved. Using this method, the channel length can be reduced to 100 nm or less, and even to 30 nm or less. Transistors can be formed. Or, extremely short wavelength light (e.g., extreme ultraviolet light) Exposure techniques using (EUV: Extreme Ultraviolet) and X-rays, etc. Fine processing may be performed using techniques.

[0248] Using the resist mask, grooves are machined into the insulating layer 175b by dry etching. The process is carried out. By selectively proceeding with the etching process, grooves 174 are formed in the insulating layer 175. ru.

[0249] Next, the exposed conductive layer 130b is selectively etched in a way that breaks it apart, and the source electrode layer 1 30. A drain electrode layer 140 can be formed (see Figure 11).

[0250] After forming the source electrode layer 130 and the drain electrode layer 140, the etching residue is removed. Therefore, a cleaning process may be performed. By performing this cleaning process, the source electrode layer 130, Short circuits in the drain electrode layer 140 can be suppressed. This cleaning process is performed using TMAH(Te Alkaline solutions such as tramethylammonium hydroxyl solution This can be done using acidic solutions such as hydrofluoric acid, diluted hydrofluoric acid, oxalic acid, or phosphoric acid. Oh, due to the cleaning process, a part of the oxide semiconductor layer 122 is etched, and the oxide semiconductor layer 1 A recess is formed in 22.

[0251] Note that the oxide semiconductor layer 121, oxide semiconductor layer 122, source electrode layer 130, drain electrode The formation sequence of the polar layer 140 can be changed. For example, the source electrode layer 130 First, a groove 174 for forming a drain electrode is provided, and then the oxide semiconductor layer 121, An oxide semiconductor layer 122 may be formed.

[0252] For example, after planarizing the silicon oxidnitride film formed as the second insulating film, the silicon oxidnitride film A resist mask is formed on a film, and the resist mask is used with a gas containing carbon and fluorine. By dry etching using the above, the silicon oxidizride is opened, and chlorine, By dry etching the conductive layer 130b using a fluorine-based gas, the source electrode Layer 130 and drain electrode layer 140 can be formed.

[0253] <Formation of the third oxide semiconductor film 123a> Next, an oxide semiconductor layer 123 is used on the oxide semiconductor layer 122 and the insulating layer 175. A third oxide semiconductor film 123a is formed. The third oxide semiconductor film 123a is formed by the first acid It can be formed in the same manner as oxide semiconductor films, and the third oxide semiconductor film 123a is the The material can be selected such that its electron affinity is lower than that of the oxide semiconductor film in example 2.

[0254] For example, as a third oxide semiconductor film 123a, In:Ga: Oxide semiconductor film with a thickness of 5 nm deposited using a Zn=1:3:2 (atomic ratio) target. You can use it.

[0255] <Formation of insulating film 150a> Next, a fourth insulating film 150a, which will become the gate insulating layer 150, is formed on the oxide semiconductor film 123a. The fourth insulating film 150a contains, for example, aluminum oxide (AlOx) and magnesium oxide. Nesium (MgOx), silicon oxide (SiOx), silicon oxide nitride (SiOxNy) silicon nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The like can be used. The fourth insulating film 150a is a laminate of the above materials. The fourth insulating film 150a can be made by sputtering, CVD (plasma CVD, MOCV). It can be formed using methods such as the D method, ALD method, and MBE method. The edge film 150a can be formed by using an insulating film in the same manner as the insulating layer 110. .

[0256] For example, silicon oxidiznitride is used as the fourth insulating film 150a by plasma CVD for 10n m can be formed.

[0257] <Formation of conductive film 160a> Next, a second conductive film 160a, which will become the gate electrode layer 160, is deposited on the fourth insulating film 150a. (See Figure 12). The second conductive film 160a can be, for example, aluminum (Al) Titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu) Yttrium (Y), Zirconium (Zr), Molybdenum (Mo), Ruthenium (Ru) ), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), Alternatively, alloy materials having these as their main components can be used. The second conductive film 160a is Sputtering method, CVD method (plasma CVD, MOCVD, ALD, etc.), MBE method, It can be formed by vapor deposition, plating, etc. Also, as the second conductive film 160a A conductive film containing nitrogen may be used, and a laminate of the above conductive film and a conductive film containing nitrogen may be used. This is also acceptable. Furthermore, the second conductive film 160a may be a single layer or a multilayer.

[0258] For example, in conductive film 160a, titanium nitride is 10 nm thick and tungsten is molten using the ALD method. A 150 nm layered structure can be created using the CVD method.

[0259] <Plating process> Next, a planarization process is performed. This planarization process is carried out using methods such as CMP or dry etching. This can be done. The planarization process may be terminated when the third insulating film 150a is exposed. The process may be terminated when the third oxide semiconductor film 123a is exposed, or when the insulating layer 175 is exposed. The process may be terminated once the material is exposed. This results in the gate electrode layer 160 and the gate insulating layer 150. This allows for the formation of an oxide semiconductor layer 123 (see Figure 13).

[0260] Furthermore, an oxide semiconductor film 123a or an insulating film 150a is placed on the flattened insulating layer 175. If available, processing may be carried out using a new resist mask. Oxide semiconductor film 1 A resist mask is formed on 23a or the insulating film 150a by a lithography process. The mask has a larger area than the upper surface of the gate electrode layer 160, and the mask has The insulating film 150a and the oxide semiconductor film 123a are selectively etched, and the gate insulating layer is formed. 150, an oxide semiconductor layer 123 can be formed.

[0261] In transistor 10, an oxide semiconductor layer 123 is provided that is less prone to oxygen vacancies. This suppresses the desorption of oxygen from the side surface of the oxide semiconductor layer 123 in the channel width direction. This suppresses the generation of oxygen deficiency. As a result, electrical characteristics are improved, and reliability is enhanced. This enables the creation of high-performance transistors.

[0262] Next, a third heat treatment may be performed. This heat treatment typically involves heating the substrate to 150°C or higher. Below the strain point, preferably 250°C to 500°C, more preferably 300°C to 450°C The temperature can be set to below °C. This heat treatment adds to the insulating layer (e.g., insulating layer 175). The oxygen diffuses and moves to the oxide semiconductor layer 122, and is present in the oxide semiconductor layer 122. It can replenish oxygen in cases of oxygen deficiency.

[0263] For example, a heat treatment can be performed at 400°C for 1 hour under an oxygen atmosphere.

[0264] Through the above process, the localized energy level density of the oxide semiconductor film is reduced, resulting in a film with excellent electrical properties. It is possible to fabricate transistors. Furthermore, the electrical characteristics can be measured through aging and stress testing. This allows for the fabrication of highly reliable transistors with minimal fluctuations.

[0265] <Variation 1 of transistor 10: Transistor 11> Regarding transistor 11, which has a different shape from transistor 10 shown in Figure 1, use Figure 14. explain.

[0266] Figures 14(A), 14(B), and 14(C) show the top view and cross-sectional view of transistor 11. Figure 14(A) is a top view of transistor 11, and Figure 14(B) is a top view of transistor 11. The dashed line in Figure 14(C) shows a cross-section between A1 and A2, and Figure 14(C) shows a cross-section between A3 and A4.

[0267] The transistor 11 has an oxide semiconductor layer 121 and an oxide semiconductor layer 122 with side surfaces (channel region) (Excluding the region), the sides of the source electrode layer 130, the drain electrode layer 140, and the sides of the insulating layer 110 Furthermore, the transistor 10 has a conductive layer 135 that is in contact with the upper surface and the lower surface of the insulating layer 170. This differs from the previous example. The conductive layer 135 has a sidewall shape as shown in Figure 14(B).

[0268] Conductive layer 135 The conductive layer 135 contains copper (Cu), tungsten (W), molybdenum (Mo), and gold (Au). Aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel Ni (nickel), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co ), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) A single element or alloy made of these materials, or an element mainly composed of oxygen, nitrogen, fluorine, It is preferable to have a single layer or a stack of conductive layers containing compounds such as silicon. When stacked, the lower conductive layer in contact with the oxide semiconductor layer 122 readily bonds with oxygen. The material has a conductive upper layer which can have a highly oxidation-resistant material. It is preferable to use high-melting-point materials such as tungsten or molybdenum that are both conductive and suitable for both properties. Furthermore, it is preferable to form it from a low-resistance conductive material such as aluminum or copper. When using a Cu-Mn alloy, manganese oxide is formed at the interface with the oxygen-containing insulator, and It is preferable because it has the function of suppressing the diffusion of Cu.

[0269] By having a conductive layer 135, it is in contact with the oxide semiconductor layer 121 and the oxide semiconductor layer 122. The area of ​​the conductive layer can be increased, thereby increasing the on-current.

[0270] <Variation 2 of transistor 10: transistor 12> Regarding transistor 12, which has a different shape from transistor 10 shown in Figure 1, see Figures 15 and 1. I will explain using number 6.

[0271] Figures 15(A), 15(B), and 15(C) show the top view and cross-sectional view of transistor 12. Figure 15(A) is a top view of transistor 12, and Figure 15(B) is a top view of transistor 12. The dashed line shows the section between A1 and A2, and Figure 15(C) shows the section between A3 and A4.

[0272] The transistor 12 has a conductive layer 165 below the insulating layer 110, an insulating layer 175, and an oxide semiconductor layer. The device has a body layer 123, a gate insulating layer 150, and an insulating layer 177 on the upper surface of the gate electrode layer 160. In this respect, it differs from transistor 10.

[0273] 《Conductive layer 165》 The conductive layer 165 can function as a bottom gate. The electrode layer 160 can be given the same potential, or a different potential. The conductive layer 165 contains, for example, copper (Cu), tungsten (W), molybdenum (Mo), and gold. (Au), Aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum (Ta ), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt Co (Toxin), Ruthenium (Ru), Platinum (Pt), Iridium (Ir), Strontium (Sr) element, alloy, or a substance consisting mainly of these materials, oxygen, nitrogen, It is preferable to have a single or multilayer conductive layer containing compounds such as fluorine and silicon. For example, the conductive layer 166 can have a material with strong oxidation resistance. For component 67, high-melting-point materials such as tungsten and molybdenum are used, which offer both heat resistance and conductivity. It is preferable that it be formed from a low-resistance conductive material such as aluminum or copper. It's nice.

[0274] 《Insulating layer 177》 The insulating layer 177 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), and Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), i Zirconium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), HAF It can contain elements such as nium (Hf), tantalum (Ta), and titanium (Ti). For example... Aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (Si Silicon oxide (Ox), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), nitride Silicon (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaO) An insulating film containing one or more of x) can be used. In addition, the insulating layer 177 is a laminate of the above materials. That's fine.

[0275] The insulating layer 177 preferably contains an aluminum oxide film. The aluminum oxide film is It has a barrier effect that prevents both hydrogen, water and other impurities, as well as oxygen, from passing through the membrane. Therefore, the aluminum oxide film is used during the transistor fabrication process and during production. After manufacturing, oxidation of impurities such as hydrogen and moisture, which can cause variations in the electrical characteristics of transistors. To prevent contamination of the material semiconductor layer 121 and the oxide semiconductor layer 122, and to prevent the presence of oxides of oxygen, which are the main component material. Prevention of emission from semiconductor layer 121 and oxide semiconductor layer 122, and prevention of oxygen leakage from insulating layer 175 It is suitable for use as a protective film that has the effect of preventing the release of essential substances.

[0276] Furthermore, it is preferable that the insulating layer 177 be a film having oxygen supply capacity. For example, insulating layer It is preferable to deposit 177 by sputtering. When the insulating layer 177 is deposited A mixed layer is formed at the interface with the insulating layer 175, and oxygen 17 is present in the mixed layer or the insulating layer 175. 2 can be added.

[0277] The transistor 12 can undergo a third heat treatment after the insulating layer 177 has been formed. The heat treatment in step 3 is typically performed at a temperature of 150°C or higher but below the substrate strain point, preferably 250°C or higher. The temperature can be below 00°C, more preferably between 300°C and 450°C. Third heating During processing, the additive that was added to the insulating layer 175 diffused into the oxide semiconductor layer 121, and the oxide semiconductor It moves to layer 122 and replenishes oxygen vacancies present in the oxide semiconductor layer 122 with oxygen. It is possible.

[0278] Furthermore, the third heat treatment can also serve as the second heat treatment. This allows the insulating layer 1 10. Oxygen 172 added to the insulating layer 175, gate insulating layer 150, oxide semiconductor layer 1 23. It moves to the oxide semiconductor layer 122 via the oxide semiconductor layer 121, etc. Oxygen can be replenished in oxygen deficiencies present in the conductive layer 122 (see Figure 16). .

[0279] This improves the transistor characteristics of transistor 12 (e.g., threshold, reliability, etc.). It can be made to happen.

[0280] Furthermore, as shown in Figure 17, transistor 12 has a structure in which transistors are arranged in parallel ( It can be a transistor 13) (see Figure 17). Furthermore, transistor 13 is as shown in Figure As shown in 18, an insulating layer 180 is placed on the insulating layer 170, and a conductive layer 1 is placed on the gate electrode layer 160. It has 90 (conductive layer 191, conductive layer 192), and the gate electrode layer 160 and the conductive layer 190 are electrically It can have a structure that is electrically connected.

[0281] Furthermore, the insulating layer 180 can be formed from the same material as the insulating layer 175. Layer 190 can be formed from the same material as the gate electrode layer 160.

[0282] Transistor 13 can increase the on-current while exhibiting good transistor characteristics. ru.

[0283] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0284] (Embodiment 2) In this embodiment, a transistor with a different structure from the transistor 10 described in Embodiment 1 is used. The method for fabricating sta 14 and transistor 14 will be described.

[0285] <Transistor 14> Figures 19(A), 19(B), and 19(C) show the upper part of a transistor 14 according to one embodiment of the present invention. These are a top view and a cross-sectional view. Figure 19(A) is a top view, and Figure 19(B) is a cross-sectional view of Figure 19(A). Figure 19(C) is a cross-sectional view between the dashed lines A1 and A2, and between the dashed lines A3 and A4 in Figure 19(A). Yes. Also, in Figure 19(A), some elements have been enlarged, reduced, or omitted for clarity. The diagram is abbreviated. Also, the direction of the dashed line A1-A2 is the channel length direction, and the direction of the dashed line A3- The A4 direction is sometimes referred to as the channel width direction.

[0286] As shown in Figures 19(A), 19(B), and 19(C), the transistor 14 has a groove 17 In 4, the source electrode layer 130 and the drain electrode layer 140 have an insulating layer 185 on their upper surfaces. This is where it differs from transistor 10. The insulating layer 185 is made up of insulating layer 170 and insulating layer 175 It is in contact with the side surface and has an oxide semiconductor layer 123 above the insulating layer 185.

[0287] 《Insulating layer 185》 The insulating layer 185 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), and Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), i Zirconium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), HAF It can contain elements such as nium (Hf), tantalum (Ta), and titanium (Ti). For example... Magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxide nitride (Si Silicon oxide (SiNxOx), silicon nitride (SiNxOx), silicon nitride (SiNx), gallium oxide Um (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), oxide Zirconium (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), acid Hafnium oxide (HfOx) and tantalum oxide (TaOx), aluminum oxide (AlOx) An insulating film containing one or more of x) can be used. In addition, the insulating layer 185 is a laminate of the above materials. It is also preferable that the insulating layer has more oxygen than the stoichiometric composition. .

[0288] Alternatively, the insulating layer 185 may be made of a low dielectric constant material (low-k material). For example, silicon oxide (SiOF) with a few percent of fluorine (F) introduced, and silicon oxide (SiOF) with a few percent of carbon (C) introduced. Silicon oxide (SiOC), fluorinated silicate glass (FSG), organic silicate glass Lass (OSG), silsesquioxane hydrogenate (HSQ), methylsilsesquioxane (M SQ), organic polymer, polyimide, fluororesin (polytetrafluoroethylene), fluorine It can be formed using amorphous carbon with added elements. By using low-k materials, the capacitance related to transistor 14 can be further reduced. can.

[0289] The transistor 14 has an insulating layer 185, which allows for processing below the resolution limit of the device. This allows for more precise processing, thus reducing development costs such as the introduction of new equipment. It is possible.

[0290] <Method for fabricating transistor 14> The method for fabricating transistor 14 is described below. Note that the method described in Embodiment 1 is not applicable. For processes similar to those described for Rangista 10, refer to the explanation provided.

[0291] As shown in Figures 20(A) and 20(B), after forming the insulating layer 170 and insulating layer 175b, grooves are formed. A resist mask 176 for forming the part is formed. The resist mask 176 is for transistor 1 Compared to creating a 0, the groove dimensions can be made wider (the design rules can be relaxed).

[0292] Next, the insulating layer 175b is selectively etched using the resist mask 176, and the insulating layer 1 Forms 75.

[0293] Next, a fourth insulating film, which will become the insulating layer 185, is formed. The fourth insulating film is formed by plasma CVD. Thermal CVD (MOCVD, ALD), sputtering, or spin coating methods, etc. It can be formed by [this method].

[0294] Next, an etch-back treatment is performed using a dry etching method to form an insulating layer 185. .

[0295] Next, the insulating layer 185 is used as a hard mask until the oxide semiconductor layer 122 is exposed. The conductive layer 130b is selectively etched, and the source electrode layer 130 and the drain electrode layer 140 It forms (see Figure 21).

[0296] Next, the third oxide semiconductor film 123a, the third insulating film 150a, and the conductive film 160a are formed sequentially. By forming a film (see Figure 22) and performing a planarization process, transistor 14 is fabricated (see Figure 23). (see).

[0297] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0298] (Embodiment 3) <Oxide semiconductor structure> This embodiment describes the structure of an oxide semiconductor.

[0299] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned) is used. Crystalline Oxide Semiconductor, Polycrystalline Oxide Semiconductor Conductor, nc-OS (nanocrystalline Oxide Semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li Examples include amorphous oxide semiconductors (such as ke Oxide Semiconductors).

[0300] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. They can be divided into conductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors and CAAC-O Examples include S, polycrystalline oxide semiconductors, and nc-OS.

[0301] Generally, an amorphous structure is defined as a structure that is not fixed in a metastable state and is isotropic. It is known that it does not have a heterogeneous structure. Also, the bond angles are flexible and short distance It can also be described as a structure that possesses order but lacks long-range order.

[0302] Conversely, in the case of oxide semiconductors, which are inherently stable, a completely amorphous (complete) semiconductor is possible. It cannot be called an oxide semiconductor (ely amorphous). Furthermore, it is not isotropic. For example, an oxide semiconductor (having a periodic structure in a minute region) is made of a completely amorphous oxide It cannot be called a semiconductor. However, a-like OS exhibits periodicity in a minute region. Although it has a structure, it is unstable due to its porous (also called void) nature. Therefore, In terms of physical properties, it can be said to be similar to an amorphous oxide semiconductor.

[0303] <caac-os> First, let me explain CAAC-OS.

[0304] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0305] Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (high-frequency analysis) is obtained using the scope. Also called a resolving TEM image.) When observing this image, multiple pellets can be identified. In high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are visible. It cannot be clearly confirmed that CAAC-OS occurs at the grain boundaries. This means that a decrease in electron mobility due to this is less likely to occur.

[0306] The following describes CAAC-OS as observed by TEM. Figure 24(A) shows, This shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. For observing high-resolution TEM images, spherical aberration correction is necessary. The Corrector function was used. High-resolution TEM images using spherical aberration correction were obtained. This is specifically called a Cs-corrected high-resolution TEM image. Acquisition of Cs-corrected high-resolution TEM images is, for example, done in Japan. This is performed using an atomic-resolution analytical electron microscope, such as the JEM-ARM200F, manufactured by this electronics company. It is possible.

[0307] Figure 24(B) shows a magnified Cs-corrected high-resolution TEM image of region (1) in Figure 24(A). Figure 24(B) shows that the metal atoms in the pellet are arranged in layers. The arrangement of metal atoms in each layer is such that the surface forming the CAAC-OS film (also called the surface to be formed) Alternatively, it reflects the irregularities of the upper surface and is parallel to the surface or upper surface of the CAAC-OS that is formed.

[0308] As shown in Figure 24(B), CAAC-OS has a characteristic atomic arrangement. Figure 24(C) The characteristic atomic arrangement is shown with auxiliary lines. Figures 24(B) and 24(C) Furthermore, the size of a single pellet can be 1 nm or larger, or 3 nm or larger. It can be seen that the size of the gap created by the tilt between the pellet and the material is approximately 0.8 nm. Therefore, pellets can also be called nanocrystals (nc). Also, CAAC-OS is CANC(C-Axis Aligned nanocry It can also be called an oxide semiconductor containing stals.

[0309] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on substrate 5120 are... The arrangement of the To 5100 can be schematically represented as a structure resembling stacked bricks or blocks. (See Figure 24(D)). The tilt between the pellets observed in Figure 24(C) The area where the condensation is occurring corresponds to region 5161 shown in Figure 24(D).

[0310] Furthermore, Figure 25(A) shows the Cs in the plane of CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown. Regions (1), (2), and (3) in Figure 25(A). Magnified Cs-corrected high-resolution TEM images are shown in Figures 25(B), 25(C), and 25(B), respectively. As shown in 25(D). From Figures 25(B), 25(C), and 25(D), the pellets are It can be confirmed that metal atoms are arranged in a triangular, square, or hexagonal shape. However, However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0311] Next, the CA was analyzed by X-ray diffraction (XRD). Let's discuss AC-OS. For example, CAAC-OS, which has an InGaZnO4 crystal. In contrast, when structural analysis is performed using the out-of-plane method, as shown in Figure 26(A)... In some cases, a peak may appear at a diffraction angle (2θ) near 31°. This peak is in InGaZ Since it is attributed to the (009) plane of the nO4 crystal, the CAAC-OS crystal is c-axis oriented. It can be confirmed that the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface.

[0312] In addition, in the structural analysis using the out-of-plane method of CAAC-OS, 2θ is 31°. In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak indicates that some of the crystals in CAAC-OS do not have c-axis orientation. This indicates that the more preferable CAAC-OS is the structural solution by the out-of-plane method. Analysis revealed a peak around 31° for 2θ, but no peak around 36° for 2θ.

[0313] On the other hand, for CAAC-OS, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-plan configuration. Structural analysis using the e method reveals a peak near 2θ = 56°. This peak corresponds to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is 56 The sample is fixed in the vicinity of °, and the analysis is performed while rotating the sample around the normal vector of the sample surface as the axis (φ axis). Even after performing a φ scan, no clear peak appears, as shown in Figure 26(B). Furthermore, if it is a single-crystal oxide semiconductor of InGaZnO4, then fixing 2θ to around 56°, φs If this occurs, the crystal plane is assigned to the equivalent of the (110) plane, as shown in Figure 26(C). Six lines are observed. Therefore, structural analysis using XRD indicates that CAAC-OS is It can be confirmed that the orientation of the a-axis and b-axis is irregular.

[0314] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe with a diameter of 300 nm is placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern like the one shown in Figure 27(A) (limited field transmission electron diffraction) is observed. Sometimes a pattern (also called a diffraction pattern) may appear. This diffraction pattern is indicative of InGaZnO4. The spot originates from the (009) plane of the crystal. Therefore, electron diffraction also reveals... The pellets contained in CAAC-OS have c-axis orientation, and the c-axis is approximately aligned with the surface to be formed or the upper surface. It can be seen that it is oriented in a vertical direction. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. Figure 27(B) shows the diffraction pattern when an electron beam with a diameter of 300 nm is incident on the surface. Figure 27 (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also shows that It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. Note that the first ring in Figure 27(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be caused by the (100) surface, etc. Also, the second ring in Figure 27(B) is (110) This is thought to be caused by the surface, etc.

[0315] As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. Crystallinity can decrease due to the inclusion of impurities or the formation of defects, so the opposite perspective is needed. CAAC-OS can also be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

[0316] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0317] When oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps, or carriers It can become a source of emissions. Furthermore, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, it may act as a carrier source by capturing hydrogen.

[0318] CAAC-OS, with its low impurity and oxygen vacancies, is an oxide semiconductor with a low carrier density. Specifically, 8 x 10 11 / cm 3 Less than 1 × 10 11 / cm 3 Less than, More preferably 1 × 10 10 / cm 3 It is less than 1 × 10 -9 / cm 3 The above career It can be made into a high-density oxide semiconductor. Such an oxide semiconductor can be made into a high-purity intrinsic or It is essentially a high-purity, intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and defects. It has a low energy level density. In other words, it can be said to be an oxide semiconductor with stable properties.

[0319] <nc-os> Next, I will explain nc-OS.

[0320] nc-OS is a region in which the crystalline part can be confirmed in high-resolution TEM images, and is clearly It has regions where the crystalline portion cannot be confirmed. The crystalline portion contained in nc-OS is They are often between 1 nm and 10 nm in size, or between 1 nm and 3 nm. Oxide semiconductors with a crystal size greater than 10 nm and less than or equal to 100 nm are subjected to microcrystalline oxidation. It is sometimes called a solid semiconductor. nc-OS, for example, in high-resolution TEM images, shows grain boundaries. It may not be possible to confirm this clearly. Furthermore, nanocrystals are the pellets in CAAC-OS. They may share the same origin. Therefore, in the following, the crystalline portion of nc-OS will be referred to as a pellet. There are cases where this happens.

[0321] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). The atomic arrangement has periodicity in the region of less than nm. In addition, nc-OS has different pellets. No regularity in crystal orientation is observed between the layers. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analysis method, nc-OS can be classified as a-like OS or amorphous oxide semiconductor. In some cases, it may be difficult to distinguish between them. For example, with nc-OS, X has a larger diameter than the pellet. When using lines, out-of-plane analysis detects peaks that indicate crystal planes. It is not released. Also, for nc-OS, a probe diameter larger than the pellet (e.g., 50n) is required. When electron diffraction is performed using an electron beam (of m or greater), a diffraction pattern similar to a halo pattern can be observed. It is measured. On the other hand, compared to nc-OS, the size is close to or smaller than the pellet size. When nanobeam electron diffraction is performed using an electron beam of a certain diameter, spots can be observed. When nanobeam electron diffraction is performed on c-OS, a high-brightness ring-shaped pattern is observed. A region may be observed. Furthermore, multiple spots may be observed within a ring-shaped region. There are cases where this is the case.

[0322] Thus, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc- The OS has RANC (Random Aligned nanocrystals) Oxide semiconductors, or NANCs (Non-Aligned nanocrystals) It can also be called an oxide semiconductor having ).

[0323] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0324] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0325] a-like OS may exhibit porosity in high-resolution TEM images. In the high-resolution TEM image, there are regions where the crystalline structure can be clearly identified, and regions where the crystalline structure cannot be identified. It has areas that cannot be accessed.

[0326] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0327] The samples to be irradiated with electrons are a-like OS (referred to as sample A) and nc-OS ( Prepare Sample B (referred to as Sample B) and CAAC-OS (referred to as Sample C). The sample is also an In-Ga-Zn oxide.

[0328] First, high-resolution cross-sectional TEM images are obtained for each sample. It can be seen that all of them have crystalline parts.

[0329] The determination of which part should be considered a single crystal can be made as follows. For example, The unit cell of an InGaZnO4 crystal has three In-O layers and a Ga-Zn-O layer. It is known to have a structure in which 6 layers, totaling 9 layers, are stacked in layers along the c-axis. The spacing between adjacent layers is approximately the same as the spacing between grid planes (also called the d value) of the (009) plane. Yes, and its value has been determined to be 0.29 nm from crystal structure analysis. Therefore, the lattice fringes Areas with a spacing of 0.28 nm or more and 0.30 nm or less are considered to be the crystalline regions of InGaZnO4. This can be done. Note that the lattice patterns correspond to the ab-plane of the InGaZnO4 crystal.

[0330] Figure 28 shows an example of investigating the average size of the crystalline regions (22 to 45 locations) in each sample. However, the length of the lattice fringes mentioned above is used as the size of the crystal portion. From Figure 28, a-lik It can be seen that the crystalline portion of eOS increases in proportion to the cumulative amount of electron irradiation. As shown in (1) in Figure 28, the initial TEM observation is approximately 1.2 nm. The crystal region (also called the initial nucleus), which was initially 4.2 × 10¹⁶ in size, changed when the cumulative irradiation dose reached 4.2 × 10¹⁶. 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 2.6 nm. On the other hand, nc-OS And CAAC-OS has a cumulative electron dose of 4.2 × 10⁻⁶ from the start of electron irradiation. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. Specifically, Figure As shown in (2) and (3) of 28, regardless of the cumulative dose of electrons, nc-OS and The size of the crystalline portion of CAAC-OS is approximately 1.4 nm and 2.1 nm, respectively. It becomes clear that...

[0331] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It can be seen that it cannot be seen. That is, a-like OS is nc-OS and CAAC-O Compared to S, it is clear that it has an unstable structure.

[0332] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density will be between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are difficult to deposit into film.

[0333] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's how it is. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It will be less than.

[0334] Note that single crystals with the same composition may not exist. In that case, crystals with different compositions in arbitrary proportions may be found. By combining single crystals, the density equivalent to that of a single crystal at a desired composition can be estimated. This is possible. The density corresponding to a single crystal of the desired composition can be obtained by combining single crystals of different compositions. The proportion can be estimated using a weighted average. However, the density should be as small as possible. It is preferable to estimate by combining different types of single crystals.

[0335] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, nc-OS, The multilayer film may have two or more types of CAAC-OS.

[0336] (Embodiment 4) In this embodiment, an example of a circuit utilizing a transistor according to one aspect of the present invention is shown in the drawings. I will explain by referring to it.

[0337] <Cross-sectional structure> Figure 29(A) shows a cross-sectional view of a semiconductor device according to one embodiment of the present invention. In Figure 29(A), X The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. Figure 29(A) The semiconductor device shown has a transistor 2200 made of a first semiconductor material at the bottom, and above The part has a transistor 2100 using a second semiconductor material. In Figure 29(A), As a transistor 2100 using a second semiconductor material, the transistor exemplified in the previous embodiment is An example of applying a transistor is shown. Note that the part to the left of the dashed line is the transistor channel. The image shows a cross-section in the longitudinal direction, with the right side representing a cross-section in the channel width direction.

[0338] It is preferable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). Germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide (e.g., gallium phosphate, indium phosphide, gallium nitride, organic semiconductors), and the second semiconductor The main material can be an oxide semiconductor. Other materials besides oxide semiconductors include single-crystal silicon Transistors using materials such as semiconductors are easy to operate at high speeds. On the other hand, transistors using oxide semiconductors By applying the transistor exemplified in the previous embodiment, an excellent sub A threshold characteristic is obtained, making it possible to create a miniature transistor. The fast switch speed enables high-speed operation, and the low off-current results in low leakage current.

[0339] Transistor 2200 is an n-channel type transistor or a p-channel type transistor. Either type of transistor is acceptable, and the appropriate transistor should be used depending on the circuit. Aside from using a transistor according to one embodiment of the present invention that uses a synthetic semiconductor, the materials and structure used are as follows: However, it is not necessary to limit the specific configuration of the semiconductor device shown here to what is presented.

[0340] In the configuration shown in Figure 29(A), an insulator 2201 and an insulator are placed on top of the transistor 2200. Transistor 2100 is provided via 2207. Also, transistor 2200 Multiple wires 2202 are provided between the transistor 2100 and the transistor. Multiple plugs 2203 embedded in the rim allow wiring to be provided in the upper and lower layers, respectively. The electrodes are electrically connected. Also, the insulator 2204 covering the transistor 2100 and Wiring 2205 and a sintered material are provided on the insulator 2204.

[0341] In this way, by stacking two types of transistors, the circuit footprint is reduced. Multiple circuits can be arranged at a higher density.

[0342] In this case, if a silicon-based semiconductor material is used for the transistor 2200 located in the lower layer, Hydrogen in the insulator placed near the semiconductor film of transistor 2200 is in the silicon dung. This terminates the ring bond and improves the reliability of transistor 2200. On the other hand, When an oxide semiconductor is used for the transistor 2100 located in the upper layer, transistor 21 Hydrogen in the insulator placed near the semiconductor film generates carriers in the oxide semiconductor. This can be one of the contributing factors, and therefore can reduce the reliability of transistor 2100. Therefore, an oxide layer is found on the upper layer of the transistor 2200 using silicon-based semiconductor material. When stacking transistors 2100 made of solid semiconductor material, hydrogen diffusion occurs between them. It is particularly effective to provide an insulator 2207 that has the function of preventing this. As a result of step 7, the reliability of transistor 2200 is improved by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, which affects transistor 2100. Reliability can also be improved at the same time.

[0343] Examples of insulators 2207 include aluminum oxide, aluminum oxide nitride, and gallium oxide. M, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, acid Hafnium nitride, yttria-stabilized zirconia (YSZ), etc., can be used.

[0344] Furthermore, the transistor 2100, which is composed of an oxide semiconductor film, is covered by the transistor It is preferable to form a blocking film on the sta 2100 that has the function of preventing hydrogen diffusion. i. The block film can be made of the same material as the insulator 2207, and is particularly acidic. It is preferable to apply aluminum oxide. The aluminum oxide film is resistant to hydrogen, moisture, and other impurities. It has a high blocking effect, preventing the permeation of both pure substances and oxygen. Therefore, an aluminum oxide film is used as the block film covering the transistor 2100. This prevents the desorption of oxygen from the oxide semiconductor film contained in transistor 2100. Both methods can prevent the ingress of water and hydrogen into the oxide semiconductor film. The lock film may be used by laminating the insulator 2204, or on the underside of the insulator 2204. It may be provided in [location].

[0345] Note that the 2200 transistor is not only a planar type transistor, but also various types It can be a transistor. For example, it can be a transistor such as a FIN (fin) type, a TRI-GATE (tri-gate) type, etc. An example of a cross-sectional view in that case is shown in Fig. 29(D). An insulator 2212 is provided on the semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at the tip. Note that an insulator may be provided on the convex portion. The insulator functions as a mask for preventing the semiconductor substrate 2 211 from being etched when forming the convex portion. Note that the tip of the convex portion does not have to be thin. For example, it may be a substantially rectangular parallelepiped convex portion, or a convex portion with a thick tip. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

[0346] <Circuit configuration example> In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described.

[0347] <CMOS inverter circuit> The circuit diagram shown in Fig. 29(B) is a so-called CMO in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series and their gates are connected. This shows the configuration of the S-inverter.

[0348] <CMOSアナログスイッチ> Furthermore, the circuit diagram shown in Figure 29(C) shows the relationship between transistor 2100 and transistor 2200. This shows the configuration with each source and drain connected. In Figure 29(A), X1- The X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. By doing so, it can function as a so-called CMOS analog switch.

[0349] <Example of a storage device> Using a transistor according to one aspect of the present invention, the stored contents can be preserved even when power is not supplied. Figure 30 shows an example of a semiconductor device (memory device) that can be stored and has no limit on the number of write cycles. This will be shown.

[0350] The semiconductor device shown in Figure 30(A) is a transistor 3200 using a first semiconductor material and a second It has a transistor 3300 and a capacitive element 3400 made of two semiconductor materials. Note that the transistor 3300 is one of the transistors described in Embodiments 1 and 2. It is possible to be there.

[0351] Figure 30(B) shows a cross-sectional view of the semiconductor device shown in Figure 30(A). Now, the configuration shown has a back gate added to transistor 3300, but the back gate A configuration without this feature is also acceptable.

[0352] Note that Figure 30(A) shows the configuration when the intermediate layer 2210 is conductive, and the intermediate layer If 2210 is insulating, then the transistor is connected using wiring 3005 as shown in Figure 22. Simply connect the TA2200 and the transistor 2100.

[0353] Transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. It is a transistor. The 3300 transistor has a low off-current, so by using it... It is possible to retain memory content for a long period of time. In other words, it does not require a refresh operation. To avoid this, or to create a semiconductor memory device with an extremely low refresh frequency. This makes it possible to significantly reduce power consumption.

[0354] In Figure 30(A), the first wiring 3001 is connected to the source electrode of transistor 3200 and electrical The second wire 3002 is electrically connected to the drain electrode of transistor 3200. It is continued. Also, the third wiring 3003 is the source electrode or of transistor 3300. Electrically connected to one of the rain electrodes, the fourth wire 3004 is connected to the gate of transistor 3300. It is electrically connected to the electrode. And the gate electrode of transistor 3200 is The source electrode or drain electrode of the transistor 3300, and the other of the capacitive element 3400 The fifth wire 3005 is electrically connected to one of the electrodes, and the other electrode of the capacitive element 3400 is connected to the other electrode. They are electrically connected.

[0355] In the semiconductor device shown in Figure 30(A), the potential of the gate electrode of transistor 3200 can be maintained. By utilizing its unique characteristics, it is possible to write, retain, and read information in the following ways: ru.

[0356] This section will explain how to write and retain information. First, the potential of the fourth wiring 3004 is set to the traction control. The potential is set to the ON state for transistor 3300, thereby turning on transistor 3300. . As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and also to the capacitor element 3400. That is, a predetermined charge is applied to the gate of the transistor 3200 (writing). Here, it is assumed that either one of two different charge levels (hereinafter referred to as Low level charge and High level charge) that give different potential levels is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is in an off state, and by turning off the transistor 3300, the charge applied to the gate of the transistor 3200 is retained (holding). Since the off - current of the transistor 3300 is extremely small, the charge on the gate of the transistor 3200 is retained for a long time.

[0357]

[0358] Next, reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 takes a different potential according to the amount of charge retained on the gate of the transistor 3200. Generally, when the transistor 3200 is an n - channel type, the apparent threshold value V when a High level charge is applied to the gate electrode of the transistor 3200 is lower than the apparent threshold value V when a Low level charge is applied to the gate electrode of the transistor 3200. Here, the apparent threshold voltage means the potential of the fifth wiring 3005 required to turn the transistor 3200 into an "on state". Therefore, when the potential of the fifth wiring 3005 is between V th_H and V th_L This is because. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 required to turn the transistor 3200 into an "on state". Therefore, the potential of the fifth wiring 3005 is set between V and V th_H th_L ​​​​​​​By setting it as V0, the charge applied to the gate of the transistor 3200 can be determined. For example, in writing, when a high-level charge is applied, the potential of the fifth wiring 3005 becomes V0 (> V th_H ), and the transistor 3200 is in the "on state" . When a low-level charge is applied, even if the potential of the fifth wiring 3005 is V0 (< V th_L ), the transistor 3200 remains in the "off state". Therefore, by determining the potential of the second wiring 3002, the stored information can be read .

[0359] When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. When the information is not read like this, a potential such that the transistor 3200 is in the "off state" regardless of the state of the gate, that is, a potential smaller than V th_H

[0360] th_L

[0361] The semiconductor device shown in FIG. 30(C) is different from FIG. 30(A ) in that the transistor 3200 is not provided. Also in this case, the writing and holding operations of information are possible by the same operation as above .

[0361] Next, the reading of information will be described. When the transistor 3300 is in the on state, the floating third wiring 3003 in the floating state and the capacitor element 3400 are connected, and the third wiring 3003 and Charge is redistributed among the capacitive elements 3400. As a result, the potential of the third wiring 3003 changes. The change in potential of the third wiring 3003 is the potential of the first terminal of the capacitive element 3400. Alternatively, it takes on different values ​​depending on the charge stored in the capacitive element 3400.

[0362] For example, let V be the potential of the first terminal of the capacitive element 3400, C be the capacitance of the capacitive element 3400, and the third terminal The capacitance component of wiring 3003 is CB, and the charge of the third wiring 3003 before redistribution is CB If the potential is VB0, then the potential of the third wiring 3003 after the charge has been redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, the state of the memory cell is the capacity element If the potential of the first terminal of child 3400 takes two states, V1 and V0 (V1 > V0), then The potential of the third wiring 3003 when position V1 is maintained is (=(CB×VB0+C×V1)) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=(C) It can be seen that this is higher than B × VB0 + C × V0) / (CB + C)).

[0363] Then, by comparing the potential of the third wiring 3003 with a predetermined potential, the information is read out. It is possible.

[0364] In this case, the first semiconductor material described above was applied to the drive circuit for driving the memory cell. A transistor is used, and a second semiconductor material is applied to transistor 3300. The zistas can be stacked on top of the drive circuit.

[0365] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By applying extremely small transistors, it is possible to retain memory contents for extremely long periods of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. Furthermore, in the absence of power supply (however, it is desirable that the potential be fixed), However, it is possible to retain memory content over a long period of time.

[0366] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as deterioration of the gate insulating layer do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved.

[0367] In this specification, active elements (transistors, diodes, etc.), passive elements ( For all terminals of capacitive elements, resistive elements, etc., the destination of their connection is not specified. However, a person skilled in the art may be able to constitute one aspect of the invention. In other words, connection Even without specifying the destination, one aspect of the invention can be said to be clear. And the connection destination is specified. If the content is described in this specification, etc., then one aspect of the invention that does not specify the connection destination is described in this specification. In some cases, it can be determined that this is stated in the document or other documentation. In particular, multiple terminals are used as connection destinations. When multiple cases are possible, it is not necessary to limit the connection destination of that terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitive elements, resistors) are distinct. By specifying the connection destination for only some of the terminals (such as those on an element), It may be possible to constitute one aspect of the invention.

[0368] Furthermore, in this specification, etc., if a certain circuit is specified, then at least the connection destination is identified, and this applies to our business. If you are an expert, you may be able to identify the invention. Or, regarding a certain circuit, However, if the function is specified, a person skilled in the art may be able to specify the invention. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in this specification, etc. Therefore, even without specifying the function of a certain circuit, if the connection destination is specified, it constitutes an invention. It is disclosed as such and can constitute one aspect of the invention. Regarding a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. This has been disclosed and can constitute one aspect of the invention.

[0369] In this specification, etc., the figures or text described in a particular embodiment may differ from the actual figures or text. Therefore, it is possible to take a part of it and constitute one aspect of the invention. If a diagram or text describing a part is included, remove a portion of that diagram or text. The information provided is disclosed as one aspect of the invention and constitutes one aspect of the invention. It is assumed that this is possible. For example, active elements (transistors, diodes) (etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic Drawings in which materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc. are described singly or in plural In the drawings or the text, a part thereof may be extracted to constitute an aspect of the invention For example, from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to extract M (M is an integer, M < N) circuit elements (transistors, capacitor elements, etc.) to constitute an aspect of the invention As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer, M < N) layers to constitute an aspect of the invention As yet another example, from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer, M < N) elements to constitute an aspect of the invention

[0370] <Imaging device> Hereinafter, an imaging device according to an aspect of the present invention will be described

[0371] FIG. 31(A) is a plan view showing an example of an imaging device 200 according to an aspect of the present invention. The imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel unit 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211 In this specification, etc., all of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be referred to as "peripheral circuit" or "driving circuit" ​​ For example, peripheral circuit 260 can be considered part of the peripheral circuitry.

[0372] Furthermore, it is preferable that the imaging device 200 has a light source 291. The light source 291 is a detection light P It can emit 1.

[0373] Furthermore, the peripheral circuits include at least logic circuits, switches, buffers, amplification circuits, or converters. It has one of the circuits. Furthermore, the peripheral circuits may be arranged on the substrate forming the pixel section 210. Furthermore, peripheral circuits may be partially or entirely implemented using semiconductor devices such as ICs. Oh, the peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280 and peripheral circuit 29 One or more of the zeros may be omitted.

[0374] Furthermore, as shown in Figure 31(B), in the pixel section 210 of the imaging device 200, Pixels 211 may be arranged at an angle. By arranging pixels 211 at an angle, the row direction and The pixel spacing (pitch) in the column direction can be shortened. This allows the imaging device 200 to This allows for a further improvement in the quality of the images being captured.

[0375] <Example of pixel configuration 1> The imaging device 200 has one pixel 211 which is composed of multiple sub-pixels 212, and each sub A filter (color filter) that transmits light in a specific wavelength range is combined with pixel 212. This allows us to obtain the information necessary to display color images.

[0376] Figure 32(A) is a plan view showing an example of pixels 211 for acquiring a color image. The pixel 211 shown in 32(A) is provided with a color filter that transmits the red (R) wavelength band. Sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") transmits the green (G) wavelength band. Sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") equipped with a color filter and Sub-pixel 212 (hereinafter referred to as "sub-pixel") is provided with a color filter that transmits the blue (B) wavelength band. It has a sub-pixel (also called "pixel 212B"). The sub-pixel 212 is used to function as a photosensor. It is possible.

[0377] Sub-pixels 212 (sub-pixels 212R, 212G, and 212B) are connected to wiring 23 1. It is electrically connected to wires 247, 248, 249, and 250. Pixel 212R, sub-pixel 212G, and sub-pixel 212B are each connected by independent wiring 25 It is connected to 3. Also, in this specification, for example, it is connected to pixel 211 of the nth row. Wires 248 and 249 are denoted as wire 248[n] and wire 249[n], respectively. To include. Also, for example, the wiring 253 connected to the pixel 211 in the mth column is defined as wiring 253[m] This is described as follows. Note that in Figure 32(A), the subpixel 212R of pixel 211 in the mth column Wiring 253[m]R is connected to the sub-pixel 212G, and wiring 253 is connected to the sub-pixel 212G. Wiring 253 connected to line 253[m]G and sub-pixel 212B is connected to wiring 253[m]B As described above, the sub-pixel 212 is electrically connected to the peripheral circuitry via the above wiring.

[0378] Furthermore, the imaging device 200 transmits color filters of adjacent pixels 211 that transmit the same wavelength band. The sub-pixels 212, each equipped with a t-axis, are electrically connected to each other via a switch. Arranged in 32(B) with n rows (where n is an integer between 1 and p) and m columns (where m is an integer between 1 and q). The sub-pixel 212 of the pixel 211, and the sub-pixel 212 located in the n+1 row and m column adjacent to the pixel 211. An example of the connection of sub-pixels 212 of the pixel 211 is shown. In Figure 32(B), n rows m Sub-pixels 212R located in a column and sub-pixels 212R located in row n+1 and column m are switched. It is connected via 201. Also, the subpixels 212G arranged in n rows and m columns, and n+1 Sub-pixels 212G, arranged in row m column, are connected via switch 202. Also, n Sub-pixel 212B located in row m and column m and sub-pixel 212B located in row n+1 and column m are It is connected via switch 203.

[0379] Furthermore, the color filters used for sub-pixel 212 are limited to red (R), green (G), and blue (B). Color film that transmits cyan (C), yellow (Y), and magenta (M) light respectively. A LUTA may be used. A sub-pixel detects light of three different wavelength bands in one pixel 211. By adding 212, it is possible to acquire a full-color image.

[0380] Alternatively, color filters that transmit red (R), green (G), and blue (B) light, respectively, are provided. In addition to the sub-pixels 212 that have been cut off, a sub-pixel with a color filter that transmits yellow (Y) light is provided. A pixel 211 having pixel 212 may be used. Alternatively, cyan (C) and yellow (Y) may be used, respectively. In addition to sub-pixels 212 equipped with a color filter that transmits ) and magenta (M) light, A pixel 21 has a sub-pixel 212 that is provided with a color filter that transmits blue (B) light. 1 may be used. Sub-pixels 2 detect light of four different wavelength bands in one pixel 211. By adding 12, the color reproduction accuracy of the acquired image can be further improved.

[0381] Furthermore, for example, in Figure 32(A), sub-pixel 212 detects the red wavelength band, and the green wavelength The ratio of the number of sub-pixels 212 that detect the bandwidth and the sub-pixels 212 that detect the blue wavelength bandwidth ( The pixel ratio (or light-receiving area ratio) does not have to be 1:1:1. For example, the pixel ratio (light-receiving area ratio) Alternatively, a Bayer array with red:green:blue = 1:2:1 may be used. Or, the pixel ratio (received The light area ratio can also be set to red:green:blue = 1:6:1.

[0382] Note that while one sub-pixel 212 may be provided in pixel 211, two or more are preferable. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the 200 unit.

[0383] Furthermore, IR (Infrared) absorbs or reflects visible light and transmits infrared light. By using a filter, an imaging device 200 that detects infrared light can be realized.

[0384] Also, an ND (Neutral Density) filter (light-reducing filter) is used. This is because when a large amount of light is incident on a photoelectric conversion element (light-receiving element), the output saturation occurs. This can prevent this. By using a combination of ND filters with different light reduction amounts, the imaging device This allows for a wider dynamic range in the image.

[0385] In addition to the filter mentioned above, a lens may also be provided at pixel 211. Here, Figure 33 An example of the arrangement of pixels 211, filter 254, and lens 255 will be explained using a cross-sectional diagram. By providing the 255 element, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in Figure 33(A), a lens 255 and a filter 25 are formed on the pixel 211. 4 (filters 254R, 254G, and 254B), and pixel circuit 2 The structure can be configured to allow light 256 to be incident on the photoelectric conversion element 220 through 30, etc.

[0386] However, as shown in the area enclosed by the dashed line, a portion of the light 256 indicated by the arrow is connected to wiring 257. It may be partially blocked by something. Therefore, as shown in Figure 33(B), the photoelectric The lens 255 and filter 254 are placed on the side of the conversion element 220, and the photoelectric conversion element 220 A structure that efficiently receives light 256 is preferred. Light 256 is received from the photoelectric conversion element 220 side. By injecting the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity is provided. It is possible.

[0387] As shown in Figure 33, the photoelectric conversion element 220 has a pn-type junction or a pin-type junction formed on it. Photoelectric conversion elements may also be used.

[0388] Furthermore, the photoelectric conversion element 220 uses a material that has the function of absorbing radiation and generating electric charge. It may be formed by absorbing radiation and generating an electric charge. Len, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy These include:

[0389] For example, if selenium is used in the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 having an optical absorption coefficient across a wide wavelength range, including X-rays and gamma rays. We can achieve 20.

[0390] Here, one pixel 211 of the imaging device 200 is, in addition to the sub-pixel 212 shown in Figure 32, Furthermore, it may have a sub-pixel 212 having a first filter.

[0391] <Example of pixel configuration 2> Below, we will discuss transistors using silicon and transistors using oxide semiconductors. An example of how pixels are constructed using this method will be explained.

[0392] Figures 34(A) and 34(B) are cross-sectional views of the elements that make up the imaging device.

[0393] The imaging device shown in Figure 34(A) is a silicon-based transistor provided on a silicon substrate 300. Transistor 351, Transistor 351 with an oxide semiconductor stacked on top of it Transistor 352 and transistor 353, and provided on the silicon substrate 300, Includes a photodiode 360 ​​having an anode 361 and a cathode 362. The sta and photodiode 360 ​​are electrically connected to various plugs 370 and wiring 371. It has a connection. Also, the anode 361 of the photodiode 360 ​​has a low resistance region 363. It has an electrical connection to plug 370 via this.

[0394] The imaging device also includes a transistor 351 and a photodie provided on the silicon substrate 300. A layer 310 having an ore 360, and a layer 3 provided in contact with the layer 310 and having wiring 371 20 is provided in contact with layer 320 and has transistors 352 and 353. A layer 330, and a layer 330 provided in contact with the layer 330, having wiring 372 and wiring 373. It has 40.

[0395] In addition, in the example cross-sectional view in Figure 34(A), transistor 3 is located on the silicon substrate 300. The configuration includes a photodiode 360 ​​with a light-receiving surface on the side opposite to the surface where 51 is formed. This configuration ensures that the optical path is not affected by various transistors, wiring, etc. This allows for the formation of pixels with a high aperture ratio. The light-receiving surface of D360 can also be the same as the surface on which transistor 351 is formed.

[0396] Furthermore, when using transistors to construct pixels, layer 310 has transistors. This layer can be used. Alternatively, layer 310 can be omitted, and the pixels can be constructed using only transistors. .

[0397] Furthermore, in the cross-sectional view of Figure 34(A), the photodiode 360 ​​provided in layer 310 and layer The transistors provided at 330 can be formed to overlap with the pixels. This allows for an increase in the integration density, that is, an increase in the resolution of the imaging device.

[0398] Furthermore, Figure 34(B) shows that the imaging device has a photodiode 365 on the layer 340 side and a transistor It can be a structure placed on top of. In Figure 34(B), for example, layer 310 is It has a silicon transistor 351 and a silicon transistor 352, and layer 320 has wiring 3 Transistor 352 and transistor 330 have 71 and use an oxide semiconductor layer in layer 330. It has 53, and layer 340 has a photodiode 365, and photodiode 365 It consists of semiconductor layer 63, semiconductor layer 64, and semiconductor layer 65, and wiring 373 and plug It is electrically connected to wiring 374 via 370.

[0399] By using the element configuration shown in Figure 34(B), the aperture ratio can be increased.

[0400] Furthermore, the photodiode 365 uses amorphous silicon film, microcrystalline silicon film, etc. A pin-type diode element may also be used. The photodiode 365 is an n-type semiconductor. A configuration in which layer 368, i-type semiconductor layer 367, and p-type semiconductor layer 366 are stacked in order. It has. It is preferable to use amorphous silicon for the i-type semiconductor layer 367. Also, The p-type semiconductor layer 366 and the n-type semiconductor layer 368 are given their respective conductivity types. Amorphous silicon or microcrystalline silicon containing a carboxylate can be used. Photodiode 365, which uses silicon as its photoelectric conversion layer, has sensitivity in the visible light wavelength range. It is highly sensitive and can easily detect weak visible light.

[0401] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0402] (Embodiment 5) <RFタグ> In this embodiment, an RF including a transistor or memory device as described in the previous embodiment is used. Tags will be explained with reference to Figure 35.

[0403] The RF tag in this embodiment has a memory circuit inside, and stores the necessary information in the memory circuit. Furthermore, it uses non-contact means, such as wireless communication, to exchange information with the outside world. Due to its characteristics, RF tags are used to identify items by reading individual information about those items. It can be used in body recognition systems, etc. However, in order to use it for these purposes, For the first time, a high level of reliability is required.

[0404] The configuration of an RF tag will be explained using Figure 35. Figure 35 shows an example of the configuration of an RF tag. This is a lock diagram.

[0405] As shown in Figure 35, the RF tag 800 is connected to the communicator 801 (also known as an interrogator, reader / writer, etc.). Antenna 8 receives a radio signal 803 transmitted from antenna 802 connected to ( It has 04. The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, and a demodulation circuit 8 It has a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Furthermore, the reverse current in the rectifying transistor included in the demodulation circuit 807 is sufficiently suppressed. A configuration may be made using a material capable of doing so, for example, an oxide semiconductor. This suppresses the decrease in rectification due to reverse current and prevents the output of the demodulation circuit from saturating. This can be prevented. In other words, the output of the demodulation circuit can be made more linear with respect to the input of the demodulation circuit. It is possible. Furthermore, the data transmission format involves a pair of coils positioned opposite each other and communicating through mutual induction. Electromagnetic coupling methods, electromagnetic induction methods that use induced electromagnetic fields for communication, and methods that use radio waves for communication. They can be broadly classified into three types of radio wave methods. The RF tag 800 shown in this embodiment uses any of these methods. It can also be used for this purpose.

[0406] Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with Tenor 802. Also, a rectifier circuit 8 05 rectifies the input AC signal generated by receiving a wireless signal with antenna 804. For example, half-wave voltage doubling rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. This is a circuit for generating input potential by converting it. Furthermore, the input side of the rectifier circuit 805 is also A limiter circuit may be provided on the output side. A limiter circuit is a circuit that limits the amplitude of the input AC signal. When the internally generated voltage is large, do not input power exceeding a certain level to the subsequent circuit. This is a circuit for controlling sea urchins.

[0407] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is a circuit. Note that the constant voltage circuit 806 may also have an internal reset signal generation circuit. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 80. This is a circuit for generating a reset signal for number 9.

[0408] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 responds to the data output from the antenna 804. This is a circuit for performing modulation.

[0409] Logic circuit 809 is a circuit for analyzing and processing demodulated signals. Memory circuit 810 is This is a circuit that holds the input information, and includes a row decoder, column decoder, memory area, etc. It has. Furthermore, ROM811 stores unique numbers (IDs), etc., and outputs them according to the processing. This is a circuit for that purpose.

[0410] Furthermore, the circuits described above can be selected or omitted as needed.

[0411] Here, the memory circuit described in the previous embodiment can be used in the memory circuit 810. A memory circuit according to one aspect of the present invention can retain information even when the power supply is cut off, It can be suitably used in RF tags. Furthermore, a memory circuit according to one aspect of the present invention is a memory for writing data. Because the power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, data It is also possible not to cause a difference in the maximum communication distance during reading and writing. Further, it is possible to suppress occurrence of malfunction or incorrect writing due to insufficient power during data writing.

[0412] Also, the memory circuit according to one aspect of the present invention can be used as a non-volatile memory, and thus can also be applied to the ROM811. In that case, it is preferable to separately prepare a command for the producer to write data into the ROM811 and prevent the user from freely rewriting it. By the producer writing the unique number before shipping and then shipping the product, it becomes possible to assign unique numbers not to all of the manufactured RF tags but only to the non-defective products to be shipped, and it becomes easy to manage customers corresponding to the products after shipping without the unique numbers of the products after shipping being discontinuous.

[0413] Note that this embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0414] (Embodiment 6) In this embodiment, a CPU including the memory device described in the previous embodiment will be described.

[0415] FIG. 36 is a block diagram showing a configuration example of a CPU using at least a part of the transistors described in the previous embodiment.

[0416] <Circuit diagram of CPU> The CPU shown in FIG. 36 has an ALU1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, and an instruction on a substrate 1190. ​Timing decoder 1193, interrupt controller 1194, timing controller 1195, Register 1196, Register Controller 1197, Bus Interface 1 It has 198, a rewritable ROM 1199, and a ROM interface 1189. The substrate 1190 uses semiconductor substrates, SOI substrates, glass substrates, etc. ROM1 199 and the ROM interface 1189 may be provided on a separate chip. Of course, The CPU shown in Figure 36 is merely one example of a simplified configuration; an actual CPU is different. They have a wide variety of configurations depending on the application. For example, the CPU or arithmetic circuit shown in Figure 36. A configuration including this is considered one core, and there are multiple such cores, with each core operating in parallel. This configuration is also acceptable. Furthermore, the number of bits that the CPU can handle in its internal arithmetic circuits and data bus is: For example, it can be 8-bit, 16-bit, 32-bit, 64-bit, etc.

[0417] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0418] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal. Also, the interrupt controller 1194 controls the CPU's program. During execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and masking. The system makes a judgment and processes based on the state. The register controller 1197 determines the address of register 1196. It generates a value and reads or writes to register 1196 depending on the CPU state.

[0419] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above.

[0420] In the CPU shown in Figure 36, a memory cell is located in register 1196. The transistors shown in Embodiments 1 to 3 can be used as the 1196 memory cells. can.

[0421] In the CPU shown in Figure 36, the register controller 1197 receives information from ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 11 In the memory cell of 96, data is retained by a flip-flop, or capacity Select whether to retain data using an element. Data retention using a flip-flop is If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, data rewriting to the capacitive element will not occur. This process can be performed to stop the supply of power voltage to the memory cells in register 1196. .

[0422] <Recording Circuit> Figure 37 is an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 1200 has a circuit 1201 in which the stored data is lost when the power is cut off, and a memory element 1200 which loses stored data when the power is cut off. A circuit 1202 that prevents data from volatilizing, a switch 1203, a switch 1204, and a logic element It comprises a sub-element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. 1202 consists of the capacitive element 1208, transistor 1209, and transistor 1210. It has a diode, a resistor, an inductor, etc., as needed. It may also have other elements such as a t-axis.

[0423] Here, the memory device described in the previous embodiment can be used in circuit 1202. When the power supply voltage to the memory element 1200 is stopped, the transistor 120 of circuit 1202 The gate of transistor 9 is input to ground potential (0V) or a potential that turns off transistor 1209. The configuration will continue to be such that the first gate of transistor 1209 is connected via a load such as a resistor. The configuration will be grounded.

[0424] Switch 1203 uses a single-conductivity (e.g., n-channel) transistor 1213. The switch 1204 is configured to have a conductivity type opposite to that of a single-conductivity type (for example, a p-channel type). An example using transistor 1214 is shown. Here, the first terminal of switch 1203 The child corresponds to one of the source and drain of transistor 1213, and the second of switch 1203. The terminals correspond to the source and drain of transistor 1213, and switch 1203 is The control signal RD input to the gate of transistor 1213 controls the first terminal and the second terminal. Continuity or non-conductivity between terminals (i.e., the on or off state of transistor 1213) ) is selected. The first terminal of switch 1204 is the source and drain of transistor 1214. Corresponding to one side of the input, the second terminal of switch 1204 is the source of transistor 1214. Corresponding to the other side of the drain, switch 1204 is input to the gate of transistor 1214. The control signal RD determines whether the first terminal and the second terminal are conductive or non-conductive (i.e., The ON or OFF state of the Rangista 1214 is selected.

[0425] One of the sources and drains of transistor 1209 is connected to the pair of electrodes of capacitive element 1208. One side of this is electrically connected to the gate of transistor 1210. Here, the connection part Let the minute be node M2. One of the sources and drains of transistor 1210 is at a low power supply potential. It is electrically connected to a wire (e.g., a GND wire) that can supply power, and the other is a switch. The first terminal of 1203 (one of the source and drain of transistor 1213) is electrically connected. The second terminal of switch 1203 (source and drain of transistor 1213) On the other hand, the first terminal of switch 1204 (the source and drain of transistor 1214) is the first terminal of switch 1204. It is electrically connected to the second terminal of switch 1204 (the terminal of transistor 1214). The other end of the drain is electrically connected to wiring that can supply the power potential VDD. The second terminal of switch 1203 (the other terminal of the source and drain of transistor 1213) ) and the first terminal of switch 1204 (one of the source and drain of transistor 1214) ) and the input terminal of logic element 1206 and one of the pair of electrodes of capacitive element 1207, These are electrically connected. Here, the connection point is called node M1. A pair of capacitive elements 1207. The other electrode can be configured to receive a constant potential. For example, a low potential The system can be configured to receive either a source potential (such as GND) or a high power supply potential (such as VDD) as input. The other of the pair of electrodes of the capacitive element 1207 is a distribution capable of supplying a low power supply potential. It is electrically connected to a wire (for example, a GND wire). This configuration allows for a constant potential to be input. For example, a low power supply potential (such as GND). ) or a high power supply potential (VDD, etc.) can be input. Capacitive element 120 The other of the pair of electrodes (8) is connected to a wire capable of supplying a low power potential (e.g., GND). It is electrically connected to a wire.

[0426] Capacitive elements 1207 and 1208 are used to absorb parasitic capacitance from transistors and wiring. It was possible to omit it by actively using it.

[0427] The control signal WE is input to the first gate (first gate electrode) of transistor 1209. Switches 1203 and 1204 use a different control signal RD than control signal WE. The conduction or non-conduction state between the first terminal and the second terminal is selected by this, and one of the terminals When there is continuity between the first and second terminals of one switch, the first terminal of the other switch and the second terminal The area between terminals 2 becomes non-conductive.

[0428] Note that in transistor 1209 in Figure 37, the second gate (second gate electrode: buck) The diagram shows a configuration having gates. The first gate receives a control signal WE, and the second gate... The control signal WE2 can be input to the terminal. The control signal WE2 is a signal with a constant potential and This should be done. The constant potential can be, for example, the ground potential GND or the potential of transistor 1209. A potential smaller than the -potential is selected. At this time, the control signal WE2 is the transistor This is a potential signal used to control the threshold voltage of the 1209, and when the gate voltage VG is 0V... The current can be further reduced. Also, the control signal WE2 has the same potential signal as the control signal WE. It may also be a number. Note that transistor 1209 is a transistor without a second gate. You can also use a ZISTA.

[0429] The source and drain of transistor 1209 are connected to the data held in circuit 1201. A signal corresponding to this is input. In Figure 36, the signal output from circuit 1201 is transmitted to the transistor. An example is shown where the source and drain of switch 1203 are input. The signal output from the second terminal (the other end of the source and drain of transistor 1213) is: The logic element 1206 inverts its logic value, resulting in an inverted signal, which is then transmitted via circuit 1220. This is then input to circuit 1201.

[0430] Note that in Figure 37, the second terminal of switch 1203 (source and terminal of transistor 1213) The signal output from the other side of Rain is routed through logic element 1206 and circuit 1220. An example of input to path 1201 is shown, but it is not limited to this. The second terminal of switch 1203 The signal output from (the other side of the source and drain of transistor 1213) is the inverse of the logic value. It may be input to circuit 1201 without being converted. For example, within circuit 1201, If there is a node that holds a signal that is the inverted logical value of the signal input from the input terminal The second terminal of switch 1203 (the other of the source and drain of transistor 1213) The signal output from this node can be input to the node in question.

[0431] Furthermore, in Figure 37, among the transistors used in the memory element 1200, Transistors other than TA1209 are made of a layer or substrate 119 made of a semiconductor other than an oxide semiconductor. A transistor can be formed where a channel is created at 0. For example, a silicon layer or It can be a transistor in which a channel is formed on a silicon substrate. Also, a memory element. All transistors used in the 1200 are transistors whose channels are formed by an oxide semiconductor layer. It can also be a transistor. Alternatively, the memory element 1200 can be anything other than transistor 1209. It may also include transistors in which the channel is formed by an oxide semiconductor layer, and the remaining A transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be used as a transistor.

[0432] For example, a flip-flop circuit can be used in circuit 1201 in Figure 37. Furthermore, logic elements such as inverters and clocked inverters can be used as logic elements 1206. It is possible.

[0433] In one aspect of the present invention, in a semiconductor device, when the power supply voltage is not supplied to the memory element 1200 The data stored in circuit 1201 is transferred to the capacitive element 120 provided in circuit 1202. It can be held by 8.

[0434] Furthermore, transistors in which channels are formed in the oxide semiconductor layer exhibit extremely low off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer has crystalline properties. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Therefore, by using the transistor as transistor 1209, memory element 1 Even when no power voltage is supplied to 200, the signal held by the capacitive element 1208 will persist for a long period of time. The memory element 1200 is thus preserved. It is possible to hold data.

[0435] Furthermore, by providing switches 1203 and 1204, pre-charge action Since it is a memory element characterized by performing an operation, after the power supply voltage is restored, the circuit 1201 This can shorten the time it takes to restore the original data.

[0436] Furthermore, in circuit 1202, the signal held by the capacitive element 1208 is transmitted to the transistor The signal is input to gate 1210. As a result, the power supply voltage to memory element 1200 is restored. After that, the signal held by the capacitive element 1208 is controlled by the state of transistor 1210 ( It can be converted to an ON state or an OFF state and read from circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitive element 1208 fluctuates slightly, the original signal It is possible to read it accurately.

[0437] Such memory elements 1200 are stored in registers and cache memory of the processor. By using it in a storage device, it prevents the loss of data in the storage device due to a power supply interruption. This is possible. Furthermore, after the power supply voltage is restored, the system will quickly return to the state it was in before the power supply was interrupted. Therefore, the entire processor, or one of the components of the processor, This allows for power-off even for short periods in multiple logic circuits, thus reducing power consumption. It can be suppressed.

[0438] In this embodiment, although the memory element 1200 was described as an example of being used in a CPU, the memory element 1 200 is a DSP (Digital Signal Processor), custom L LSIs such as SIs and PLDs (Programmable Logic Devices), R This can also be applied to the F (Radio Frequency) tag.

[0439] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0440] (Embodiment 7) This embodiment describes an example of the configuration of a display device using a transistor according to one aspect of the present invention. explain.

[0441] <Display device circuit configuration example> Figure 38(A) is a top view of a display device according to one embodiment of the present invention, and Figure 38(B) is a top view of the present invention. This describes a pixel circuit that can be used when applying liquid crystal elements to the pixels of a display device in one embodiment. This is a circuit diagram for doing so. Also, Figure 38(C) shows the pixels of a display device according to one embodiment of the present invention. This is a circuit diagram illustrating a pixel circuit that can be used when applying an EL element. .

[0442] The transistors placed in the pixel area can be formed according to Embodiments 1 to 3. Furthermore, since the transistor can easily be made into an n-channel type, the n-channel transistor is used in the drive circuit. A part of the drive circuit, which can be constructed using channel-type transistors, is made up of transistors in the pixel section. They are formed on the same substrate. In this way, the pixel portion and the drive circuit are formed in the transient as shown in the above embodiment. By using STA, a highly reliable display device can be provided.

[0443] Figure 38(A) shows an example of a top view of an active-matrix display device. The circuit board of the display device. On 700 are a pixel section 701, a first scan line drive circuit 702, and a second scan line drive circuit 70 3. It has a signal line driving circuit 704. Multiple signal lines are connected to the signal line driving circuit in the pixel section 701. Extending from 704, multiple scan lines are arranged to drive the first scan line drive circuit 702 and the second It is arranged as an extension from the scan line drive circuit 703. Note the intersection region of the scan line and signal line. Each of these has pixels, each having a display element, arranged in a matrix. The board 700 is a connection part for FPC (Flexible Printed Circuit), etc. It is connected to the timing control circuit (also called a controller or control IC) via this.

[0444] Figure 38(A) shows the first scan line drive circuit 702, the second scan line drive circuit 703, and the signal line The drive circuit 704 is formed on the same substrate 700 as the pixel unit 701. Therefore, it is not externally installed. Since the number of components such as drive circuits is reduced, costs can be reduced. Also, the circuit board 7 If the drive circuit is located outside of 00, it becomes necessary to extend the wiring, increasing the number of connections between wires. It is possible to reduce the number of connections between the wiring when the drive circuit is placed on the same circuit board 700. This can improve reliability or yield. Circuit 702, the second scan line drive circuit 703, or the signal line drive circuit 704 are located on board 70 The configuration may be implemented on 0 or provided outside the circuit board 700.

[0445] <Liquid crystal display device> Furthermore, an example of the pixel circuit configuration is shown in Figure 38(B). Here, as an example, a VA-type liquid crystal display... This shows a pixel circuit that can be applied to the pixels of a display device.

[0446] This pixel circuit can be applied to configurations in which a single pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. It is configured to allow this to happen. This allows for the individual pixels of a multi-domain designed pixel to be... The signals applied to the electrode layer can be controlled independently.

[0447] The scan line 712 of transistor 716 and the scan line 713 of transistor 717 are different. It is separated so that a gate signal can be applied. On the other hand, signal line 714 is a transistor It is used in common with the transistor 716 and the transistor 717. The transistor 717 can be any transistor as described in Embodiments 1 to 3. This makes it possible to provide a highly reliable liquid crystal display device.

[0448] Furthermore, the first pixel electrode is electrically connected to transistor 716, and transistor 71 The second pixel electrode is electrically connected to 7. The first pixel electrode and the second pixel electrode are, They are separated. The shapes of the first and second pixel electrodes are as follows: There are no limitations. For example, the first pixel electrode can be V-shaped.

[0449] The gate electrode of transistor 716 is connected to scan line 712, and the gate electrode of transistor 717 The gate electrode is connected to scan line 713. Different gate signals are connected to scan line 712 and scan line 713. By assigning different numbers, the operating timings of transistors 716 and 717 are made different, and the liquid crystal The orientation can be controlled.

[0450] Furthermore, the capacitive wiring 710, the gate insulating layer which functions as a dielectric, and the first pixel electrode layer A retention capacitance may be formed by a capacitive electrode electrically connected to a second pixel electrode layer.

[0451] In a multi-domain design, each pixel is equipped with a first liquid crystal element 718 and a second liquid crystal element 719. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. It can be done.

[0452] Note that the pixel circuit shown in Figure 38(B) is not limited to this. For example, as shown in Figure 38(B) The pixel circuit now includes switches, resistors, capacitives, transistors, sensors, or logic You may add circuits or other components.

[0453] <Organic EL display device> Another example of a pixel circuit configuration is shown in Figure 38(C). Here, a display using an organic EL element is shown. The pixel structure of the device is shown.

[0454] Organic EL elements emit electrons from one of a pair of electrodes when a voltage is applied to the light-emitting element. On the other hand, holes are injected into layers containing luminescent organic compounds, and an electric current flows. Through the recombination of electrons and holes, the luminescent organic compound forms an excited state, It emits light when the excited state returns to the ground state. This mechanism explains why such light emission occurs. The device is called a current-excited light-emitting element.

[0455] Figure 38(C) shows an example of an applicable pixel circuit. Here, an n-channel type An example is shown where two transistors are used for one pixel. Furthermore, this pixel circuit is a digital time scale. A controlled drive can be applied.

[0456] Applicable pixel circuit configurations and pixel operation when digital time-gradation driving is applied. I will explain.

[0457] Pixel 720 consists of a switching transistor 721, a driving transistor 722, and a light-emitting element. It has a sub-element 724 and a capacitive element 723. The switching transistor 721 is a The source electrode layer is connected to scan line 726, and the first electrode (source electrode layer and drain electrode layer) One side is connected to signal line 725, and the second electrode (the other side of the source electrode layer and drain electrode layer) is connected to signal line 725. ) is connected to the gate electrode layer of the drive transistor 722. In 22, the gate electrode layer is connected to the power line 727 via the capacitive element 723, and the first electrode is electrically... The power line 727 is connected, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light-emitting element 724 corresponds to the common electrode 728. The common electrode 728 is identical. It is electrically connected to a common potential line formed on the substrate.

[0458] The switching transistor 721 and the driving transistor 722 are of the same type as in Embodiment 1. Transistors, as described in section 3, can be used as appropriate. This allows for highly reliable organic We can provide an EL display device.

[0459] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to the low power supply potential. The power supply potential is a potential lower than the high power supply potential supplied to power line 727, for example, GND. The forward threshold of the light-emitting element 724 The high and low power supply potentials are set so that they are equal to or greater than the value voltage, and the potential difference between them is used to power the light-emitting element 724 By applying a current to the light-emitting element 724, an electric current is passed through it, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and at least the forward voltage... Includes high-value voltage.

[0460] Furthermore, the capacitive element 723 is replaced by the gate capacitance of the drive transistor 722, thus saving space. It can be abbreviated.

[0461] Next, we will explain the signal input to the drive transistor 722. Voltage input Voltage drive method In this case, the driving transistor 722 is either fully on or completely off. A video signal like this is input to the drive transistor 722. To operate the 722 in the linear region, a voltage higher than the voltage of the power line 727 is used for the drive. It is applied to the gate electrode layer of transistor 722. Additionally, the signal line 725 is driven by the power line voltage. Apply a voltage greater than or equal to the threshold voltage Vth of transistor 722.

[0462] When performing analog grayscale driving, the gate electrode layer of the driving transistor 722 has an emissive element 72 A voltage greater than or equal to the sum of the forward voltage of transistor 4 and the threshold voltage Vth of the drive transistor 722. Apply the signal. Also, input the video signal so that the drive transistor 722 operates in the saturation region. This forces current to flow through the light-emitting element 724. Furthermore, the drive transistor 722 is operated in the saturation region. To achieve this, the potential of the power line 727 is set higher than the gate potential of the drive transistor 722. By converting the video signal to analog, the light-emitting element 724 receives a current corresponding to the video signal. It can perform flow and analog gradation driving.

[0463] Note that the pixel circuit configuration is not limited to the pixel configuration shown in Figure 38(C). For example, Figure 38 (C) The pixel circuit shown contains switches, resistors, capacitives, sensors, transistors or You can add circuits and other components.

[0464] When applying the transistor exemplified in the above embodiment to the circuit exemplified in Figure 38, the low potential The source electrode (first electrode) is on the side with the high potential, and the drain electrode (second electrode) is on the high potential side with the electrical currents. The configuration is designed to connect them precisely. Furthermore, the potential of the first gate electrode is controlled by a control circuit, etc. The second gate electrode is connected to a potential lower than the potential applied to the source electrode by wiring (not shown). The system should be configured to accept the potentials exemplified above, such as by applying them.

[0465] For example, in this specification, etc., display element, display device having a display element, light-emitting element A light-emitting device, which is a device having a sub-element and a light-emitting element, can be used in various forms or It can have various elements. Display elements, display devices, light-emitting elements, or light-emitting devices are, for example, EL (electroluminescent) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) (etc.), transistors (transistors that emit light in response to current), electron emission elements, liquid crystal elements Electronic ink, electrophoretic elements, grating light bulbs (GLV), plasma displays PDP (Photographic Display Panel), MEMS (Micro-Electro-Mechanical Systems), Digital Micromirror devices (DMD), DMS (Digital Microshutter), M IRASOL®, IMOD (Interference Modulation) element , electrowetting elements, piezoelectric ceramic displays, carbon nanotubes It has at least one display element that uses electrical or magnetic A display medium having properties such as contrast, brightness, reflectance, and transmittance that change due to atmospheric effects. It is acceptable to have them. An example of a display device using EL elements is an EL display. An example of a display device using an electron emission element is a field emission display ( FED) or SED flat-panel display (SED: Surface-conductive) Examples include liquid crystal elements (e.g., ion Electron-emitter Display). An example of a display device using this method is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). LCD displays, reflective LCD displays, direct-view LCD displays, projection LCD displays Examples include displays. Examples include electronic paper.

[0466] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0467] (Embodiment 8) In this embodiment, a display module to which a semiconductor device according to one aspect of the present invention is applied is shown in Figure We will use item 29 to explain.

[0468] <Display Module> The display module 6000 shown in Figure 39 consists of an upper cover 6001 and a lower cover 6002. In between, touch panel 6004 connected to FPC6003, and FPC6005 connected Display panel 6006, backlight unit 6007, frame 6009, printed circuit board It has 6010 and battery 6011. Furthermore, it has a backlight unit 6007 and battery Features such as the Lee 6011 and Touch Panel 6004 may not be available.

[0469] One embodiment of the present invention is, for example, a display panel 6006 or a printed circuit board. It can be used in integrated circuits that are implemented in [the device].

[0470] The upper cover 6001 and the lower cover 6002 are the touch panel 6004 and the display panel. The shape and dimensions can be appropriately modified to match the size of the 6006.

[0471] The touch panel 6004 is a resistive or capacitive touch panel. It can be used superimposed on 006. Also, the opposing substrate (encapsulation substrate) of the display panel 6006. It is also possible to give the display panel 6 a touch panel function. It is also possible to add an optical touch panel function by providing a light sensor within each pixel of 006. Yes. Alternatively, an electrode for a touch sensor can be provided within each pixel of the display panel 6006, and a capacitive method can be used. It is also possible to add a touch panel function to the model.

[0472] The backlight unit 6007 has a light source 6008. The light source 6008 is used as a backlight. A configuration using a light-diffusing plate, provided at the end of unit 6007, is also possible.

[0473] Frame 6009 provides protection for the display panel 6006, as well as generating signals from the printed circuit board 6010. It functions as an electromagnetic shield to block the generated electromagnetic waves. Also, the frame 600 9 may also function as a heat sink.

[0474] Printed circuit board 6010 is a power supply circuit and a signal for outputting video and clock signals. It has a power processing circuit. The power supply that provides power to the power supply circuit is an external commercial power supply. This is also fine, or a separate battery 6011 may be used. Battery 6011 can be omitted.

[0475] Furthermore, the display module 6000 includes additional components such as polarizing plates, phase difference plates, and prism sheets. They may also be provided.

[0476] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0477] (Embodiment 9) This embodiment describes an example of the use of a semiconductor device according to one aspect of the present invention.

[0478] <Package using a lead frame type interposer> Figure 40(A) shows the cross-sectional structure of a package using a lead frame type interposer. A perspective view is shown. The package shown in Figure 40(A) is a semiconductor device according to one aspect of the present invention. The corresponding chip 1751 is bonded to the interposer 1750 by wire bonding. It is connected to terminal 1752. Terminal 1752 is connected to chip 17 of interposer 1750. 51 is positioned on the surface on which it is mounted. And tip 1751 is molded resin It may be sealed by 1753, but with a portion of each terminal 1752 exposed during sealing. Make it happen.

[0479] The configuration of an electronic device (mobile phone) module with a package mounted on a circuit board is shown in the diagram. This is shown in Figure 40(B). The mobile phone module shown in Figure 40(B) is a printed circuit board 18 Unit 01 contains package 1802 and battery 1804. Also, the display element A printed circuit board 1801 is mounted on panel 1800, which is provided with a child, by FPC1803. It is implemented.

[0480] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0481] (Embodiment 10) In this embodiment, an electronic device and a lighting device according to one aspect of the present invention will be described with reference to the drawings. do.

[0482] <Electronic equipment> Electronic devices and lighting devices can be manufactured using a semiconductor device according to one embodiment of the present invention. Using a semiconductor device of one embodiment, highly reliable electronic devices and lighting devices can be manufactured. Electronic devices and lighting with improved touch sensor detection sensitivity using a semiconductor device according to one aspect of the invention We can manufacture the device.

[0483] Examples of electronic devices include television equipment (also known as televisions or television receivers). (u) Monitors for computers, digital cameras, digital video cameras, digital Photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game consoles, portable Examples include mobile information terminals, sound playback devices, and large game machines such as pachinko machines.

[0484] Furthermore, if an electronic device or lighting device according to one aspect of the present invention is flexible, it can be used on the interior walls of houses and buildings. Alternatively, it can be incorporated along the curved surfaces of exterior walls, or the interior or exterior of automobiles. ru.

[0485] Furthermore, an electronic device according to one aspect of the present invention may have a secondary battery and use contactless power transmission. It would be preferable if it could also charge a secondary battery.

[0486] Examples of secondary batteries include lithium polymer batteries (lithium iodine) which use a gel electrolyte. Lithium-ion secondary batteries (such as polymer batteries), lithium-ion batteries, nickel-metal hydride batteries Nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air-based rechargeable batteries, nickel-zinc batteries, silver-zinc batteries Examples include batteries.

[0487] An electronic device according to one aspect of the present invention may have an antenna. The antenna receives a signal. This allows the display unit to show images, information, etc. Also, electronic devices can use secondary batteries. If available, the antenna may be used for contactless power transmission.

[0488] Figure 41(A) shows a portable game console, comprising a casing 7101, casing 7102, display unit 7103, Display unit 7104, microphone 7105, speaker 7106, operation keys 7107, stylus It has 7108, etc. A semiconductor device according to one aspect of the present invention is built into a housing 7101 It can be used in integrated circuits, CPUs, etc. Display unit 7103 or display unit 7104 By using a light-emitting device according to one aspect of the present invention, the user experience is excellent and quality does not deteriorate. We can provide a portable game console that is less prone to problems. The game console has two display units 7103 and 7104, but the portable game The number of display units the device has is not limited to this.

[0489] Figure 41(B) shows a smartwatch, consisting of a casing 7302, a display unit 7304, and operation buttons. It has 7311, 7312, connection terminal 7313, band 7321, clasp 7322, etc. A semiconductor device according to one aspect of the present invention includes a memory, CPU, etc., built into a housing 7302. It can be used for this purpose.

[0490] Figure 41(C) shows a portable information terminal, which includes a display unit 7502 incorporated into the housing 7501, as well as Control buttons 7503, external connection port 7504, speaker 7505, microphone 7506 , and a display unit 7502, etc. A semiconductor device according to one aspect of the present invention is a housing 7501 It can be used for the mobile memory, CPU, etc. built into it. The 502 can achieve extremely high definition, making it full HD despite its small to medium size. It can display various resolutions, such as 4K or 8K, and obtain extremely sharp images. can.

[0491] Figure 41(D) shows a video camera, consisting of a first housing 7701, a second housing 7702, and a display unit 77 03, it has an operation key 7704, a lens 7705, a connector 7706, etc. Operation key 770 4 and lens 7705 are provided in the first housing 7701, and the display unit 7703 is in the second housing It is located in body 7702. And the first housing 7701 and the second housing 7702 are connected. They are connected by part 7706, and the angle between the first housing 7701 and the second housing 7702 is, The connection part 7706 can be used to change the video displayed in the display unit 7703. A configuration that switches according to the angle between the first housing 7701 and the second housing 7702 in 6. It is permissible to do so. The position at the focal point of lens 7705 may be equipped with an imaging device according to one embodiment of the present invention. This is possible. A semiconductor device according to one aspect of the present invention is a cluster built into the first housing 7701 It can be used in integrated circuits, CPUs, and the like.

[0492] Figure 41(E) shows a digital signage display unit 7902 installed on a utility pole 7901. The display device according to one aspect of the present invention is used in the control circuit of the display unit 7902. It is possible.

[0493] Figure 42(A) shows a notebook personal computer, consisting of a casing 8121 and a display unit 8122 The present invention includes a keyboard 8123, a pointing device 8124, and the like. The semiconductor device in question is applicable to the CPU and memory built into the housing 8121. Yes, it is possible. Furthermore, the display unit 8122 can be made with very high resolution, and is suitable for medium-sized and compact devices. It can display 8K resolution while simultaneously producing extremely sharp images.

[0494] Figure 42(B) shows the exterior of the automobile 9700. Figure 42(C) shows the driver's seat of the automobile 9700. The car 9700 consists of a body 9701, wheels 9702, dashboard 9703, and lights. It has the T9704, etc. A semiconductor device according to one aspect of the present invention is a display unit of an automobile 9700, and It can be used in integrated circuits for control. For example, the display unit 9710 shown in Figure 42(C) Alternatively, a semiconductor according to one aspect of the present invention can be provided in the display unit 9715.

[0495] Display units 9710 and 9711 are display devices installed on the windshield of an automobile, or is an input / output device. A display device or input / output device according to one aspect of the present invention is a display device, or Alternatively, by fabricating the electrodes of the input / output device from a light-transmitting conductive material, To create a display device or input / output device that is transparent, allowing the other side to be seen through, in other words, a see-through state. This is possible. If it is a see-through display device or input / output device, then the operation of the automobile 9700 It does not obstruct the view even when turning. Therefore, a display device or input / output display according to one aspect of the present invention The power device can be installed on the windshield of the automobile 9700. Furthermore, the display device, Alternatively, the input / output device may be equipped with a display device or a transistor for driving the input / output device. In such cases, organic transistors using organic semiconductor materials or transistors using oxide semiconductors are used. It is advisable to use a transmissive transistor, such as a light-transmitting transistor.

[0496] The display unit 9712 is a display device provided on the pillar portion. For example, a camera provided on the vehicle body By displaying the image from the imaging device on the display unit 9712, the field of view obstructed by the pillar is compensated for. It can be completed. The display unit 9713 is a display device provided on the dashboard. For example, by displaying images from an imaging device installed on the vehicle body on the display unit 9713, This allows you to compensate for the view obstructed by the dashboard. In other words, on the outside of the car By displaying images from the installed imaging device, blind spots are compensated for, and safety is enhanced. This is possible. Furthermore, by displaying images that fill in the gaps in the unseen areas, it becomes more natural and less jarring. Safety checks can be performed without any issues.

[0497] Furthermore, Figure 42(D) shows the interior of a car with bench seats for both the driver and passenger. The display unit 9721 is a display device or input / output device provided in the door section. By displaying the image from the imaging means installed on the vehicle body on the display unit 9721, It can compensate for the field of view obstructed by A. Also, the display unit 9722 is provided on the handle. This is a display device. The display unit 9723 is a display provided in the center of the seat surface of the bench seat. It is a device. Furthermore, the display device is installed on the seat or backrest, and the display device is... The heat generated by the display device can also be used as a seat heater.

[0498] Display unit 9714, display unit 9715, or display unit 9722 displays navigation information, speed This includes the odometer, tachometer, mileage, fuel level, gear status, air conditioning settings, and more. It can provide various kinds of information. Also, the display items and layout displayed on the display unit can be customized. These can be changed as needed to suit the user's preferences. The above information is displayed on the display unit 9. It can also be displayed on display units 710 to 9713, display unit 9721, and display unit 9723. Furthermore, the display units 9710 to 9715 and 9721 to 9723 are illuminated. It can also be used as a device. In addition, display units 9710 to 9715, display unit Units 9721 through 9723 can also be used as heating devices.

[0499] Figure 43(A) also shows the external appearance of camera 8000. Camera 8000 is housed in housing 8001 , display unit 8002, operation button 8003, shutter button 8004, coupling unit 8005, etc. It has [a certain feature]. Furthermore, the camera 8000 can be fitted with a lens 8006.

[0500] The coupling portion 8005 has electrodes and, in addition to the viewfinder 8100 described later, also a strobe device, etc. It can be connected.

[0501] Here, we'll use camera 8000 and replace lens 8006 by removing it from housing 8001. While this configuration allows for such a setup, the lens 8006 and the housing could also be integrated.

[0502] By pressing the shutter button 8004, an image can be taken. Also, the display unit 80 Unit 02 functions as a touch panel, and by touching the display unit 8002, imaging is performed. It is also possible to do so.

[0503] A display device or input / output device according to one aspect of the present invention can be applied to the display unit 8002. ru.

[0504] Figure 43(B) shows an example of the camera 8000 with the viewfinder 8100 attached. It is.

[0505] The viewfinder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc.

[0506] The housing 8101 has a coupling portion that engages with the coupling portion 8005 of the camera 8000, The viewfinder 8100 can be attached to the camera 8000. Furthermore, the connection point is electrically powered. It has electrodes, and displays images and other data received from camera 8000 via these electrodes on display unit 8102. It can be made to happen.

[0507] Button 8103 functions as a power button. Button 8103 activates the display unit 8 You can switch the display of 102 on or off.

[0508] A semiconductor device according to one aspect of the present invention is applied to the integrated circuit and image sensor located inside the housing 8101. It can be used.

[0509] Note that in Figures 43(A) and 43(B), the camera 8000 and the viewfinder 8100 are connected to separate electronic devices. The container was designed to be detachable, but the housing 8001 of the camera 8000 is the present invention. A viewfinder equipped with a display device or input / output device of one form may be incorporated.

[0510] Figure 43(C) also shows the external appearance of the head-mounted display 8200.

[0511] The head-mounted display 8200 consists of the mounting part 8201, the lens 8202, and the main body 820 3. It has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has a battery It has a built-in TERI 8206 chip.

[0512] Cable 8205 supplies power from battery 8206 to main unit 8203. Main unit 820 3 is equipped with a wireless receiver and displays received video information such as image data on the display unit 8204. It is possible to do so. In addition, the camera installed in the main unit 8203 can capture the movement of the user's eyeballs and eyelids. By capturing this information and calculating the coordinates of the user's viewpoint based on that information, the user's viewpoint is entered. It can be used as a means of force.

[0513] Furthermore, the attachment portion 8201 may be provided with multiple electrodes in positions that come into contact with the user. The main unit 8203 detects the current flowing through the electrodes in response to the user's eye movements, It may also have a function to recognize the user's viewpoint. Furthermore, it may detect the current flowing through the electrode. This may provide a function to monitor the user's pulse. Also, the attachment part 8201 It may have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc., and may have a function of displaying the biological information of the user on the display unit 8204. Also, it may detect the movement of the user's head, etc., and change the video displayed on the display unit 8204 according to the movement. 者の生体情報を表示部8204に表示する機能を有していてもよい。また、使用者の頭部 の動きなどを検出し、表示部8204に表示する映像をその動きに合わせて変化させても よい。

[0514] The semiconductor device according to an aspect of the present invention can be applied to the integrated circuit inside the main body 8203. 。

[0515] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. 合わせて実施することができる。

[0516] (Embodiment 11) In this embodiment, a usage example of an RF tag using the semiconductor device according to an aspect of the present invention will be described with reference to FIG. 44. 図44を用いながら説明する。

[0517] <Usage Example of RF Tag> The applications of RF tags are extensive. For example, banknotes, coins, securities, bearer bonds, documents (such as driver's licenses and resident cards, see FIG. 44(A)), vehicles (such as bicycles, see FIG. 44(B) 参照)、包装用容器類(包装紙やボトル等、図44(C)参照)、記録媒体(DVDやビ 参照)、身の回り品(鞄や眼鏡等、図44(D)参照)、食品類、植物類、動物類、 デオテープ等、身の回り品(鞄や眼鏡等、図44(D)参照)、食品類、植物類、動物類、 人体、衣類、生活用品類、薬品や薬剤を含む医療品、または電子機器(液晶表示装置、E L表示装置、テレビジョン装置、または携帯電話)等の物品、若しくは各物品に取り付け る荷札(図44(E)、図44(F)参照)等に設けて使用することができる。

[0518] The RF tag 4000 according to an aspect of the present invention can be attached to the surface or embedded in an object. It is fixed to the product. For example, in the case of a book, it is embedded in the paper, and in the case of a package made of organic resin. The RF tag is embedded inside the organic resin and fixed to each article. The 4000 is designed to be small, thin, and lightweight, and even after being fixed to an object, it does not affect the design of the object itself. It does not impair the integrity of banknotes, coins, securities, bearer bonds, or certificates. By providing an RF tag 4000 according to one aspect of the present invention to the same type of object, an authentication function can be provided. This allows for counterfeiting to be prevented by utilizing this authentication function. Furthermore, packaging containers... The present invention applies to items such as recording media, personal belongings, food products, clothing, household goods, or electronic devices. By attaching RF tags related to the configuration, the efficiency of systems such as inspection systems can be improved. It is possible to attach an RF tag according to one aspect of the present invention to vehicles as well. This enhances security against theft and other crimes.

[0519] As described above, an RF tag using a semiconductor device according to one aspect of the present invention is provided in this embodiment. By using it for each of the listed applications, the operating power, including information writing and reading, can be reduced. Therefore, it becomes possible to extend the maximum communication range. Also, even when the power is cut off Because it can retain information for extremely long periods, it is also suitable for applications where the frequency of writing and reading is low. It can be used suitably.

[0520] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible. [Explanation of symbols]

[0521] 10 transistors 11 transistors 12 transistors 13 transistors 14 transistors 63 Semiconductor layer 64 Semiconductor layer 65 Semiconductor layer 100 circuit boards 110 Insulating layer 120 oxide semiconductor layer 121 Oxide semiconductor layer 122 Oxide semiconductor layer 123 Oxide semiconductor layer 123a Oxide semiconductor film 124 oxide semiconductor layer 130 Source electrode layer 130b conductive layer 131 Source electrode layer 132 Source electrode layer 135 Conductive layer 140 Drain electrode layer 141 Drain electrode layer 142 Drain electrode layer 150 Gate Insulation Layer 150a insulating film 160 Grid Unit Layer 160a conductive film 161 Grid control platform 162 Grid control layer 163 Grid control layer 165 Conductive layer 166 Conductive layer 167 Conductive layer 170 Insulating layer 171 Mixed layer 172 Oxygen 174 Groove 175 Insulating layer 175b Insulating layer 176 Resist Mask 177 Insulating layer 180 Insulating layer 185 Insulating layer 190 conductive layer 191 Conductive layer 192 Conductive layer 200 Imaging device 201 Switch 202 Switch 203 Switch 210 pixel section 211 pixels 212 subpixels 212B subpixels 212G sub-pixels 212R sub-pixels 220 Photoelectric conversion element 230-pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 filters 254B filter 254G filter 254R filter 255 lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 silicon substrates 310 layers 320 layers 330 layers 340 layers 351 transistors 352 transistors 353 transistors 360 Photodiodes 361 Anodes 362 Cathode 363 Low resistance region 365 Photodiodes 366 Semiconductor Layers 367 Semiconductor layer 368 Semiconductor Layers 370 plug 371 Wiring 372 Wiring 373 Wiring 374 Wiring 601 Precasa 602 Precasa 700 circuit boards 701 pixel section 702 Scan Line Drive Circuit 703 Scan line drive circuit 704 Signal Line Drive Circuit 710 Capacitance wiring 712 scan lines 713 scan lines 714 signal line 716 transistors 717 transistors 718 Liquid crystal elements 719 Liquid crystal elements 720 pixels 721 Switching Transistors 722 Driver Transistor 723 Capacitive element 724 Light-emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RF tags 801 Communication device 802 Antenna 803 Wireless signal 804 Antenna 805 Rectifier circuit 806 Constant Voltage Circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuits 810 Memory circuit 811 ROM 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Element 1207 Capacitive element 1208 Capacitive element 1209 Transistors 1210 Transistors 1213 Transistors 1214 Transistors 1220 Circuit 1223 Oxide semiconductor layer 1700 Substrate to be coated 1701 Chamber 1702 Road Room 1703 Pre-processing room 1704 Chamber 1705 Chamber 1706 Unloading Room 1711a Raw material supply section 1711b Raw material supply section 1712a High-speed valve 1712b High-speed valve 1713a Raw material inlet 1713b Raw material inlet 1714 Raw material discharge port 1715 Exhaust system 1716 PCB holder 1720 Transport Room 1750 Interposer 1751 chips 1752 terminal 1753 Mold resin 1800 panels 1801 Printed Wiring Board 1802 Package 1803 FPC 1804 Battery 2100 transistors 2200 transistors 2201 Insulator 2202 Wiring 2203 Plug 2204 Insulator 2205 Wiring 2207 Insulator 2210 Mesopotamian 2211 Semiconductor substrate 2212 Insulator 2213 Terminal 2214 Gate Insulator 2215 Drain area 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitive element 4000 RF tags 5100 pellets 5120 circuit board 5161 area 6000 Display Module 6001 Top cover 6002 Lower cover 6003 FPC 6004 Touch Panel 6005 FPC 6006 Display Panel 6007 Backlight Unit 6008 Light source 6009 Frame 6010 Printed Circuit Board 6011 Battery 7101 enclosure 7102 enclosure 7103 Display section 7104 Display sec...

Claims

[Claim 1] The first insulating layer, The first oxide semiconductor layer on the first insulating layer, The second oxide semiconductor layer on the first oxide semiconductor layer, The source electrode layer and drain electrode layer on the second oxide semiconductor layer, The first insulating layer, the source electrode layer, and the second insulating layer on the drain electrode layer, The third insulating layer on the second insulating layer, A third oxide semiconductor layer on the second oxide semiconductor layer, The gate insulating layer on the third oxide semiconductor layer, The gate electrode layer on the gate insulating layer, It has, The second insulating layer is an oxygen barrier layer having regions in contact with the side surface of the first oxide semiconductor layer, the side surface of the second oxide semiconductor layer, the side surface of the source electrode layer, and the side surface of the drain electrode layer. The third oxide semiconductor layer has regions that are in contact with the side surface of the second oxide semiconductor layer, the side surface of the source electrode layer, the side surface of the drain electrode layer, the side surface of the second insulating layer, and the side surface of the third insulating layer. A semiconductor device characterized by the following.

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