Pad structure for semiconductor devices

Abstract

We provide semiconductor devices. [Solution] An aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a first die and a second die that are face-joined. The first die includes a first transistor formed on the front side of the first die in the semiconductor portion and a contact structure disposed in an insulating portion outside the semiconductor portion. The second die includes a substrate and a second transistor formed on the front side of the second die. Furthermore, the semiconductor device includes a first pad structure disposed on the back side of the first die, the first pad structure being conductively coupled to the contact structure. The ends of the contact structure protrude from the insulating portion into the first pad structure. Furthermore, in some embodiments, the semiconductor device includes a connection structure disposed on the back side of the first die and conductively coupled to the semiconductor portion.

Description

Technical Field

[0001] This application generally describes embodiments related to semiconductor memory devices.

Background Art

[0002] Generally, semiconductor devices (e.g., semiconductor chips) communicate with the external world via various input / output (I / O) pad structures, such as signaling pad structures, power / ground (P / G) pad structures, etc. In some examples, a semiconductor chip can include a plurality of metal layers formed on a circuit above a substrate. One or more metal layers are used to form pad structures that are conductively coupled to the circuit above the substrate. The pad structures can be formed to facilitate the attachment of bonding wires that can conductively couple the pad structures to external components, such as power supplies, grounds, other semiconductor chips, metal lines on a printed circuit board (PCB), etc.

Summary of the Invention

Means for Solving the Problems

[0003] Aspects of the present disclosure provide a semiconductor device. The semiconductor device includes a first die and a second die that are face-to-face joined. The first die includes a first transistor formed on a front side of the first die within a semiconductor portion and a contact structure disposed at least within an insulating portion outside the semiconductor portion. The second die includes a substrate and a second transistor formed on a front side of the second die. Further, the semiconductor device includes a first pad structure disposed on a back side of the first die, and the first pad structure is conductively coupled to the contact structure. An end of the contact structure protrudes from the insulating portion into the first pad structure. Further, in some embodiments, the semiconductor device includes a connection structure disposed on the back side of the first die and conductively connected to the semiconductor portion.

[0004] In one embodiment, the interface between the connecting structure and the semiconductor portion is substantially flat on the semiconductor portion. In some examples, the lower and upper end faces of the connecting structure on the semiconductor portion are approximately the same size.

[0005] In some embodiments, the contact structure includes at least a first metallic material different from a second metallic material in the first pad structure. In one example, the first metallic material includes tungsten and the second metallic material includes aluminum.

[0006] In some examples, due to the protrusion of the end of the contact structure, the lower end surface of the first pad structure that forms an interface with the insulating portion has a recess corresponding to the end of the contact structure.

[0007] In some embodiments, the first die includes at least a memory cell array formed on a semiconductor portion, and the second die includes peripheral circuits for the memory cell array. Contact structures on the first die are electrically coupled to input / output circuits on the second die via bonding structures.

[0008] In some embodiments, the first die includes input / output circuits electrically coupled to a contact structure.

[0009] Aspects of this disclosure provide a method for manufacturing a semiconductor device. The method includes the step of joining a first die and a second die face to face. The first die includes a first substrate, a first transistor formed in the semiconductor portion on the front side of the first die, and a contact structure disposed in an insulating portion outside the semiconductor portion. The second die includes a second substrate having a second transistor formed on the front side of the second substrate. Furthermore, the method includes the step of removing the first substrate from the back side of the first die. Removal of the first substrate exposes the ends of the contact structure on the back side of the first die. The method then includes the step of forming a first pad structure on the back side of the first die, which is conductively connected to the contact structure. The ends of the contact structure protrude inward from the insulating portion into the first pad structure.

[0010] In some embodiments, the method further includes the step of forming a connection structure on the back side of the first die that is electrically connected to the semiconductor portion. In one embodiment, the semiconductor portion is exposed from the back side of the first die by removing the first substrate, and the method also includes the step of depositing a layer for forming the connection structure. The interface of this layer with respect to the semiconductor portion is substantially flat across the semiconductor portion. In some examples, the method includes patterning the layer for forming the connection structure. The lower and upper end faces of the connection structure on the semiconductor portion are substantially the same size.

[0011] In some embodiments, the method includes the step of depositing a second metallic material, different from the first metallic material, onto a contact structure which includes at least a first metallic material. The first pad structure includes at least the second metallic material. The first metallic material can be tungsten, and the second metallic material can be aluminum, in one example.

[0012] The aspects of this disclosure will be best understood from the following detailed description when read in conjunction with the attached figures. Note that, in accordance with standard industry practice, various features are not depicted to scale. In fact, for the sake of clarity, the dimensions of various features may be arbitrarily increased or decreased. [Brief explanation of the drawing]

[0013] [Figure 1] This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. [Figure 2] This is a flowchart outlining the process for forming semiconductor devices. [Figure 3] This is a cross-sectional view of a semiconductor device during the manufacturing process according to several embodiments. [Figure 4] This is a cross-sectional view of a semiconductor device during the manufacturing process according to several embodiments. [Figure 5] This is a cross-sectional view of a semiconductor device during the manufacturing process according to several embodiments. [Figure 6] This is a cross-sectional view of a semiconductor device during the manufacturing process according to several embodiments. [Modes for carrying out the invention]

[0014] The following disclosure provides many different embodiments or examples for carrying out different features of the subject matter provided. Specific examples of components and arrangements are described below for the sake of brevity of the disclosure. Of course, these are merely examples and are not intended to limit the scope. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features so that the first and second features are not in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various embodiments. This repetition is for the sake of brevity and clarity and does not in itself indicate relationships between the various embodiments and / or between the configurations considered.

[0015] Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to facilitate descriptions of the relationship between one element or feature and another, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be oriented in other ways (by 90-degree rotation or other directions), and the spatially relative descriptors used herein shall be interpreted accordingly.

[0016] Aspects of this disclosure provide techniques for forming pad structures for a semiconductor device comprising two face-to-face bonded dies (e.g., a first die and a second die). The pad structures are formed on the back side of one of the two dies, e.g., the first die. The techniques for forming pad structures simplify the process of forming pad structures by eliminating the need to form through-silicon contacts (TSCs) from the back side of the first die. In some embodiments, circuit components are formed on the front sides of the two dies. Furthermore, at least a contact structure is formed from the front side of the first die within the insulating portion of the first die, and this contact structure is connected to an input / output (I / O) circuit. One of the pad structures on the back side of the first die, such as the first pad structure, is conductively coupled to a contact structure, and the contact structure includes an end projecting inward from the insulating portion into the first pad structure. In some examples, the first die includes a semiconductor portion comprising a transistor formed within the semiconductor portion. In some embodiments, a connection structure is formed in the pad structure and conductively coupled to the semiconductor portion. In one example, the connection structure is conductively coupled to the semiconductor portion without forming contacts based on contact holes from the back side of the first die. In some examples, the pad structure and the connection structure can be formed using the same metal layer.

[0017] According to some aspects of this disclosure, a semiconductor memory device can be a semiconductor memory device in which one of two dies includes a memory cell array formed on the front side and is called an array die, and the other of the two dies includes peripheral circuits formed on the front side and is called a peripheral die. In some examples, the peripheral circuits are formed using complementary metal-oxide-semiconductor (CMOS) technology and the peripheral die is also called a CMOS die. Pad structures and connection structures can be formed on the back side of the array die or on the back side of the peripheral die.

[0018] In some embodiments, the pad structure and connection structure are formed on the back side of the array die. The array die includes a memory cell array formed on the semiconductor portion. Then, in one example, the connection structure conductively coupled to the semiconductor portion can be configured to provide a connection of the memory cell array to an array common source (ACS).

[0019] According to some aspects of this disclosure, two dies (e.g., an array die and a peripheral die) are formed separately on two wafers. In some embodiments, a first wafer containing the array die and a second wafer containing the peripheral die are formed separately. For example, the first wafer can be manufactured to optimize the density and performance of the memory cell array without compromising on the manufacturing limitations imposed by the peripheral circuitry. Similarly, the second wafer can be manufactured to optimize the performance of the peripheral circuitry without compromising on the manufacturing limitations imposed by the memory cell array. In some embodiments, the first and second wafers can be joined face-to-face using wafer bonding technology, so that the array die on the first wafer is bonded to the peripheral die on the second wafer, respectively. The technology provided in this disclosure can then be used to manufacture a pad structure on the back side of one of the two wafers.

[0020] Figure 1 shows a cross-sectional view of a semiconductor device, such as semiconductor memory device 100, according to some embodiments of the present disclosure. The semiconductor memory device 100 comprises two dies that are face-to-face bonded. Pad structures and connection structures are formed on the back side of one of the two dies using techniques provided in the present disclosure.

[0021] Specifically, in the example of FIG. 1, the semiconductor memory device 100 includes a face-to-face joined array die 102 and a CMOS die 101. Note that in some embodiments, the semiconductor memory device can include a plurality of array dies and a CMOS die. The plurality of array dies and the CMOS die can be stacked and joined to each other. Each CMOS die can be coupled to a plurality of array dies to drive each array die in a similar manner.

[0022] The semiconductor device 100 can be any suitable device. In some examples, the semiconductor device 100 includes at least a first wafer and a second wafer that are face-to-face joined. The array die 102 is arranged together with other array dies on the first wafer, and the CMOS die 101 is arranged together with other CMOS dies on the second wafer. The first wafer and the second wafer are joined to each other, that is, the array die on the first wafer is joined to the corresponding CMOS die on the second wafer. In some examples, the semiconductor device 100 is a semiconductor chip having at least an array die 102 and a CMOS die 101 joined to each other. In one example, the semiconductor chip is cut from wafers joined to each other. In another example, the semiconductor device 100 is a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0023] The array die 102 includes one or more semiconductor portions 105 and an insulating portion 106 between the semiconductor portions 105. The memory cell array can be formed within the semiconductor portion 105, and the insulating portion can isolate the semiconductor portions 105 and provide a space for the contact structure 170. The CMOS die 101 includes a substrate 104 and peripheral circuits formed on the substrate 104. For simplicity, the main surface (of the die or wafer) is referred to as the X-Y plane, and the direction perpendicular to the main surface is referred to as the Z direction.

[0024] In addition, in the example in Figure 1, the connection structure 121 and pad structures 122-123 are formed on the back side of one of two dies, such as the array die 102. Specifically, in the example in Figure 1, the pad structures 122-123 are located above the insulating portion 106, and each of the pad structures 122-123 can be electrically connected to one or more contact structures 170. In the example in Figure 1, the connection structure 121 is located above the semiconductor portion 105 and is electrically connected to the semiconductor portion 105. In some examples, the semiconductor portion 105 is coupled to an array common source (ACS) for the memory cell array, and the connection structure 121 is located above the semiconductor portion 105 for the blocks of the memory cell array. In some examples, the connection structure 121 is formed of a metal layer with relatively low resistivity, and if the connection structure 121 covers a relatively large portion of the semiconductor portion 105, the connection structure 121 can connect the ACS of the blocks of the memory cell array with very low parasitic resistance. The connection structure 121 may include a portion configured as a pad structure for the ACS to receive ACS signals from an external source. The pad structures 122-123 and the connecting structure 121 are made of a suitable metal material, such as aluminum, which facilitates the attachment of bonding wires. In some examples, the pad structures 122-123 include a titanium layer 126 and an aluminum layer 128, and the connecting structure 121 includes a titanium silicide layer 127 and an aluminum layer 128.

[0025] Please note that, for the sake of ease of illustration, some components of the semiconductor memory device 100, such as the passivation structure, are not shown.

[0026] The array die 102 initially includes a substrate and a semiconductor portion 105, and an insulating portion 106 is formed on the substrate. The substrate is removed before the formation of the pad structures 122-123 and the connection structure 121.

[0027] Figure 2 is a flowchart outlining a process 200 for forming a semiconductor memory device, such as the semiconductor memory device 100 according to some embodiments of this disclosure, and Figures 3 to 6 show cross-sectional views of the semiconductor device 100 during the process according to some embodiments. Process 200 begins at S201 and proceeds to S210.

[0028] In S210, the first die and the second die are joined face to face. The first die includes a first substrate and a semiconductor portion and an insulating portion disposed on the front side of the first substrate. The insulating portion can insulate the semiconductor portion. The first die also includes a first transistor formed within the semiconductor portion from the front side of the first die. Furthermore, the first die includes a contact structure disposed within the insulating portion outside the semiconductor portion. The insulating portion insulates the contact structure from each other and can also insulate it from the semiconductor portion. The second die includes a second substrate having a second transistor formed on the front side of the second die.

[0029] In some embodiments, the first die is an array die, such as array die 102, and the second die is a CMOS die, such as CMOS die 101. In some examples, the first die can be a CMOS die and the second die can be an array die.

[0030] Figure 3 shows a cross-sectional view of the semiconductor memory device 100 after the bonding process of the two dies. The semiconductor memory device 100 includes an array die 102 and a CMOS die 101 that are bonded face to face.

[0031] In some embodiments, the array die 102 is manufactured together with other array dies on the first wafer, and the CMOS die 101 is manufactured together with other CMOS dies on the second wafer. In some examples, the first and second wafers are manufactured separately. For example, the memory cell array and I / O contact structure are formed on the first wafer using a process that operates on the front side of the first wafer. Also, the first bonding structure is formed on the front side of the first wafer. Similarly, peripheral circuits are formed on the second wafer using a process that operates on the front side of the second wafer, and the second bonding structure is formed on the front side of the second wafer.

[0032] In some embodiments, a first wafer and a second wafer can be joined face-to-face using wafer-to-wafer bonding technology. A first bonding structure on the first wafer is bonded to a corresponding second bonding structure on the second wafer, and thus array dies on the first wafer are bonded to CMOS dies on the second wafer, respectively.

[0033] The array die 102 includes a substrate 103. One or more semiconductor portions 105 and insulating portions 106 are formed on the substrate 103. The insulating portion 106 is formed of an insulating material that can insulate the semiconductor portion 105, such as silicon oxide. Furthermore, a memory cell array can be formed on the semiconductor portion 105, and a contact structure can be formed on the insulating portion 106. The CMOS die 101 includes a substrate 104 and peripheral circuits formed on the substrate 104.

[0034] Substrates 103 and 104 can each be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. Substrates 103 and 104 can each contain semiconductor materials, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. The group IV semiconductor can include Si, Ge, or SiGe. Substrates 103 and 104 may each be a bulk wafer or an epitaxial layer. In some examples, the substrate is formed of multiple layers. For example, as shown in Figure 3, substrate 103 includes multiple layers, such as a bulk portion 111, a silicon oxide layer 112, and a silicon nitride layer 113.

[0035] In the example shown in Figure 3, a memory cell array is formed on the substrate 103 of the array die 102, and peripheral circuits are formed on the substrate 104 of the CMOS die 101. The array die 102 and the CMOS die 101 are positioned facing each other (the surface on which the circuits are arranged is called the front, and the opposite surface is called the back), and are joined to each other.

[0036] In some examples, a semiconductor section 105 is formed on a substrate 103, and a block of three-dimensional (3D) NAND memory cell strings can be formed within the semiconductor section 105. The semiconductor section 105 is conductively coupled to a common source of the array of memory cell strings. In some examples, the memory cell array is formed in a core region 115 as an array of vertical memory cell strings. In addition to the core region 115, the array die 102 includes a step region 116 and an isolation region 117. The step region 116 is used to facilitate connections, for example, to the gates of memory cells in the vertical memory cell string, the gates of selection transistors, etc. The gates of memory cells in the vertical memory cell string correspond to word lines for the NAND memory architecture. The isolation region 117 is used to form the isolation section 106.

[0037] In the example shown in Figure 3, the vertical memory cell string 180 is shown as a representation of an array of vertical memory cell strings formed in the core region 115. The vertical memory cell string 180 is formed within a stack of layers 190. The stack of layers 190 includes alternately stacked gate layers 195 and insulating layers 194. The gate layers 195 and insulating layers 194 are configured to form vertically stacked transistors. In some examples, the stack of transistors includes memory cells and selection transistors, such as one or more bottom selection transistors, one or more top selection transistors, etc. In some examples, the stack of transistors may include one or more dummy selection transistors. The gate layer 195 corresponds to the gate of the transistor. The gate layer 195 is made of a gate stacking material, such as a high-dielectric constant (high-k) gate insulator layer, a metal gate (MG) electrode, etc. The insulating layer 194 is made of an insulating material, such as silicon nitride, silicon dioxide, etc.

[0038] According to some aspects of this disclosure, a vertical memory cell string is formed by channel structures 181 extending vertically (Z-direction) within a stack of layers 190. The channel structures 181 can be arranged separately from each other in the XY plane. In some embodiments, the channel structures 181 are arranged in the form of an array between gate line cut structures (not shown). The gate line cut structures are used to facilitate the replacement of the sacrificial layer by the gate layer 195 in a gate-last process. The array of channel structures 181 can have any suitable array shape, e.g., a matrix array shape along the X and Y directions, a zigzag array shape along the X or Y direction, a honeycomb (e.g., hexagonal) array shape, etc. In some embodiments, each of the channel structures has a circular shape in the XY plane and a pillar shape in the XZ and YZ planes. In some embodiments, the quantity and arrangement of channel structures between gate line cut structures are not limited.

[0039] In some embodiments, the channel structure 181 has a pillar shape extending in the Z direction perpendicular to the direction of the main surface of the substrate 103. In embodiments, the channel structure 181 is formed of a circular material in the XY plane and extends in the Z direction. For example, the channel structure 181 includes functional layers, e.g., a blocking insulating layer 182 (e.g., silicon oxide), a charge storage layer 183 (e.g., silicon nitride), a tunnel insulating layer 184 (e.g., silicon oxide), a semiconductor layer 185, and an insulating layer 186 that is circular in the XY plane and extends in the Z direction. In one example, the blocking insulating layer 182 (e.g., silicon oxide) is formed on the sidewall of the hole for the channel structure 181 (in the stack of layers 190), and then the charge storage layer 183 (e.g., silicon nitride), the tunnel insulating layer 184, the semiconductor layer 185, and the insulating layer 186 are sequentially stacked from the sidewall. The semiconductor layer 185 can be any suitable semiconductor material, such as polysilicon or single-crystal silicon, and the semiconductor material may be undoped or may contain p-type or n-type dopants. In some examples, the semiconductor material is an undoped intrinsic silicon material. However, due to defects, the intrinsic silicon material may, in some examples, 10 10 cm -3 It can have a carrier density of the order of . The insulating layer 186 may be formed of an insulating material such as silicon oxide and / or silicon nitride, and / or as voids.

[0040] According to some aspects of this disclosure, the channel structure 181 and the stack of layers 190 together form a memory cell string 180. For example, the semiconductor layer 185 corresponds to the channel portion of a transistor in the memory cell string 180, and the gate layer 195 corresponds to the gate of a transistor in the memory cell string 180. Generally, a transistor has a gate that controls the channel, and there are drains and sources on both sides of the channel. For simplicity, in the example of Figure 3, the bottom side of the channel for the transistor in Figure 3 is called the drain, and the top side of the channel for the transistor in Figure 3 is called the source. Note that the drain and source can be switched under certain driving configurations. In the example of Figure 3, the semiconductor layer 185 corresponds to the connected channel of a transistor. For a particular transistor, the drain of that particular transistor is connected to the source of the lower transistor below that particular transistor, and the source of that particular transistor is connected to the drain of the upper transistor above that particular transistor in the example of Figure 3. This connects the transistors in the memory cell string 180 in series. Note that "upper" and "lower" are used specifically in Figure 3, where the array die 102 is arranged upside down.

[0041] The memory cell string 180 includes memory cell transistors (or memory cells). The memory cell transistors can have different threshold voltages based on carrier trapping in the portion of the charge storage layer 183 corresponding to the floating gate for the memory cell transistor. For example, if a significant amount of holes are trapped (stored) in the floating gate of the memory cell transistor, the threshold voltage of the memory cell transistor is lower than a predetermined value, and the memory cell transistor is in an unprogrammed state (also called the erased state), corresponding to logic "1". When the holes are discharged from the floating gate, the threshold voltage of the memory cell transistor exceeds a predetermined value, and therefore the memory cell transistor is in a programmed state, corresponding to logic "0" in some examples.

[0042] The memory cell string 180 includes one or more top selection transistors configured to couple / disconnect memory cells in the memory cell string 180 to bit lines, and one or more bottom selection transistors configured to couple / disconnect memory cells in the memory cell string 180 to ACS.

[0043] The top-select transistor is controlled by a top-select gate (TSG). For example, if the TSG voltage (voltage applied to the TSG) is greater than the threshold voltage of the top-select transistor, the top-select transistor in the memory cell string 180 is turned on, and the memory cells in the memory cell string 180 are coupled to the bit lines (for example, the drains of the memory cell strings are coupled to the bit lines). If the TSG voltage (voltage applied to the TSG) is less than the threshold voltage of the top-select transistor, the top-select transistor is turned off, and the memory cells in the memory cell string 180 are disconnected from the bit lines (for example, the drains of the memory cell strings are disconnected from the bit lines).

[0044] Similarly, the bottom selection transistor is controlled by a bottom selection gate (BSG). For example, if the BSG voltage (voltage applied to the BSG) is greater than the threshold voltage of the bottom selection transistor in the memory cell string 180, the bottom selection transistor is turned on, and the memory cells in the memory cell string 180 are coupled to the ACS (for example, the sources of the strings of memory cells in the memory cell string 180 are coupled to the ACS). If the BSG voltage (voltage applied to the BSG) is less than the threshold voltage of the bottom selection transistor, the bottom selection transistor is turned off, and the memory cells are disconnected from the ACS (for example, the sources of the strings of memory cells in the memory cell string 180 are disconnected from the ACS).

[0045] As shown in Figure 3, the upper part of the semiconductor layer 185 in the channel hole corresponds to the source side of the vertical memory cell string 180, and the upper part is labeled 185(S). In the example in Figure 3, a common source layer 189 is formed by conductive connection to the source of the vertical memory cell string 180. The common source layer 189 may include one or more layers. In some examples, the common source layer 189 includes silicon material, e.g., intrinsic polysilicon, doped polysilicon (e.g., N-type doped silicon, P-type doped silicon, etc.), and others. In some examples, the common source layer 189 may include a metal silicide to improve conductivity. The common source layer 189 is similarly conductively connected to the sources of other vertical memory cell strings (not shown) in the semiconductor section 105, thus forming an array common source (ACS).

[0046] According to some aspects of the present disclosure, the semiconductor portion 105 and the common source layer 189 are conductively coupled in some examples, and thus the semiconductor portion 105 can be configured as an array common source for a vertical memory cell string formed in the semiconductor portion 105.

[0047] In the example shown in Figure 3, in the channel structure 181, the semiconductor layer 185 extends vertically downward from the source side of the channel structure 181, forming the bottom corresponding to the drain side of the vertical memory cell string 180. The bottom of the semiconductor layer 185 is labeled 185(D). Note that the drain side and source side are named for ease of explanation. The drain side and source side may perform functions different from those indicated by their names.

[0048] In the example shown in Figure 3, interconnection structures such as vias 162, metal wires 163, bonding structures 164, and others can be formed to electrically couple the bottom of the semiconductor layer 185(D) to the bit line (BL).

[0049] Furthermore, in the example shown in Figure 3, the stepped region 116 includes a stepped region 116 formed to facilitate word line connections to the gates of transistors (e.g., memory cells, top-selection transistors, bottom-selection transistors, etc.). For example, the word line connection structure 150 includes a word line contact plug 151 conductively coupled to each other, a via structure 152, and a metal wire 153. The word line connection structure 150 can electrically couple WL to the gate terminals of transistors in the memory cell string 180.

[0050] In the example shown in Figure 3, a contact structure 170 is formed in the insulating region 117. In some embodiments, the contact structure 170 can be formed simultaneously with the word wire connection structure 150 by processing on the front side of the array die 102. Thus, in some examples, the contact structure 170 has a similar structure to the word wire connection structure 150. Specifically, the contact structure 170 may include a contact plug 171, a via structure 172, and a metal wire 173 that are electrically coupled to each other.

[0051] In some examples, a mask containing patterns for contact plugs 171 and word wire contact plugs 151 can be used. This mask is used to form contact holes for contact plugs 171 and word wire contact plugs 151. Contact holes can be formed using an etching process. In one example, etching of the contact hole for word wire contact plug 151 can be stopped on the gate layer 195, and etching of the contact hole for contact plug 171 can be stopped within the oxide layer 112. Furthermore, the contact holes can be filled with appropriate liner layers (e.g., titanium / titanium nitride) and metal layers (e.g., tungsten) to form contact plugs such as contact plugs 171 and word wire contact plugs 151. In addition, back-end offline (BEOL) processes are used to form various connection structures such as via structures, metal wires, and bonding structures.

[0052] Furthermore, in the example shown in Figure 3, bonding structures are formed on the front sides of the array die 102 and the CMOS die 101, respectively. For example, bonding structures 174 and 164 are formed on the front side of the array die 102, and bonding structures 131 and 134 are formed on the front side of the CMOS die 101.

[0053] In the example shown in Figure 3, the array die 102 and the CMOS die 101 are positioned facing each other (circuit side facing up, substrate side facing down) and bonded to each other. The corresponding bonding structures on the array die 102 and the CMOS die 101 are aligned and bonded to each other, forming bonding interfaces that conductively couple the appropriate components on the two dies. For example, bonding structure 164 and bonding structure 131 are bonded to each other to couple the drain side of the memory cell string 180 with a bit line (BL). In another example, bonding structure 174 and bonding structure 134 are bonded to each other to couple a contact structure 170 on the array die 102 with the I / O circuit on the CMOS die 101.

[0054] Returning to S220, the first substrate of the first die is removed from the back side of the first die. The removal of the first substrate exposes the semiconductor portion and the contact structure 170 on the back side of the first die.

[0055] Figure 4 shows a cross-sectional view of the semiconductor memory device 100 after the first substrate 103 has been removed from the array die 102. In the example in Figure 4, the bulk portion 111, the silicon oxide layer 112, and the silicon nitride layer 113 have been removed from the back side of the array die 102. In some examples, after a wafer-to-wafer bonding process, a first wafer with the array die is bonded to a second wafer with a CMOS die. The first substrate is then thinned from the back side of the first wafer. In one example, a chemical mechanical polishing (CMP) or grinding process is used to remove most of the bulk portion 111 of the first wafer. Alternatively, a suitable etching process can be used to remove the remaining bulk portion 111, the silicon oxide layer 112, and the silicon nitride layer 113 from the back side of the first wafer. By removing the bulk portion 111, the silicon oxide layer 112, and the silicon nitride layer 113, the ends of the contact structure 170 protruding from the insulating portion 106 (as indicated by 175) can be exposed. By removing the bulk portion 111, the silicon oxide layer 112, and the silicon nitride layer 113, the semiconductor portion 105 can also be exposed.

[0056] Referring back to Figure 2, at S230, a pad structure and a connection structure are formed on the back side of the first die. In some embodiments, the pad structure includes a first pad structure which is conductively connected to the contact structure 170. The connection structure is conductively connected to the semiconductor portion 150.

[0057] In some embodiments, the pad structure and connection structure are formed primarily of aluminum (Al). In some embodiments, an interface layer can be formed between the aluminum and the semiconductor portion 105. In some examples, a metal silicide thin film can be used as the interface layer. In one example, a metal silicide thin film can be used to enable ohmic contact between the aluminum and the semiconductor portion 105. In another example, the metal silicide thin film is used to form local interconnections to the semiconductor portion 105. In yet another example, the metal silicide thin film is used as a diffusion barrier to prevent aluminum diffusion into the semiconductor portion 105.

[0058] In some cases, titanium is deposited entirely on the back side of a first wafer that is bonded face-to-face with a second wafer, and then heated in a nitrogen atmosphere. The titanium can react with the exposed silicon surface (such as the semiconductor portion 105) to form titanium silicide. The unreacted portions of titanium (e.g., above the insulating portion, above the edges of the contact structure 170, etc.) form silicide.

[0059] Next, a metal film can be formed on the back surface of the first wafer. Figure 5 shows a cross-sectional view of the semiconductor memory device 100 after the metal film has been deposited. In the example in Figure 5, a metal film 120 has been deposited on the back surface of the first wafer. The metal film 120 may have an uneven surface due to protrusions from the edges of the contact structure 170. In some embodiments, the metal film 120 includes a titanium layer 126 and an aluminum layer 128. In embodiments, the titanium layer 126 on the semiconductor portion 105 can react with the silicon surface to form titanium silicide 127. For example, the titanium layer 126 is deposited and heated in a nitrogen atmosphere. Then, the aluminum layer 128 is deposited.

[0060] The metal film 120 can be patterned to form pad structures and connection structures. Figure 6 shows a cross-sectional view of the semiconductor memory device 100 after the metal film 120 has been patterned to form pad structures 122-123 and connection structure 121. In the example in Figure 6, the pad structures 122-123 are each connected to a contact structure 170 and positioned above the insulating portion 106, and the connection structure 121 is connected to the semiconductor portion 105. In some embodiments, a photolithography process is used to define the patterns of the pad structures 122-123 and connection structure 121 in a photoresist layer according to a mask, and then an etching process is used to transfer the patterns to the metal film 120 to form the pad structures 122-123 and connection structure 121.

[0061] According to aspects of this disclosure, the film of the connection structure 121 is deposited directly onto the semiconductor portion 105, and therefore the interface between the connection structure 121 and the semiconductor portion 105 is substantially flat over the semiconductor portion 105. In related examples, the semiconductor portion 105 can be covered with an insulating layer, contact holes are formed within the insulating layer, and then a suitable metal layer is deposited (inside the holes and on top of the insulating layer) to form contacts and connections. Compared to related examples, the connection structure 121 is formed within the insulating layer without using contact holes, the interface between the connection structure 121 and the semiconductor portion 105 is relatively flat, and the lower and upper end faces of the connection structure 121 on the semiconductor portion 105 are substantially the same, provided that differences in etch profiles are ignored.

[0062] According to another aspect of this disclosure, the metal film 120 may have an uneven surface due to the protrusion of the end of the contact structure 170. For example, the lower end surface of the metal film 120 that forms an interface with the insulating portion 106 may have a recess corresponding to the end of the contact structure 170, and therefore the lower end surfaces of the pad structures 122-123 may have a recess corresponding to the end of the contact structure 170.

[0063] The wafer manufacturing process can be continued with further processes, such as passivation, testing, and dicing.

[0064] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the disclosure. Those skilled in the art should understand that the disclosure may readily be used as a basis for designing or modifying other processes and structures to carry out the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures will not depart from the spirit and scope of the disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the disclosure. [Explanation of Symbols]

[0065] 100 Semiconductor memory devices 101 CMOS dies 102 array die 103 circuit board 104 circuit board 105 Semiconductor Section 106 Insulation part 111 Bulk section 112 Silicon Oxide Layer 113 Silicon Nitride Layer 115 Core Areas 116 Stairs area 117 Insulation Area 120 Metal film 121 Connection Structure 122 Pad Structure 123 Pad structure 126 Titanium layer 127 Titanium silicide layer 128 Aluminum layer 131 Bonding structure 134 Bonding structure 150 Word Line Connection Structure 151 Word wire contact plug 152 via structure 153 Metal wire 162 Beer 163 Metal wire 164 Bonding structure 170 Contact Structure 171 Contact Plug 172 Via Structure 173 Metal wire 174 Bonding structure 175 End 180 memory cell string 181 Channel Structure 182 Blocking Insulation Layer 183 Charge storage layer 184 Tunnel Insulation Layer 185 Semiconductor layer 186 Insulating layer 189 Common Source Layer 190 layers 194 Insulating layer 195 Gate Layer

Claims

1. A first die and a second die joined face to face, wherein the first die includes a first transistor formed on the front side of the first die within a semiconductor portion and a contact structure disposed in an insulating portion outside the semiconductor portion, and the second die includes a substrate and a second transistor formed on the front side of the second die; and A first pad structure disposed on the back side of the first die and electrically coupled to the contact structure, wherein the end of the contact structure protrudes from the insulating portion into the first pad structure. A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, further comprising a connection structure disposed on the back side of the first die and electrically connected to the semiconductor portion.

3. The semiconductor device according to claim 2, wherein the interface between the connection structure and the semiconductor portion is substantially flat on the semiconductor portion.

4. The semiconductor device according to claim 2, wherein the lower end surface and the upper end surface of the connection structure on the semiconductor portion are substantially the same size.

5. The semiconductor device according to claim 1, wherein the contact structure includes at least a first metallic material different from the second metallic material in the first pad structure.

6. The semiconductor device according to claim 5, wherein the first metallic material comprises tungsten and the second metallic material comprises aluminum.

7. The semiconductor device according to claim 1, wherein the lower end surface of the first pad structure, which forms an interface with the insulating portion, has a recess corresponding to the end of the contact structure.

8. The semiconductor device according to claim 1, wherein the first die comprises at least a memory cell array formed within the semiconductor portion, and the second die comprises peripheral circuits for the memory cell array.

9. The semiconductor device according to claim 8, wherein the contact structure on the first die is electrically coupled to an input / output circuit on the second die via a bonding structure.

10. The semiconductor device according to claim 1, wherein the first die comprises an input / output circuit electrically coupled to the contact structure.

11. A method for manufacturing semiconductor devices, A step of joining a first die and a second die face to face, wherein the first die comprises a first substrate, a first transistor formed in the semiconductor portion on the front side of the first substrate, and a contact structure disposed in the insulating portion outside the semiconductor portion, and the second die comprises a second substrate having a second transistor formed on the front side of the second substrate, A step of removing the first substrate from the back side of the first die, wherein the removal of the first substrate exposes the end of the contact structure on the back side of the first die. A step of forming a first pad structure on the back side of the first die, which is electrically connected to the contact structure, wherein the end of the contact structure protrudes from the insulating portion into the first pad structure, and Methods that include...

12. The method according to claim 11, further comprising the step of forming a connection structure on the back side of the first die that is electrically connected to the semiconductor portion.

13. The removal of the first substrate involves exposing the semiconductor portion from the back side of the first die, and the method is as follows: The method according to claim 12, comprising the step of depositing a layer for forming the connection structure, wherein the interface of the layer with respect to the semiconductor portion is substantially flat on the semiconductor portion.

14. The method according to claim 13, further comprising the step of patterning the layer for forming the connection structure, wherein the lower end surface and the upper end surface of the connection structure on the semiconductor portion are substantially the same size.

15. The method according to claim 11, further comprising the step of depositing a second metal material different from the first metal material on the contact structure which includes at least a first metal material, wherein the first pad structure includes at least the second metal material.

16. The method according to claim 15, wherein the first metal material comprises tungsten and the second metal material comprises aluminum.

17. The step of forming the first pad structure is The method according to claim 11, further comprising the step of depositing one or more layers on the insulating portion to form the first pad structure, wherein the end of the contact structure protrudes from the insulating portion, and the lower end surface of one or more layers forming an interface with the insulating portion has a recess corresponding to the end of the contact structure.

18. The method according to claim 11, wherein the first die comprises at least a memory cell array formed within the semiconductor portion, and the second die comprises peripheral circuits for the memory cell array.

19. The step of joining the first die and the second die facing each other is, The method according to claim 18, further comprising the step of joining a first bonding structure on a first die to a second bonding structure on a second die, wherein the first bonding structure is electrically coupled to the contact structure on the first die, and the second bonding structure is electrically coupled to an input / output circuit on the second die.

20. The method according to claim 11, wherein the first die comprises an input / output circuit electrically coupled to the contact structure.

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