Semiconductor equipment

JP2026093452APending Publication Date: 2026-06-09MITSUBISHI ELECTRIC CORP

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
MITSUBISHI ELECTRIC CORP
Filing Date
2024-11-28
Publication Date
2026-06-09

AI Technical Summary

Benefits of technology

【0007】 本開示の半導体装置によれば、突出部酸化膜142の厚みt2が下段酸化膜141の厚みt1より大きいため、下段電極に対向する上段突出部の表面積を低減できる。その結果、ゲート耐圧が向上する効果が得られる。

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 2026093452000001_ABST
    Figure 2026093452000001_ABST
Patent Text Reader

Abstract

This disclosure aims to improve the gate breakdown voltage in a semiconductor device having a two-stage trench electrode structure. [Solution] The upper electrode 15U includes an upper base portion 15U1 and an upper projection portion 15U2 that protrudes toward the second main surface S2 from the lower surface, which is the surface of the upper base portion 15U1 toward the second main surface S2. The upper electrode 15U is convex toward the second main surface S2 due to the upper base portion 15U1 and the upper projection portion 15U2. The oxide film 14 comprises a lower oxide film 141 formed on the side surface of the trench 13 in contact with the lower electrode 15D, an upper oxide film 143 formed on the side surface of the trench 13 in contact with the upper base portion 15U1, a projection portion oxide film 142 formed on the side surface of the trench 13 in contact with the upper projection portion 15U2, and a boundary oxide film 144 formed between the upper electrode 15U and the lower electrode 15D. The thickness t2 of the projection portion oxide film 142 is greater than the thickness t1 of the lower oxide film 141.
Need to check novelty before this filing date? Find Prior Art

Claims

1. A semiconductor substrate having a first main surface and a second main surface which is the main surface opposite to the first main surface, A first-conductivity type drift layer formed on the semiconductor substrate, A second conductive base layer formed on the first main surface side of the drift layer, A trench extending from the first main surface through the base layer to the drift layer, The oxide film covering the inner surface of the trench, A trench electrode embedded in the trench via the oxide film, Equipped with, The trench electrode is Lower electrode and It includes an upper electrode formed on the first main surface side of the lower electrode, The upper electrode is, Upper base and The upper base includes an upper projection that protrudes from the lower surface, which is the surface on the second main surface side of the upper base, toward the second main surface side, The upper base and the upper projection give the surface a convex shape toward the second main surface. The aforementioned oxide film is A lower oxide film formed on the side surface of the trench in contact with the lower electrode, An upper oxide film formed on the side surface of the trench in contact with the upper base, The oxide film formed on the side surface of the trench in contact with the upper protrusion, The system comprises a boundary oxide film formed between the upper electrode and the lower electrode, The thickness t2 of the protruding oxide film is greater than the thickness t1 of the lower oxide film. Semiconductor equipment.

2. If θ1 is the angle with respect to the horizontal of the line connecting the lower end of the central part of the upper protrusion and the lower end of the side surface of the upper base, then 0° < θ1 < 90°. The semiconductor device according to claim 1.

3. The lower end of the upper protrusion is located below the deepest part of the base layer. The distance L1 from the deepest part of the base layer to the lower end of the side surface of the upper base is smaller than the protruding length L2 of the upper protrusion. The semiconductor device according to claim 1 or claim 2.

4. The lower end of the upper protrusion is located below the deepest part of the base layer. The distance L1 from the deepest part of the base layer to the lower end of the upper protrusion is greater than the protrusion length L2 of the upper protrusion. The semiconductor device according to claim 1 or claim 2.

5. The width w1 of the upper projection is greater than the projection length L2 of the upper projection. The semiconductor device according to claim 1 or claim 2.

6. The width w1 of the upper projection is smaller than the projection length L2 of the upper projection. The semiconductor device according to claim 1 or claim 2.

7. The thickness t4 of the boundary oxide film is smaller than the thickness t3 of the protruding oxide film. The semiconductor device according to claim 1 or claim 2.

8. The thickness t4 of the boundary oxide film is greater than the thickness t3 of the protruding oxide film. The semiconductor device according to claim 1 or claim 2.

9. If θ2 is the angle with respect to the horizontal direction of the lower surface of the upper base portion that is in contact with the oxide film of the protruding portion, then 0° < θ2 < 90°. The semiconductor device according to claim 1 or claim 2.

10. The system further comprises a first-conductivity type carrier storage layer formed between the drift layer and the base layer. The semiconductor device according to claim 1 or claim 2.

11. The depth d2 of the central part of the upper projection is greater than the depth d3 of the end of the upper projection. The semiconductor device according to claim 1 or claim 2.

12. The lower surface of the aforementioned upper protrusion is flat. The semiconductor device according to claim 1 or claim 2.

13. The thickness t4 of the boundary oxide film is smaller than the thickness t1 of the lower oxide film. The semiconductor device according to claim 1 or claim 2.

14. The thickness t4 of the boundary oxide film is greater than the thickness t1 of the lower oxide film. The semiconductor device according to claim 1 or claim 2.

15. Of the upper electrode and the lower electrode, one is a gate electrode and the other is a gate electrode, emitter electrode, or control gate electrode. The semiconductor device according to claim 1 or claim 2.