Semiconductor device and method for manufacturing a semiconductor device

JP2026093486APending Publication Date: 2026-06-09DENSO CORP +2

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
DENSO CORP
Filing Date
2024-11-28
Publication Date
2026-06-09

AI Technical Summary

Benefits of technology

【0007】 この半導体装置では、端部フィンの幅が、上方から下方に向かって徐々に広くなっている。このため、上方から下方に向かって幅が一定であるフィンと比較して、フィンの幅方向に加わる力に対する強度が高い。したがって、大きな熱応力が発生しても、当該端部フィンが支持層の上面に対して傾斜するように変形することを抑制することができる。

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Abstract

We propose a technology to suppress fin deformation caused by thermal stress. [Solution] The semiconductor substrate has a support layer and a plurality of fins protruding from the upper surface of the support layer. The plurality of fins are arranged with spacing in a first direction and each extends along a second direction intersecting the first direction. The upper surface of the support layer has an element region where the plurality of fins are provided and an external region adjacent to the element region in the first direction. The gate insulating film is distributed across the element region and the external region and covers the upper surface of the support layer and the surface of each fin. The gate electrode is distributed across the external region from within each recess between the plurality of fins and also covers the gate insulating film. The width of one or more end fins located at the ends of the plurality of fins in the first direction gradually widens from top to bottom.
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Claims

1. A semiconductor device (10) comprising a semiconductor substrate (12), a gate insulating film (24), and a gate electrode (26), The aforementioned semiconductor substrate Support layer (14), A plurality of fins (20) protruding from the upper surface (14a) of the support layer, It has, The plurality of fins are arranged at intervals in a first direction, and each extends along a second direction that intersects the first direction. The upper surface of the support layer has an element region (16) on which the plurality of fins are provided, and an external region (18) adjacent to the element region in the first direction. The gate insulating film is distributed across the element region and the external region, and covers the upper surface of the support layer and the surface of each fin. The gate electrode is distributed from within each recess (23) between the plurality of fins across the external region and covers the gate insulating film. The width of one or more end fins (20a) located at the ends of the plurality of fins in the first direction gradually increases from top to bottom. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the width of the lower end of the end fin is wider than the width of the lower end of the other fins (20b) among the plurality of fins.

3. The semiconductor device according to claim 1 or 2, wherein the height of the end fin is greater than the height of the other fins among the plurality of fins.

4. The semiconductor device according to claim 1 or 2, wherein the coefficient of linear expansion of the semiconductor substrate is higher than the coefficient of linear expansion of the gate electrode.

5. The semiconductor device according to claim 1 or 2, wherein the width of each fin is 200 nm or less.

6. A method for manufacturing a semiconductor device (10), A step of forming a first mask (52) on the upper surface (50a) of a semiconductor substrate (50), The process involves forming a second mask (54) on the upper surface (52a) of the first mask, A step of forming a plurality of grooves (56) on the upper surface (54a) of the second mask by etching, wherein the first mask is exposed at the bottom surface of the plurality of grooves, and the plurality of mask portions (55) which are the remaining portions of the second mask and the plurality of grooves are arranged alternately in a first direction, A step of forming a third mask (58) on the upper surface of the mask portion, the side surface of the mask portion, and the bottom surface of the groove, wherein the thickness of the third mask (58a) covering the end side surface (55a) located at the end in the first direction of the side surface of the plurality of mask portions is greater than the thickness of the third mask covering the other side surface of the plurality of mask portions, A step of removing by etching the portion of the third mask that covers the upper surface of the plurality of mask portions and the portion that covers the bottom surface of the plurality of grooves, such that the third mask remains on the side surface of the plurality of mask portions. The step of removing the second mask, A step of etching the first mask so that the upper surface of the semiconductor substrate is exposed through the third mask, The process of removing the third mask, A step of etching the semiconductor substrate through the first mask, A method for manufacturing a semiconductor device, comprising: