Semiconductor manufacturing jig, and method for manufacturing a semiconductor manufacturing jig

Abstract

The present invention provides semiconductor manufacturing jigs using materials with different physical properties, and a method for manufacturing semiconductor manufacturing jigs. [Solution] The semiconductor manufacturing jig according to this disclosure is a semiconductor manufacturing jig 1 used in a semiconductor manufacturing apparatus. The semiconductor manufacturing jig 1 comprises a first layer 11 having a first resistivity, and a second layer 12 laminated with the first layer 11 and having a second resistivity different from the first resistivity. The second resistivity is greater than the first resistivity, or the second resistivity is less than the first resistivity.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor manufacturing tool and a method for manufacturing a semiconductor manufacturing tool.

Background Art

[0002] In a plasma etching apparatus for etching a semiconductor wafer, an etcher ring is used as a semiconductor manufacturing tool for holding the wafer to be etched (Patent Document 1). Such an etcher ring is formed of, for example, CVD-SiC (Silicon Carbide) formed by CVD (Chemical Vapor Deposition).

[0003] When making an etcher ring of CVD-SiC, it is common to use a material with uniform physical properties. Even for an etcher ring having a structure in which two or more layers of SiC are laminated to have a predetermined thickness, it is made using a material with uniform physical properties.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, there is a problem that, like conventional semiconductor manufacturing tools, simply using a material with uniform physical properties cannot provide various semiconductor manufacturing tools according to the uses of semiconductor manufacturing apparatuses.

[0006] The present disclosure has been made to solve the above problems, and an object thereof is to provide a semiconductor manufacturing tool using materials with different physical properties and a method for manufacturing a semiconductor manufacturing tool.

Means for Solving the Problems

[0007] A semiconductor manufacturing jig relating to a certain aspect of this disclosure is a semiconductor manufacturing jig used in a semiconductor manufacturing apparatus. The semiconductor manufacturing jig comprises a first layer having a first resistivity and a second layer laminated with the first layer and having a second resistivity different from the first resistivity.

[0008] A method for manufacturing a semiconductor manufacturing jig relating to another aspect of this disclosure is a method for manufacturing a semiconductor manufacturing jig used in a semiconductor manufacturing apparatus. The method for manufacturing a semiconductor manufacturing jig includes the steps of: forming a first layer having a first resistivity around a substrate; laminating a second layer having a second resistivity different from the first resistivity onto the first layer; processing the laminated first and second layers into a predetermined shape; and removing the substrate. [Effects of the Invention]

[0009] The semiconductor manufacturing jig according to this disclosure comprises a first layer having a first resistivity and a second layer laminated with the first layer and having a second resistivity different from the first resistivity. Therefore, a variety of semiconductor manufacturing jigs can be provided to suit the application of the semiconductor manufacturing equipment. [Brief explanation of the drawing]

[0010] [Figure 1] This is a plan view of a semiconductor manufacturing jig in Embodiment 1. [Figure 2] This is a cross-sectional view of the semiconductor manufacturing jig in Embodiment 1. [Figure 3] This is a schematic diagram of a CVD film deposition apparatus for manufacturing semiconductor manufacturing jigs in Embodiment 1. [Figure 4] This is a cross-sectional view of a substrate used in the manufacture of a semiconductor manufacturing jig in Embodiment 1. [Figure 5] This is a cross-sectional view of a laminate in which a first layer and a second layer are laminated around a base material in Embodiment 1. [Figure 6] This is a cross-sectional view of a laminated body showing a portion of a semiconductor manufacturing jig obtained by processing the laminated body of Embodiment 1 with a processing apparatus. [Figure 7] This is a flowchart showing the manufacturing process of a semiconductor manufacturing jig according to Embodiment 1. [Figure 8] This is a cross-sectional view of the semiconductor manufacturing jig in Embodiment 2. [Figure 9] This is a cross-sectional view of a laminated body showing a portion of a semiconductor manufacturing jig obtained by processing the laminated body of Embodiment 2 with a processing apparatus. [Figure 10] This is a plan view of a semiconductor manufacturing jig in a modified example. [Modes for carrying out the invention]

[0011] The embodiments of this disclosure will be described in detail below with reference to the drawings. While multiple embodiments will be described below, it has been intended from the outset that the configurations described in each embodiment may be combined as appropriate. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and their descriptions will not be repeated.

[0012] [Embodiment 1] (Configuration of semiconductor manufacturing jigs) This disclosure describes semiconductor manufacturing jigs used in semiconductor manufacturing equipment. In particular, it describes semiconductor manufacturing jigs used in semiconductor manufacturing equipment that uses plasma (for example, plasma etching equipment), such as etcher rings. However, the semiconductor manufacturing jigs according to this disclosure are not limited to etcher rings. Figure 1 is a plan view of semiconductor manufacturing jig 1 in Embodiment 1. Figure 2 is a cross-sectional view of semiconductor manufacturing jig 1 in Embodiment 1. In Figure 2, a cross-section along the center line of the ring-shaped semiconductor manufacturing jig 1 shown in Figure 1 is shown.

[0013] The semiconductor manufacturing tool 1 is an etcher ring used inside a plasma etching apparatus. The semiconductor manufacturing tool 1 is an annular member in which a first layer 11 and a second layer 12 having a different specific resistance from the first layer 11 are laminated. The first layer 11 is composed of SiC (Silicon Carbide) having a first specific resistance. The second layer 12 is composed of SiC having a second specific resistance different from the first specific resistance. For example, assuming that the first specific resistance is within the range of 1 Ωcm to 25 Ωcm used in a general etcher ring, the second specific resistance is set to a value greater than the first specific resistance, such as 50 Ωcm or more or 100 Ωcm or more. Conversely, assuming that the second specific resistance is within the range of 1 Ωcm to 25 Ωcm used in a general etcher ring, the first specific resistance is set to a value less than 1 Ωcm and less than the second specific resistance.

[0014] Note that the second specific resistance only needs to be different by at least a value exceeding the manufacturing variation of the first specific resistance. Or, the second specific resistance only needs to be different in at least the order of the first specific resistance. Further or, the second specific resistance only needs to be a value exceeding the specification range of the first specific resistance. Also, the magnitude relationship between the first specific resistance and the second specific resistance is not limited to the first specific resistance < the second specific resistance, and the first specific resistance > the second specific resistance may also be applicable.

[0015] In the semiconductor manufacturing tool 1, the second layer 12 is laminated below the first layer 11. Since the semiconductor manufacturing tool 1 is annular, a circular space portion 13 is formed on the inner peripheral side, and a portion where the first layer 11 and the second layer 12 are laminated is formed on the outside thereof. In the semiconductor manufacturing tool 1, a portion with only the second layer 12 is further formed on the outside. The semiconductor manufacturing tool 1 has an upper surface (first main surface) for holding the wafer 2 and a lower surface (second main surface) facing the upper surface. When viewed in plan from the upper surface as shown in FIG. 1, the first layer 11 having the first specific resistance is arranged in the inner peripheral side (inner side) portion, and the second layer 12 having the second specific resistance is arranged on the outer peripheral side (outer side).

[0016] In the semiconductor manufacturing tool 1, a holding portion 14 for holding the wafer 2 to be etched as shown in FIG. 2 is provided at the inner peripheral side portion on the upper surface of the first layer 11. The wafer 2 has a disk shape. The holding portion 14 is thinner than other portions of the semiconductor manufacturing tool 1, and a step is formed between the holding portion 14 and other portions.

[0017] Generally, in a semiconductor manufacturing tool such as an etcher ring, it is required to make the resistivity uniform in the plane of the upper surface. However, in the semiconductor manufacturing tool 1 according to the present embodiment, by disposing the first layer 11 having a first resistivity at the inner peripheral side portion and the second layer 12 having a second resistivity at the outer peripheral side, the resistivity is made different in the plane of the upper surface. By making the resistivity different in the plane of the upper surface, the density of the plasma etcher generated inside the plasma etching apparatus can be partially changed. For example, when the relationship of the first resistivity < the second resistivity is established, the semiconductor manufacturing tool 1 can increase the density of the plasma etcher at the inner peripheral side because the resistivity of the second layer 12 at the outer peripheral side is large. By using the semiconductor manufacturing tool 1 having different resistivities in the plane of the upper surface in the plasma etching apparatus, the processing state of the wafer 2 can be changed as compared with the case of using a conventional semiconductor manufacturing tool.

[0018] (Manufacturing Apparatus for Semiconductor Manufacturing Tool) FIG. 3 is a schematic view of a CVD film forming apparatus for manufacturing the semiconductor manufacturing tool 1 in Embodiment 1.

[0019] The CVD film forming apparatus 4 includes a chamber 41, a high-frequency power source 42, a vacuum pump 43, a source gas container 44, a first valve 451, a second valve 452, and a control device 49.

[0020] The control device 49 consists of a CPU (Central Processing Unit) 491, memory (ROM (Read Only Memory) and RAM (Random Access Memory)) 492, input / output buffers (not shown), etc. The CPU 491 loads the program stored in ROM into RAM, etc., and executes it. The program stored in ROM includes the control processing procedures to be executed by the control device 49, and parameters for depositing films with different resistivity. The control device 49 controls various devices in the CVD film deposition apparatus 4 according to such a program.

[0021] The control device 49 controls various devices in the chamber 41, such as the high-frequency power supply 42, the vacuum pump 43, the first valve 451, and the second valve 452.

[0022] Inside the chamber 41 are a film deposition stage 46, a heater 47, and a shower head 48. The heater 47 is located inside the shower head 48. Above the film deposition stage 46, the substrate 5 of the semiconductor manufacturing jig 1 to be deposited is held. The substrate 5 is made of, for example, graphite. The substrate 5 is held so that film deposition is performed all around its perimeter. The substrate 5 may be made of a material other than graphite.

[0023] The first valve 451 is located in the gas path between the vacuum pump 43 and the chamber 41. The second valve 452 is located in the gas path between the raw material gas container 44 and the chamber 41.

[0024] When a film is to be deposited on the substrate 5 in the CVD film deposition apparatus 4, the control device 49 closes the second valve 452, opens the first valve 451, and operates the vacuum pump 43. As a result, the inside of the chamber 41 becomes a vacuum.

[0025] Subsequently, the control device 49 closes the first valve 451 to maintain a vacuum inside the chamber 41, and then opens the second valve 452. This allows the raw material gas to be supplied from the raw material gas container 44 into the chamber 41. When the raw material gas is supplied into the chamber 41, the control device 49 controls the supply of high-frequency power from the high-frequency power supply 42 to the electrodes of the shower head 48. This causes the raw material gas inside the chamber 41 to be plasma-generated and released from the shower head 48.

[0026] When a film is deposited on a substrate 5 in the CVD deposition apparatus 4, the control device 49 supplies power to the heater 47 and controls the heater to heat up. As a result, the substrate 5, which is the object to be deposited on, is heated, and a film of the substance contained in the raw material gas is formed on the object. The resistivity of the deposited film can be changed by adjusting parameters such as the flow rate of the raw material gas, the high-frequency power, and the amount of heating by the heater. The resistivity of the deposited film can also be adjusted by adjusting the amount of impurities added as dopants (including zero).

[0027] In such a CVD film deposition apparatus 4, a SiC film is deposited around the substrate 5 to produce a semiconductor manufacturing jig 1 as shown in Figures 1 and 2.

[0028] The manufacturing equipment for the semiconductor manufacturing jig 1 includes, in addition to the CVD film deposition apparatus 4, processing equipment (not shown) for machining the semiconductor manufacturing jig 1, such as cutting.

[0029] (Method of manufacturing a semiconductor manufacturing jig 1) Figures 4 to 6, described below, show examples of simultaneously manufacturing two semiconductor manufacturing jigs 1. In Figures 4 to 6, the boundary between the manufacturing ranges of the two semiconductor manufacturing jigs 1 is indicated by a dashed line 70 to clarify the manufacturing range of each individual semiconductor manufacturing jig 1.

[0030] Figure 4 is a cross-sectional view of the base material 5 used in the manufacture of the semiconductor manufacturing jig 1 in Embodiment 1. The base material 5 is a ring-shaped member in which the thickness of the first portion 51 on the outer circumference is thinner than the thickness of the second portion 52 on the inner circumference. Because the base material 5 is ring-shaped, a circular space 53 is formed on the inner circumference. The shapes of the first portion 51 and the second portion 52 of the base material 5 are determined to be the cross-sectional shape of the interface between the laminated first layer and the second layer.

[0031] Figure 5 is a cross-sectional view of a laminate 6 in which a first layer 61 and a second layer 62 are laminated around a base material 5 in Embodiment 1.

[0032] When forming the laminate 6 shown in Figure 5, first, a first layer 61 is formed around the substrate 5 in the CVD deposition apparatus 4. The first layer 61 is the layer that becomes the first layer 11 of the semiconductor manufacturing jig 1. The first layer 61 is a layer of SiC with first resistivity.

[0033] Subsequently, a second layer 62 is formed around the first layer 61 in the CVD deposition apparatus 4. The second layer 62 is the second layer 12 of the semiconductor manufacturing jig 1. The second layer 62 is a layer of SiC with second resistivity. Since the substrate 5 of the laminate 6 is ring-shaped, a circular space 63 is formed on the inner circumference after the first layer 61 and the second layer 62 are laminated.

[0034] As shown in Figure 5, the shape of the base material 5 is such that the thickness of the first portion 51 on the outer circumference is thinner than the thickness of the second portion 52 on the inner circumference. Accordingly, the shape of the first layer 61 of the laminate 6 follows the shape of the base material 5 and has a step between the outer and inner regions. Furthermore, the shape of the second layer 62 of the laminate 6 follows the shape of the first layer 61 and has a step between the outer and inner regions.

[0035] After the laminate 6 shown in Figure 5 is formed in the CVD film deposition apparatus 4, the laminate 6 can be processed in the processing apparatus to obtain a semiconductor manufacturing jig 1 with the shape shown in Figures 1 and 2.

[0036] Figure 6 is a cross-sectional view of the laminate 6 showing a portion of the semiconductor manufacturing jig 1 obtained by processing the laminate 6 of Embodiment 1 with a processing device. As shown in Figure 6, two semiconductor manufacturing jigs 1 can be obtained from the laminate 6.

[0037] In the following, the processing portion for obtaining the semiconductor manufacturing jig 1 will be described using the semiconductor manufacturing jig 1 shown at the bottom of the figure as a representative example from the two semiconductor manufacturing jig 1 regions shown in Figure 6. In the processing apparatus, the laminate 6 is processed as shown below to obtain the semiconductor manufacturing jig 1 with the configuration shown in Figure 2.

[0038] In the case of the laminate 6, to obtain the semiconductor manufacturing jig 1 shown at the bottom of the figure, the processing apparatus first performs a process of cutting the lower surface of the laminate 6 to the position of the dashed line 71, for example, to flatten it, and then cutting the upper surface of the laminate 6 to the position of the dashed line 72, for example, to flatten it. As a result, both end faces of the laminate 6 in the stacking direction are flattened.

[0039] Next, the processing apparatus performs the following processes: cutting the outer circumference of the laminate 6 to a position such as the dashed line 73 to expose the first portion 51 of the base material 5, and cutting the inner circumference of the laminate 6 to a position such as the dashed line 74 to expose the second portion 52 of the base material 5.

[0040] In the process of exposing the first portion 51 of the base material 5, the outer circumference of the laminate 6 is cut to the same position as the predetermined outer circumference dimension of the semiconductor manufacturing jig 1, as shown by the dashed line 73, using the center of the circle of the base material 5 as the reference position. In the process of exposing the second portion 52 of the base material 5, the inner circumference of the laminate 6 is cut to the same position as the predetermined inner circumference dimension of the semiconductor manufacturing jig 1, as shown by the dashed line 74, using the center of the circle of the ring-shaped base material 5 as the reference position.

[0041] In the process of exposing the first portion 51 of the base material 5, it is sufficient to cut the laminate 6 until at least the outer and inner ends of the base material 5 are exposed. Cutting up to the position indicated by the dashed line 73 in Figure 6 and cutting up to the position indicated by the dashed line 74 in Figure 6 may be performed after the base material 5 has been removed.

[0042] Next, a chemical treatment is performed to remove the substrate 5. As a result, in the laminate 6, the first member for creating the semiconductor manufacturing jig 1 shown above the dashed line 70 in Figure 6 and the second member for creating the semiconductor manufacturing jig 1 shown below the dashed line 70 in Figure 6 are separated.

[0043] In the following section, we will explain the processing method for creating the semiconductor manufacturing jig 1, with respect to the components for creating the semiconductor manufacturing jig 1 shown in the lower part of Figure 6.

[0044] The second component for creating the semiconductor manufacturing jig 1, shown on the lower side of Figure 6, is held in the processing section of the processing device with the side of the planarized second layer 62 facing downwards, as described above. The processing device then cuts the upper surface of the semiconductor manufacturing jig 1 until the second layer 62 is exposed.

[0045] Specifically, the upper surface of the second member is cut, using the lower end of the substrate 5 as the reference position, so that the cross-sectional shape of the semiconductor manufacturing jig 1 becomes the cross-sectional shape shown in Figure 2. The processing device cuts the second member up to the position of the dashed line 75 in Figure 6, and then cuts the second member further up to the position of the dashed line 76. The positions for cutting the upper surface of the second member can be estimated in advance based on the elapsed time from the start to the end of film deposition of the first layer 61(11) and the second layer 62(12), and the film deposition rate of the first layer 61 and the second layer 62.

[0046] Furthermore, the lower surface of the second member is machined, using the lower end of the substrate 5 as the reference position, so that the cross-sectional shape of the semiconductor manufacturing jig 1 becomes the cross-sectional shape shown in Figure 2. For example, the second member is machined up to the position of the dashed line 77 in Figure 6. The position to be machined on the lower surface of the second member can be estimated in advance based on the elapsed time from the start to the end of film deposition of the first layer 61(11) and the second layer 62(12), and the film deposition rate of the first layer 61 and the second layer 62.

[0047] As a result, the semiconductor manufacturing jig 1 has a configuration in which the first layer 11 and the second layer 12 are stacked on the outside of the space 13, as shown in Figure 2, and further outside, a portion consisting only of the second layer 12 is formed.

[0048] By performing the same processing on the first component as described above for the second component, a semiconductor manufacturing jig 1 with the configuration shown in Figure 2 can be obtained.

[0049] In Embodiment 1, as described above, after forming a laminate 6 as shown in Figure 5 with a CVD film deposition apparatus 4, the laminate 6 is processed with a processing apparatus as shown in Figure 6, thereby obtaining a semiconductor manufacturing jig 1 with the configuration shown in Figures 1 and 2 from the laminate 6.

[0050] (Manufacturing process for semiconductor manufacturing jigs) Figure 7 is a flowchart of the manufacturing process for the semiconductor manufacturing jig 1 of Embodiment 1. Using Figure 7, we will summarize the flow of the manufacturing process to realize the manufacturing method for the semiconductor manufacturing jig 1 described in Figures 4 to 6 above.

[0051] The manufacturing process shown in Figure 7 summarizes the manufacturing method of the semiconductor manufacturing jig 1 described above, and is primarily explained to clarify the flow of the manufacturing process.

[0052] In step S1, a first layer 61 of SiC with a first resistivity is formed around the substrate 5 in the CVD deposition apparatus 4. Specifically, in step S1, as described above, the first layer 61 is formed around the substrate 5 so as shown in Figure 5.

[0053] In step S2, a second layer 62 of SiC with a second resistivity is formed around the first layer 61 in the CVD deposition apparatus 4. Specifically, in step S2, as described above, the second layer 62 is formed around the first layer 61 so as shown in Figure 5. By performing steps S1 and S2, a laminate 6 as shown in Figure 5 is formed.

[0054] In step S3, the processing apparatus processes the upper surface of the laminate 6 to a flat surface and the lower surface of the laminate 6 to a flat surface. In step S3, as described above, the upper surface of the laminate 6 shown in Figure 6 is flattened to the position of the dashed line 72, and the lower surface is flattened to the position of the dashed line 71.

[0055] In step S4, the processing device exposes the inner and outer circumferences of the base material 5. Specifically, in step S4, as described above, the inner circumference of the laminate 6 is cut to the position of the predetermined dashed line 74, using the position of the center of the circle of the base material 5 shown in Figure 6 as the reference position. Furthermore, in step S4, as described above, the outer circumference of the laminate 6 is cut to the position of the predetermined dashed line 73, using the position of the center of the circle of the base material 5 shown in Figure 6 as the reference position.

[0056] In step S5, the substrate 5 is removed in the processing apparatus. Specifically, in step S5, the substrate 5 exposed in step S4 is removed by chemical treatment. This yields the first and second members as described above.

[0057] In step S6, the processing apparatus cuts the cross-sectional shape of the first or second member so that it matches the cross-sectional shape of the semiconductor manufacturing jig 1 shown in Figure 2. In other words, the processing apparatus processes the first or second member to form the configuration of the semiconductor manufacturing jig 1, as shown in Figure 2, in which the first layer 11 and the second layer 12 are stacked on the outside of the space 13, and further outside there is a portion where only the second layer 12 is formed.

[0058] Specifically, in step S6, as described above, the upper surface of the semiconductor manufacturing jig 1 is cut down to the position of the dashed line 75, using the lower end of the substrate 5 shown in Figure 6 as the reference position. Also, in step S6, as described above, the lower surface of the semiconductor manufacturing jig 1 is cut down to the position of the dashed line 76, using the lower end of the substrate 5 shown in Figure 6 as the reference position.

[0059] By performing the manufacturing process as described above, a semiconductor manufacturing jig 1 with the configuration shown in Figures 1 and 2 can be obtained.

[0060] In the semiconductor manufacturing jig 1 of Embodiment 1, an example was shown in which the first layer 11 and the second layer 12 are made of the same SiC. However, the invention is not limited to this, and the first layer 11 and the second layer 12 may be made of different materials. For example, the second layer 12 may be made of a silicon material other than SiC.

[0061] Furthermore, the semiconductor manufacturing jig 1 is not limited to being made of two layers of SiC stacked together, but may also be made of three or more layers of SiC stacked together. For example, in order to increase the thickness of the semiconductor manufacturing jig 1, it may have a structure in which three or more layers of SiC are stacked together. When stacking three or more layers of SiC, the resistivity of the third layer may be the same as or different from the first resistivity of the first layer 11 or the second resistivity of the second layer 12.

[0062] As described above, the semiconductor manufacturing jig 1 according to Embodiment 1 comprises a first layer 11 having a first resistivity and a second layer 12 laminated with the first layer 11 and having a second resistivity different from the first resistivity, so the configuration can be adjusted to suit the application in which the semiconductor manufacturing jig 1 is used. Furthermore, when viewed from above in a plan view, the semiconductor manufacturing jig 1 has the first layer 11 arranged on the inner circumference side and the second layer 12 arranged on the outer circumference side, which allows the density of the plasma etcher to be changed within the plane of the upper surface.

[0063] [Embodiment 2] Next, the semiconductor manufacturing jig 1a according to Embodiment 2 will be described using Figures 8 to 9. Note that the manufacturing method of the semiconductor manufacturing jig 1a according to Embodiment 2 is basically the same as the manufacturing method of the semiconductor manufacturing jig 1 shown in Embodiment 1, which was described in Figures 3 to 7, so a detailed explanation will not be repeated.

[0064] (Configuration of semiconductor manufacturing jigs) Figure 8 is an overall cross-sectional view of the semiconductor manufacturing jig 1a in Embodiment 2. The semiconductor manufacturing jig 1a shown in Figure 8 is shown in cross-section along the center line of the ring shape. In the semiconductor manufacturing jig 1a, a second layer 12a is formed below the first layer 11a, having a different resistivity from the first layer 11a. The first layer 11a is made of SiC having a first resistivity, similar to the first layer 11 described above. The second layer 12a is made of SiC having a second resistivity, similar to the second layer 12 described above.

[0065] The semiconductor manufacturing jig 1a is annular in shape, so a circular space 13 is formed on its inner circumference, and a holding portion 14 for holding the wafer 2 is provided on the outside of it. The holding portion 14 is formed by the stacking of the first layer 11a and the second layer 12a. The semiconductor manufacturing jig 1a also has a portion outside the holding portion 14 where the first layer 11a and the second layer 12a are stacked. The semiconductor manufacturing jig 1a has an upper surface (first main surface) for holding the wafer 2 and a lower surface (second main surface) opposite the upper surface. The semiconductor manufacturing jig 1a is configured such that the first layer 11a is placed on the upper surface and the second layer 12a is placed on the lower surface.

[0066] The wafer 2 is fixed by a chuck device provided in the plasma etching apparatus. On the other hand, the semiconductor manufacturing jig 1a is placed around the chuck device. Therefore, when cooling the wafer 2 and the semiconductor manufacturing jig 1a in the plasma etching apparatus, the cooling efficiency of the wafer 2, which is in close contact with the chuck device, is high, while the cooling efficiency of the semiconductor manufacturing jig 1a, which is merely placed on top, is low. To address this, it is conceivable to improve the cooling efficiency of the semiconductor manufacturing jig 1a by making the second resistivity of the second layer 12a on the lower surface smaller than the first resistivity of the first layer 11a on the upper surface, thereby increasing the thermal conductivity of the lower surface that is in contact with the apparatus.

[0067] (Method of manufacturing jigs for semiconductor manufacturing) Figure 9 is a cross-sectional view of the laminate showing a portion of the semiconductor manufacturing jig 1a obtained by processing the laminate of Embodiment 2 with a processing apparatus. As shown in Figure 9, two semiconductor manufacturing jigs 1a can be obtained from the laminate 6.

[0068] The method for manufacturing the semiconductor manufacturing jig 1a of Embodiment 2 is the same as the method described in Embodiment 1 using Figures 4 and 5, up to the point of forming a laminate 6 by stacking a first layer 61 and a second layer 62 around a substrate 5.

[0069] In the following, we will describe the processing portion for obtaining the semiconductor manufacturing jig 1a, using the semiconductor manufacturing jig 1a shown at the bottom of the figure as a representative example from the two semiconductor manufacturing jig 1a regions shown in Figure 9. In the processing apparatus, the laminate 6 is processed as shown below to obtain a semiconductor manufacturing jig 1a with the structure shown in Figure 8.

[0070] In the case of the laminate 6, to obtain the semiconductor manufacturing jig 1a shown at the bottom of the figure, the processing apparatus first performs a process of cutting the lower surface of the laminate 6 to the position of the dashed line 71a to flatten it, and then cutting the upper surface of the laminate 6 to the position of the dashed line 72a to flatten it. As a result, both end faces of the laminate 6 in the stacking direction are flattened.

[0071] Next, the processing apparatus performs the following processes: cutting the outer circumference of the laminate 6 to a position such as the dashed line 73a to expose the first portion 51 of the base material 5, and cutting the inner circumference of the laminate 6 to a position such as the dashed line 74a to expose the second portion 52 of the base material 5.

[0072] In the process of exposing the first portion 51 of the base material 5, the outer circumference of the laminate 6 is cut to the same position as the predetermined outer circumference dimension of the semiconductor manufacturing jig 1a, as shown by the dashed line 73a, using the center of the circle of the base material 5 as the reference position. In the process of exposing the second portion 52 of the base material 5, the inner circumference of the laminate 6 is cut to the same position as the predetermined inner circumference dimension of the semiconductor manufacturing jig 1a, as shown by the dashed line 74a, using the center of the circle of the ring-shaped base material 5 as the reference position.

[0073] In the process of exposing the first portion 51 of the base material 5, the laminate 6 only needs to be cut until at least the outer and inner ends of the base material 5 are exposed. Cutting up to the position indicated by the dashed line 73a in Figure 9 and cutting up to the position indicated by the dashed line 74a in Figure 9 may be performed after the base material 5 has been removed.

[0074] Next, a chemical treatment is performed to remove the substrate 5. As a result, in the laminate 6, the first member for creating the semiconductor manufacturing jig 1a, shown above the dashed line 70 in Figure 9, and the second member for creating the semiconductor manufacturing jig 1a, shown below the dashed line 70 in Figure 9, are separated.

[0075] In the following section, we will explain the processing method for creating the semiconductor manufacturing jig 1a, with respect to the components for creating the semiconductor manufacturing jig 1a shown at the bottom of Figure 9.

[0076] The second component for creating the semiconductor manufacturing jig 1a, shown at the bottom of Figure 8, is held in the processing section of the processing device with the side of the planarized second layer 62 facing downwards, as described above. The processing device then cuts the upper surface of the semiconductor manufacturing jig 1a until the second layer 62 is exposed.

[0077] Specifically, the upper surface of the second member is cut using the lower end of the substrate 5 as the reference position, so that the cross-sectional shape of the semiconductor manufacturing jig 1a becomes the cross-sectional shape shown in Figure 8. The processing device cuts the second member up to the position of the dashed line 75a in Figure 9, and then cuts the second member further up to the position of the dashed line 76a. The positions for cutting the upper surface of the second member can be estimated in advance based on the elapsed time from the start to the end of film deposition of the first layer 61 (11a) and the second layer 62 (12a), and the film deposition rates of the first layer 61 and the second layer 62.

[0078] Furthermore, the lower surface of the second member is machined, using the lower end of the substrate 5 as the reference position, so that the cross-sectional shape of the semiconductor manufacturing jig 1a becomes the cross-sectional shape shown in Figure 8. For example, the second member is machined up to the position of the dashed line 77a in Figure 9. The position to be machined on the lower surface of the second member can be estimated in advance based on the elapsed time from the start to the end of film deposition of the first layer 61 (11a) and the second layer 62 (12a), and the film deposition rate of the first layer 61 and the second layer 62.

[0079] As a result, the semiconductor manufacturing jig 1a has a configuration in which a first layer 11a is formed on the upper surface and a second layer 12a is formed on the lower surface, as shown in Figure 8.

[0080] By performing the same processing on the first component as described above for the second component, a semiconductor manufacturing jig 1a with the configuration shown in Figure 8 can be obtained.

[0081] In Embodiment 2, as described above, after forming a laminate 6 as shown in Figure 5 with the CVD film deposition apparatus 4, the laminate 6 is processed with the processing apparatus as shown in Figure 9, thereby obtaining a semiconductor manufacturing jig 1a with the configuration shown in Figure 8 from the laminate 6.

[0082] [Differentiation] In the semiconductor manufacturing jig 1 according to Embodiment 1, a configuration in which the resistivity differs radially on the upper surface was described, as shown in Figure 1. Specifically, in the semiconductor manufacturing jig 1 shown in Figure 1, the inner circumference side is composed of a first layer 11 with a first resistivity, and the outer circumference side is composed of a second layer 12 with a second resistivity. Furthermore, in the semiconductor manufacturing jig 1a according to Embodiment 2, a configuration in which the resistivity differs in the thickness direction was described, as shown in Figure 8. Specifically, in the semiconductor manufacturing jig 1a shown in Figure 8, the upper surface side is composed of a first layer 11a with a first resistivity, and the lower surface side is composed of a second layer 12a with a second resistivity. However, the semiconductor manufacturing jig according to this disclosure is not limited to a configuration in which the resistivity differs radially or in the thickness direction. The semiconductor manufacturing jig according to this disclosure only needs to have a part with different resistivity in any part of its configuration.

[0083] For example, a semiconductor manufacturing jig may have a configuration in which the resistivity differs in the circumferential direction on its upper surface. Figure 10 is a plan view of a modified semiconductor manufacturing jig 1b. When viewed from above in a plan view, as shown in Figure 10, the semiconductor manufacturing jig 1b has different resistivity in quarters. Specifically, the semiconductor manufacturing jig 1b is composed of a first region with a layer 11c having a first resistivity, a second region with a layer 12c having a second resistivity, a third region with a layer 11d having a first resistivity, and a fourth region with a layer 12d having a second resistivity. In the semiconductor manufacturing jig 1b, the region is divided by two layers with different resistivity, but the region may be divided by three or more layers with different resistivity. Also, in the semiconductor manufacturing jig 1b, the upper surface region is divided equally into quarters, but the upper surface region does not have to be divided equally.

[0084] The manufacturing method for semiconductor manufacturing jig 1b allows for the formation of regions with different resistivity by, for example, repeatedly performing the process of depositing and processing SiC using a CVD film deposition apparatus.

[0085] [Pattern] (Section 1) The semiconductor manufacturing jig relating to this disclosure is A semiconductor manufacturing jig used in semiconductor manufacturing equipment, A first layer having a first resistivity, The device comprises a first layer and a second layer stacked on top of it, the second layer having a second resistivity different from the first resistivity.

[0086] (Article 2) The semiconductor manufacturing jigs described in Article 1 are: The second resistivity is greater than the first resistivity.

[0087] (Article 3) The semiconductor manufacturing fixtures described in Article 1 or Article 2 are: The semiconductor manufacturing jig has a first main surface and a second main surface facing the first main surface. When viewed from the first main surface in a plan view, the first layer is located in the inner part, and the second layer is located in the outer part.

[0088] (Article 4) The semiconductor manufacturing fixture described in any one of paragraphs 1 to 3 is: The semiconductor manufacturing jig has a first main surface and a second main surface facing the first main surface. The first layer is placed on the first main surface, and the second layer is placed on the second main surface.

[0089] (Article 5) The semiconductor manufacturing fixture described in any one of paragraphs 1 to 4 is: The first and second layers are made of SiC.

[0090] (Article 6) The semiconductor manufacturing fixture described in any one of paragraphs 1 to 5 is: The semiconductor manufacturing equipment is a plasma etching system.

[0091] (Section 7) The semiconductor manufacturing fixture described in any one of paragraphs 1 to 6 is: The jig used in semiconductor manufacturing is an etcher.

[0092] (Paragraph 8) The method for manufacturing semiconductor manufacturing jigs relating to this disclosure is: A method for manufacturing semiconductor manufacturing jigs used in semiconductor manufacturing equipment, A step of forming a first layer having a first resistivity around the substrate, A step of laminating a second layer having a second resistivity different from the first resistivity onto the first layer, A process of processing the stacked first and second layers into a predetermined shape, The process includes a step of removing the substrate.

[0093] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims rather than by the description of the embodiments above, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of symbols]

[0094] 1,1a,1b Semiconductor manufacturing jig, 2 Wafer, 4 CVD film deposition apparatus, 5 Substrate, 6 Laminate, 11,11a,61 First layer, 12,12a,62 Second layer, 13,53,63 Space, 14 Holding section, 41 Chamber, 42 High-frequency power supply, 43 Vacuum pump, 44 Raw material gas container, 46 Film deposition stage, 47 Heater, 48 Shower head, 49 Control device.

Claims

1. A semiconductor manufacturing jig used in semiconductor manufacturing equipment, A first layer having a first resistivity, A semiconductor manufacturing jig comprising: a first layer laminated with a second layer having a second resistivity different from the first resistivity.

2. The semiconductor manufacturing jig according to claim 1, wherein the second resistivity is greater than the first resistivity.

3. The semiconductor manufacturing jig has a first main surface and a second main surface facing the first main surface. The semiconductor manufacturing jig according to claim 1 or claim 2, wherein, when viewed from the first main surface in a plan view, the first layer is arranged in the inner portion and the second layer is arranged in the outer portion.

4. The semiconductor manufacturing jig has a first main surface and a second main surface facing the first main surface. The semiconductor manufacturing jig according to claim 1 or claim 2, wherein the first layer is arranged on the first main surface and the second layer is arranged on the second main surface.

5. The semiconductor manufacturing jig according to claim 1 or claim 2, wherein the first layer and the second layer are made of SiC.

6. The semiconductor manufacturing apparatus is a plasma etching apparatus, as described in claim 1 or claim 2.

7. The semiconductor manufacturing jig according to claim 1 or claim 2, wherein the semiconductor manufacturing jig is an etchering ring.

8. A method for manufacturing semiconductor manufacturing jigs used in semiconductor manufacturing equipment, A step of forming a first layer having a first resistivity around the substrate, A step of laminating a second layer having a second resistivity different from the first resistivity onto the first layer, A process of processing the stacked first and second layers into a predetermined shape, A method for manufacturing a semiconductor manufacturing jig, comprising the step of removing the aforementioned substrate.

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