Semiconductor wafer reproduction apparatus and semiconductor wafer reproduction method

Abstract

We provide a semiconductor wafer reproduction device that cuts and reproduces semiconductor wafers. [Solution] The system comprises a planar arrangement means 11 for taking out the fractured chips from an assembly of fractured chips obtained by cutting a semiconductor wafer and arranging each one individually on a plane; a surface arrangement means 12 for arranging each fractured chip on a plane with its surface facing upwards; a shape / circuit pattern detection and storage means 13 for detecting the shape data and circuit pattern data formed on the surface of each fractured chip, and storing them with identification information; and a reproduction means 14 for comparing data from the semiconductor wafer before it was cut with the data stored in the shape / circuit pattern detection and storage means 13, and reproducing the position of each fractured chip on the semiconductor wafer before it was cut by arranging each fractured chip.

Description

Technical Field

[0001] This invention relates to a semiconductor wafer reproduction apparatus and a semiconductor wafer reproduction method.

Background Art

[0002] In the process of manufacturing semiconductor devices, semiconductor wafers may be cut accidentally or for testing purposes. In this case, it is extremely unfavorable in terms of confidentiality if even one of the cut chips generated by the cutting is lost. Therefore, a method is adopted to check whether the cut chips generated by the cutting are lost by reproducing the semiconductor wafer before the cut chips are arranged and cut.

[0003] Conventionally, techniques such as chip posture adjustment, rotation, imaging of the surface image of the wafer surface, registering the positional relationship of the wafer as an image, and assigning an ID to a semiconductor chip are known, but there is no disclosure regarding a specific method for restoring the wafer.

[0004] Patent Document 1 discloses a method for restoring the positions of semiconductor components on a wafer on which those semiconductor components were placed after cutting the semiconductor components from the wafer, and an apparatus configured to implement this method.

[0005] This method is a method for obtaining a mapping rule for mapping a second variable belonging to a second set consisting of second variables to a plurality of first variables belonging to a first set consisting of first variables. Specifically, it includes steps of initializing the mapping rule, preparing the first set and the second set, where the first set has more variables than the second set, randomly selecting a plurality of first variables, the number of the selected first variables corresponding to at least the following number, that is, the first set has more variables than the second set by that number, and repeating the following steps a) to d).

[0006] In other words, steps a) to d) are, a) A step of training the machine learning system to determine the second variable, which is mapped according to the mapping rule, depending on the first variable of the first set that does not include the selected first variable, b) A step of obtaining a cost matrix, wherein the entries of the cost matrix represent the distance between predictions of the machine learning system, depending on the first variable of the first set and the second variable of the second set. c) A step of optimizing the mapping rule in relation to the cost matrix such that the mapping of the first variable to the second variable according to the mapping rule yields the minimum total cost based on the entries in the cost matrix. d) A step of selecting a first variable which is not mapped to one of the second variables by the optimized mapping rule, That is the case.

[0007] Patent Document 2 discloses a novel and improved semiconductor wafer processing method that makes it possible to manufacture semiconductor devices without a decrease in productivity even when using cracked semiconductor wafers.

[0008] The method described in Patent Document 2 is a method for processing a broken semiconductor wafer used in the manufacture of a semiconductor device. The broken semiconductor wafer is restored to its original state and bonded to a predetermined substrate via foam tape. Furthermore, a resin is coated onto the restored semiconductor wafer, the resin is dried, cuts are made in the shape of the semiconductor wafer, the foam tape is foamed, the semiconductor wafer is peeled off in the shape of the semiconductor wafer, and the resin is cured with a predetermined resin curing means. By performing predetermined post-processing on the semiconductor wafer restored in this way, throughput and yield can be improved.

[0009] Patent Document 3 discloses that when a semiconductor wafer is broken, it is practically impossible to accurately restore it to its original shape, and because the shape of the object to be processed is not fixed, a lot of manual work is required in the transportation by automated machines and processing in each processing device, making it difficult to reduce labor and lowering productivity.

[0010] Therefore, the invention described in Patent Document 3 was made in view of the above-mentioned problems, and its purpose is to provide a means to reduce manual labor in transportation by automated machines and processing in each processing device.

[0011] Patent Document 3 describes a method for loading and unloading substrates into and out of one or more processing apparatuses for processing substrates, characterized in that a tray holding the substrates with the back surface of the processing surface of the substrates in contact with the tray surface is loaded into and out of the one or more processing apparatuses. The substrates are configured in which multiple broken pieces of a substrate are arranged in substantially the shape of the original substrate. [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] Japanese Patent Publication No. 2023-036038 [Patent Document 2] Japanese Patent Publication No. 2000-049065 [Patent Document 3] Japanese Patent Publication No. 2001-210708 [Overview of the project] [Problems that the invention aims to solve]

[0013] The present invention provides a semiconductor wafer reproduction apparatus and a semiconductor wafer reproduction method that can detect an excess or deficiency of even one of the fractured chips caused by a fractured semiconductor wafer by reproducing the fractured semiconductor wafer. [Means for solving the problem]

[0014] A semiconductor wafer reproduction apparatus according to an embodiment of the present invention comprises: a planar arrangement means for taking out fractured chips from an aggregate of fractured chips, which is an assembly of multiple fractured chips generated when a semiconductor wafer is fractured, and arranging each one individually on a plane; a surface arrangement means for detecting the surface based on the color of the front and back sides of each fractured chip that has been individually arranged on a plane, and arranging each fractured chip on a plane with the surface facing up; a shape and circuit pattern detection and storage means for detecting the shape data and circuit pattern data formed on the surface of each fractured chip that has been arranged with the surface facing up, and storing them with identification information; and a reproduction means that has the shape data and circuit pattern data formed on the surface of a semiconductor wafer before it was fractured, compares the shape data and circuit pattern data of this semiconductor wafer with the shape data and circuit pattern data of the fractured chips stored in the shape and circuit pattern detection and storage means, identifies the position of each fractured chip on the semiconductor wafer before it was fractured, and reproduces the semiconductor wafer before it was fractured by arranging each fractured chip.

[0015] A semiconductor wafer reproduction method according to an embodiment of the present invention comprises: a planar arrangement step of taking out fractured chips from an aggregate of fractured chips, which is an assembly of multiple fractured chips resulting from the fracture of a semiconductor wafer, and arranging each one individually on a plane; a surface arrangement step of detecting the surface based on the colors of the front and back of each fractured chip that have been individually arranged on a plane, and arranging each fractured chip on a plane with the surface facing up; a shape and circuit pattern detection and storage step of detecting the shape data and circuit pattern data formed on the surface of each fractured chip that has been arranged with the surface facing up, and storing them with identification information; and a reproduction step of having the shape data and circuit pattern data of a semiconductor wafer before it was fractured, comparing the shape data and circuit pattern data of this semiconductor wafer with the shape data and circuit pattern data of the fractured chips stored in the shape and circuit pattern detection and storage step, identifying the position of each fractured chip on the semiconductor wafer before it was fractured, and arranging each fractured chip to reproduce the semiconductor wafer before it was fractured. [Brief explanation of the drawing]

[0016] [Figure 1] A block diagram of a semiconductor wafer reproduction apparatus according to an embodiment of the present invention, configured using a computer system. [Figure 2] A block diagram of means for realizing a semiconductor wafer reproduction device according to an embodiment of the present invention, which is stored in an external memory device. [Figure 3] A perspective view of a semiconductor wafer before it was cut. [Figure 4] A plan view of a fractured chip resulting from the fracture of a semiconductor wafer. [Figure 5] A flowchart illustrating the operation of the semiconductor wafer reproduction apparatus of this embodiment. [Figure 6] Side view of an assembly of stacked fractured chips. [Figure 7] A side view of each individual cut chip arranged on a flat surface. [Figure 8]A diagram showing an example of identification information stored in a storage area for shape data of an external storage device and the shape data and circuit pattern data of a corresponding diced chip. [Figure 9] A diagram showing an example of color data captured by a camera. [Figure 10] A diagram showing an example of a state in which a part of an A-type diced chip having an outer peripheral shape that matches the outer peripheral shape of the semiconductor wafer before dicing is arranged along the outer peripheral shape of the original semiconductor wafer. [Figure 11] A diagram showing an example of a state in which all A-type diced chips having an outer peripheral shape that matches the outer peripheral shape of the semiconductor wafer before dicing are arranged along the outer peripheral shape of the original semiconductor wafer. [Figure 12] A diagram showing an example of a state in which B-type diced chips other than all A-type diced chips having an outer peripheral shape that matches the outer peripheral shape of the semiconductor wafer before dicing are arranged along the original semiconductor wafer.

Embodiments for Carrying Out the Invention

[0017] Hereinafter, embodiments of a semiconductor wafer reproduction apparatus and a semiconductor wafer reproduction method of the present invention will be described with reference to the accompanying drawings. In each figure, the same reference numerals are given to the same components and redundant descriptions are omitted. The semiconductor wafer reproduction apparatus according to an embodiment of the present invention is constituted by a computer system 100 shown in FIG. 1.

[0018] This computer system 100 is configured such that, for example, a CPU 110 forming the core of a personal computer or the like shown in FIG. 1 controls a camera 200 to image a diced chip, obtains the image data, and based on this image data, obtains the shape data and surface circuit pattern data of the diced chip, and uses this to control a manipulator 300 to arrange each diced chip to reproduce the semiconductor wafer before dicing.

[0019] As shown in Figure 1, the computer system 100 is configured such that the CPU 110 uses programs and data in the main memory 111 to construct a semiconductor wafer reproduction device. The CPU 110 is connected to an external storage interface 113, an input interface 114, a display interface 115, and I / O interfaces 160 and 170 via a bus 112.

[0020] An external storage device 123 is connected to the external storage interface 113. The external storage device 123 stores programs and data necessary for the system to operate, which the CPU 110 can read and use from the main memory 111 as needed. For this reason, the external storage device 123 stores programs that implement the planar arrangement means 11, the surface arrangement means 12, the shape / circuit pattern detection and storage means 13, the reproduction means 14, the area calculation means 15, the determination means 16, and the outer perimeter part reproduction means 17. An input device 124 such as a keyboard or touch panel and a pointing device 122 such as a mouse are connected to the input interface 114. A display device 125 having a screen such as an LCD is connected to the display interface 115, and the display device 125 implements output means for various displays. A camera 200 is connected to the IO interface 160, and the camera 200 functions to obtain image data by capturing multiple fractured chips resulting from the fracture of a semiconductor wafer from the top, side, and other necessary directions. The number of cameras 200 is arbitrary. A manipulator 300 is connected to the IO interface 170, which can move the fractured chip by sucking and gripping it. Multiple manipulators 300, each capable of independently moving the fractured chip by sucking and gripping it, may be provided.

[0021] As shown in Figure 2, the planar arrangement means 11, surface arrangement means 12, shape / circuit pattern detection and storage means 13, reproduction means 14, area calculation means 15, determination means 16, and outer peripheral part reproduction means 17, which are stored in the external storage device 123, will be described below. The planar arrangement means 11 takes out fractured chips from an aggregate of fractured chips, which is made up of multiple fractured chips generated when a semiconductor wafer is fractured, and arranges each one individually on a plane.

[0022] As shown in Figure 3, a semiconductor wafer before being cut is, for example, disc-shaped, with a rectangular die 42 separated by scribe lines 41. The scribe lines 41 are so thin that they are indistinguishable to the naked eye. After wafer processing is complete, the wafer is cut along the scribe lines 41 with a diamond blade to form a semiconductor chip from the die 42 portion.

[0023] In this embodiment, since the wafer is cut by hand or other means without using a diamond blade for testing, the area kk around the cut chip of one chip takes on the shape of a jagged wavy line LL as shown in Figure 4(c). Also, Figure 4(a) shows a type A cut chip 44 that includes the outer periphery of the semiconductor wafer before cutting, and Figure 4(b) shows a type B cut chip 45 that does not include the outer periphery of the semiconductor wafer before cutting. Note that in type A cut chips 44 and type B cut chips 45, the cut line is basically horizontal or vertical, or the cut is only slightly tilted by 1 to 2 degrees from horizontal or vertical. Figure 4(a) may not include a die 42. Figure 4(b) may include two or more dies 42. Circuit patterns are provided on the front and back sides of cut chips that include two or more dies 42.

[0024] The surface arrangement means 12 detects the surface based on the color of the front and back of each individual fractured chip arranged on a plane, and arranges each fractured chip on the plane with the surface facing up. The shape / circuit pattern detection and storage means 13 detects the shape data and circuit pattern data formed on the surface of each fractured chip arranged with the surface facing up, and stores them with identification information. The reproduction means 14 has the shape data and circuit pattern data formed on the surface of the semiconductor wafer before it was fractured, and compares the shape data and circuit pattern data of this semiconductor wafer with the shape data and circuit pattern data of the fractured chips stored in the shape / circuit pattern detection and storage means 13 to identify the position of each fractured chip on the semiconductor wafer before it was fractured, and reproduces the semiconductor wafer before it was fractured by arranging each fractured chip.

[0025] The area calculation means 15 uses the shape data of the fractured chips stored in the shape / circuit pattern detection and storage means 13 to obtain the area data of each fractured chip stored in the shape / circuit pattern detection and storage means 13. The determination means 16 compares the sum of the area data of all fractured chips obtained by the area calculation means 15 with the total area data of the semiconductor wafer before fracture, and determines whether there are any missing fractured chips or inappropriate fractured chips included in the aggregate of fractured chips.

[0026] The peripheral portion reproduction means 17 is provided in the reproduction means 14 and detects which position near the outer edge of the semiconductor wafer before it was cut the fractured chip whose peripheral shape matches a portion of the outer shape, and arranges the fractured chip at the position where the outer shape matches.

[0027] In the above description, the shape and circuit pattern detection and storage means 13 detects the shape data and circuit pattern data formed on the surface of each of the fractured chips arranged with their surfaces facing upwards, and stores them with identification information. In reality, as shown in Figure 2, the identification information and the shape data and circuit pattern data of the corresponding fractured chip are stored together in the shape data storage area 18 of the external storage device 123.

[0028] The semiconductor wafer reproduction apparatus of this embodiment operates according to the flowchart shown in Figure 5, so the operation will be explained using this flowchart. The multiple fractured chips 51 generated when the semiconductor wafer is fractured are used for purposes such as testing, and the necessary parts are assembled into an assembly 50 as shown in Figure 6. In this state, the CPU 110 takes out one fractured chip from each of the stacked fractured chips in the assembly, grasps it with the side containing the circuit pattern facing upwards, and proceeds to the next process (S11).

[0029] Next, the CPU 110 assigns identification information to the extracted fractured chip 51 and detects the shape data and attached circuit pattern data of the fractured chip (S12). Furthermore, the CPU 110 stores the identification information, the corresponding shape data and circuit pattern data of the fractured chip (including the current position information of the fractured chip) as a set in the shape data storage area 18 of the external memory device (S13). The stored identification information and the corresponding shape data and circuit pattern data of the fractured chip are stored as shown in Figure 8, and the shape data and circuit pattern data can be image data including color data captured by the camera 200.

[0030] Furthermore, the CPU 110 arranges the fractured chips being processed, which have identification information stored in the shape data storage area 18, in a planar arrangement area with their surface facing upwards (S14). Figure 7 shows a side view of each fractured chip 51 arranged individually on the plane. Since the shape data and circuit pattern data are image data including color data captured by the camera 200, the color data of the front of the semiconductor wafer before fracture is stored in advance as image data, for example, as shown in Figure 9(a), and the color data of the back of the semiconductor wafer before fracture is stored in advance as image data, for example, as shown in Figure 9(b). Based on a comparison of this stored color data with the color data of the fractured chip captured by the camera 200, the front and back sides can be detected. The position information of the fractured chips is updated and stored each time the arrangement is updated. Here, it is detected whether identification information has been assigned to all fractured chips (S20), and if the branch is NO, the process returns to step S11 and continues.

[0031] If the branch is YES in step S20, the CPU 110 uses the shape data of each fractured chip stored in the shape data storage area to obtain area data, compares the sum of the area data of all fractured chips obtained with the total area data of the semiconductor wafer before fracture, and determines whether there are any missing fractured chips or inappropriate fractured chips included in the above-mentioned assembly of fractured chips 50 (S15). By displaying this result on the display device 125, for example, preliminary knowledge can be obtained before reconstructing the semiconductor wafer, such as whether there are any missing fractured chips or whether fractured chips from different semiconductor wafers have been mixed in.

[0032] Furthermore, for A-type fractured chips that have an outer perimeter shape matching the outer perimeter shape of the semiconductor wafer before fracture, the CPU 110 changes the orientation of the A-type fractured chip so that its outer perimeter shape matches the outer perimeter shape of the semiconductor wafer, and places it in a position where the outer perimeter shapes match (S16). For example, as shown in Figure 10, if there is an outer perimeter line GL of the semiconductor wafer before fracture, the A-type fractured chip 44 is changed in orientation so that its own outer perimeter shape and circuit pattern match the outer perimeter shape of the semiconductor wafer, and is placed in a state where its own outer perimeter shape matches the outer perimeter shape of the semiconductor wafer. All A-type fractured chips 44 that have an outer perimeter shape matching the outer perimeter shape of the semiconductor wafer before fracture are placed in the same manner. Figure 11 shows the state after all A-type fractured chips 44 have been placed.

[0033] Next, the CPU 110 changes the orientation of a Type B fractured chip that does not have an outer edge shape that matches the outer edge shape of the semiconductor wafer before fracture, so that its outer edge shape and circuit pattern match a part of the boundary line shape of a fractured chip that is already placed on it, and further positions the Type B fractured chip in this orientation at a position where the outer edge shape of the Type B fractured chip matches a part of the boundary line shape (matching the shape of the jagged wavy line LL) (S17).

[0034] As shown in Figure 12, once all A-type fracture chips 44 have been placed, in the initial stages thereafter, B-type fracture chips 45 with an outer perimeter shape that matches the shape of the edges of the A-type fracture chips 44 that are not connected to other fracture chips are detected based on the shape data storage area 18 of the external storage device 123 and image data captured by the camera 200 of the current placement state. When there are no more A-type fracture chips 44 that are on the outer perimeter and not connected to other fracture chips, B-type fracture chips 45 with an outer perimeter shape that matches the shape of the edges that are not connected to other fracture chips are detected based on the shape data storage area 18 of the external storage device 123 and image data captured by the camera 200 of the current placement state. The B-type fracture chips 45 detected in this way are then repositioned so that they match the circuit pattern of the semiconductor wafer, and placed in positions that match the shape of the edges that are not connected to other fracture chips, as indicated by the arrows in Figure 12. This process is basically performed for all B-type fracture chips 45, from the periphery towards the center, until all fracture chips are placed and the process is complete.

[0035] As described above, in this invention, by cutting and reconstructing a semiconductor wafer, it becomes possible to detect an excess or deficiency even if only one of the fractured chips resulting from the cutting is present. [Explanation of symbols]

[0036] 11 Planar arrangement means 12 Surface arrangement means 13. Shape / Circuit Pattern Detection and Storage Means 14 Reproduction means 15 Area calculation method 16 Judgment means 17 External part reproduction means 18. Storage area for shape data, etc. 41 Scribeline 44 Type A splitting chip 45 Type B Split Chip 50 Aggregate 51 Split Chips 100 Computer Systems 110 CPU 111 Main Memory 112 Bus 113 External Storage Interface 114 Input Interfaces 115 Display Interface 122 Pointing devices 123 External storage device 124 Input Devices 125 Display device 160 I / O interfaces 170 IO interfaces 200 Cameras 300 Manipulators GL Outer boundary

Claims

1. A planar arrangement means for taking out fractured chips from an aggregate of fractured chips, which is an assembly of multiple fractured chips resulting from the fracture of a semiconductor wafer, and arranging each one individually on a plane, A surface arrangement means detects the surface based on the color of the front and back of each individual cut chip arranged on a plane, and arranges each cut chip on a plane with the surface facing upwards, A shape and circuit pattern detection and storage means detects the shape data and circuit pattern data formed on the surface of each of the cut chips arranged with their surface facing upwards, and stores them with identification information. The system has shape data and circuit pattern data formed on the surface of a semiconductor wafer before it is fractured, and compares the shape data and circuit pattern data of this semiconductor wafer with the shape data and circuit pattern data of fractured chips stored in the shape / circuit pattern detection and storage means to identify the position of each fractured chip on the semiconductor wafer before it was fractured, and reproduces the semiconductor wafer before it was fractured by arranging each fractured chip. A semiconductor wafer reproduction apparatus characterized by comprising the following:

2. An area calculation means that uses shape data of the fractured chips stored in the shape and circuit pattern detection and storage means to obtain area data of each fractured chip stored in the shape and circuit pattern detection and storage means, A determination means compares the sum of the area data of all fractured chips obtained by the area calculation means with the total area data of the semiconductor wafer before fracture, and determines whether there are missing fractured chips or inappropriate fractured chips included in the assembly of fractured chips. The semiconductor wafer reproduction apparatus according to claim 1, characterized by comprising the following:

3. The semiconductor wafer reproduction apparatus according to claim 1, characterized in that the reproduction means includes an outer peripheral reproduction means that detects at which position near the outer periphery of the semiconductor wafer prior to being cut a fractured chip whose outer peripheral shape matches a part of the outer peripheral shape of the semiconductor wafer prior to being cut, and arranges the fractured chip at the position where the outer peripheral shape matches.

4. The semiconductor wafer reproduction apparatus according to claim 1, characterized in that the reproduction means rotates the fractured chip and determines the position where it was placed based on the circuit pattern data of the fractured chip.

5. The semiconductor wafer reproduction apparatus according to claim 3, characterized in that the outer peripheral portion reproduction means determines the position of a fractured chip having circuit pattern data before determining the position of a fractured chip that does not have circuit pattern data.

6. The semiconductor wafer reproduction apparatus according to claim 3, characterized in that the reproduction means performs the processing by the outer peripheral portion reproduction means before processing the fractured chips in which a part of the outer peripheral shape of the semiconductor wafer before fracture does not match a part of the outer peripheral shape.

7. The semiconductor wafer reproduction apparatus according to claim 6, characterized in that the reproduction means performs processing on the fractured chips in which a part of the outer peripheral shape of the semiconductor wafer before fracture does not match a part of the outer peripheral shape of the semiconductor wafer before fracture, after the completion of processing by the outer peripheral partial reproduction means.

8. The semiconductor wafer reproduction apparatus according to claim 7, characterized in that, when processing a fractured chip in which a part of the outer peripheral shape of the semiconductor wafer before fracture does not match a part of the outer peripheral shape, the reproduction means detects a position in which the outer peripheral shape pattern data that is in contact with an unadjacent fractured chip caused by an already placed fractured chip matches the shape data of an unplaced fractured chip, and then places the chip.

9. The semiconductor wafer reproduction apparatus according to claim 1, comprising a manipulator that moves fractured chips by sucking and gripping them, and characterized in that it reproduces the semiconductor wafer before it was fractured by actually arranging each fractured chip.

10. A planar arrangement step involves taking out the fractured chips from an aggregate of fractured chips, which is an assembly of multiple fractured chips resulting from the fracture of a semiconductor wafer, and arranging each one individually on a plane, A surface arrangement step involves detecting the surface based on the color of the front and back of each individual cut chip, which are laid out on a plane, and arranging each cut chip on a plane with the surface facing upwards, For each of the cut chips arranged with their surface facing upwards, the shape data and circuit pattern data formed on the surface are detected and stored with identification information in a shape and circuit pattern detection and storage step. The process involves having shape data and circuit pattern data formed on the surface of a semiconductor wafer before it is fractured, comparing the shape data and circuit pattern data of this semiconductor wafer with the shape data and circuit pattern data of the fractured chips accumulated in the shape and circuit pattern detection and accumulation step, identifying the position of each fractured chip on the semiconductor wafer before it was fractured, and reconstructing the semiconductor wafer before it was fractured by arranging each fractured chip. A semiconductor wafer reproduction method characterized by comprising the following:

11. An area calculation step is performed to obtain area data for each fractured chip stored in the shape and circuit pattern detection and storage step using the shape data for the fractured chips stored in the shape and circuit pattern detection and storage step, A determination step is performed to compare the sum of the area data of all fractured chips obtained in the area calculation step with the total area data of the semiconductor wafer before fracture, and to determine whether there are any missing fractured chips or any inappropriate fractured chips included in the assembly of fractured chips. The semiconductor wafer reproduction method according to claim 10, characterized by comprising the above.

12. The semiconductor wafer reproduction method according to claim 10, characterized in that the reproduction step includes an outer peripheral reproduction step for detecting at what position near the outer periphery of the semiconductor wafer prior to cleavage the cleaved chip, whose outer peripheral shape matches a portion of the outer peripheral shape of the semiconductor wafer prior to cleavage, was located.

13. The semiconductor wafer reproduction method according to claim 10, characterized in that the reproduction step involves rotating the fractured chip to determine its position based on the circuit pattern data of the fractured chip.

14. The semiconductor wafer reproduction method according to claim 12, characterized in that, in the outer peripheral portion reproduction step, the position determination of the fractured chip having circuit pattern data is performed before the position determination of the fractured chip not having circuit pattern data.

15. The semiconductor wafer reproduction method according to claim 12, characterized in that the reproduction step is performed before the processing for the fractured chip in which a part of the outer peripheral shape of the semiconductor wafer before fracture does not match a part of the outer peripheral shape of the semiconductor wafer before fracture.

16. The semiconductor wafer reproduction method according to claim 15, characterized in that, after the completion of the processing by the outer peripheral portion reproduction step, processing is performed on the fractured chip whose outer peripheral shape does not match a part of the outer peripheral shape of the semiconductor wafer before fracture.

17. The semiconductor wafer reproduction method according to claim 16, characterized in that, in the reproduction step, when processing fractured chips in which a part of the outer peripheral shape of the semiconductor wafer before fracture does not match a part of the outer peripheral shape, the position in which the outer peripheral shape pattern data in contact with an unadjacent fractured chip caused by an already placed fractured chip matches the shape data of an unplaced fractured chip is detected and the chip is placed.

18. The semiconductor wafer reproduction method according to claim 10, characterized in that a manipulator is used to move the fractured chips by sucking and gripping them, and the fractured chips are actually lined up to reproduce the semiconductor wafer before it was fractured.

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