Electronic devices with inverted lead pins
Inverting the lead pins and die mounting pads in the electronic device configuration addresses the issue of arc discharge by minimizing the external electric field, thereby safeguarding the IC and PCB from damage.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2026-03-16
- Publication Date
- 2026-06-09
AI Technical Summary
Arc discharge occurs between low-voltage lead pins and the electrical termination on the printed circuit board due to an external electric field, leading to damage to electronic components.
The electronic device is configured with inverted lead pins and die mounting pads, where the low-voltage die and high-voltage die are embedded in the package with an offset, and the lead pins extend away from the package in a direction opposite to the die mounting pads, increasing the distance between them and reducing the external electric field.
The inverted configuration substantially reduces or eliminates the external electric field, preventing arc discharge and protecting the IC and PCB from damage.
Smart Images
Figure 2026094452000001_ABST
Abstract
Description
Technical Field
[0001] This application relates to an electronic device having inverted lead pins.
Background Art
[0002] An integrated circuit (IC) requires a conductive connection to provide a conductive connection between the contact pads of the IC to the IC package leads or lead pins. In some applications, the IC includes a low voltage side having a low voltage die and a high voltage side having a high voltage die. When the IC is powered on, an electric field is generated inside the IC package (internal electric field) between the die attachment pads on both the low voltage side and the high voltage side. The internal electric field is isolated by the package and has little impact on the IC. However, the electric field spreads outside the IC package (external electric field) on the low voltage side of the IC towards the low voltage lead pins. The external electric field causes an arc to occur between the lead pins on the low voltage side of the IC. Arc discharge can also occur between the low voltage lead pins and the electrical termination on the printed circuit board to which the IC is attached. Arc discharge ultimately leads to damage to the electronic components including the IC.
Summary of the Invention
[0003] As an example, an electronic device including a package is described. This package has a longitudinal centerline, a mounting portion on one side of the longitudinal centerline, and an unmounted portion on the opposite side of the longitudinal centerline. A low-voltage die mounting pad is embedded in the unmounted portion of the package and includes a first side facing toward the longitudinal centerline and a second side facing away from the longitudinal centerline. A low-voltage die is mounted on the first side of the low-voltage die mounting pad. Inverted low-voltage lead pins extend from the package toward the mounting portion and away from the unmounted portion of the package. A high-voltage die mounting pad is embedded in the unmounted portion of the package and includes a first side facing toward the longitudinal centerline and a second side facing away from the longitudinal centerline. A high-voltage die is mounted on the first side of the high-voltage die mounting pad. Inverted high-voltage lead pins extend from the package toward the mounting portion and away from the unmounted portion of the package.
[0004] In another example, an integrated circuit including a package is described. The package has a longitudinal centerline extending from the low-voltage side to the high-voltage side of the package. The package further includes a mounting portion on one side of the longitudinal centerline and a non-mounting portion on the opposite side of the longitudinal centerline. The low-voltage die mounting pad is embedded in the package and includes a first side facing toward the longitudinal centerline toward the mounting portion of the package and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package. The low-voltage die pad is also displaced by a first offset from the longitudinal centerline toward the non-mounting portion of the package. The low-voltage die is mounted on the first side of the low-voltage die mounting pad. The low-voltage lead pins extend from the package away from the longitudinal centerline, opposite to the direction of the first offset. The high-voltage die mounting pad is embedded in the package and includes a first side facing toward the longitudinal centerline toward the mounting portion of the package and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package. The high-voltage die pad is displaced with a first offset from the longitudinal centerline toward the non-mounted portion of the package. The high-voltage die is mounted on the first side of the high-voltage die mounting pad. The inverted high-voltage lead pins extend from the package away from the longitudinal centerline, in the opposite direction to the first offset.
[0005] In another example, a method includes mounting a low-voltage die to a low-voltage die mounting pad and a high-voltage die to a high-voltage die mounting pad. The first end of at least one low-voltage lead pin is mounted to the low-voltage die mounting pad, and the first end of at least one high-voltage lead pin is mounted to the high-voltage die mounting pad. The low-voltage die and the high-voltage die are placed in a cavity defined in the package body of the integrated circuit. The low-voltage die, the high-voltage die, the low-voltage die mounting pad, and the high-voltage die mounting pad are sealed within the package of the integrated circuit, where the low-voltage die mounting pad and the high-voltage die mounting pad are displaced by a first offset from the longitudinal centerline of the package of the integrated circuit toward the unmounted portion of the package. The second end of at least one low-voltage lead pin and the second end of at least one high-voltage lead pin, which are located outside the package, are curved away from the longitudinal centerline of the package and in the opposite direction to the first offset. [Brief explanation of the drawing]
[0006] [Figure 1] This is a top perspective view of the example integrated circuit.
[0007] [Figure 2A] This is an end view of an example integrated circuit.
[0008] [Figure 2B] This is an infrared image of the end view of the example integrated circuit shown in Figure 2A.
[0009] [Figure 3A] This is an inverted end view of the example electronic device.
[0010] [Figure 3B] Figure 3A is an uninverted end view of the example electronic device.
[0011] [Figure 3C]This is an infrared image of the end view of the example electronic device shown in Figure 3A.
[0012] [Figure 4] Figures 3A and 3B illustrate the manufacturing process of the electronic devices shown. [Modes for carrying out the invention]
[0013] Figure 1 is a top perspective view of an exemplary integrated circuit (IC) 100, including a low-voltage side 102 and a high-voltage side 104. This type of IC receives an electric field generated inside and outside the package 106 of the IC 100 due to the potential difference between the low-voltage side 102 and the high-voltage side 104. Specifically, the low-voltage side includes one or more low-voltage dies 108 mounted on a low-voltage die pad 110 and low-voltage lead pins 112 extending from the low-voltage die mounting pad 110. Similarly, the high-voltage side 104 includes one or more high-voltage dies 114 mounted on a high-voltage die pad 116 and high-voltage lead pins 118 extending from the high-voltage lead pins 118. In some exemplary ICs, the high-voltage side 104 may further include a power enhancement device 120 made of magnetic material, mounted on a printed circuit board 122 (e.g., a transformer). The power enhancement device 120 generates a magnetic field to enhance the power supplied to the high-voltage side 104. An electric field is generated between the low-voltage die pad 110 and the high-voltage die pad 116 due to the potential difference between these two adjacent low-voltage and high-voltage die pads 110 and 116. The electric field extends outside the package 106 adjacent to the low-voltage lead pins 112 due to the proximity of the high-voltage die pad 116 to the low-voltage lead pins 112. The electric field generated outside the package 106 adjacent to the low-voltage lead pins generates an arc between the IC and the printed circuit board (PCB) on which the IC is mounted, or simply between the adjacent low-voltage lead pins 112. Arc discharge damages the IC and / or PCB. Therefore, described herein are electronic devices (e.g., integrated circuits) that reduce or eliminate the intensity of the electric field generated outside the package of an electronic device adjacent to low-voltage lead pins, and methods for manufacturing such electronic devices. The electronic device includes a low-voltage side and a high-voltage side. The low-voltage side includes a low-voltage die mounted on a low-voltage die mounting pad. Similarly, the high-voltage side includes a high-voltage die mounted on a high-voltage die mounting pad. Lead pins are mounted on the low and high-voltage mounting pads respectively and extend out of the electronic device package in the reverse direction.In other words, the electronic device has an inverted configuration such that the distance between the high-voltage die mounting pad and the low-voltage lead pin does not generate an electric field outside the package in close proximity to the low-voltage lead pin. That is, the die and die mounting pad are embedded in the package inverted, contrary to conventional convention. Furthermore, the lead pins extend from both sides of the package perpendicular to the longitudinal axis of the electronic device, opposite to conventional convention. Figure 2A is an end view of an exemplary integrated circuit (IC) 200A similar to the IC shown in Figure 1, which includes a low-voltage side 202 and a high-voltage side 204, and a package 206 made of a molded compound (e.g., an epoxy compound) that electrically insulates the low-voltage side 202 from the high-voltage side 204. The package 206 includes a longitudinal centerline CL1 extending from the low-voltage side 202 to the high-voltage side 204. The longitudinal centerline CL1 is located in the center of the package 206 in a direction perpendicular to the longitudinal centerline CL1, as indicated by the double-headed arrow A between the first (non-mounting) surface 208 and the second (mounting) surface 210 of the package 206. The mounting surface 210 of the package 206 is the side of the package 206 that faces the PCB when the IC 200A is mounted to the PCB. Therefore, the portion of the package 206 between the longitudinal centerline CL1 and the non-mounting surface 208 is the non-mounting portion NMP of the package 206. Similarly, the portion of the package 206 between the longitudinal centerline CL1 and the mounting surface 210 is the mounting portion MP of the package 206.
[0014] The low-voltage side 202 includes a low-voltage die 212 mounted on a low-voltage die mounting pad (DAP) 214. Similarly, the high-voltage side 204 includes a high-voltage die 216 mounted on a high-voltage die mounting pad (DAP) 218. Both the low-voltage die 212 and the high-voltage die 216 have electronic devices located within them. The low-voltage die 212 and the low-voltage DAP 214 are electrically isolated from the high-voltage die 216 and the high-voltage DAP 218 by the package 206. The low-voltage DAP 214 and the high-voltage DAP 218 are embedded in the mounting portion MP of the package such that both the low-voltage die 212 and the high-voltage die 216 are centrally located along the longitudinal centerline CL1 of the package 206. In other words, both the low-voltage die 212 and the high-voltage die 216 are located midway between the non-mounting surface 208 and the mounting surface 210 of the package 206. IC200A may further include a power enhancement device 220 made of a magnetic material (e.g., a transformer) attached to the high-voltage DAP 218. The power enhancement device 220 generates a magnetic field to enhance the power supplied to the high-voltage side 204. IC200A further includes low-voltage lead pins 222 on the low-voltage side 202 and high-voltage lead pins 224 on the high-voltage side 204. At least one low-voltage pin 202 is attached to and extends from the low-voltage DAP 214, and at least one high-voltage pin 224 is attached to and extends from the high-voltage DAP 218. Both the low-voltage lead pin 222 and the high-voltage lead pin 224 exit the package 206 at exit openings 226, 228 defined in the package 206, respectively, and extend outward from each side of the package 206 along the longitudinal centerline CL1. Next, both the low-voltage lead pin 222 and the high-voltage lead pin 224 are curved toward the high-voltage DAP 218 and the second surface 210 of the package 206. The mounting surfaces 230 of both the low-voltage and high-voltage lead pins 222 and 224 extend beyond the second surface 210 of the package 206 by a predetermined distance d (e.g., 0.314 to 0.414 microns). Figure 2B is an end-view infrared image of an exemplary IC200B similar to IC200A shown in Figure 2A.The infrared image in Figure 2A shows the presence or absence of electric fields dispersed inside and outside package 206. Specifically, the shaded areas enclosed by the dotted circles 232 inside and outside package 206 indicate the presence of electric fields. As mentioned above, the electric field 232 is generated by the potential difference between the low-voltage side 202 and the high-voltage side 204 during the startup and / or operation of ICs 200A and 200B. Specifically, during startup, the voltage on the high-voltage DAP 218 can increase to approximately 7,000 volts, which can damage the low-voltage side 202. The electric field 232A inside package 206 is isolated by package 206 and therefore its effect on the IC or other nearby electronic components is negligible. However, the electric field 232B outside the package is located close to the low-voltage lead pin 222, which can cause arcing between the IC and the printed circuit board (PCB) on which the IC is mounted, thereby damaging the IC and / or the PCB. The electric field 232B exists due to the configuration of the low-voltage lead pin 222 relative to the high-voltage DAP 218. More specifically, as described above, the low-voltage lead pin 222 is curved toward the high-voltage DAP 218. Therefore, both the high-voltage DAP 218 and the low-voltage lead pin 222 are on the same side of the longitudinal centerline CL1. Thus, the distance Dl between the high-voltage DAP 218 and the low-voltage lead pin 222 is close enough to generate the electric field 232B outside the package 206. The electric field 232B causes an arc between the IC and the printed circuit board (PCB) on which the IC is mounted, which damages the IC and / or the PCB. Figure 3A is an inverted end view, and Figure 3B is an uninverted end view of the exemplary IC 300A, which has a lead pin configuration that reduces the overall electric field, substantially reduces its intensity, or substantially eliminates the electric field outside the IC adjacent to the low-voltage lead pin. More specifically, the configuration of IC300A increases the distance D2 between the low-voltage lead pins and the high-voltage die mounting pads so that the electric field outside the package is substantially reduced or eliminated so as not to adversely affect it. IC300A includes a low-voltage side 302, a high-voltage side 304, and a package 306 made of a molding compound (e.g., an epoxy compound) that electrically insulates the low-voltage side 302 from the high-voltage side 304.Package 306 includes a longitudinal centerline CL2 extending from the low-voltage side 302 to the high-voltage side 304. The longitudinal centerline CL2 is centrally located within package 306 in a direction perpendicular to the longitudinal centerline CL2, as indicated by the double-headed arrow A between the first (non-mounting) surface 308 and the second (mounting) surface 310 of package 306. The mounting surface 310 of package 306 is the side of package 306 that faces the PCB when IC 300A is mounted on the PCB. The portion of package 306 between the longitudinal centerline CL2 and the non-mounting surface 308 is the non-mounting portion NMP of package 306. Similarly, the portion of package 306 between the longitudinal centerline CL2 and the mounting surface 310 is the mounting portion MP of package 306.
[0015] The low-voltage side 302 includes a low-voltage die 312 mounted on a low-voltage die mounting pad (DAP) 314. Specifically, the low-voltage die 312 is mounted on the side (first side) of the low-voltage die mounting pad 314 that faces toward the longitudinal centerline CL2 and toward the mounting portion MP of the package 306 (away from the non-mounting portion NMP). The opposite side (second side) of the low-voltage die mounting pad 314 faces away from the longitudinal centerline CL2 and away from the mounting portion MP of the package 306 (away from the non-mounting portion NMP). Similarly, the high-voltage side 304 includes a high-voltage die 316 mounted on a high-voltage die mounting pad (DAP) 318. Specifically, the high-voltage die 316 is mounted on the side (first side) of the high-voltage die mounting pad 318 that faces toward the longitudinal centerline CL2 and toward the mounting portion MP of the package 306 (away from the non-mounting portion NMP). The opposite side (second side) of the high-voltage die mounting pad 318 faces away from the longitudinal centerline CL2 and away from the mounting portion MP of the package 306 (towards the non-mounting portion NMP). Both the low-voltage die 312 and the high-voltage die 316 have internally located electronic devices. The low-voltage die 312 and the low-voltage DAP 314 are electrically isolated from the high-voltage die 316 and the high-voltage DAP 318 by the package 306. The low-voltage DAP 314 and the high-voltage DAP 318 are embedded in the non-mounting portion NMP of the package 306 and displaced by a first offset OS1 from the longitudinal centerline CL2 so that both the low-voltage die 312 and the high-voltage die 316 are centered along the longitudinal centerline CL2 of the package 306. In other words, both the low-voltage die 312 and the high-voltage die 316 are positioned midway between the non-mounting surface 308 and the mounting surface 310 of the package 306. This configuration is in contrast to the configuration of IC200A shown in Figure 2A, in which the low and high voltage DAPs 214 and 218 are embedded in the mounting section MP of package 206.In this example IC300A, IC300A includes a power enhancement device, which comprises a first layer of magnetic material 320 attached to a high-voltage DAP 318, a printed circuit board 322 positioned on the first layer of magnetic material 320, and a second layer of magnetic material 324 (e.g., a transformer). The power enhancement device generates a magnetic field to enhance (e.g., increase) the power supplied to the high-voltage side 304. The power enhancement device may be attached to a first side of an extension portion 326 of the high-voltage DAP 318, where the extension portion 326 is embedded in the unattached portion NMP of the package 306, with the first side facing the longitudinal centerline CL2. The extension portion 326 is embedded in the unattached portion NMP of the package 306 such that the extended portion is displaced by a second offset OS2 from the longitudinal centerline CL2, and the PCB 322 is centrally positioned along the longitudinal centerline CL2 of the package 306. IC300A further includes a low-voltage lead pin 328 on the low-voltage side 302 and a high-voltage lead pin 330 on the high-voltage side 304. At least one first end 332 of a low-voltage lead pin 328 is attached to and extends from a low-voltage DAP 314, and at least one first end 334 of a high-voltage lead pin 330 is attached to and extends from a high-voltage DAP 318. The first ends 332, 334 of both the low-voltage DAP 314 and the high-voltage lead pin 330 are sealed along the centerline CL2 within the package 306. Both the low-voltage lead pin 328 and the high-voltage lead pin 330 exit the package 306 at exit openings 336, 338 defined on each side of the package 306 along the longitudinal centerline CL2 of the package 306. The second end 340 of the low-voltage lead pin 328 and the second end 342 of the high-voltage lead pin 330 extend outward from each side of the package 306 along the longitudinal centerline CL2. The second end 340 of the low-voltage lead pin 328 and the second end 342 of the high-voltage lead pin 330 transition away from the non-mounting portion NMP of the package 306 and therefore away from the high-voltage DAP 318 (e.g., curve, bend, etc.).The mounting surfaces 344 of both the low-voltage lead pins 328 and the high-voltage lead pins 330 extend beyond the second surface 310 of the package 306 by a predetermined distance (e.g., 0.314 to 0.414 microns). As shown in Figure 3B, the integrated circuit 300A has an inverted configuration. When IC300A is flipped for mounting, the low-voltage die 312 and the high-voltage die 316 are inverted relative to the low-voltage DAP 314 and the high-voltage DAP 318. In other words, the low-voltage die and the high-voltage die 316 are mounted on the opposite side of the low-voltage DAP 314 and the high-voltage DAP 318, respectively, compared to IC200A in the embodiment shown in Figure 2A. Therefore, the low-voltage die 312 and the high-voltage die 316 are mounted upside down when IC300A is mounted on the PCB. However, inverted mounting does not affect the operation or performance of IC300A, low-voltage die 312, high-voltage die 316, or the electronic devices inside dies 312 and 316. The inverted configuration facilitates the reduction or removal of the electric field outside package 306, as described herein.
[0016] Figure 3C is an end-view infrared image of an exemplary IC300B, similar to the exemplary IC300A shown in Figure 3A. The infrared image in Figure 3A shows the presence or absence of an electric field dispersed inside the package 306. Specifically, the shaded area enclosed by the dotted circle 346 inside the package 306 indicates the presence of an electric field. As described above, the electric field 346 is generated by the potential difference between the low-voltage side 302 and the high-voltage side 304. The electric field 346A inside the package 306 is isolated by the package 306 and therefore its effect on the IC or other nearby electronic components can be ignored. However, the electric field 232B that was outside the package 206 shown in Figures 2A and 2B no longer exists in the exemplary IC300B shown in Figure 3C. In other words, the electric field no longer exists outside the package 306 adjacent to the low-voltage lead pin 328. The electric field 346B outside the package no longer exists due to the configuration of the low-voltage lead pin 328 relative to the high-voltage DAP 318. More specifically, as described above, the low-voltage lead pin 328 transitions away from the high-voltage DAP 318 and toward the first surface 308 of the package 306 (e.g., curves, bends, etc.). Therefore, the high-voltage DAP 318 is on the opposite side of the longitudinal centerline CL2 from the low-voltage lead pin 328, which is in contrast to the example ICs 200A and 200B shown in Figures 2A and 2B. Consequently, the distance D2 between the high-voltage DAP 318 and the low-voltage lead pin 328 is greater than the distance Dl between the high-voltage DAP 218 and the low-voltage lead pin 222 described above. As a result, the electric field strength is reduced, so as not to adversely affect the integrated circuits 300A and 300B, or the electric field is eliminated.
[0017] Figure 4 shows an exemplary process 400 for manufacturing the electronic device shown in Figure 3A. In 402, the low-voltage die and the high-voltage die (e.g., the low-voltage die 312 and the high-voltage die 316) are mounted to the low-voltage and high-voltage die mounting pads, respectively. In 404, the first end of at least one low-voltage lead pin (e.g., low-voltage lead pin 328) and the first end of at least one high-voltage lead pin (e.g., high-voltage lead pin 330) are mounted to the low-voltage and high-voltage DAPs, respectively. In 406, the low-voltage die and the high-voltage die are placed in a cavity defined in the body of the package of the electronic device (e.g., IC300A). In 408, the low-voltage die, the high-voltage die, the low-voltage die mounting pad, and the high-voltage die mounting pad are sealed within the package of the integrated circuit. The sealing involves injecting sealing material into the cavity of the body to surround the low and high voltage die mounting pads, the low and high voltage dies, and the first end of at least one low voltage lead pin and the first end of at least one high voltage lead pin. The sealing further includes curing the sealing material. In 410, the second end of at least one low voltage lead pin and the second end of at least one high voltage lead pin, which are located outside the package, are operated to curve (e.g., bend, curve, angle, etc.) away from the longitudinal centerline of the package and in the opposite direction to the first offset.
[0018] In this description, the terms “overlay,” “overlaying,” “underlay,” and “below” (and their derivatives) refer to the relative positions of two adjacent surfaces in a selected orientation. Similarly, the terms “top” and “bottom” refer to opposing surfaces in a selected orientation. Likewise, the terms “upper side” and “lower side” refer to relative positions in a selected orientation. Even if the examples used throughout this description indicate only one selected orientation, that orientation is arbitrary, and other orientations are possible within the scope of this description (e.g., upside down, rotated 90 degrees, etc.). Furthermore, in this description, the term “based on” means at least partially based.
[0019] Within the scope of the claims of the present invention, modifications may be made to the exemplary embodiments described, and other embodiments are possible.
Claims
1. It is an electronic device, A package having a longitudinal centerline, wherein the package has a mounting portion on one side of the longitudinal centerline and a non-mounting portion on the opposite side of the longitudinal centerline, A low-voltage die mounting pad embedded in the non-mounted portion of the package, the low-voltage die mounting pad having a first side facing toward the longitudinal centerline and a second side facing away from the longitudinal centerline, The low-voltage die attached to the first side of the low-voltage die mounting pad, Multiple inverted low-voltage lead pins extending from the package toward the mounting portion and toward the non-mounting portion of the package, A high-voltage die mounting pad embedded in the non-mounted portion of the package, the high-voltage die mounting pad having a first side facing toward the longitudinal centerline and a second side facing away from the longitudinal centerline, A high-voltage die attached to the first side of the high-voltage die mounting pad, and Multiple inverted high-voltage lead pins extending from the package toward the mounting portion and toward the non-mounting portion of the package, Electronic devices, including those mentioned above.
2. The electronic device according to claim 1, An electronic device in which the low-voltage die and the high-voltage die are positioned centrally on the longitudinal centerline of the package.
3. The electronic device according to claim 2, An electronic device in which the plurality of inverted low-voltage lead pins and the plurality of inverted high-voltage lead pins exit the package at an exit opening defined in the package along the longitudinal centerline of the package.
4. The electronic device according to claim 1, An electronic device in which at least one of the plurality of low-voltage lead pins is attached to the low-voltage die mounting pad, and at least one of the plurality of high-voltage lead pins is attached to the high-voltage die mounting pad.
5. The electronic device according to claim 1, An electronic device in which the mounting surfaces of the plurality of low-voltage lead pins and the mounting surfaces of the plurality of high-voltage lead pins extend beyond the mounting surface of the package by a predetermined distance.
6. The electronic device according to claim 1, An electronic device further comprising a power enhancement device attached to the high-voltage die mounting pad, wherein the power enhancement device increases the power supplied to the high-voltage die mounting pad.
7. The electronic device according to claim 6, An electronic device in which the power enhancement device is made of a magnetic material that generates a magnetic field to increase the power supplied to the high-voltage die mounting pad.
8. It is an integrated circuit, A package having a longitudinal center line extending from the low-voltage side to the high-voltage side of the package, and including a mounting portion on one side of the longitudinal center line and a non-mounting portion on the opposite side of the longitudinal center line, A low-voltage die mounting pad embedded in the package, comprising a first side facing toward the longitudinal centerline toward the mounting portion of the package, and the package The low-voltage die mounting pad having a second side facing away from the longitudinal centerline toward the non-mounting portion of the package, the low-voltage die mounting pad being displaced with a first offset from the longitudinal centerline toward the non-mounting portion of the package, The low-voltage die attached to the first side of the low-voltage die mounting pad, Multiple inverted low-voltage lead pins extending from the package in a direction away from the longitudinal centerline and in the direction opposite to the first offset, A high-voltage die mounting pad embedded in the package, having a first side facing toward the longitudinal centerline toward the mounting portion of the package, and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package, wherein the high-voltage die mounting pad is displaced by a first offset from the longitudinal centerline toward the non-mounting portion of the package. A high-voltage die attached to the first side of the high-voltage die mounting pad, and Multiple inverted high-voltage lead pins extending from the package, away from the longitudinal centerline and in a direction opposite to the direction of the first offset, An integrated circuit, including
9. The integrated circuit according to claim 8, An integrated circuit in which the low-voltage die and the high-voltage die are positioned centrally on the longitudinal centerline of the package.
10. The integrated circuit according to claim 9, An integrated circuit in which the plurality of inverted low-voltage lead pins and the plurality of inverted high-voltage lead pins exit the package at an exit opening defined in the package along the longitudinal centerline of the package.
11. The integrated circuit according to claim 8, An integrated circuit in which at least one of the plurality of low-voltage lead pins is attached to the low-voltage die mounting pad, and at least one of the plurality of high-voltage lead pins is attached to the high-voltage die mounting pad.
12. The integrated circuit according to claim 8, An integrated circuit in which the mounting surfaces of the plurality of low-voltage lead pins and the mounting surfaces of the plurality of high-voltage lead pins extend beyond the mounting surface of the package by a predetermined distance.
13. The integrated circuit according to claim 8, An integrated circuit further comprising a power enhancement device for increasing the power supplied to the high-voltage side, wherein the high-voltage die mounting pad includes an extension embedded in the unmounted portion of the package, which is displaced with a second offset from the longitudinal centerline of the package toward the unmounted portion of the package, and the power enhancement device is mounted to the extension of the high-voltage die mounting pad.
14. The integrated circuit according to claim 13, The power enhancement device has a first magnetic layer attached to one side of the extended portion of the high-voltage die mounting pad facing the longitudinal centerline, A printed circuit board attached to the first magnetic layer, and A second magnetic layer attached to the printed circuit board, An integrated circuit, including
15. The integrated circuit according to claim 14, An integrated circuit in which the printed circuit board is positioned in the center along the longitudinal centerline of the package.
16. It is a method, Mounting low-voltage dies to low-voltage die mounting pads, and high-voltage dies to high-voltage die mounting pads. Attaching the first end of at least one low-voltage lead pin to the low-voltage die mounting pad, and attaching the first end of at least one high-voltage lead pin to the high-voltage die mounting pad, The low-voltage die and the high-voltage die are placed in a cavity defined in the package body of the integrated circuit. The package of the integrated circuit comprises sealing the low-voltage die, the high-voltage die, the low-voltage die mounting pad, and the high-voltage die mounting pad, wherein the low-voltage die mounting pad and the high-voltage die mounting pad are displaced from the longitudinal centerline of the package of the integrated circuit by a first offset in the direction toward the non-mounted portion of the package, and The second end of the at least one low-voltage lead pin and the second end of the at least one high-voltage lead pin, which are located outside the package, are curved away from the longitudinal centerline of the package and in a direction opposite to the direction of the first offset. A method that includes this.
17. The method according to claim 16, Sealing is the injection of sealing material into the cavity of the body, wherein the sealing material surrounds the low and high voltage die mounting pads, the low and high voltage dies, the first end of at least one low voltage lead pin, and the first end of at least one high voltage lead pin, and The sealing material is cured. Methods that include...
18. The method according to claim 16, A method in which the low-voltage die and the high-voltage die are sealed in the center along the longitudinal centerline of the package.
19. The method according to claim 16, A method wherein the first end of at least one low-voltage lead pin and the first end of at least one high-voltage lead pin are sealed along the longitudinal centerline of the package.
20. The method according to claim 16, The method further includes removing the package from the mold before bending the second end of the at least one low-voltage lead pin and the second end of the at least one high-voltage lead pin.