Semiconductor device and method for manufacturing the same

Abstract

To improve the reliability of semiconductor devices having back-side electrodes. [Solution] The semiconductor device CP comprises a semiconductor substrate SB, a semiconductor element formed on the main surface of the semiconductor substrate SB, and a back electrode BE formed on the back surface RS of the semiconductor substrate SB. The back electrode BE includes a silver film or a copper film. The back surface RS of the semiconductor substrate SB has a recessed portion KB1. The back surface ES of the back electrode BE has a recessed portion KB2.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and is suitably applicable, for example, to a semiconductor device having a back surface electrode and a method for manufacturing the same. [Background technology]

[0002] When manufacturing a semiconductor package using a semiconductor chip with back electrodes, the semiconductor chip is mounted on a die pad via a conductive bonding material. This electrically connects the back electrodes of the semiconductor chip to the die pad via the conductive bonding material.

[0003] Patent Document 1 (Japanese Patent Publication No. 2023-173191) discloses a technique for mounting a semiconductor chip having back electrodes onto a die pad via solder. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-173191 [Overview of the project] [Problems that the invention aims to solve]

[0005] It is desirable to improve the reliability of semiconductor devices using semiconductor chips with back-side electrodes.

[0006] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0007] According to one embodiment, the semiconductor device comprises a semiconductor substrate and a back electrode formed on the back surface of the semiconductor substrate. The back electrode includes a silver film or a copper film. The back surface of the semiconductor substrate has a first recess, and the back surface of the back electrode has a second recess. [Effects of the Invention]

[0008] According to one embodiment, the reliability of semiconductor devices can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a top view of the semiconductor device according to Embodiment 1. [Figure 2] This is a rear view of the semiconductor device according to Embodiment 1. [Figure 3] This is a cross-sectional view of the main part of the semiconductor device according to Embodiment 1. [Figure 4] This is a partially enlarged plan view, showing an enlarged portion of Figure 2. [Figure 5] This is a plan view of the semiconductor device according to Embodiment 1. [Figure 6] This is a cross-sectional view of a key part during the manufacturing process of the semiconductor device according to Embodiment 1. [Figure 7] Figure 6 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 8] Figure 7 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 9] Figure 8 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 10] Figure 9 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 11] Figure 10 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 12] Figure 11 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 13] Figure 12 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 14] Figure 13 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 15] Figure 14 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 16] Figure 15 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 17]It is a cross-sectional view of a main part during the manufacturing process of a semiconductor device following FIG. 16. [Figure 18] It is an explanatory diagram of a laser annealing process. [Figure 19] It is a cross-sectional view of the semiconductor package of Embodiment 1. [Figure 20] It is a partial enlarged cross-sectional view showing a part of FIG. 19 enlarged. [Figure 21] It is a graph showing the correlation between the energy density of the laser light irradiated on the semiconductor substrate in the laser annealing process and the density of the recessed portions formed in the laser annealing process.

Embodiments for Carrying Out the Invention

[0010] In the following embodiments, when necessary for convenience, they will be described by being divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to a partial or entire modification example, details, supplementary explanation, etc. of the other. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and unless it is clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number. Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified and unless it is clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise specified and unless it is clearly not so in principle, it includes those substantially approximate or similar to the shape, etc. This also applies to the above numerical values and ranges.

[0011] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0012] Furthermore, in the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to improve readability. Conversely, hatching may be added to plan views to improve readability.

[0013] Furthermore, a planar view corresponds to viewing the semiconductor substrate SB from a plane approximately parallel to the main surface MS or the back surface RS. Also, the bottom surface and the lower surface have the same meaning.

[0014] (Embodiment 1) <About the structure of semiconductor device CP> The semiconductor device CP of Embodiment 1 will be described with reference to Figures 1 to 5. Figure 3 is a cross-sectional view along line AA in Figure 1. Figure 4 is a partially enlarged plan view showing an enlarged portion of Figure 2 (region RG1). Figure 5 is a plan view showing a portion of Figure 2 (region RG1), where the back surface electrode BE is omitted and the back surface RS of the semiconductor substrate SB is shown.

[0015] As shown in Figures 1 to 5, the semiconductor device CP of Embodiment 1 includes a semiconductor substrate SB, an IGBT (Insulated Gate Bipolar Transistor) 1, an insulating film IL, a protective film PF, an emitter electrode EE, a gate electrode GE, and a back surface electrode BE.

[0016] The semiconductor substrate SB is made of, for example, single-crystal silicon. The semiconductor substrate SB has a main surface MS and a back surface RS opposite to the main surface MS. The thickness direction of the semiconductor substrate SB corresponds to the direction from one main surface MS or back surface RS to the other, and is approximately perpendicular to either the main surface MS or the back surface RS of the semiconductor substrate SB.

[0017] The semiconductor device CP of Embodiment 1 has an IGBT1 as a semiconductor element. The semiconductor device CP having the IGBT1 is used, for example, as a power switching element.

[0018] As shown in Figure 3, IGBT1 is a trench gate type IGBT. IGBT1 has a trench gate electrode TG, a gate insulating film GF, an n-type emitter region ER, a p-type semiconductor region PR, an n-type drift region DF, an n-type field stop region FS, and a p-type collector region CR.

[0019] The n-type emitter region ER, the p-type semiconductor region PR, the n-type drift region DF, the n-type field stop region FS, and the p-type collector region CR are formed within the semiconductor substrate SB.

[0020] The p-type collector region (p-type semiconductor region) CR is formed in layers within the semiconductor substrate SB, extending to a predetermined depth from the back surface RS of the semiconductor substrate SB. Therefore, the back surface RS of the semiconductor substrate SB is composed of the p-type collector region CR.

[0021] The back electrode BE is formed on the back surface RS of the semiconductor substrate SB. Therefore, the p-type collector region CR and the back electrode BE are in contact with each other. Since the back electrode BE is electrically connected to the p-type collector region CR, it functions as a collector electrode.

[0022] The back electrode BE includes a silver film. For example, the back electrode BE includes an aluminum film BE1 on the back surface RS of the semiconductor substrate SB, a titanium film BE2 on the aluminum film BE1, a nickel film BE3 on the titanium film BE2, and a silver film BE4 on the nickel film BE3. The back electrode BE is formed over the entire back surface RS of the semiconductor substrate SB.

[0023] The back surface RS of the semiconductor substrate SB has a recess (concave, groove) KB1 (see Figures 3 and 5). The recess KB1 is locally recessed on the nearly flat back surface RS of the semiconductor substrate SB. The recess KB1 is groove-like (wrinkled). The back electrode BE is in contact with the semiconductor substrate SB, and a portion of the back electrode BE is formed within the recess KB1.

[0024] The back surface ES of the back electrode BE has a recess (concave, groove) KB2 (see Figures 3 and 4). The recess KB2 is locally recessed on the nearly flat back surface ES of the back electrode BE. The recess KB2 is groove-like (wrinkled). In a plan view, the recess KB2 is formed in a position that overlaps with the recess KB1. In other words, in a plan view, the recess KB2 is formed in a position that is approximately in agreement with the recess KB1.

[0025] The back surface ES of the back electrode BE is the surface opposite to the surface in contact with the semiconductor substrate SB. Therefore, the back surface ES of the back electrode BE constitutes the back surface of the semiconductor device CP. Consequently, the back surface of the semiconductor device CP has a recessed portion KB2. The back surface ES of the back electrode BE is composed of the silver film BE4 contained within the back electrode BE.

[0026] The n-type field stop region (n-type semiconductor region) FS is formed in layers on the p-type collector region CR. The p-type collector region CR and the n-type field stop region FS are in contact with each other. A PN junction is formed between the p-type collector region CR and the n-type field stop region FS.

[0027] The n-type drift region (n-type semiconductor region) DF is formed in layers on the n-type field stop region FS. The n-type drift region DF and the n-type field stop region FS are in contact with each other. The n-type field stop region FS is interposed between the n-type drift region DF and the p-type collector region CR. The n-type impurity concentration in the n-type field stop region FS is higher than the n-type impurity concentration in the n-type drift region DF.

[0028] The n-type field stop region (FS) has the function of preventing the punch-through phenomenon from occurring when the IGBT is turned off. The punch-through phenomenon is a phenomenon in which the depletion layer growing from the p-type semiconductor region (PR) into the n-type drift region (DF) comes into contact with the p-type collector region (CR). In addition, the n-type field stop region (FS) has the function of limiting the amount of holes injected from the p-type collector region (CR) into the n-type drift region (DF).

[0029] The p-type semiconductor region (channel formation region) PR is formed on the n-type drift region. The p-type semiconductor region PR and the n-type drift region DF are in contact with each other.

[0030] The n-type emitter region (n-type semiconductor region) ER is formed from the main surface MS of the semiconductor substrate SB to a predetermined depth. The n-type emitter region ER and the p-type semiconductor region PR are in contact with each other.

[0031] The n-type emitter region ER is not in contact with the n-type drift region DF, and a p-type semiconductor region PR is interposed between the n-type emitter region ER and the n-type drift region DF. The n-type impurity concentration in the n-type emitter region ER is higher than the n-type impurity concentration in the n-type drift region DF.

[0032] The trench gate electrode TG is formed in a groove TR formed in the semiconductor substrate SB, via a gate insulating film GF. The groove TR extends from the main surface MS of the semiconductor substrate SB toward the back surface RS of the semiconductor substrate SB. The groove TR penetrates the n-type emitter region ER and the p-type semiconductor region PR, reaching the n-type drift region DF. The bottom surface of the groove TR is deeper than the bottom surface of the p-type semiconductor region PR, and shallower than the bottom surface of the n-type drift region DF. The gate insulating film GF is formed on the bottom surface and sides of the groove TR. The gate insulating film GF is made of, for example, a silicon oxide film. The trench gate electrode TG is made of, for example, a polycrystalline silicon film containing n-type impurities.

[0033] The n-type emitter region ER and the p-type semiconductor region PR are in contact with the gate insulating film GF formed on the side surface of the groove TR. The n-type emitter region ER is adjacent to the trench gate electrode TG via the gate insulating film GF. A portion of the p-type semiconductor region PR is located below the n-type emitter region ER and is also adjacent to the trench gate electrode TG via the gate insulating film GF. The bottom surface of the n-type emitter region ER is the boundary between the n-type emitter region ER and the p-type semiconductor region PR. Therefore, a PN junction is formed on the bottom surface of the n-type emitter region ER. Below the bottom surface of the p-type semiconductor region PR, there is an n-type drift region DF. Therefore, a PN junction is formed on the bottom surface of the p-type semiconductor region PR.

[0034] An insulating film (interlayer insulating film) IL is formed on the main surface MS of the semiconductor substrate SB, covering the n-type emitter region ER and the trench gate electrode TG. The insulating film IL is made of, for example, a silicon oxide film. The emitter electrode EE and gate electrode GE are formed on the insulating film IL.

[0035] A contact hole CT1 is formed within the insulating film IL. The contact hole CT1 penetrates the insulating film IL and the n-type emitter region ER to reach the p-type semiconductor region PR. A portion of the emitter electrode EE is embedded within the contact hole CT1. The emitter electrode EE is in contact with the n-type emitter region ER, which is exposed from the side of the contact hole CT1, and is electrically connected to that n-type emitter region ER. Furthermore, the emitter electrode EE is in contact with the p-type semiconductor region PR, which is exposed at the bottom of the contact hole CT1, and is electrically connected to that p-type semiconductor region PR.

[0036] The semiconductor device CP has an insulating protective film (passivation film) PF as its uppermost layer. The protective film PF is made of an insulating film, preferably a resin film such as polyimide resin. The protective film PF is formed on the insulating film IL so as to cover a portion of the emitter electrode EE and a portion of the gate electrode GE.

[0037] An opening for a pad (bonding pad) is formed within the protective film PF. The opening OPE of the protective film PF is formed so as to be enclosed within the emitter electrode EE in a plan view. A portion of the emitter electrode EE is exposed from the opening OPE of the protective film PF. The emitter pad (bonding pad for the emitter) PDE is formed by the emitter electrode EE exposed from the opening OPE of the protective film PF. In addition, an opening OPG of the protective film PF is formed so as to be enclosed within the gate electrode GE in a plan view. A portion of the gate electrode GE is exposed from the opening OPG of the protective film PF. The gate pad (bonding pad for the gate) PDG is formed by the gate electrode GE exposed from the opening OPG of the protective film PF.

[0038] An IGBT1 has multiple unit transistors (IGBT cells), which are connected in parallel to each other. The channel of each of the unit transistors is formed along a groove TR within the p-type semiconductor region PR. The operating current of the IGBT1 flows between the emitter electrode EE and the back electrode BE through the n-type emitter region ER of the unit transistors, the channels of the unit transistors, the n-type drift region DF, the n-type field stop region FS, and the p-type collector region CR. Therefore, the operating current of the IGBT1 flows along the thickness direction of the semiconductor substrate SB.

[0039] The trench gate electrodes TG of multiple unit transistors are electrically connected to each other through a gate connection portion (not shown) formed integrally with the trench gate electrode TG and gate wiring (not shown) formed integrally with the gate electrode GE, and are also electrically connected to the gate electrode GE.

[0040] The n-type emitter regions ER of multiple unit transistors are electrically connected to the emitter electrode EE, and are also electrically connected to each other through the emitter electrode EE.

[0041] The collector regions of multiple unit transistors are electrically connected to each other through the collector region CR and the back electrode BE.

[0042] An IGBT1 is a power transistor (power system transistor) used as a power switching element. Instead of an IGBT, a trench-gate type power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) can be used as the power transistor included in the semiconductor device CP. In that case, the n-type emitter region ER becomes the source region, the emitter electrode EE becomes the source electrode, the n-type drift region DF and n-type field stop region FS become the drain region, the collector region CR is not formed, and the back electrode BE becomes the drain electrode.

[0043] <Regarding the manufacturing process of semiconductor device CPs> The method for manufacturing the semiconductor device of Embodiment 1 will be described with reference to Figures 6 to 17.

[0044] As shown in Figure 6, a semiconductor substrate SB is prepared. At this stage, the semiconductor substrate SB is a semiconductor wafer that is substantially circular in shape when viewed from above. The semiconductor substrate SB has a main surface MS and a back surface RS opposite to the main surface MS. At this stage, the back surface RS of the semiconductor substrate SB does not have the recessed portion KB1 and is a flat surface. The semiconductor substrate SB is made of, for example, single-crystal silicon. An n-type semiconductor substrate into which n-type impurities have been introduced can be used as the semiconductor substrate SB. An epitaxial wafer having a semiconductor substrate and an epitaxial semiconductor layer formed on the semiconductor substrate can also be used as the semiconductor substrate SB.

[0045] Next, as shown in Figure 7, grooves TR are formed in the semiconductor substrate SB using photolithography and etching techniques. Then, gate insulating film GF is formed on the sides and bottom of the grooves TR using a method such as thermal oxidation. Subsequently, a trench gate electrode TG is formed in the grooves TR via the gate insulating film GF. For example, a polysilicon film is formed on the main surface MS of the semiconductor substrate SB so as to fill the grooves TR. Then, by removing the polysilicon film outside the grooves TR by etching or the like, a trench gate electrode TG made of the polysilicon film inside the grooves TR can be formed.

[0046] Next, as shown in Figure 8, a p-type semiconductor region PR and an n-type emitter region ER are formed in the semiconductor substrate SB using ion implantation. The p-type semiconductor region PR can be formed by implanting p-type impurities into the semiconductor substrate SB from the main surface MS. The n-type emitter region ER can be formed by implanting n-type impurities into the semiconductor substrate SB from the main surface MS.

[0047] The steps in Figure 7 and Figure 8 are processes for forming semiconductor elements (in this case, IGBTs) on the main surface MS of the semiconductor substrate SB.

[0048] Next, as shown in Figure 9, an insulating film IL is formed on the main surface MS of the semiconductor substrate SB so as to cover the trench gate electrode TG. The insulating film IL can be formed using methods such as CVD (Chemical Vapor Deposition).

[0049] Next, as shown in Figure 10, contact holes CT1 are formed in the insulating film IL using photolithography and etching techniques. The contact holes CT1 are formed so as to penetrate the insulating film IL and the n-type emitter region ER to reach the p-type semiconductor region PR.

[0050] Next, a metal film is formed on the insulating film IL to fill the contact hole CT1, and then the metal film is patterned using photolithography and etching techniques. This forms the emitter electrode EE, gate electrode GE (see Figure 1 above), and gate wiring (not shown), as shown in Figure 10.

[0051] Next, as shown in Figure 11, a protective film PF made of polyimide resin or the like is formed on the insulating film IL so as to cover the emitter electrode EE, the gate electrode GE, and the gate wiring. Then, an opening OPE and an opening OPG (see Figure 1 above) are formed within the protective film PF. The emitter electrode EE exposed through the opening OPE of the protective film PF forms the emitter pad PDE. The gate electrode GE exposed through the opening OPG of the protective film PF forms the gate pad PDG (see Figure 1 above).

[0052] Next, as shown in Figure 12, the thickness of the semiconductor substrate SB is reduced by grinding the back surface RS of the semiconductor substrate SB (back surface grinding process). For example, the back surface grinding process of the semiconductor substrate SB can be performed after applying a protective tape (not shown) to cover the protective film PF on the main surface MS side of the semiconductor substrate SB. In this case, by making the amount of grinding in the central part of the back surface RS of the semiconductor substrate SB greater than the amount of grinding in the peripheral part of the back surface RS of the semiconductor substrate SB, the thickness of the central part of the semiconductor substrate SB can be made thinner than the thickness of the peripheral part of the semiconductor substrate SB. The thickness T2 of the semiconductor substrate SB after the back surface grinding process (see Figure 12) is smaller than the thickness T1 of the semiconductor substrate SB before the back surface grinding process (see Figure 11).

[0053] Next, wet etching is performed on the back surface RS of the semiconductor substrate SB (back surface etching process). This further reduces the thickness of the semiconductor substrate SB. At this stage, the thickness T2 of the semiconductor substrate SB is, for example, 15 micrometers or more and 350 micrometers or less. The back surface grinding process may cause strain in the area near the back surface RS of the semiconductor substrate SB. By performing the back surface etching process after the back surface grinding process, the occurrence of strain within the semiconductor substrate SB can be suppressed.

[0054] Next, as shown in Figure 13, an n-type field stop region FS and a p-type collector region CR are formed within the semiconductor substrate SB. The n-type field stop region FS can be formed by ion implantation of n-type impurities. The p-type collector region CR can be formed by ion implantation of p-type impurities. In the ion implantation step for forming the n-type field stop region FS, n-type impurities are implanted into the semiconductor substrate SB from the back surface RS of the semiconductor substrate SB. In the ion implantation step for forming the p-type collector region CR, p-type impurities are implanted into the semiconductor substrate SB from the back surface RS of the semiconductor substrate SB. The p-type collector region CR may be formed after the n-type field stop region FS is formed, or the n-type field stop region FS may be formed after the p-type collector region CR is formed. The semiconductor substrate SB between the n-type field stop region FS and the p-type semiconductor region PR constitutes the n-type drift region DF.

[0055] Next, as shown in Figure 14, an insulating film ZF is formed on the back surface RS of the semiconductor substrate SB. The thermal expansion coefficient (thermal expansion rate) of the insulating film ZF is different from that of the semiconductor substrate SB. It is preferable that the insulating film ZF is a film that can be easily removed later. It is preferable that the insulating film ZF is a silicon oxide film or a silicon nitride film. The insulating film ZF can be formed using methods such as APM (Ammonia-hydrogen Peroxide Mixture) treatment, plasma oxidation, ozone oxidation, CVD method, ALD (Atomic Layer Deposition) method, coating method, spin coating method, sol-gel method, sputtering method, and vapor deposition ion plating method.

[0056] Since the n-type field stop region FS and p-type collector region CR are formed before the insulating film ZF is formed, the ion implantation that forms the n-type field stop region FS and the ion implantation that forms the p-type collector region CR can be prevented from being hindered by the insulating film ZF. As a result, the n-type field stop region FS with the desired impurity concentration distribution and the p-type collector region CR with the desired impurity concentration distribution can be accurately formed.

[0057] Next, the semiconductor substrate SB is subjected to laser annealing (laser annealing process). This activates the p-type and n-type impurities introduced into the semiconductor substrate SB.

[0058] The laser annealing process is performed after the formation of the n-type field stop region (FS) and the p-type collector region (CR). Therefore, the n-type impurities injected into the n-type field stop region (FS) and the p-type impurities injected into the p-type collector region (CR) can be activated by the laser annealing process.

[0059] Figure 15 shows the state after the laser annealing process is completed. As shown in Figure 15, the laser annealing process forms a depression KB1 within the back surface RS of the semiconductor substrate SB. The details of the laser annealing process and the reason why the depression KB1 is formed during the laser annealing process will be explained later.

[0060] Next, as shown in Figure 16, the insulating film ZF is removed. For example, the insulating film ZF can be removed by etching. Wet etching is preferred as the etching method for removing the insulating film ZF. The etching process for removing the insulating film ZF is carried out under conditions where the etching rate of the semiconductor substrate SB is smaller than the etching rate of the insulating film ZF. This allows for the selective removal of the insulating film ZF.

[0061] Next, as shown in Figure 17, a back electrode BE is formed on the back surface RS of the semiconductor substrate SB. The back electrode BE can be formed using methods such as sputtering.

[0062] For example, an aluminum film is formed on the entire back surface RS of a semiconductor substrate SB by sputtering, a titanium film is formed on the aluminum film by sputtering, a nickel film is formed on the titanium film by sputtering, and a silver film is formed on the nickel film by sputtering. This makes it possible to form a back surface electrode BE containing an aluminum film, a titanium film, a nickel film, and a silver film.

[0063] The back electrode BE of the semiconductor substrate SB is formed conformally with respect to the back surface RS of the semiconductor substrate SB. Therefore, reflecting the fact that the back surface RS of the semiconductor substrate SB has a recess KB1, a recess KB2 is formed within the back surface ES of the back electrode BE. In a plan view, the position of the recess KB2 approximately coincides with the position of the recess KB1.

[0064] Next, remove (peel off) the protective tape from the semiconductor substrate SB (protective film PF).

[0065] Next, the semiconductor substrate SB is cut into individual pieces by dicing. During this process, the back electrode BE, insulating film IL, and protective film PF are also cut along with the semiconductor substrate SB. This completes the manufacturing of the semiconductor device CP as a semiconductor chip.

[0066] <About the laser annealing process> The details of the laser annealing process will be explained with reference to Figure 18. Figure 18 shows a cross-sectional view of the semiconductor device CP.

[0067] Laser annealing is performed by irradiating the back surface RS of the semiconductor substrate SB with laser light. Since the laser annealing is performed with an insulating film ZF formed on the back surface RS of the semiconductor substrate SB, the laser light is irradiated to the back surface ZF1 of the insulating film ZF formed on the back surface RS of the semiconductor substrate SB. Therefore, the laser light is irradiated to the back surface RS of the semiconductor substrate SB through the insulating film ZF. Note that the back surface ZF1 of the insulating film ZF is the surface opposite to the surface in contact with the back surface RS of the semiconductor substrate SB.

[0068] In laser annealing, instead of irradiating the entire back surface RS of the semiconductor substrate SB at once, pulsed laser light is locally irradiated onto a portion of the back surface RS of the semiconductor substrate SB.

[0069] For example, as shown as state C1 in Figure 18, pulsed laser light LS is irradiated onto region D1 of the semiconductor substrate SB.

[0070] The incident direction of the pulsed laser beam LS is approximately perpendicular to the back surface RS of the semiconductor substrate SB or the back surface ZF1 of the insulating film ZF. The pulsed laser beam LS is incident on the back surface ZF1 of the insulating film ZF, passes through the insulating film ZF, and then is incident on the back surface RS of the semiconductor substrate SB, traveling a predetermined distance within the semiconductor substrate SB. Within the semiconductor substrate SB, the region D1 irradiated by the pulsed laser beam LS and its vicinity are heated.

[0071] Subsequently, as shown as state C2 in Figure 18, the semiconductor substrate SB is moved, and then, as shown as state C3 in Figure 18, pulsed laser light LS is irradiated onto region D2 of the semiconductor substrate SB. As a result, region D2 and its vicinity are heated within the semiconductor substrate SB. In a plan view, region D2 is located next to region D1. In a plan view, region D2 may partially overlap with region D1. In that case, in a plan view, the area of ​​region D2 that overlaps with region D1 is, for example, about 50 percent or more and 90 percent or less of the total area of ​​region D2.

[0072] Subsequently, as shown as state C4 in Figure 18, the semiconductor substrate SB is moved, and then, as shown as state C5 in Figure 18, pulsed laser light LS is irradiated onto region D3 of the semiconductor substrate SB. As a result, region D3 and its vicinity are heated within the semiconductor substrate SB. In a plan view, region D3 is located next to region D2. In a plan view, region D3 may partially overlap with region D2. In that case, in a plan view, the area of ​​region D3 that overlaps with region D2 is, for example, about 50 percent or more and 90 percent or less of the total area of ​​region D3.

[0073] The movement of the semiconductor substrate SB is performed to shift (move) the irradiation position of the pulsed laser beam LS onto the semiconductor substrate SB. Therefore, in the laser annealing process, after locally irradiating a part of the back surface RS of the semiconductor substrate SB with the pulsed laser beam LS, the irradiation position of the laser beam is shifted, and the pulsed laser beam is locally irradiated onto another part of the back surface RS of the semiconductor substrate SB, and this operation is repeated. By repeatedly irradiating with pulsed laser beam and shifting the irradiation position, the entire back surface RS of the semiconductor substrate SB is subjected to laser annealing. As described above, when the irradiation position of the pulsed laser beam LS onto the semiconductor substrate SB is shifted by moving the semiconductor substrate SB, the configuration of the laser annealing apparatus can be simplified.

[0074] The reason why a recess KB1 is formed within the back surface RS of the semiconductor substrate SB by laser annealing is explained below.

[0075] Laser annealing is performed with an insulating film ZF formed on the back surface RS of the semiconductor substrate SB. The insulating film ZF is made of a material that allows pulsed laser light LS to pass through the film and reach the semiconductor substrate SB. If a metal film is used instead of the insulating film ZF, the pulsed laser light LS is reflected by the metal film, preventing it from passing through and making it difficult to reach the semiconductor substrate SB.

[0076] The thermal expansion coefficient of the insulating film ZF differs from that of the semiconductor substrate SB. Furthermore, since the insulating film ZF is removed after the laser annealing process, it is preferable that the insulating film ZF is easily removable by etching or other means. The insulating film ZF is preferably a silicon oxide film or a silicon nitride film. The thermal expansion coefficient of a silicon oxide film is smaller than that of the silicon substrate (semiconductor substrate SB). The thermal expansion coefficient of a silicon nitride film is also smaller than that of the silicon substrate (semiconductor substrate SB). Therefore, the case where an insulating film (here, a silicon oxide film or silicon nitride film) having a thermal expansion coefficient smaller than that of the semiconductor substrate SB is used as the insulating film ZF will be explained.

[0077] In state C1 shown in Figure 18, region D1 within the semiconductor substrate SB is heated and melted by pulsed laser light LS. After irradiation of region D1 with pulsed laser light LS ends, the temperature of region D1 within the semiconductor substrate SB decreases, and region D1 within the semiconductor substrate SB recrystallizes. When region D1 within the semiconductor substrate SB recrystallizes (during cooling), region D1 within the semiconductor substrate SB is distorted due to the difference between the thermal expansion of the insulating film ZF and the thermal expansion of the semiconductor substrate SB, and a depression KB1 caused by the distortion may be formed within region D1 within the semiconductor substrate SB.

[0078] Here, the thermal expansion coefficient of the insulating film ZF (silicon oxide film or silicon nitride film) is smaller than that of the semiconductor substrate SB (silicon substrate). In this case, when region D1 within the semiconductor substrate SB recrystallizes, the thermal expansion of the semiconductor substrate SB is greater than that of the insulating film ZF, so a depression KB1 caused by strain is formed within region D1 of the semiconductor substrate SB.

[0079] On the other hand, if the thermal expansion coefficient of the insulating film ZF is greater than that of the semiconductor substrate SB, when region D1 within the semiconductor substrate SB recrystallizes, the amount of thermal expansion of the semiconductor substrate SB is less than the amount of thermal expansion of the insulating film ZF. As a result, a protrusion (convex portion) caused by strain is formed within region D1 of the semiconductor substrate SB. In other words, if the thermal expansion coefficient of the insulating film ZF is greater than that of the semiconductor substrate SB, a protrusion is formed instead of a depression KB1.

[0080] In state C3 of Figure 18, region D2 within the semiconductor substrate SB is heated and melted by pulsed laser light LS. When irradiation of region D2 with pulsed laser light LS ends, the temperature of region D2 within the semiconductor substrate SB decreases, and region D2 within the semiconductor substrate SB recrystallizes. Therefore, when region D2 within the semiconductor substrate SB recrystallizes (during cooling), region D2 within the semiconductor substrate SB is distorted due to the difference between the thermal expansion of the insulating film ZF and the thermal expansion of the semiconductor substrate SB, and a depression KB1 caused by the distortion may be formed within region D2 within the semiconductor substrate SB.

[0081] Similarly, in state C5 of Figure 18, after the irradiation of region D3 with pulsed laser light LS is complete, when region D3 in the semiconductor substrate SB recrystallizes (during cooling), a depression KB1 caused by strain may be formed within region D3 in the semiconductor substrate SB.

[0082] As described above, by repeatedly irradiating the semiconductor substrate SB with pulsed laser light LS and moving the substrate SB (moving the laser light irradiation position), the pulsed laser light LS is irradiated over the entire back surface RS of the semiconductor substrate SB. As a result, a recess KB1 is formed over the entire back surface RS of the semiconductor substrate SB.

[0083] Unlike Embodiment 1, this assumes a case where the entire semiconductor substrate SB is heated at once using a lamp annealing or the like. In this case, the entire semiconductor substrate SB warps due to the difference between the thermal expansion of the insulating film ZF and the thermal expansion of the semiconductor substrate SB, and therefore the recess KB1 is not formed within the back surface RS of the semiconductor substrate SB. Furthermore, it is difficult to melt the entire semiconductor substrate SB at once using a heating device such as a lamp annealing.

[0084] In Embodiment 1, a pulsed laser beam LS is locally irradiated onto a part of the semiconductor substrate SB (e.g., region D1), so that a part of the semiconductor substrate SB (e.g., region D1) can be locally dissolved. As a result, when a part of the semiconductor substrate SB (e.g., region D1) undergoes localized recrystallization, a depression KB1 caused by strain is formed within that part of the semiconductor substrate SB (e.g., region D1).

[0085] Pulsed laser light LS, incident on the semiconductor substrate SB from the back surface RS, attenuates as it travels through the substrate SB and does not reach the main surface MS. The penetration depth of the laser light from the back surface RS into the semiconductor substrate SB is, for example, about 2 micrometers. Therefore, when irradiated with pulsed laser light LS, the region near the back surface RS of the semiconductor substrate SB dissolves and then recrystallizes, while the region near the main surface MS of the semiconductor substrate SB does not dissolve. Alternatively, when irradiated with pulsed laser light LS, the temperature of the region near the main surface MS of the semiconductor substrate SB is lower than the temperature of the region near the back surface RS of the semiconductor substrate SB. Therefore, by performing laser annealing with an insulating film IL formed on the main surface MS of the semiconductor substrate SB and an insulating film ZF formed on the back surface RS of the semiconductor substrate SB, a depression KB1 can be formed within the back surface RS of the semiconductor substrate SB without adversely affecting the area near the main surface MS of the semiconductor substrate SB. For this reason, the depression KB1 is formed within the back surface RS of the semiconductor substrate SB, not on the main surface MS of the semiconductor substrate SB.

[0086] The thickness of the semiconductor substrate SB during the laser annealing process is preferably 15 micrometers or more. This allows for the formation of a recess KB1 within the back surface RS of the semiconductor substrate SB without adversely affecting the semiconductor elements (IGBTs in this case) formed within the semiconductor substrate SB. The thickness of the semiconductor substrate SB during the laser annealing process is approximately the same as the thickness of the semiconductor substrate SB contained in the manufactured semiconductor device CP. For this reason, the thickness of the semiconductor substrate SB contained in the manufactured semiconductor device CP is preferably 15 micrometers or more.

[0087] If the thickness of the insulating film ZF is too small, the strain generated within the semiconductor substrate SB during recrystallization of a portion of the substrate (e.g., region D1) will be small due to the difference between the thermal expansion of the insulating film ZF and the thermal expansion of the semiconductor substrate SB. In this case, the depression KB1 is less likely to form within the back surface RS of the semiconductor substrate SB. On the other hand, if the thickness of the insulating film ZF is too large, the amount of laser light that passes through the insulating film ZF and is incident on the back surface RS of the semiconductor substrate SB will decrease. For this reason, the thickness of the insulating film ZF is preferably 0.5 nanometers or more and 500 nanometers or less.

[0088] Furthermore, it is preferable that the melting point of the insulating film ZF is higher than the melting point of the semiconductor substrate SB. The melting points of silicon oxide and silicon nitride are both higher than the melting point of the silicon substrate. As a result, while the semiconductor substrate SB is locally dissolved by the pulsed laser light LS, the insulating film ZF does not dissolve even when irradiated with the pulsed laser light LS. Since the insulating film ZF does not dissolve even when irradiated with the pulsed laser light LS, evaporation of the insulating film ZF can be prevented. In addition, since the back surface RS of the semiconductor substrate SB is covered with insulating film ZF, even if the semiconductor substrate SB is locally dissolved by the pulsed laser light LS, evaporation of the semiconductor substrate SB can be prevented by the insulating film ZF.

[0089] <About semiconductor packaging (PKG)> Figure 19 is a cross-sectional view showing an example of a semiconductor package (semiconductor device, electronic device) PKG assembled using a semiconductor device CP. Figure 20 is a partially enlarged cross-sectional view showing an enlarged portion of Figure 19 (region RG2).

[0090] As shown in Figures 19 and 20, the semiconductor package PKG comprises a die pad (chip mounting area) DP, a semiconductor device CP placed on the die pad DP via a conductive bonding material BD1, a lead LD, a bonding wire BW, a metal plate MP, and a sealing area MR.

[0091] The semiconductor device CP is mounted on the die pad DP via a conductive bonding material BD1 such that the back surface ES of the back surface electrode BE faces the die pad DP via the bonding material BD1. Therefore, the back surface electrode BE of the semiconductor device CP is electrically connected to the die pad DP via the conductive bonding material BD1. The bonding material BD1 is a die bonding material. In Embodiment 1, the bonding material BD1 contains silver. For example, the bonding material BD1 is made of sintered silver. The bonding material BD1 is in contact with the back surface electrode BE, and a portion of the bonding material BD1 is formed within the recessed portion KB2.

[0092] The gate pad PDG of the semiconductor device CP is electrically connected to the lead LD via bonding wire BW. The die pad DP and lead LD are made of metallic material, such as copper, copper alloy, silver, or silver alloy. A portion of the lead LD is exposed from the sealing portion MR and can function as an external terminal (gate terminal). The back surface of the die pad DP is exposed from the back surface of the sealing portion MR and can function as an external terminal (drain terminal).

[0093] One end of the metal plate MP is electrically connected to the emitter pad PDE of the semiconductor device CP via a conductive bonding material BD2. The other end of the metal plate MP protrudes from the sealing portion MR. The metal plate MP protruding from the sealing portion MR can function as an external terminal (emitter terminal). The other end of the metal plate MP can also be electrically connected to an emitter lead via a conductive bonding material. In that case, the emitter lead functions as the emitter terminal.

[0094] The sealing portion MR is made of a resin material and may contain fillers, etc. A portion of the die pad DP, a portion of the metal plate MP, a portion of the lead LD, the semiconductor device CP, and the bonding wire BW are sealed by the sealing portion MR.

[0095] <About the assembly process of semiconductor packages (PKG)> An example of the assembly process (manufacturing process) of a semiconductor package (PKG) shown in Figures 19 and 20 will be explained below.

[0096] Prepare a lead frame equipped with a die pad DP and a lead LD.

[0097] Next, the semiconductor device CP is placed on the die pad DP of the lead frame via a conductive bonding material BD1 (die bonding process). The semiconductor device CP is placed on the die pad DP via the conductive bonding material BD1 such that the back surface ES of the back electrode BE faces the upper surface of the die pad DP. After that, the bonding material BD1 is cured.

[0098] After the die bonding process, a metal plate connection process and a wire bonding process are performed. In the metal plate connection process, one end of the metal plate MP is electrically connected to the emitter pad PDE of the semiconductor device CP via a conductive bonding material BD2. In the wire bonding process, the gate pad PDG and lead LD of the semiconductor device CP are electrically connected via bonding wire BW. The wire bonding process may be performed after the metal plate connection process, or the metal plate connection process may be performed after the wire bonding process.

[0099] After the metal plate joining process and the wire bonding process, a sealing portion MR is formed.

[0100] Next, the lead LD and die pad DP are separated from the frame of the lead frame. Then, if necessary, processes such as bending the lead LD and plating the exposed parts of the lead LD and die pad DP are performed.

[0101] This allows for the assembly of semiconductor packages (PKG).

[0102] <Regarding the background of the consideration> The inventors of this application are considering using a silver film instead of a gold film as the back electrode for semiconductor chips. Therefore, they are considering forming a metal film containing a silver film when forming the back electrode on the back surface of a semiconductor substrate. Using a silver film instead of a gold film can reduce the manufacturing cost of semiconductor chips.

[0103] Furthermore, heat generated in the semiconductor chip is dissipated to the die pad via the die bonding material. If the die bonding material has high thermal conductivity, the heat generated in the semiconductor chip can be efficiently conducted to the die pad via the die bonding material, thereby suppressing the temperature rise of the semiconductor chip. Silver has a higher thermal conductivity than solder. For this reason, we are considering using silver as the die bonding material.

[0104] However, silver is more susceptible to oxidation than gold. Furthermore, silver is more permeable to oxygen than gold. Therefore, silver is easily affected by heat generated by semiconductor chips or by oxygen in the environment. Consequently, if the adhesion between the die bonding material and the back electrode of the semiconductor chip is poor, the silver film constituting the back electrode of the semiconductor chip, or the silver constituting the die bonding material, may oxidize, potentially causing delamination at the interface between the die bonding material and the back electrode of the semiconductor chip. Alternatively, oxygen permeating the silver film may oxidize a metal film (e.g., a nickel film) in contact with the silver film, potentially causing delamination within the back electrode (e.g., at the interface between the silver film and the nickel film). If delamination occurs at the interface between the die bonding material and the back electrode of the semiconductor chip, or within the back electrode itself, the reliability of the manufactured semiconductor package will decrease. Therefore, when using a silver film instead of a gold film as the back electrode of a semiconductor chip, it is desirable to improve the adhesion between the die bonding material and the back electrode of the semiconductor chip.

[0105] <Main Features and Effects> The semiconductor device CP comprises a semiconductor substrate SB and a back electrode BE formed on the back surface RS of the semiconductor substrate SB. The back electrode BE contains a silver film. The back surface RS of the semiconductor substrate SB has a recess KB1, and the back surface ES of the back electrode BE has a recess KB2 at a position that overlaps with the recess KB1 in a plan view. When manufacturing a semiconductor package PKG using the semiconductor device CP, the semiconductor device CP is placed on a die pad DP via a conductive bonding material BD1.

[0106] To improve the adhesion between the back electrode BE of the semiconductor device CP and the bonding material BD1, it is effective to increase the effective surface area of ​​the back electrode BE of the semiconductor device CP. Having a recessed portion KB2 on the back electrode BE of the semiconductor device CP increases its effective surface area, thereby improving the adhesion between the back electrode BE and the bonding material BD1. In other words, compared to the case where the back electrode BE does not have a recessed portion KB2, the contact area between the back electrode BE and the bonding material BD1 can be increased when the back electrode BE has a recessed portion KB2, thereby improving the adhesion between the back electrode BE and the bonding material BD1. Note that when the back electrode BE does not have a recessed portion KB2, the back surface ES of the back electrode BE is a flat surface.

[0107] This improves the adhesion between the back electrode BE of the semiconductor device CP and the bonding material BD1, thereby suppressing or preventing delamination at the interface between the back electrode BE and the bonding material BD1, or within the back electrode BE itself. This improves the reliability of semiconductor packages manufactured using the semiconductor device CP.

[0108] The back surface RS of the semiconductor substrate SB has a recess KB1. Therefore, in the back electrode BE conformally formed on the back surface RS of the semiconductor substrate SB, a recess KB2 is formed at a position that overlaps with the recess KB1 in a plan view. Thus, if the back surface RS of the semiconductor substrate SB has a recess KB1, a back electrode BE having a recess KB2 can be formed.

[0109] As described above, recesses KB1 can be formed by performing laser annealing on the back surface RS of the semiconductor substrate SB with an insulating film ZF formed on it. Since the process of forming recesses KB1 also serves as an activation annealing process for impurities introduced into the semiconductor substrate SB, recesses KB1 can be formed while preventing an increase in the number of manufacturing steps for the semiconductor device. Therefore, the number of manufacturing steps for the semiconductor device can be reduced, and the manufacturing cost of the semiconductor device can be reduced.

[0110] The bonding material BD1 used as the die bonding material preferably contains silver. This improves the thermal conductivity of the bonding material BD1, allowing heat generated in the semiconductor device CP to be efficiently conducted to the die pad DP via the bonding material BD1. As a result, the temperature rise of the semiconductor device CP during operation can be suppressed. Consequently, the reliability of the semiconductor package PKG equipped with the semiconductor device CP can be further improved.

[0111] The back electrode BE of the semiconductor device CP does not have a gold film, but has a silver film. Therefore, the back surface ES of the back electrode BE of the semiconductor device CP is composed of a silver film. In addition, the bonding material BD1 used as a die bonding material contains silver. As mentioned above, silver is more easily oxidized than gold. In Embodiment 1, the back electrode BE of the semiconductor device CP has a recessed portion KB2, which increases the effective surface area of ​​the back electrode BE of the semiconductor device CP, thereby improving the adhesion between the back electrode BE of the semiconductor device CP and the bonding material BD1. Therefore, even if the back electrode BE has a silver film, and even if the bonding material BD1 contains silver, delamination at the interface between the back electrode BE of the semiconductor device CP and the bonding material BD1, or within the back electrode BE, can be suppressed or prevented. This improves the reliability of the semiconductor package equipped with the semiconductor device CP.

[0112] The presence of a recessed portion KB2 on the back electrode BE of the semiconductor device CP increases the contact area between the back electrode BE and the bonding material BD1, thereby reducing the thermal resistance in heat conduction from the back electrode BE to the bonding material BD1. As a result, heat generated in the semiconductor device CP can be efficiently conducted to the die pad DP via the bonding material BD1. This suppresses the temperature rise of the semiconductor device CP during operation, further improving the reliability of the semiconductor package PKG containing the semiconductor device CP.

[0113] Figure 21 is a graph showing the correlation between the energy density of the laser light (pulsed laser light LS) irradiated onto the semiconductor substrate SB during the laser annealing process and the density of the depressions KB1 formed during the laser annealing process.

[0114] The density of depressions shown on the vertical axis of the graph in Figure 21 represents the density of depressions KB1 within the back surface RS of the semiconductor substrate SB, and corresponds to the total distance (sum of lengths) of depressions KB1 per unit area on the back surface RS of the semiconductor substrate SB. In other words, the value obtained by dividing the total distance of depressions KB1 formed within a predetermined planar region by the area of ​​that predetermined planar region corresponds to the density of depressions KB1. Therefore, the density of depressions KB1 is 7 μm / μm 2 In this case, in a plan view, the total length of the depression KB1 formed within a square region with sides of 1 micrometer is, on average, 7 micrometers. Since depression KB2 is formed in a position overlapping with depression KB1 in a plan view, the density of depression KB2 is approximately the same as the density of depression KB1. Therefore, the density of depression KB1 is 7 μm / μm 2 In that case, the density of the depression KB2 is also approximately 7 μm / μm 2 That is the case.

[0115] The density of the recessed portion KB2 refers to the density of recessed portions KB2 within the back surface ES of the back electrode BE, and corresponds to the total distance (sum of lengths) of the recessed portions KB2 per unit area on the back surface ES of the back electrode BE.

[0116] As can be seen from the graph of FIG. 21, when the energy density of the laser light irradiated on the semiconductor substrate SB in the laser annealing process is low, the recess KB1 is hardly formed in the back surface RS of the semiconductor substrate SB. On the other hand, when the energy density of the laser light irradiated on the semiconductor substrate SB is high, the recess KB1 is likely to be formed in the back surface RS of the semiconductor substrate SB. Therefore, by adjusting the energy density of the laser light irradiated on the semiconductor substrate SB, the density of the recess KB1 in the back surface RS of the semiconductor substrate SB can be controlled. For example, by setting the energy density of the laser light irradiated on the semiconductor substrate SB to 1.4 J / cm 2 or more, a recess KB1 having a density of 7 μm / μm 2 or more can be formed. Therefore, a recess KB2 having a density of 7 μm / μm 2 or more can be formed.

[0117] If the density of the recess KB2 is 7 μm / μm 2 or more, the surface area of the back surface electrode BE of the semiconductor device CP can be efficiently increased, so that the adhesion between the back surface electrode BE of the semiconductor device CP and the bonding material BD1 can be accurately improved. Therefore, the density of the recess KB2 is preferably 7 μm / μm 2 or more. In order to achieve this, the density of the recess KB1 is preferably 7 μm / μm 2 or more. Therefore, the energy density of the laser light irradiated on the semiconductor substrate SB in the laser annealing process is preferably 1.4 J / cm 2 or more.

[0118] The depth of the recess KB1 is, for example, about 0.05 micrometers or more and 0.5 micrometers or less. The depth of the recess KB2 is, for example, about 0.05 micrometers or more and 0.5 micrometers or less. The thickness of the back surface electrode BE is, for example, about 400 nm or more and 3000 nm or less.

[0119] In Embodiment 1, a recess KB1 is formed in the back surface RS of the semiconductor substrate SB, thereby forming a back electrode BE having a recess KB2 on the back surface RS of the semiconductor substrate SB. This increases the effective surface area of ​​the back electrode BE of the semiconductor substrate SB, thereby improving the adhesion between the back electrode BE of the semiconductor device CP and the die bonding material (bonding material BD1). Furthermore, the thermal resistance between the back electrode BE of the semiconductor device CP and the die bonding material can be reduced. For this reason, Embodiment 1 and Embodiment 2 described later are effective when applied to semiconductor devices having back electrodes. Accordingly, the semiconductor element formed on the main surface MS of the semiconductor substrate SB is not limited to IGBTs.

[0120] However, when the semiconductor device CP is equipped with a power transistor, the amount of heat generated by the semiconductor device CP during operation is large. The large amount of heat generated by the semiconductor device CP promotes the oxidation of the silver film contained in the back electrode BE, or the oxidation of the silver contained in the bonding material BD1. For this reason, when the semiconductor element formed on the main surface MS of the semiconductor substrate SB is a power transistor such as an IGBT, the effect of applying Embodiment 1 or Embodiment 2 described later is extremely large.

[0121] (Embodiment 2) A modified version of the laser annealing process in Embodiment 1 described above will be explained as Embodiment 2.

[0122] In the above embodiment 1, the laser annealing process is performed in a single laser annealing treatment. The single laser annealing treatment is performed using the method described with reference to Figure 18. That is, in a single laser annealing treatment, the pulsed laser light LS is irradiated over the entire back surface RS of the semiconductor substrate SB by repeatedly moving the semiconductor substrate SB and irradiating it with pulsed laser light LS. In this case, the semiconductor substrate SB irradiated with pulsed laser light LS dissolves locally. That is, in the above embodiment 1, the energy density of the pulsed laser light LS is set to an energy density that can dissolve the semiconductor substrate SB.

[0123] In Embodiment 2, the laser annealing process is performed by two laser annealing treatments. The two laser annealing treatments include a first laser annealing treatment and a second laser annealing treatment.

[0124] The first laser annealing treatment is performed using the method described with reference to Figure 18 above. That is, in the first laser annealing treatment, the semiconductor substrate SB is moved and irradiated with pulsed laser light LS repeatedly, thereby irradiating the entire back surface RS of the semiconductor substrate SB with pulsed laser light LS. In the first laser annealing treatment, the semiconductor substrate SB irradiated with pulsed laser light LS does not dissolve. In other words, in Embodiment 2, the energy density of the pulsed laser light LS in the first laser annealing treatment is set to an energy density that does not dissolve the semiconductor substrate SB.

[0125] In Embodiment 2, a second laser annealing treatment is performed after the first laser annealing treatment. The second laser annealing treatment is performed using the method described with reference to Figure 18 above. That is, in the second laser annealing treatment, the pulsed laser light LS is irradiated over the entire back surface RS of the semiconductor substrate SB by repeatedly moving the semiconductor substrate SB and irradiating it with pulsed laser light LS. In the second laser annealing treatment, the semiconductor substrate SB irradiated with pulsed laser light LS dissolves locally. That is, in Embodiment 2, the energy density of the pulsed laser light LS in the second laser annealing treatment is set to an energy density that can dissolve the semiconductor substrate SB. For this reason, the energy density of the laser light (pulsed laser light LS) in the second laser annealing treatment is greater than the energy density of the laser light (pulsed laser light LS) in the first laser annealing treatment.

[0126] By applying the laser annealing process of Embodiment 2, the density of the depressions KB1 within the back surface RS of the semiconductor substrate SB can be further increased. The reason for this is explained below.

[0127] During the first laser annealing process, stress is generated within the insulating film ZF due to the difference in thermal expansion coefficients between the insulating film ZF and the semiconductor substrate SB, and this stress is retained within the insulating film ZF. If the semiconductor substrate SB is irradiated with pulsed laser light LS and melts, the stress within the insulating film ZF is released. However, in the first laser annealing process, the semiconductor substrate SB does not melt when irradiated with pulsed laser light LS, so the stress generated due to the irradiation of pulsed laser light LS is retained within the insulating film ZF.

[0128] During the second laser annealing process, the semiconductor substrate SB, irradiated with pulsed laser light LS, is heated and melted. When the melted region within the semiconductor substrate SB recrystallizes (during cooling), the semiconductor substrate SB is distorted due to the difference in thermal expansion between the insulating film ZF and the semiconductor substrate SB, resulting in the formation of a depression KB1 within the semiconductor substrate SB caused by this distortion.

[0129] The second laser annealing treatment is performed while stress is retained within the insulating film ZF after the first laser annealing treatment. This increases the strain generated within the semiconductor substrate SB during the second laser annealing treatment, thereby promoting the formation of depressions KB1. Therefore, the laser annealing process of Embodiment 2 makes it easier to form depressions KB1 and increase the density of depressions KB1 compared to the laser annealing process of Embodiment 1.

[0130] On the other hand, in the first embodiment described above, the laser annealing process can be simplified compared to the second embodiment. Therefore, in the first embodiment, the manufacturing process for semiconductor devices can be simplified. In addition, the manufacturing time for semiconductor devices can be shortened, and the throughput of semiconductor devices can be improved.

[0131] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0132] Like silver, copper is cheaper than gold, but it is more easily oxidized than gold. Therefore, even when the back electrode BE contains a copper film instead of a silver film, the problems and effects described in Embodiment 1 may occur. For this reason, Embodiments 1 and 2 can be applied even when the back electrode BE contains a copper film instead of a silver film. Also, Embodiments 1 and 2 can be applied even when the bonding material BD1 contains copper instead of silver. That is, in Embodiments 1 and 2, the back electrode BE may have a copper film instead of a silver film, and the bonding material BD1 may contain copper instead of silver. For this reason, it is possible that the back electrode BE has a copper film and the bonding material BD1 is sintered copper. Thus, comprehensively, the back electrode BE has a silver film or a copper film, and the bonding material BD1 contains silver or copper. In this case, the back surface ES of the back electrode BE is composed of a silver film or a copper film. [Explanation of symbols]

[0133] 1 IGBT BD1,BD2 Bonding material BE back electrode BW Bonding Wire C1, C2, C3, C4, C5 status CP Semiconductor CR p-type collector area D1,D2,D3 area DF n-type drift region DP Die Pad EE emitter electrode ER n-type emitter region ES reverse side FS n-type field stop region GE Terminal GF gate insulating film IL insulating film KB1, KB2 recessed area LD Lead LS pulsed laser light MP metal plate MR sealing part MS main surface OPE,OPG opening PDE Emitter Pad PDG Gate Pad PF protective film PKG Semiconductor Package PR p-type semiconductor region RG1,RG2 area RS (Reverse Side) TG Trench Gridgate ZF insulating film ZF1 back

Claims

1. A semiconductor substrate having a main surface and a back surface opposite to the main surface, A semiconductor element formed on the main surface of the semiconductor substrate, A back electrode formed on the back surface of the semiconductor substrate, Equipped with, The aforementioned back electrode includes a silver film or a copper film. The back surface of the semiconductor substrate has a first recessed portion, The back surface of the aforementioned back electrode has a second recess, wherein the semiconductor device is provided.

2. In the semiconductor device described in claim 1, A semiconductor device wherein, in a plan view, the second recess is formed in a position that overlaps with the first recess.

3. In the semiconductor device described in claim 1, A semiconductor device wherein the first recess and the second recess are each groove-shaped.

4. In the semiconductor device described in claim 1, The density of the second recess within the back surface of the back electrode is 7 μm / μm ２ That concludes the semiconductor device.

5. In the semiconductor device described in claim 1, A semiconductor device wherein the back surface of the back electrode is composed of the silver film or the copper film.

6. In the semiconductor device described in claim 1, The chip mounting section, A conductive bonding material is disposed between the chip mounting portion and the back electrode, Equipped with, The back surface of the back electrode faces the chip mounting portion via the bonding material, A semiconductor device wherein the back electrode is electrically connected to the chip mounting portion via the bonding material.

7. In the semiconductor device according to claim 6, The aforementioned bonding material is a semiconductor device containing silver or copper.

8. In the semiconductor device described in claim 1, The semiconductor device is a trench-gate transistor, which is a semiconductor device.

9. In the semiconductor device described in claim 1, The aforementioned back electrode is in contact with the semiconductor substrate, A semiconductor device in which a portion of the back surface electrode is formed within the first recess.

10. In the semiconductor device according to claim 6, The bonding material is in contact with the back electrode, A semiconductor device in which a portion of the bonding material is formed within the second recess.

11. (a) A step of preparing a semiconductor substrate having a main surface and a back surface opposite to the main surface, (b) After step (a), a step of forming an insulating film on the back surface of the semiconductor substrate, (c) After step (b), a step of performing laser annealing on the semiconductor substrate, (d) After step (c), a step of removing the insulating film, (e) After step (d), a step of forming a back electrode on the back surface of the semiconductor substrate, It has, The aforementioned back electrode includes a silver film or a copper film. The thermal expansion coefficient of the insulating film differs from that of the semiconductor substrate. In the laser annealing process, laser light is irradiated onto the back surface of the semiconductor substrate through the insulating film. In step (c) above, the laser annealing process forms a first recess on the back surface of the semiconductor substrate, A method for manufacturing a semiconductor device, wherein the back surface of the back electrode formed in step (e) has a second recess.

12. In the method for manufacturing a semiconductor device according to claim 11, A method for manufacturing a semiconductor device, wherein, in a plan view, the second recess is formed at a position overlapping with the first recess.

13. In the method for manufacturing a semiconductor device according to claim 11, A method for manufacturing a semiconductor device, wherein the insulating film is a silicon oxide film or a silicon nitride film.

14. In the method for manufacturing a semiconductor device according to claim 11, (a1) A step of forming a semiconductor element on the main surface of the semiconductor substrate after step (a) and before step (b), A method for manufacturing a semiconductor device, further comprising the above.

15. In the method for manufacturing a semiconductor device according to claim 14, (a2) After step (a1) and before step (b), a step of injecting p-type impurities or n-type impurities into the semiconductor substrate from the back surface of the semiconductor substrate. A method for manufacturing a semiconductor device, further comprising the above.

16. In the method for manufacturing a semiconductor device according to claim 11, A method for manufacturing a semiconductor device, wherein, in the laser annealing process, the semiconductor substrate irradiated with laser light is locally dissolved.

17. In the method for manufacturing a semiconductor device according to claim 11, The laser annealing process includes a first laser annealing process and a second laser annealing process performed after the first laser annealing process. A method for manufacturing a semiconductor device, wherein the energy density of the laser light in the second laser annealing process is greater than the energy density of the laser light in the first laser annealing process.

18. In the method for manufacturing a semiconductor device according to claim 17, In the second laser annealing process, the semiconductor substrate irradiated with laser light dissolves locally, A method for manufacturing a semiconductor device, wherein, in the first laser annealing process, the semiconductor substrate irradiated with laser light does not dissolve.

19. In the method for manufacturing a semiconductor device according to claim 11, A method for manufacturing a semiconductor device, wherein the first recess and the second recess are each groove-shaped.

20. In the method for manufacturing a semiconductor device according to claim 11, The density of the second recess within the back surface of the back electrode is 7 μm / μm ２ The above is a method for manufacturing a semiconductor device.

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