Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device

Abstract

The present invention provides a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that reduce manufacturing costs. [Solution] The method involves forming an SJ structure that reduces costs by reducing the number of repetitions of the multi-stage epitaxial process by using a resist film of a predetermined thickness as an ion implantation mask and implanting p-type impurities at room temperature with high acceleration energy to form a p-type column region 42. Then, using a cathodoluminescence method, the average value of the bottom value of the SiC CL emission intensity near the center in the X direction of the n-type column region 41, normalized by the integrated intensity of the SiC CL emission in the band edge emission of SiC from 375 nm to 396 nm, is taken as A, and the average value of the peak value of the SiC CL emission intensity near the center in the X direction of the p-type column region is taken as B, where B / A is less than 1.3.

Description

[Technical Field] 【0001】 This disclosure relates to silicon carbide semiconductor devices and methods for manufacturing silicon carbide semiconductor devices. [Background technology] 【0002】 Patent documents 1 and 2 below describe a technique for forming an SJ structure using a multi-stage epitaxial method in an SJ-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field-effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) in which the drift layer is arranged alternately and repeatedly in a direction parallel to the main surface of the semiconductor substrate, with n-type and p-type regions. [Prior art documents] [Patent Documents] 【0003】 [Patent Document 1] Japanese Patent Publication No. 2015-216182 [Patent Document 2] International Publication No. 2020 / 110514 [Overview of the project] [Problems that the invention aims to solve] 【0004】 In the formation of SJ structures using the multi-stage epitaxial method, the following steps are repeated in the same order under identical conditions: stacking of n-type epitaxial layers (epitaxial growth), formation of an ion implantation mask, ion implantation of p-type impurities, and removal of the ion implantation mask. When silicon carbide (SiC) is used as the semiconductor material, impurities do not diffuse easily within SiC, so it is common to reduce the thickness of the n-type epitaxial layer and increase the number of stages (layers). In addition, ion implantation is performed under heating conditions of around 500°C to prevent residual crystal defects generated during ion implantation. Therefore, the multi-stage epitaxial method requires a large number of repetitions, and both heating and cooling processes are necessary during the ion implantation process, resulting in a longer manufacturing lead time and higher manufacturing costs. 【0005】 This disclosure aims to provide silicon carbide semiconductor devices and methods for manufacturing silicon carbide semiconductor devices that can reduce costs. [Means for solving the problem] 【0006】 A silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A parallel pn layer is provided inside a semiconductor substrate made of silicon carbide. The parallel pn layer is formed by alternately arranging a first conductivity type region and a second conductivity type region in a first direction parallel to the first main surface of the semiconductor substrate. A first semiconductor region of the second conductivity type is provided between the first main surface of the semiconductor substrate and the parallel pn layer. A predetermined element structure is provided between the first main surface of the semiconductor substrate and the parallel pn layer, through which current flows via the pn junction between the first semiconductor region and the first conductivity type region. A first electrode is electrically connected to the first semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate. If we consider the integrated intensity of the L1 line cathodoluminescence emission of silicon carbide obtained using the cathodoluminescence method, or the integrated intensity of the cathodoluminescence emission of silicon carbide in a band with a longer wavelength than the L1 line cathodoluminescence emission and a broader peak width than the L1 line cathodoluminescence emission, and define A as the average of the bottom values ​​of the silicon carbide cathodoluminescence emission intensity near the center of the first direction in the first conductivity type region normalized by the integrated intensity of the band edge emission of silicon carbide, and define B as the average of the peak values ​​of the silicon carbide cathodoluminescence emission intensity near the center of the first direction in the second conductivity type region obtained using the cathodoluminescence method, then the ratio of B to A (B / A) is less than 1.3. 【0007】 Furthermore, a method for manufacturing a silicon carbide semiconductor device according to one aspect of this disclosure is a method for manufacturing a silicon carbide semiconductor device comprising a parallel pn layer in which a first conductivity type region and a second conductivity type region are alternately and repeatedly arranged in a direction parallel to the first main surface of a semiconductor substrate made of silicon carbide, and is as follows: A first step is performed to form the parallel pn layer on a starting substrate made of silicon carbide that forms the second main surface of the semiconductor substrate by a multi-stage epitaxial method. A second step is performed to form a first semiconductor region of the second conductivity type on the parallel pn layer. A third step is performed to form an element structure through which current flows via a pn junction between the first semiconductor region and the first conductivity type region. A fourth step is performed to form a first electrode electrically connected to the first semiconductor region. A fifth step is performed to form a second electrode on the second main surface of the semiconductor substrate. The first step includes a lamination step and a first injection step. In the lamination step, a first conductivity type epitaxial layer made of silicon carbide is epitaxially grown. In the first implantation step, a resist film with a thickness of 3.0 μm or more is used as a mask, and a second conductivity type impurity is implanted as a first ion at room temperature to selectively form a diffusion region that will become the second conductivity type region in the first conductivity type epitaxial layer, leaving the portion of the first conductivity type epitaxial layer excluding the diffusion region as the first conductivity type region. [Effects of the Invention] 【0008】 The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device described herein have the effect of improving throughput and reducing costs. [Brief explanation of the drawing] 【0009】 [Figure 1] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view (part 1) showing the state of a silicon carbide semiconductor device during the manufacturing process according to Embodiment 1. [Figure 3] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 4]This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device in the process of being manufactured according to Embodiment 1. [Figure 5] This is a cross-sectional view (part 4) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 6] This is a cross-sectional view (part 1) showing the silicon carbide semiconductor device in the process of being manufactured according to Embodiment 2. [Figure 7] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device according to Embodiment 2 in the process of manufacturing. [Figure 8] This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device according to Embodiment 2 in the process of manufacturing. [Figure 9] This is a cross-sectional view (part 4) showing the silicon carbide semiconductor device according to Embodiment 2 during the manufacturing process. [Figure 10] This is a cross-sectional view (part 5) showing the silicon carbide semiconductor device according to Embodiment 2 in the process of manufacturing. [Figure 11] This characteristic diagram shows the results of a simulation of the relationship between the average range of p-type impurities ion-implanted into an ion implantation mask and the acceleration energy during ion implantation. [Figure 12] This is a schematic diagram illustrating the results of a simulation of the concentration distribution of p-type impurities ion-implanted into an SiO2 film. [Figure 13] This is a schematic diagram illustrating the results of a simulation of the concentration distribution of p-type impurities ion-implanted in a resist film. [Figure 14] This is a cross-sectional image of a resist film obtained by coating and baking a SiC substrate and then fabricating a trench pattern for an SJ structure using photolithography. [Figure 15] This is a schematic cross-sectional view showing an SEM image of a cross-section of an SJ-MOSFET containing parallel pn layers. [Figure 16] Figure 15 is a schematic cross-sectional view showing the CL image of the cross-section. [Figure 17] Figure 16 is a characteristic diagram showing the CL emission intensity distribution of SiC in the CL image. [Figure 18]Figure 16 is a characteristic diagram showing the CL emission intensity distribution of SiC in the CL image. [Figure 19] Figure 15 is a schematic cross-sectional view showing the CL image of the cross-section. [Figure 20] Figure 19 is a characteristic diagram showing the CL emission intensity distribution of SiC in the CL image. [Figure 21] Figure 19 is a characteristic diagram showing the CL emission intensity distribution of SiC in the CL image. [Figure 22] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device as an example. [Figure 23] Figures 18 and 21 show the normalized CL emission intensity data for the peak value near the center of the p column and the bottom value near the center of the n column of the normalized CL emission intensity waveform, along with the calculated average values ​​(peak mean, bottom mean) and ratios of these values. [Modes for carrying out the invention] 【0010】 <Summary of the embodiments of this disclosure> (1) A silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A parallel pn layer is provided inside a semiconductor substrate made of silicon carbide. The parallel pn layer is formed by alternately arranging a first conductivity type region and a second conductivity type region in a first direction parallel to the first main surface of the semiconductor substrate. A first semiconductor region of the second conductivity type is provided between the first main surface of the semiconductor substrate and the parallel pn layer. A predetermined element structure is provided between the first main surface of the semiconductor substrate and the parallel pn layer, through which current flows via the pn junction between the first semiconductor region and the first conductivity type region. A first electrode is electrically connected to the first semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate. If we consider the integrated intensity of the L1 line cathodoluminescence emission of silicon carbide obtained using the cathodoluminescence method, or the integrated intensity of the cathodoluminescence emission of silicon carbide in a band with a longer wavelength than the L1 line cathodoluminescence emission and a broader peak width than the L1 line cathodoluminescence emission, and define A as the average of the bottom values ​​of the silicon carbide cathodoluminescence emission intensity near the center of the first direction in the first conductivity type region normalized by the integrated intensity of the band edge emission of silicon carbide, and define B as the average of the peak values ​​of the silicon carbide cathodoluminescence emission intensity near the center of the first direction in the second conductivity type region obtained using the cathodoluminescence method, then the ratio of B to A (B / A) is less than 1.3. 【0011】 According to the disclosure described above, the minority carrier lifetime of the first conductivity type region of the parallel pn layer is shortened, and the spreading of basal plane dislocations is prevented, thereby improving the reliability of the silicon carbide semiconductor device. 【0012】 (2) In addition, in the silicon carbide semiconductor device according to this disclosure, in (1) above, the second conductivity type region of the parallel pn layer has a periodic distribution in the depth direction of the impurity concentration that determines its conductivity type. 【0013】 According to the disclosure described above, parallel pn layers can be formed using a multi-stage epitaxial method, as will be described later. 【0014】 (3) A method for manufacturing a silicon carbide semiconductor device according to one aspect of this disclosure is a method for manufacturing a silicon carbide semiconductor device comprising a parallel pn layer in which a first conductivity type region and a second conductivity type region are alternately and repeatedly arranged in a direction parallel to the first main surface of a semiconductor substrate made of silicon carbide, and is as follows: A first step is performed in which the parallel pn layer is formed on a starting substrate made of silicon carbide that forms the second main surface of the semiconductor substrate by a multi-stage epitaxial method. A second step is performed in which a first semiconductor region of the second conductivity type is formed on the parallel pn layer. A third step is performed in which an element structure is formed through which current flows through the pn junction between the first semiconductor region and the first conductivity type region. A fourth step is performed in which a first electrode is electrically connected to the first semiconductor region. A fifth step is performed in which a second electrode is formed on the second main surface of the semiconductor substrate. The first step includes a lamination step and a first injection step. In the lamination step, a first conductivity type epitaxial layer made of silicon carbide is epitaxially grown. In the first implantation step, a resist film with a thickness of 3.0 μm or more is used as a mask, and a second conductivity type impurity is implanted as a first ion at room temperature to selectively form a diffusion region that will become the second conductivity type region in the first conductivity type epitaxial layer, leaving the portion of the first conductivity type epitaxial layer excluding the diffusion region as the first conductivity type region. 【0015】 According to the disclosure described above, when forming parallel pn layers using a multi-stage epitaxial method, the first conductivity type epitaxial layer, which becomes the first conductivity type region of the parallel pn layer, can be epitaxially grown with a small number of stages by increasing the thickness of each stage. This reduces the number of repetitions in the series of processes using the multi-stage epitaxial method, simplifies the manufacturing process, shortens the lead time, and thus reduces the manufacturing cost of silicon carbide semiconductor devices. 【0016】 (4) Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in (3) above, the first step includes a mask step of forming the resist film on the first conductivity type epitaxial layer, with an opening in the portion facing the formation region of the second conductivity type region, and in the lamination step, the thickness of the first conductivity type epitaxial layer is 1 μm or more. In the mask step, the thickness of the resist film is 3.0 μm or more and 20.0 μm or less. In the first implantation step, the first ion implantation may be performed with the resist film as a mask at an acceleration energy of 1.5 MeV or more and 15 MeV or less. 【0017】 According to the disclosure described above, it is possible to implant a second conductivity type impurity into the first conductivity type epitaxial layer to the extent that it penetrates the first conductivity type epitaxial layer in the depth direction and reaches the lower layer, and to impart to the resist film a mask function that is sufficient to shield the second conductivity type impurity that has been implanted with the first ion. 【0018】 (5) In addition, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in (3) or (4) above, in the first implantation step, the second conductivity type impurity of the first ion implantation is preferably aluminum. 【0019】 According to the disclosure described above, aluminum, which has a relatively high diffusion coefficient in silicon carbide (SiC), can be used as the second conductive impurity. 【0020】 (6) Furthermore, in any one of the above-described steps (3) to (5), the method for manufacturing a silicon carbide semiconductor device according to this disclosure is to epitaxially grow a first conductivity type epitaxial layer having an impurity concentration lower than the design value of the impurity concentration of the first conductivity type region in the lamination step. The first step may further include a second implantation step in which the impurity concentration of the first conductivity type epitaxial layer is increased to the design value by implanting the first conductivity type impurity into a second ion at room temperature. 【0021】 According to the disclosure described above, even when the impurity concentration of the first conductivity type epitaxial layer is adjusted by second ion implantation of the first conductivity type impurity, the first conductivity type epitaxial layer can be epitaxially grown with a small number of layers by increasing the thickness of each layer. 【0022】 (7) In addition, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the second implantation step described in (6) above, the second ion implantation may be performed at room temperature without heating the semiconductor substrate. 【0023】 According to the disclosure described above, since heating and cooling of the semiconductor substrate are not required, lead time can be improved. 【0024】 <Knowledge forming the basis of this disclosure> The inventors have made the following discovery as a result of diligent research. First, the structure of the silicon carbide semiconductor device with a superjunction (SJ) structure of the reference example will be explained using the case where the breakdown voltage is 1.2kV class as an example. Figure 22 is a cross-sectional view showing the structure of the silicon carbide semiconductor device of the reference example. The silicon carbide semiconductor device 210 of the reference example shown in Figure 22 has a trench gate structure on the front side (main surface on the p-type epitaxial layer 223 side) of the semiconductor substrate (semiconductor chip) 220 made of silicon carbide (SiC), and the n of the drift layer 202 + This is a vertical SJ-MOSFET with an SJ structure in which the source region 204 side (the front side of the semiconductor substrate 220) is a parallel pn layer 243. 【0025】 The parallel pn layer 243 is formed by a multi-stage epitaxial method using high-temperature injection, which will be described later. When the thickness T200 of the parallel pn layer 243 is, for example, about 5 μm, the parallel pn layer 243 is formed by epitaxially growing seven n-type epitaxial layers 222 (222b~222h) on top of an n-type buffer region 202a (n-type epitaxial layer 222a). Specifically, in the manufacturing method of the silicon carbide semiconductor device 210 in the reference example, in the formation of the parallel pn layer 243, first, n +An n-type epitaxial layer 222a (222), which will become an n-type buffer region 202a, is epitaxially grown on the front surface of the starting substrate 221. 【0026】 Next, an oxide film (silicon oxide (SiO2) film) with a thickness of approximately 2.0 μm is formed on the n-type epitaxial layer 222a. Then, a resist film with a thickness of approximately 2.0 μm is formed on the oxide film, and a mask of the oxide film is formed using photolithography technology. Then, using this oxide film as an ion implantation mask, p-type impurities are ion-implanted (hereinafter referred to as high-temperature implantation) while the semiconductor substrate is heated to approximately 500°C (a cooling process is also required in conjunction with the heating process), thereby forming a p-type region that will become a p-type column region 242 on the surface region of the n-type epitaxial layer 222a exposed at the openings of the oxide film. This high-temperature implantation is performed at a low acceleration energy in the range of approximately 60 keV to 700 keV in order to prevent the p-type impurities from penetrating the oxide film which is the ion implantation mask. 【0027】 Next, an n-type epitaxial layer 222b is epitaxially grown on the n-type buffer region 202a to increase the thickness of the n-type epitaxial layer 222, which will become the drift layer 202. The thickness T205 of the n-type epitaxial layer 222b is, for example, about 0.65 μm. Next, a series of steps from forming an oxide film with a thickness of about 2.0 μm to implanting p-type impurities at high temperature are performed in the same manner. By repeating this series of steps multiple times (in this case, the remaining 6 times), a parallel pn layer 243 with a predetermined thickness T200 is formed. The thickness T203 of the portion of the n-type epitaxial layer 222 on the n-type buffer region 202a is about 4.55 μm (= 0.65 μm × 7 layers). The portion of the n-type epitaxial layer 222 that remains n-type without ion implantation between adjacent p-type column regions 242 becomes the n-type column region 241. 【0028】 In the manufacturing method described in this example, the following steps are repeated under the same conditions in this order until the parallel pn layer 243 reaches a predetermined thickness T200: lamination of the n-type epitaxial layer 222, formation of an ion implantation mask (oxide film), high-temperature implantation of p-type impurities (both heating and cooling processes are required), and removal of the ion implantation mask. This increases the number of steps and lengthens the lead time, thus increasing the manufacturing cost. When forming a trench gate structure, the manufacturing cost is further increased because the n-type epitaxial layer 222 and the p-type epitaxial layer 223 are epitaxially grown (laminated) on the parallel pn layer 243. Therefore, the problem to be solved in this embodiment is cost reduction. 【0029】 The inventors have found that by performing ion implantation to form a p-type column region at room temperature (RT) without heating the semiconductor substrate (hereinafter referred to as room temperature implantation), and by increasing the ion acceleration energy during ion implantation compared to the manufacturing method of the reference example, it is possible to form a parallel pn layer with fewer steps and a shorter lead time than the manufacturing method of the reference example. 【0030】 Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. 【0031】 (Details of Embodiment 1) The structure of the silicon carbide semiconductor device according to Embodiment 1 will be described below. FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. The silicon carbide semiconductor device 10 according to Embodiment 1 shown in FIG. 1 has a trench gate structure (element structure) on the front surface side of a semiconductor substrate (semiconductor chip) 20 made of silicon carbide (SiC), and is a vertical SJ-MOSFET having a SJ structure in which a part of the drift layer 2 is a parallel pn layer 43. That is, the drift layer 2 in FIG. 1 exemplifies a semi-SJ structure having a drift layer (parallel pn layer 43) of SJ structure provided on a bulk-type drift layer (n-type buffer region 2a). Only one unit cell (functional unit of the element) of the MOSFET is shown in FIG. 1, but a plurality of unit cells having the same structure are arranged in parallel adjacent to each other on the semiconductor substrate 20. 【0032】 The semiconductor substrate 20 is an n + -type SiC epitaxial substrate formed by epitaxially growing drift layer 2 and p-type base regions (first semiconductor regions) 3, i.e., epitaxial layers 22 and 23, in this order on the front surface of an n + -type starting substrate 21. The semiconductor substrate 20 has the first main surface (the surface of the p-type epitaxial layer 23) on the p-type epitaxial layer 23 side as the front surface, and the n + -type starting substrate 21 side's second main surface (the back surface of the n + -type starting substrate 21) as the back surface. The n + -type starting substrate 21 serves as an n + -type drain region 1. The n + -type starting substrate 21 is, for example, a single crystal bulk substrate of 4H-SiC (tetragonal periodic hexagonal crystal of silicon carbide). The thickness T sub of the n 【0033】 -type starting substrate 21 is, for example, about 350 μm. + The drift layer 2 is composed of an n-type epitaxial layer 22 between a p-type base region 3 (p-type epitaxial layer 23) and an n + -type drain region 1 (n + -type starting substrate 21). The lower surface (the surface on the n +It is adjacent to the drain region 1. The parallel pn layer 43 is adjacent to the drift layer 2, at least n + This is the source region 4 side (the front side of the semiconductor substrate 20), and is formed in the drift layer 2 (n-type epitaxial layer 22) by a multi-stage epitaxial method using room temperature injection (see Figures 2-5 described later). 【0034】 Here, room temperature, in natural science, refers to the ambient temperature at which matter does not absorb or release heat and is not affected by temperature (i.e., does not convect), and is close to the temperature range in which matter does not change temperature or changes temperature only gently (i.e., there is almost no heat conduction between materials). Specifically, room temperature is close to the control temperature of a room where a silicon carbide semiconductor manufacturing line is installed (e.g., a clean room), for example, around 20°C (e.g., between 15°C and 25°C). 【0035】 In other words, room-temperature implantation is a method of performing ion implantation without heating the object to be implanted in the chamber (processing chamber) of the ion implantation apparatus with a heater or the like. Instead, the chamber is kept at a temperature close to the controlled temperature of the room where the ion implantation apparatus is installed, and the chamber is evacuated to a high degree of vacuum. During ion implantation, heat is generated due to the flow of the ion beam current, but this temperature change is sufficiently weak depending on the beam current density and the ion implantation time settings. The temperature change is so small that the organic resist film deposited on the silicon carbide semiconductor substrate does not melt or carbonize, and remains intact. 【0036】 The multi-stage epitaxial method is a method in which epitaxial layers are epitaxially grown (stacked) in multiple stages (multiple times), and each time, an ion implantation mask is used to selectively implant a diffusion region of the same conductivity adjacent to each other in the depth direction Z. Thickness T of the parallel pn layer 43 sj If the thickness is, for example, about 5 μm, the parallel pn layer 43 is formed by epitaxially growing two n-type epitaxial layers 22 (22b, 22c) in two stages. 【0037】 The parallel pn layer 43 is formed by alternately arranging n-type regions (n-type column regions (first conductivity type regions)) 41 and p-type regions (p-type column regions (second conductivity type regions)) 42 adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 20. The n-type column regions 41 and p-type column regions 42 are arranged in a stripe pattern, extending linearly in a second direction Y parallel to the front surface of the semiconductor substrate 20 and perpendicular to the first direction X. The n-type column regions 41 and p-type column regions 42 are arranged in a stripe pattern on the lower surface + It is adjacent to the type drain region 1 or the n-type buffer region 2a described later. 【0038】 The adjacent n-type column region 41 and p-type column region 42 are roughly in charge balance. The statement that the adjacent n-type column region 41 and p-type column region 42 are roughly in charge balance means that the charge amount, expressed as the product of the carrier concentration (concentration of activated n-type impurities) of the n-type column region 41 and its width in the short direction (first direction X), is roughly in equilibrium with the charge amount, expressed as the product of the carrier concentration (concentration of activated p-type impurities) of the p-type column region 42 and its width in the short direction. 【0039】 The n-type column region 41 is composed of the portion of the n-type epitaxial layer 22 (22b, 22c) that remains as it was during epitaxial growth. Therefore, the impurity concentration profile of the n-type column region 41 is a box profile shape with an approximately uniform impurity concentration in the depth direction Z. The impurity concentration of the n-type column region 41 is, for example, 1.0 × 10⁻⁶. 15 / cm 3 The above 1.0 × 10 17 / cm 3 Approximately the following, preferably 5.0 × 10 15 / cm 3 The above 1.0 × 10 17 / cm 3The following is an example. The impurity concentration profile of the p-type column region 42 is controlled to have a box profile shape by multi-stage injection. Multi-stage injection is the process of ion implanting a predetermined dose of impurity in multiple stages (multiple times) with different acceleration energies. The impurity concentration of the p-type column region 42 is, for example, 1.0 × 10⁻⁶. 16 / cm 3 The above 1.0 × 10 18 / cm 3 The following extent, preferably 1.0 × 10 16 / cm 3 The above 5.0 × 10 17 / cm 3 The following is the extent of the problem. Although not particularly limited, since Al (p-type impurity) is ion-implanted into the n-type epitaxial layer to form a p-type column region, the Al impurity concentration is set higher than the n-type impurity concentration to account for the cancellation of n-type and p-type impurities. 【0040】 Even when the p-type column region 42 is represented as a box profile due to multi-stage implantation of p-type impurities (acceptor impurities), the p-type regions 42a and 42b of each stage (epitaxial layers 22b and 22c) have cross-sections with one peak and two bottoms in the impurity concentration distribution in the depth direction Z. The Gaussian distribution of impurities in each cross-section with one peak and two bottoms is interconnected in the depth direction Z, forming a periodic distribution that represents the periodic distribution of impurities in the longitudinal cross-section of the p-type column region 42 (the impurity concentration distribution in the depth direction Z as viewed from a cross-sectional view perpendicular to the main surface of the semiconductor substrate 20). Since the p-type column region 42 is formed by ion implantation, crystal defects (crystal damage) occur. 【0041】 These ion-implanted crystal defects can be recovered by annealing in the case of a silicon (Si) substrate, but remain even after annealing in a SiC substrate (semiconductor substrate 20). The periodic distribution of acceptor impurities (Al) and crystal defects in the longitudinal cross-sectional structure of the p-type column region 42 are structural traces resulting from repeated epitaxial growth and ion implantation. Since the n-type column region 41 remains as an epitaxially grown layer, no periodic impurity concentration distribution or crystal defects are observed in the longitudinal cross-sectional structure of the n-type column region 41 in the depth direction Z. The periodic impurity concentration distribution of the p-type column region 42 is maintained even after predetermined heat treatment. 【0042】 The n-type column region 41 and the p-type column region 42 have, for example, a substantially uniform width in the X direction with respect to the depth Z direction. The adjacent n-type column region 41 and p-type column region 42 only need to be roughly charge-balanced, and the respective widths in the X direction of the n-type column region 41 and p-type column region 42 are set as appropriate. For example, the width in the X direction of the n-type column region 41 may be wider than the width in the X direction of the p-type column region 42. The substantially uniform width, substantially uniform impurity concentration, and roughly balanced charge amount mean that they have the same width, the same impurity concentration, and the same charge amount, respectively, within a range that includes tolerances due to process variations (e.g., ±5%). 【0043】 Furthermore, regarding the integrated intensity of CL emission of SiC on the L1 line at wavelengths from 422 nm to 428 nm obtained by the cathodoluminescence (CL) method, or the integrated intensity of CL emission of SiC in a broad-peaked band on the longer wavelength side from 468 nm to 570 nm, if A is the average value of the bottom value of the CL emission intensity of SiC near the center of the first direction X in the n-type column region 41 normalized by the integrated intensity of band-edge emission of SiC at wavelengths from 375 nm to 396 nm, and B is the average value of the peak value of the CL emission intensity of SiC near the center of the first direction X in the p-type column region 42 obtained using the CL method, then the ratio of B to A (B / A) is less than 1.3 (see Figures 15-21 and 23 described later). 【0044】 The CL method is a technique used to analyze the crystal structure, impurities, and defect state near the irradiation surface of an object by irradiating the irradiation surface of an object with accelerated electrons and analyzing the emission intensity distribution of the emitted photons. The higher the acceleration voltage of the electrons (electron beam) irradiated onto the object during CL analysis (hereinafter referred to as CL analysis), the deeper the CL emission intensity distribution obtained from the irradiation surface. The CL measurement temperature is 28K. The CL emission of the L1 line of SiC and the CL emission with a broad peak width on the long wavelength side of SiC will be discussed later. 【0045】 Of the drift layer 2, parallel pn layers 43 and n + The portion between the type drain region 1 may be an n-type buffer region (an n-type region that is not an SJ structure) 2a. The thickness T of the parallel pn layer 43. sj If the thickness is approximately 5 μm, then the thickness T of the n-type buffer region 2a buf For example, it is about 4.4 μm. The impurity concentration in the n-type buffer region 2a is less than or equal to the impurity concentration in the n-type column region 41. The impurity concentration in the n-type buffer region 2a is, for example, 5.0 × 10⁻⁶. 15 / cm 3 The above 2.5 × 10 16 / cm 3 The following is an example. While not particularly limited, in a typical semi-SJ structure, the impurity concentration in the n-type buffer region 2a is lower than the impurity concentration in the n-type column region 41. 【0046】 The trench gate structure is provided between the front surface of the semiconductor substrate 20 and the parallel pn layer 43. The trench gate structure consists of a p-type base region 3 and a n-type base region. + Type source area 4, p ++ It consists of a type contact region 5, a trench 6, a gate insulating film 7, and a gate electrode 8. The trench 6 is in the depth direction Z n + The current penetrates the p-type source region 4 and the p-type base region 3, and through the n-type current diffusion region 33 to form the p + The column reaches type region 31. The trench 6 extends in a stripe-like pattern along the longitudinal direction (second direction Y) of the p-type column region 42. 【0047】 The trench 6 faces the n-type column region 41 in the depth direction Z. Inside the trench 6, a gate electrode 8 is provided via a gate insulating film 7. One unit cell is formed in one trench 6 (i.e., between the mesa centers of adjacent trenches 6). One unit cell may be formed between the centers of adjacent trenches 6. + Type source region 4 and p ++ The type contact region 5 is a diffusion region formed in the p-type epitaxial layer 23 by ion implantation. 【0048】 n + Type source region 4 and p ++ The p-type contact regions 5 are selectively provided between the front surface of the semiconductor substrate 20 and the p-type base region 3, in contact with the p-type base region 3. + The mold source region 4 is in contact with the gate insulating film 7 on the side wall of the trench 6. ++ The contact area 5 is positioned away from the trench 6. ++ The type contact area 5 does not need to be provided. In this case, p ++ Instead of the type contact region 5, the p-type base region 3 extends to the front surface of the semiconductor substrate 20. 【0049】 n + Type source region 4 and p ++ The portion excluding the type contact region 5 is the p-type base region 3. Between the p-type base region 3 and the parallel pn layer 43, + Type regions 31, 32 and n-type current diffusion region 33 are selectively provided. + Type region 31, and p + A portion of the type region 32 (32a) is located deeper than the bottom surface of the trench 6. n-type current diffusion region 33 and p + The type regions 31 and 32 are the remaining portion (the portion that remains without ion implantation) of the n-type epitaxial layer (first conductive type epitaxial layer) 22 and the diffusion region formed in the n-type epitaxial layer 22 by ion implantation, respectively. 【0050】 Of the n-type epitaxial layer 22, p+ The portion excluding the n-type regions 31 and 32 and the n-type current diffusion region 33 is the drift layer 2. + The n-type regions 31 and 32 are fixed at the potential of the source electrode 11 and have the function of mitigating the electric field applied to the gate insulating film 7 at the bottom of the trench 6 by depleting them when the MOSFET is off (or by depleting the n-type current diffusion region 33, or both). + The mold regions 31 and 32 extend in the longitudinal direction (second direction Y) of the trench 6 for approximately the same length as the trench 6. 【0051】 p + The mold region 31 is provided separately from the p-type base region 3 and faces the bottom surface of the trench 6 in the depth direction Z. + The type region 31 is in contact with the n-type column region 41 on its lower surface. + The mold region 31 may be in contact with the gate insulating film 7 at the bottom of the trench 6, or it may be away from the trench 6. + The p-type region 32 is adjacent to the p-type base region 3 between the trenches 6 and p + It is provided separately from the mold region 31. + The type region 32 is in contact with the p-type column region 42 on its lower surface. 【0052】 The n-type current diffusion region 33 is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. The n-type current diffusion region 33 has the function of facilitating the diffusion of electron current from the channel (n-type inversion layer) to the n-type column region 41 when the MOSFET is turned on, and is a low-resistance region with a higher impurity concentration than the n-type column region 41. The n-type current diffusion region 33 consists of adjacent p + The n-type current diffusion region 33 is located between the type regions 31 and 32 and is in contact with these regions and the p-type base region 3. The n-type current diffusion region 33 is in contact with the n-type column region 41 on its lower surface. 【0053】 The n-type current diffusion region 33 is a p-type base region 3 and p +The current reaches the trench 6 between the n-type region 31 and the gate insulating film 7 on the side wall of the trench 6. The n-type current diffusion region 33 may have the same impurity concentration as the n-type column region 41. In this case, the n-type column region 41 consists of adjacent p + It extends between type regions 31 and 32 and reaches the p-type base region 3, and is in contact with the p-type base region 3 on its upper surface, and the p-type base region 3 and p + The material reaches the trench 6 between the mold region 31 and the trench 6, and contacts the gate insulating film 7 on the side wall of the trench 6. 【0054】 The interlayer insulating film 9 is provided over the entire surface of the front surface of the semiconductor substrate 20 and covers the gate electrode 8. The source electrode (first electrode) 11 is in the contact hole 9a of the interlayer insulating film 9. + Type source region 4 and p ++ Ohmic contact is made to the p-type contact region 5, and the p-type base region 3, n + Type source region 4 and p ++ It is electrically connected to the contact area 5. The drain electrode (second electrode) 12 is on the back surface (n) of the semiconductor substrate 20. + It is provided on the entire surface of the main surface on the mold starting substrate 21 side, n + Type drain region 1(n + It makes ohmic contact with the starting substrate 21). 【0055】 The operation of the silicon carbide semiconductor device 10 (SJ-MOSFET) according to Embodiment 1 will be described. When a positive voltage is applied to the drain electrode 12 with respect to the source electrode 11, p ++ Type contact region 5, p-type base region 3, p-type column region 42 and p + n-type regions 31, 32, n-type current diffusion region 33, n-type column region 41, n-type buffer region 2a and n + The drain region 1 and the pn junction (main junction) are reverse-biased. In this state, if the voltage applied to the gate electrode 8 is less than the gate threshold voltage, the MOSFET remains in the off state. 【0056】 When the MOSFET is off, p from the main junction +The electric field applied to the gate insulating film 7 is relaxed by the depletion layers that spread into the p-type regions 31 and 32. A predetermined breakdown voltage is ensured as the depletion layers spread outward (toward the end portion side of the semiconductor substrate 20). Also, when the MOSFET is off, the pn junction between the p-type column region 42 and the n-type column region 41 is reverse-biased, and a depletion layer spreads from the pn junction, with the parallel pn layer 43 bearing the breakdown voltage. Thereby, a predetermined breakdown voltage exceeding the breakdown voltage achievable with the impurity concentration of the drift layer 2 (the impurity concentration of the n-type column region 41) is ensured. 【0057】 On the other hand, when a gate voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 8 while a positive voltage is applied to the drain electrode 12 with respect to the source electrode 11, a channel (n-type inversion layer) is formed in a portion along the sidewall of the trench 6 in the p-type base region 3. Thereby, a main current (drift current) flows from the n-type drain region 1 through the n-type buffer region 2a, the n-type column region 41, the n-type current diffusion region 33, and the channel toward the n-type source region 4, and the MOSFET turns on. + type drain region 1 to the n-type buffer region 2a, the n-type column region 41, the n-type current diffusion region 33, and through the channel to the n + type source region 4, and the MOSFET turns on. 【0058】 The manufacturing method of the silicon carbide semiconductor device 10 according to Embodiment 1 will be described by taking the case where the breakdown voltage class is 1.2 kV as an example. FIGS. 2 to 5 are cross-sectional views showing the state during the manufacture of the silicon carbide semiconductor device according to Embodiment 1. First, an n + type epitaxial layer 22a (22) that will become the n-type buffer region 2a of the drift layer 2 is epitaxially grown on the front surface of the n + type starting substrate 21 that will become the drain region 1 (FIG. 2). The thickness T + of the n-type starting substrate 21 sub is, for example, about 350 μm. The impurity concentration and thickness of the n-type epitaxial layer 22a are respectively the same as the impurity concentration (for example, 1.8×10 16 / cm 3 level) and thickness T buf of the n-type buffer region 2a. 【0059】 Next, an n-type epitaxial layer (first conductive epitaxial layer) 22b, which will become the drift layer 2, is epitaxially grown on the n-type epitaxial layer 22a (lamination process: Figure 2). The n-type epitaxial layers 22a and 22b are typically grown continuously by CVD. The impurity concentration of the n-type epitaxial layer 22b is, for example, 3.0 × 10⁻⁶. 16 / cm 3 It is approximately the thickness T of the n-type epitaxial layer 22b. m This is, for example, about 1 μm or more. Thickness T of n-type epitaxial layer 22b m The thickness of this layer can be as thick as possible, as long as the p-type impurities injected at room temperature with the high acceleration energy described later penetrate through to reach the lower layer (n-type epitaxial layer 22a), for example, it may be about 2.5 μm. 【0060】 Next, a resist film 51, which serves as an ion implantation mask, is formed on the n-type epitaxial layer 22b. The thickness T1 of the resist film 51 is thick enough to shield p-type impurities implanted at room temperature with high acceleration energy 52, for example, in the range of 3.0 μm to 20.0 μm. For example, the thickness T1 of the resist film 51 is about 6.0 μm, and the film density of the resist film 51 after baking is 1.2 g / cm³. 3 If sufficient, p-type impurities implanted at room temperature with a high acceleration energy of about 5 MeV 52 can be adequately shielded (see Figure 13). As for the resist material, a novolac resin-based resist may be used, or other materials may be used. In addition, a chemically amplified resist may be used, or a non-chemically amplified resist may be used. Next, a predetermined mask pattern is transferred to the resist film 51 using photolithography technology and developed to open up the portion corresponding to the formation region of the p-type column region 42 (masking step: Figure 3). 【0061】 Next, using the resist film 51 as a mask, p-type impurities (second conductive type impurities) are implanted at room temperature (first ion implantation) 52, thereby forming a p-type region (diffusion region) 42a that becomes the p-type column region 42 in the surface region of the n-type epitaxial layer 22b exposed at the opening 51a of the resist film 51 (first implantation step: FIG. 3). This room temperature implantation 52 is performed as multi-stage implantation in 13 steps with an acceleration energy within a range of, for example, 120 keV or more and 5 MeV or less, and the impurity concentration profile of the p-type region 42a is made into a box profile shape. The room temperature implantation 52 has a high acceleration energy (maximum acceleration energy) within a range of, for example, 1.5 MeV or more and 15 MeV or less as the maximum acceleration energy of ion implantation within at least one step. The dopant for the room temperature implantation 52 is, for example, aluminum (Al). 【0062】 By implanting p-type impurities at room temperature with a high acceleration energy in the room temperature implantation 52, the diffusion depth of the p-type impurities becomes deeper. Therefore, using the resist film 51 as an ion implantation mask, as described above, the thickness T m of the n-type epitaxial layer 22b and the thickness T1 of the resist film 51 are increased, so that the n-type epitaxial layer 22 that becomes the drift layer 2 can be epitaxially grown with a reduced number of steps by increasing the thickness T m of each stage. As a result, compared with the manufacturing method of the reference example (that is, when forming the p-type column region 242 by high temperature implantation: see FIG. 22), the number of repetitions of a series of steps by the multi-stage epitaxial method (that is, stacking of the n-type epitaxial layer, formation of the ion implantation mask, room temperature implantation of p-type impurities, and removal of the ion implantation mask) can be reduced. Then, the resist film 51 is removed. 【0063】 For example, in the manufacturing method of the reference example, due to the characteristics of the SiC material, the main junctions (p ++ type contact region 205, p-type base region 203, p-type column region 242, and p + type regions 231, 232, and the n-type current diffusion region 233, n-type column region 241, n-type buffer region 202a, and n +Large currents (drain-source currents) tend to flow through the body diode (parasitic diode) formed by the drain region 201 and the pn junction. This can lead to current degradation and significant reverse recovery losses during switching. To reduce reverse recovery losses during switching, it is necessary to reduce the amount of charge accumulated in the drift layer 202. 【0064】 On the other hand, in Embodiment 1, by performing ion implantation 52 at room temperature with high acceleration energy to form the p-type column region 42, the number of ion implantation defects in the drift layer 2 increases, and the minority carrier lifetime in the drift layer 2 can be shortened compared to the manufacturing method in the reference example. As a result, the main junction (p ++ Type contact region 5, p-type base region 3, p-type column region 42 and p + n-type regions 31, 32, n-type current diffusion region 33, n-type column region 41, n-type buffer region 2a and n + Because large currents are less likely to flow through the body diode formed by the drain region 1 and the pn junction, current degradation is suppressed, and thus switching losses can be reduced. 【0065】 Next, an n-type epitaxial layer (first conductive epitaxial layer) 22c, which will become the drift layer 2, is epitaxially grown on the n-type epitaxial layer 22b (lamination process: Figure 4). The impurity concentration and thickness T of the n-type epitaxial layer 22c. m These are the same as the n-type epitaxial layer 22b. Next, a resist film is formed on the n-type epitaxial layer 22c (22). The thickness of this resist film is approximately the same as the thickness T1 of the resist film 51 (see Figure 3), for example, about 6.0 μm. After forming the resist film in this way, a series of steps are performed in the same manner as when implanting the resist film at room temperature with high acceleration energy using this resist film as an ion implantation mask to remove the resist film, in the same manner as when implanting the n-type epitaxial layer 22b at room temperature 52 (see Figure 3). 【0066】 Specifically, each time n-type epitaxial layers 22b and 22c, which will become drift layers 2, are epitaxially grown on the n-type epitaxial layer 22a, p-type regions 42a and 42b are selectively formed by photolithography and room-temperature implantation 52, respectively. The p-type regions 42a and 42b of the n-type epitaxial layers 22b and 22c are connected in the depth direction Z, forming p-type column regions 42. The portions of the n-type epitaxial layers 22b and 22c that remain n-type without ion implantation between adjacent p-type column regions 42 become n-type column regions 41, and a parallel pn layer 43 consisting of n-type column regions 41 and p-type column regions 42 is formed (first step: Figure 5). 【0067】 The conditions for room-temperature injection 52 into each n-type epitaxial layer 22b and 22c are the same. The impurity concentration and width of the p-type regions 42a and 42b are set according to the charge amount of the portion that becomes the n-type column region 41 of the n-type epitaxial layers 22b and 22c. Thickness T of the parallel pn layer 43 sj This represents the total thickness of the two n-type epitaxial layers 22b and 22c, which is approximately 5 μm (= 2.5 μm × 2). Note that the thickness T of the n-type epitaxial layer 22b is considered to account for variations in the thickness of the epitaxial layer during epitaxial growth. m The thickness of the n-type epitaxial layer 22b is set to approximately 2.25 μm to 2.45 μm, so that the p-type regions 42a and 42b facing each other in the depth direction Z are joined more reliably. m The parameters may be adjusted. By forming the p-type column region 42 by injection at room temperature 52, the number of stages required to epitaxially grow the n-type epitaxial layer 22 in multiple stages is reduced compared to the manufacturing method in the reference example. 【0068】 Next, the thickness of the n-type epitaxial layer 22 is further increased by epitaxial growth. Then, photolithography and ion implantation under predetermined conditions are repeated multiple times to increase the thickness of the n-type epitaxial layer 22, and p + Type regions 31, 32 and n-type current diffusion region 33 are selectively formed, respectively. + The type region 32 is formed by a multi-stage epitaxial method, with the lower part (n +(Part on the drain region 1 side) 32a and upper part (n + The n-type current diffusion region 33 is formed in two stages, with the source region 4 (part 32b) being the other part. The n-type current diffusion region 33 is formed in two stages, the lower part 33a and the upper part 33b, by a multi-stage epitaxial method. 【0069】 Next, a p-type epitaxial layer 23, which will become the p-type base region 3, is epitaxially grown on the n-type epitaxial layer 22 (second step). Through these steps, n + A semiconductor substrate (semiconductor wafer) 20 is fabricated (manufactured) by sequentially epitaxially growing epitaxial layers 22 and 23 on the front surface of a mold starting substrate 21. The thickness T is measured from the top surface of the parallel pn layer 43 to the front surface of the semiconductor substrate 20. st (See Figure 1) is, for example, about 2.45 μm. Next, a trench gate structure, an interlayer insulating film 9, and a source electrode 11 are formed on the front side of the semiconductor substrate 20 by a general method (third and fourth steps), and a drain electrode 12 is formed on the back side of the semiconductor substrate 20 (fifth step), thereby completing the silicon carbide semiconductor device 10 shown in Figure 1. 【0070】 For the manufacturing process of the UMOSFET structure formed on top of the parallel pn layer 43, see, for example, International Publication No. 2017 / 064949. Note that in steps 3 and 4, as shown in Figure 1, p + type area 31,32,n + Type source area 4, p ++ When forming the type contact region 5 by ion implantation, substrate heating to approximately 500°C is used. These regions are made, for example, 4 × 10⁻¹⁶ in size to reduce resistance. 19 / cm 3 This is because if a dose is selected that results in an impurity concentration exceeding a certain level, and ion implantation with this dose is performed at room temperature, the crystal will be severely damaged, leading to increased resistance. 【0071】 As described above, according to Embodiment 1, when forming a parallel pn layer using a multi-stage epitaxial method, the p-type column region is formed by implanting p-type impurities at room temperature with high acceleration energy. Since the diffusion depth of p-type impurities is increased by implanting p-type impurities at room temperature with high acceleration energy, the thickness of each stage of the n-type epitaxial layer, which becomes the drift layer, can be increased, and epitaxial growth can be performed with fewer stages. For example, a parallel pn layer that was conventionally formed with a total of 64 stages by 8 stages of multi-stage implantation and 8 layers of epitaxial growth can be formed with a total of 26 stages by 13 stages of multi-stage implantation and 2 layers of epitaxial growth. As a result, the number of repetitions of the series of processes in the multi-stage epitaxial method can be reduced, the manufacturing process is simplified, the lead time is shortened, and costs can be reduced. 【0072】 Furthermore, according to Embodiment 1, by forming a p-type column region by implanting p-type impurities at room temperature with high acceleration energy, the number of ion implantation defects in the drift layer increases, thereby shortening the minority carrier lifetime in the drift layer. As a result, large currents are less likely to flow through the body diode formed at the main junction (pn junction), and current degradation is suppressed, thus reducing switching losses. 【0073】 (Details of Embodiment 2) The method for manufacturing a silicon carbide semiconductor device according to Embodiment 2 is described below. Figures 6 to 10 are cross-sectional views showing the silicon carbide semiconductor device during the manufacturing process according to Embodiment 2. The silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device according to Embodiment 2 is the same as that of Embodiment 1 (see Figure 1). The difference between the method for manufacturing a silicon carbide semiconductor device according to Embodiment 2 and the method for manufacturing a silicon carbide semiconductor device 10 according to Embodiment 1 (see Figures 2 to 5) is that not only the p-type column region 42, but also the n-type buffer region 2a and the n-type column region 41 are formed by room temperature injection 62, 64, and 66 at high acceleration energy. 【0074】 Specifically, in Embodiment 2, n+ On the front surface of the starting substrate 21, the n-type buffer region 2a of the drift layer 2 is n - An epitaxial layer 61(22) of type n is epitaxially grown. The thickness of the epitaxial layer 61 is equal to the thickness T of the n-type buffer region 2a. buf It is the same as n during epitaxial growth. - The impurity concentration in the type 10 epitaxial layer 61 is lower than the design value for the impurity concentration in the n-type buffer region 2a, for example, 8.5 × 10⁻⁶. 15 / cm 3 This is the extent of the problem. Next, the impurity concentration in the epitaxial layer 61 is increased by injecting n-type impurities (first conductivity type impurities) at room temperature 62 to reach a predetermined impurity concentration in the n-type buffer region 2a, i.e., the design value for the impurity concentration in the n-type buffer region 2a (Figure 6). 【0075】 This room-temperature implantation 62 is performed as a multi-stage implantation, and the impurity concentration profile of the epitaxial layer 61 is made into, for example, a box profile shape. For example, if the thickness of the epitaxial layer 61 is about 4.4 μm, the room-temperature implantation 62 is performed with an acceleration energy in the range of, for example, 120 keV to 15850 keV when the dopant is phosphorus (P). The room-temperature implantation 62 is performed with an acceleration energy in the range of, for example, 60 keV to 8360 keV when the dopant is nitrogen (N). The room-temperature implantation 62 is performed with a maximum acceleration energy of, for example, 1.5 MeV to 16 MeV when ion implanting phosphorus (maximum acceleration energy), and 1.0 MeV to 9.0 MeV when ion implanting nitrogen (maximum acceleration energy). Furthermore, the room-temperature implantation 62 may be a multi-stage implantation including ion implantation of phosphorus and ion implantation of nitrogen. However, from a safety perspective, when nitrogen implantation is performed... 14 N- 12 It is better to limit the acceleration energy to a level that does not exceed the Coulomb barrier against the activation of C nuclei, thereby creating conditions within a range that prevents radiation activation. 【0076】 Next, on top of the n-type epitaxial layer 22a, the drift layer 2 is formed n -An epitaxial layer of type 63 (first conductive type epitaxial layer) 63 is epitaxially grown (first step: Figure 7). n during epitaxial growth - The impurity concentration in the n-type epitaxial layer 63 is lower than the design value for the impurity concentration in the n-type column region 41. - The impurity concentration of the epitaxial layer 63 of type n during epitaxial growth is - The impurity concentration is approximately the same as that of the n-type epitaxial layer 61. The thickness of the epitaxial layer 63 is the same as the thickness T of the n-type epitaxial layer 22b (see Figure 2) in Embodiment 1. m This is the same as above. Next, the impurity concentration in the epitaxial layer 63 is increased by implanting n-type impurities at room temperature (second ion implantation) 64 to a predetermined impurity concentration in the n-type column region 41, i.e., the design value for the impurity concentration in the n-type column region 41 (second implantation step: Figure 8). 【0077】 This room-temperature implantation 64 is performed as a multi-stage implantation to create a box profile shape for the impurity concentration profile of the epitaxial layer 63. For example, if the thickness of the epitaxial layer 63 is about 2.5 μm, the room-temperature implantation 64 is performed with an acceleration energy in the range of approximately 120 keV to 6850 keV when the dopant is phosphorus. The room-temperature implantation 64 is performed with an acceleration energy in the range of approximately 60 keV to 4300 keV when the dopant is nitrogen. The room-temperature implantation 64 is performed with a maximum acceleration energy of at least one step of high acceleration energy (maximum acceleration energy) in the range of approximately 1.5 MeV to 7.0 MeV when ion implanting phosphorus, and high acceleration energy (maximum acceleration energy) in the range of approximately 1.0 MeV to 4.3 MeV when ion implanting nitrogen. The room-temperature implantation 64 may also be a multi-stage implantation including ion implantation of phosphorus and ion implantation of nitrogen. The safety considerations for room temperature injection 64, including nitrogen injection, are the same as for room temperature injection 62. 【0078】 Next, similar to Embodiment 1, a p-type region 42a, which will become the p-type column region 42, is formed on the surface region of the n-type epitaxial layer 22b (corresponding to the n-type epitaxial layer 63 after room temperature implantation 62) by photolithography and room temperature implantation 52 of p-type impurities at high acceleration energy (masking step and first implantation step). Then, the resist film 51 used as an ion implantation mask for the formation of the p-type region 42a is removed (see Figure 3). The conditions for this resist film 51 and room temperature implantation 52 are the same as in Embodiment 1. 【0079】 Next, on top of the n-type epitaxial layer 22b, the drift layer 2 is n - An epitaxial layer of type 65 (first conductive type epitaxial layer) 65 is epitaxially grown (first step: Figure 9). n during epitaxial growth - The impurity concentration of the epitaxial layer 65 of type n during epitaxial growth is - The impurity concentration is approximately the same as that of the n-type epitaxial layer 63. The thickness of the epitaxial layer 65 is the same as the thickness T of the n-type epitaxial layer 22c (see Figure 4) in Embodiment 1. m This is the same as before. Next, the impurity concentration in the epitaxial layer 65 is increased by room temperature implantation of n-type impurities at high acceleration energy (second ion implantation) 66 to achieve a predetermined impurity concentration in the n-type column region 41 (second implantation step: Figure 10). The conditions for room temperature implantation 66 are the same as for room temperature implantation 64. 【0080】 Next, similar to Embodiment 1, a p-type region 42b, which will become the p-type column region 42, is formed on the surface region of the n-type epitaxial layer 22c (corresponding to the n-type epitaxial layer 65 after room temperature implantation 66) by photolithography and room temperature implantation 52 of p-type impurities at high acceleration energy (masking step and first implantation step). Then, the resist film 51 used as an ion implantation mask for the formation of the p-type region 42b is removed (see Figure 3). The conditions for this resist film 51 and room temperature implantation 52 are the same as in Embodiment 1. 【0081】 As a result, similar to Embodiment 1, the p-type regions 42a and 42b of the n-type epitaxial layers 22b and 22c are connected in the depth direction Z, thereby forming a p-type column region 42. The portion that remains n-type between adjacent p-type column regions 42 of the n-type epitaxial layers 22b and 22c becomes an n-type column region 41, and a parallel pn layer 43 consisting of n-type column regions 41 and p-type column regions 42 is formed. Subsequently, similar to Embodiment 1, p + By sequentially carrying out the steps from the process of forming the n-type regions 31, 32 and the n-type current diffusion region 33, the silicon carbide semiconductor device 10 shown in Figure 1 is completed. The impurity concentration in the n-type column region 41 is, for example, 1.0 × 10⁻⁶. 15 / cm 3 The above 1.0 × 10 17 / cm 3 Approximately the following, preferably 5.0 × 10 15 / cm 3 The above 1.0 × 10 17 / cm 3 The impurity concentration in the p-type column region 42 is, for example, 1.0 × 10⁻⁶. 16 / cm 3 The above 1.0 × 10 18 / cm 3 The following extent, preferably 1.0 × 10 16 / cm 3 The above 5.0 × 10 17 / cm 3 It is approximately as follows. 【0082】 As described above, according to Embodiment 2, the same effects as in Embodiment 1 can be obtained even when both the n-type column region and the p-type column region are formed by room temperature injection at high acceleration energy. 【0083】 (Verification 1) First, in Verification 1, we verified the selection of mask materials used for high-energy ion implantation. Figure 11 is a characteristic diagram showing the simulation results of the relationship between the average range of p-type impurities ion-implanted into the ion implantation mask, which is the implantation target, and the acceleration energy during ion implantation. The "SRIM-2013" software was used for the simulation. Figure 11 shows the simulation results of the relationship between the average range of p-type impurities ion-implanted into the ion implantation mask and the acceleration energy of the ion implantation, with various acceleration energies changed. 【0084】 Aluminum (Al) was used as the p-type dopant for ion implantation into the ion implantation mask. Two samples were used as ion implantation masks: an oxide film (SiO2 film) deposited by CVD and a commonly available resist film. The film density of the SiO2 film was set to 2.26 g / cm³ as a simulation parameter. 3 The resist film density is 1.21 g / cm³. 3 The settings were adjusted accordingly. The film densities of these samples are measured values ​​obtained by XRR (X-Ray Reflectivity). 【0085】 Figure 12 is a schematic diagram illustrating the simulation results of the concentration distribution of p-type impurities ion-implanted into the SiO2 film, which is the implantation target. Figure 12 shows the simulation results of the spread of p-type impurities ion-implanted from a predetermined point (1 point) 73 on the surface (ion implantation surface) of the SiO2 film 72. In Figure 12, the area 74 where there are many p-type impurities is indicated by hatching, and p-type impurities that have spread outside of this area 74 are omitted from the illustration. 【0086】 The extent of p-type impurities can be estimated using scanning capacitance microscopy (SCM), scanning nonlinear dielectric microscopy (SNDM), scanning microwave microscopy (SMM), etc. (the same applies to Figure 13, which will be discussed later). 【0087】 The horizontal axis of Figure 12 represents the depth [μm] from the ion implantation surface (surface of the SiO2 film 72). The vertical axis of Figure 12 represents the length of lateral diffusion of p-type impurities from a predetermined point 73 (=0 [μm]) on the ion implantation surface in a direction parallel to the ion implantation surface (lateral direction). Figures 12(a) and (b) show the cases where the acceleration energy for ion implantation into the SiO2 film 72 is 700 keV and 1.88 MeV, respectively. 【0088】 Al was used as the p-type dopant (p-type impurity) to be ion-implanted into the SiO2 film 72. The SiO2 film 72 was assumed to have a thickness d1 of 2 μm and to be deposited on a SiC substrate 71 by CVD. The film density of the SiO2 film 72 is the same as that of the SiO2 film used as a sample in the simulation in Figure 11. The SiO2 film used as a sample in the simulations in Figures 11 and 12 corresponds to the oxide film used as an ion implantation mask in the reference manufacturing method (formation of p-type column region 242: see Figure 22). 【0089】 As shown in Figure 11, the SiO2 film demonstrated a higher effectiveness as an ion implantation mask (effectiveness in shielding ion-implanted p-type impurities) compared to the resist film under the same ion implantation conditions. Figure 11 indicates that, for example, with an acceleration energy of 5 MeV, the SiO2 film requires a thickness of approximately 3.6 μm or more, and the resist film requires a thickness of approximately 4.8 μm or more. However, when depositing an SiO2 film on a SiC substrate using plasma CVD, significant warping of the SiC substrate becomes apparent when the SiO2 film thickness reaches approximately 3 μm, thus limiting the practical thickness of the SiO2 film mask to approximately 2 μm. 【0090】 In the simulation shown in Figure 12, the SiO2 film 72 is limited to a thickness of 2 μm. In ion implantation with an acceleration energy of 700 keV, ions do not reach the SiC substrate 71 (Figure 12(a)), and the SiO2 film 72 functions as a mask. However, in ion implantation with an acceleration energy of 1.88 MeV, ions do reach the SiC substrate 71 (Figure 12(b)), and the SiO2 film 72 does not function as a mask. From the viewpoint of preventing warping of the SiC substrate 71, it can be seen that the SiO2 film 72 is not suitable as a mask for high-energy ion implantation in the MeV class. 【0091】 In contrast, as described later in Verification 3, the resist film does not cause warping of the SiC substrate even with a film thickness of about 7 μm, making it suitable as a mask for high-acceleration energy ion implantation. Although the resist film is inferior to the SiO2 film in terms of heat resistance, no problems occur in room temperature implantation. In other words, the inventors have found that the combination of a resist film and room temperature implantation is a solution that satisfies the requirements of masking implanted ions, preventing warping of the SiC substrate, and mitigating the heat resistance of the mask material in high-energy ion implantation. 【0092】 (Verification 2) Next, in Verification 2, the masking effect of the resist film was further verified. Figure 13 is a schematic diagram illustrating the simulation results of the concentration distribution of p-type impurities ion-implanted into the resist film, which is the implantation target. Figure 13 shows the simulation results of the spread of p-type impurities ion-implanted from a predetermined point (1 point) 82 on the surface (ion implantation surface) of the resist film 81. In Figure 13, the area 83 where there are many p-type impurities is indicated by hatching, and p-type impurities that have spread to locations outside of this area 83 are omitted from the illustration. 【0093】 The horizontal axis of Figure 13 represents the depth [μm] from the ion implantation surface (surface of the resist film 81). The vertical axis of Figure 13 represents the length of lateral diffusion of p-type impurities from a predetermined point 82 (=0 [μm]) on the ion implantation surface in a direction parallel to the ion implantation surface (lateral direction). Figures 13(a) to (c) show the cases where the ion implantation acceleration energy is 1.88 MeV, 5 MeV, and 14.5 MeV, respectively. 【0094】 Al was used as the p-type dopant (p-type impurity) during ion implantation. The resist film 81 was assumed to be deposited on a SiC substrate (not shown) with a thickness of 10 μm and d11. Since the resist film 81 is formed by coating, the lead time can be shorter than that of a 2 μm SiO2 film, even with a thickness of 10 μm. The film density of the resist film 81 is the same as that of the resist film used as a sample in the simulation in Figure 11. The resist film 81 used as a sample in the simulation in Figure 13 corresponds to the resist film 51 used as an ion implantation mask in the silicon carbide semiconductor device manufacturing method according to Embodiment 1 (Figures 2-5). 【0095】 When the thickness d11 of the resist film 81 was 10 μm, the average ranges of p-type impurities ion-implanted into the resist film 81 with acceleration energies of 1.88 MeV, 5 MeV, and 14.5 MeV were 2.75 μm, 4.81 μm, and 8.72 μm, respectively (Figure 13 (a) to (c)). It was confirmed that the ion-implanted p-type impurities stopped at a predetermined depth d12 within the resist film 81 and did not penetrate the resist film 81. 【0096】 Furthermore, the results shown in Figure 13(b) confirm that a thickness d11 of the resist film 81 of approximately 3 μm is sufficient to adequately shield p-type impurities implanted with an acceleration energy of 1.88 MeV, and that a thickness d11 of the resist film 81 of approximately 6 μm is sufficient to adequately shield p-type impurities implanted with an acceleration energy of 5 MeV. 【0097】 (Verification 3) Furthermore, in Verification 3, the pattern formation of a thick resist film was verified by fabricating a sample. Figure 14 is a cross-sectional SEM (Scanning Electron Microscope) image of a resist film on a 4-inch SiC substrate, where a trench pattern for an SJ structure was processed (transferred and developed) using photolithography after coating and baking. A commercially available resist manufactured by Tokyo Ohka Kogyo Co., Ltd. was used as the resist. The set value for the thickness d21 of the resist film 92 was 6.8 μm, and a resist film 92 of 6.7 μm was formed. This thickness of 6.7 μm of the resist film 92 is sufficient to serve as a mask for high-energy ion implantation of about 5 MeV, as shown in the results of Figure 13(c) above. Even with the formation of a thick resist film 92 of approximately 6.7 μm, there was almost no warping of the SiC substrate 91, and the photolithography process could be performed. 【0098】 The results shown in Figure 14 confirm that a good trench mask pattern can be formed even when the thickness d21 (=6.7 μm) of the resist film 92 is increased. In Figure 14, the opening 92a of the resist film 92 had a maximum width of 1.41 μm and a minimum width of 1.35 μm. 【0099】 (Verification 4) In Verification 4, the difference between ion implantation at room temperature and 500°C was verified in the distribution of ion implantation defects in the parallel pn layer 43 by actually fabricating samples. Figure 15(a) is a reference example of Figure 22, and is a schematic cross-sectional image of the SEM of a cross-section of an SJ-MOSFET (hereinafter referred to as "reference example") containing a parallel pn layer implanted under substrate heating conditions of approximately 500°C. Figure 15(b) is a schematic cross-sectional image of the SEM of a cross-section of an SJ-MOSFET (hereinafter referred to as "example") containing a parallel pn layer formed by changing the ion implantation conditions for forming the structure of the reference example to room temperature implantation. Figures 16 and 19 are schematic cross-sectional images (hereinafter referred to as CL images) of the cross-section of Figure 15 obtained by cathodoluminescence (CL) analysis. Figures 17 and 18 are characteristic diagrams showing the CL emission intensity distribution of SiC (4H-SiC single crystal) in the CL image of Figure 16. In Figures 15(b), 16(b), and 19(b), in order to distinguish the parallel pn layer of the example by room temperature injection from the parallel pn layer of the reference example by high-temperature injection, reference numerals 41 to 43 are used for the n-type column region, p-type column region, and parallel pn layer of the example, respectively, similar to Embodiment 1 which uses room temperature injection. Figures 20 and 21 are characteristic diagrams showing the CL emission intensity distribution of SiC (4H-SiC single crystal) in the CL image of Figure 19. Figure 23 is a table showing the normalized CL emission intensity data of the peak value near the center of the p-column (p-type column region 42, 242) and the bottom value near the center of the n-column (n-type column region 41, 241) of the normalized CL emission intensity waveform in Figures 18 and 21, as well as the calculated results of their average values ​​(peak average (B), bottom average (A)) and ratio (B / A). 【0100】 Figures 15, 16, and 19(a) and (b) show reference examples (500°C implantation) and examples (room temperature implantation), respectively. Figures 15, 16, and 19 show SEM images, CL emission images of SiC at the integrated intensity of the L1 line from wavelengths 422 nm to 428 nm, and CL emission images of SiC at the integrated intensity of a broad-band peak width (wavelength) on the longer wavelength side from 468 nm to 570 nm, respectively. Note that the emission intensity of the CL images in Figures 16 and 19 is the relative integrated intensity normalized by dividing by the integrated intensity of CL emission due to SiC band edge emission. SiC band edge emission is free exciton emission with a center wavelength around the observation wavelength of 385 nm as determined by CL analysis. In Figures 16 and 19, the CL emission intensity of SiC band edge emission is the value obtained by integrating the emission intensity of free exciton emission in the range of observation wavelengths from 375 nm to 396 nm. 【0101】 Figure 17(a) shows the CL emission intensity distribution of SiC at the cutting lines A1-A1' and B1-B1' in Figure 16. Figure 17(b) shows the CL emission intensity distribution of SiC at the cutting lines A2-A2' and B2-B2' in Figure 16. Figure 18 shows the CL emission intensity distribution of SiC at the cutting lines A3-A3' and B3-B3' in Figure 16. Figure 20(a) shows the CL emission intensity distribution of SiC at the cutting lines A1-A1' and B1-B1' in Figure 19. Figure 20(b) shows the CL emission intensity distribution of SiC at the cutting lines A2-A2' and B2-B2' in Figure 19. Figure 21 shows the CL emission intensity distribution of SiC at the cutting lines A3-A3' and B3-B3' in Figure 19. 【0102】 Cutting lines A1-A1' and B1-B1' pass through n-type column regions 41 and 241, respectively, as shown in Figure 15, and are perpendicular to the front surface of semiconductor substrates 20 and 220 (indicated as "n-column longitudinal direction" in Figures 17(a) and 20(a)). Cutting lines A2-A2' and B2-B2' pass through p-type column regions 42 and 242, respectively, and are perpendicular to the front surface of semiconductor substrates 20 and 220 (indicated as "p-column longitudinal direction" in Figures 17(b) and 20(b)). The cutting lines A3-A3' and B3-B3' are parallel to the first direction X (the direction in which the n-type column regions 41,241 and p-type column regions 42,242 are adjacent to each other) and pass through positions corresponding to the n-type column regions 41,241 and p-type column regions 42,242 in Figure 15 (indicated as "transverse cross-section of pn column" in Figures 18 and 121). 【0103】 L1-line emission of SiC is a peak (mountain) originating from the L1 line, occurring around the observation wavelength of 425 nm as determined by CL analysis. The L1 line is a C antisite defect (point defect) where a Si atom is replaced by a C atom, or a Si antisite defect (point defect) where a C atom is replaced by a Si atom. The CL emission intensity of the L1-line emission of SiC is the sum of the CL emission intensities of SiC in the observation wavelength range from 422 nm to 428 nm. The vertical axis in Figures 17 and 18 represents the relative intensity (normalized CL emission intensity) normalized by dividing the CL emission intensity of the L1-line emission of SiC by the CL emission intensity of the band-edge emission of SiC. The horizontal axis in Figure 17 is the depth (vertical position) from the top surface (=0 μm) of the semiconductor substrate 20, 220. The horizontal axis in Figure 18 is the distance (lateral position) from a predetermined position (=0 μm) in the first direction X. 【0104】 Broad-peak emission (CL emission) on the long-wavelength side of SiC refers to a peak that occurs around the observation wavelength of 480 nm as determined by CL analysis, and has a broader peak width than band-edge emission or L1-line emission. The detailed attribution of broad emission is unclear, but it is thought to be CL emission related to impurities. The CL emission intensity of broad-peak emission on the long-wavelength side of SiC is the sum of the CL emission intensities of SiC in the observation wavelength range from 468 nm to 570 nm. The vertical axis in Figures 20 and 21 represents the relative intensity (normalized CL emission intensity) normalized by dividing the CL emission intensity of broad-peak emission on the long-wavelength side of SiC by the CL emission intensity of band-edge emission of SiC. The horizontal axis in Figure 20 represents the depth (vertical position) from the top surface (=0 μm) of the semiconductor substrate 20, 220. The horizontal axis in Figure 21 represents the distance (lateral position) from a predetermined position (=0 μm) in the first direction X. 【0105】 Figure 23 shows the normalized CL emission intensities of the peak values ​​(peaks 1, 2, and 3 in Figures 18 and 21) near the center of the first direction X for three adjacent p-type column regions 42, and the average value of the normalized CL emission intensities of these peak values ​​(peak average (B)) for all p-type column regions 42. It is presumed that the peak average for all p-type column regions 42 will be approximately the same as this peak average. It also shows the normalized CL emission intensities of the bottom values ​​(bottoms 1, 2, and 3 in Figures 18 and 21) near the center of the first direction X for two adjacent n-type column regions 41, and the average value of the normalized CL emission intensities of these bottom values ​​(bottom average (A) which is the average of bottoms 1 and 2). It is presumed that the peak average for all n-type column regions 41 will be approximately the same as this peak average. 【0106】 For a reference example (Al ion implantation conditions for p-column: implanted at 500°C), the normalized CL emission intensities of the peaks (peaks 1', 2', and 3' in Figures 18 and 21) near the center of the first direction X for three adjacent p-type column regions 242, along with their average peak values ​​(B). The normalized CL emission intensities of the bottoms (bottoms 1', 2', and 3' in Figures 18 and 21) near the center of the first direction X for two adjacent n-type column regions 241, along with their average bottom values ​​(A). The "Ratio (B / A)" in Figure 23 is the ratio of the average bottom value to the average peak value (=average peak value / average bottom value). 【0107】 The embodiment is an SJ-MOSFET equipped with a parallel pn layer having the same structure as the parallel pn layer 243 of the silicon carbide semiconductor device 210 (see Figure 22) of the reference example described above. The parallel pn layer was formed by a multi-stage epitaxial method using room temperature implantation according to the manufacturing method of the reference example described above. The set temperature for room temperature implantation was 24°C. The reference example is an SJ-MOSFET equipped with the structure of the silicon carbide semiconductor device 210 shown in Figure 22, and the parallel pn layer 243 was formed by a multi-stage epitaxial method using high temperature (set temperature 500°C) implantation. The set temperature for high temperature implantation was 500°C. The conditions for the embodiment, other than the ion implantation temperature during the formation of the p-type column region 42, are the same as those of the reference example. 【0108】 The results shown in Figures 16 and 19 indicate that, compared to the reference example (Figures 16(b) and 19(b)), the CL emission intensity in the n-type column region 41 is higher in both the L1-line emission of SiC and the broad-peak emission of SiC on the long-wavelength side (the n-type column region 41 in the CL image is brighter). This confirms that many ion implantation defects diffuse into the n-type column region 41 and remain even after activation annealing. Therefore, it is presumed that forming the parallel pn layer 43 by room temperature implantation, as in the example, results in more ion implantation defects remaining in the n-type column region 41 and a shorter minority carrier lifetime compared to forming the parallel pn layer 243 by high-temperature implantation, as in the reference example. 【0109】 From the results shown in Figure 17 and Figure 20, it was confirmed that, compared to the reference example, the CL emission intensity of SiC was greater in both the n-type column region 41 and the p-type column region 42, for both the L1-line emission of SiC and the emission of SiC with a broad peak width on the long-wavelength side. In particular, the increase in the CL emission intensity of SiC in the n-type column region 41 was significant. The CL emission intensity of SiC in the p-type column regions 42 and 42 was almost the same in the example and the reference example. As shown in Figures 18 and 21, forming the parallel pn layer 43 by room temperature injection as in the example results in a smaller ratio (B / A) of the average peak values ​​(B) when the average bottom value (A) is set to 1.0 for the SiC CL emission intensity near the center of the first direction X in the n-type column region 41 and the SiC CL emission intensity near the center of the first direction X in the p-type column region 42, normalized by the SiC band edge emission intensity. For example, as shown in Figure 23, the ratio decreases from approximately 1.64 to approximately 1.28 for L1 line emission and from approximately 1.63 to approximately 1.27 for broad emission (i.e., to less than 1.3). 【0110】 4 x 10 19 / cm 3 p ++ When forming type contact regions 5 etc. by ion implantation, there is a concern that high doses of ion implantation may damage the crystal and increase its resistance. Therefore, p ++ When forming a low-resistance region to create a low-resistance contact with a metal electrode, such as in contact region 5, ion implantation is performed at a high temperature of about 500°C. On the other hand, 1.0 × 10 15 / cm 3 The above 1.0 × 10 17 / cm 3 Approximately the following, preferably 5.0 × 10 15 / cm 3 The above 1.0 × 10 17 / cm 3 The n-type column region 41 and 1.0 × 10⁻¹⁰ have impurity concentrations of the following magnitude. 16 / cm 3 The above 1.0 × 10 18 / cm 3The following extent, preferably 1.0 × 10 16 / cm 3 The above 5.0 × 10 17 / cm 3 In low-dose ion implantation, which forms a p-type column region 42 with impurity concentrations below the specified level, room-temperature implantation was adopted because increased crystal damage does not affect the resistance value. By adopting room-temperature implantation, a resist film can be used as the ion implantation mask, resulting in a shorter lead time compared to when an SiO2 film is used as the ion implantation mask. 【0111】 Furthermore, from the results of Verification 2, it was confirmed that by using a resist film with a thickness of 3 μm or more as a mask, it is possible to shield p-type impurities implanted with an acceleration energy of 1.88 MeV. Since ion implantation is performed with a high acceleration energy on the order of MeV, the depth of the region formed by ion implantation can also be increased. In addition, from the results of Verification 3, it was confirmed that a pattern of a predetermined width can be processed by using a resist film with a thickness of 6.7 μm as a mask. Furthermore, from the results of Verification 4, it was confirmed that n-type column regions 41 and p-type column regions 42 can be formed by room temperature implantation using a resist film with a thickness of 3 μm or more as a mask. Therefore, in the formation of the parallel pn layer 43 of Embodiment 1, the number of stages of multi-stage implantation can be reduced, and both heating and cooling processes can be eliminated, thus significantly shortening the manufacturing lead time of the silicon carbide semiconductor device 10. 【0112】 In summary, this disclosure is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of this disclosure. For example, this disclosure is applicable not only to MOSFETs, but also to silicon carbide semiconductor devices with an SJ structure in which the drift layer is a parallel pn layer, such as IGBTs and diodes. Furthermore, although Figure 1 of Embodiment 1 uses a semi-SJ structure as an example, the bulk-type drift layer (n-type buffer region 2a) can be omitted and the parallel pn layer 43 can be made n +A full SJ structure may be provided on the mold starting substrate 21. [Industrial applicability] 【0113】 As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to this disclosure are useful for power semiconductor devices used in power converters, power supply devices for various industrial machines, and the like. [Explanation of Symbols] 【0114】 1,201 n + Type drain region 2,202 drift layers 2a,202a n-type buffer area 3,203 p-type base region 4,204 n + Type source area 5,205 p ++ Type Contact Area 6,206 Trench 7,207 Gate insulating film 8,208 gate gate 9,209 Interlayer insulating film 9a,209a Contact Hole 10,210 Silicon Carbide Semiconductor Devices 11,211 source electrodes 12,212 drain electrodes 20,220 semiconductor substrates 21,221 n + Mold starting substrate 22,22a~22c,222,222a~222h n-type epitaxial layer 23,223 p-type epitaxial layer 31,32,231,232 p + type area 33,233 n-type current diffusion region 41,241 n-type column regions 42,242 p-type column regions 43,243 parallel pn layers 51. Resist film (resist mask) 51a Aperture of the resist film 52,62,64,66 Room temperature injection 61, 63, 65 n-type (n during epitaxial growth) - Type) Epitaxial layer T1: Thickness of the resist film T buf ,T202 n-type buffer area thickness T m ,T205 n-type epitaxial layer thickness T sj Thickness of parallel pn layer in T200 T st ,T204 Thickness from the top surface of the parallel pn layer to the front surface of the semiconductor substrate T sub ,T201 n + Thickness of the starting substrate for the mold X First direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z-direction (depth)

Claims

[Claim 1] A parallel pn layer is provided inside a semiconductor substrate made of silicon carbide, in which a first conductivity type region and a second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate. A first semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the parallel pn layer, A device structure provided between the first main surface of the semiconductor substrate and the parallel pn layer, through which current flows via the pn junction between the first semiconductor region and the first conductivity type region, A first electrode electrically connected to the first semiconductor region, A second electrode provided on the second main surface of the semiconductor substrate, Equipped with, Silicon carbide L obtained using the cathodoluminescence method 1 The integrated intensity of the cathodoluminescence emission of the line, or the L 1 The L at a longer wavelength than the cathodoluminescence emission of the line 1 A silicon carbide semiconductor device characterized in that, with respect to the integrated intensity of silicon carbide cathodoluminescence emission in a band with a broader peak width than linear cathodoluminescence emission, when A is the average value of the bottom values ​​of the silicon carbide cathodoluminescence emission intensity near the center of the first direction in the first conductivity type region normalized by the integrated intensity of the band edge emission of silicon carbide, and B is the average value of the peak values ​​of the silicon carbide cathodoluminescence emission intensity near the center of the first direction in the second conductivity type region obtained using the cathodoluminescence method, the ratio of B to A (B / A) is less than 1.

3. [Claim 2] The silicon carbide semiconductor device according to claim 1, characterized in that the second conductivity type region of the parallel pn layer has a periodic distribution in the depth direction of the impurity concentration that determines its conductivity type. [Claim 3] A method for manufacturing a silicon carbide semiconductor device comprising a parallel pn layer in which a first conductivity type region and a second conductivity type region are alternately and repeatedly arranged in a direction parallel to the first main surface of a silicon carbide semiconductor substrate, A first step involves forming the parallel pn layer on a starting substrate made of silicon carbide, which forms the second main surface of the semiconductor substrate, using a multi-stage epitaxial method. A second step involves forming a first semiconductor region of a second conductivity type on the parallel pn layer, A third step is to form an element structure through which current flows via a pn junction between the first semiconductor region and the first conductivity type region, A fourth step of forming a first electrode electrically connected to the first semiconductor region, A fifth step involves forming a second electrode on the second main surface of the semiconductor substrate, Includes, The first step is, A lamination process for epitaxially growing a first conductive epitaxial layer made of silicon carbide, A method for manufacturing a silicon carbide semiconductor device, comprising: a first implantation step of selectively forming a diffusion region that becomes the second conductivity region in the first conductivity type epitaxial layer by first ion implantation of a second conductivity type impurity at room temperature using a resist film with a thickness of 3.0 μm or more as a mask, and leaving the portion of the first conductivity type epitaxial layer excluding the diffusion region as the first conductivity type region. [Claim 4] The first step includes a mask step of forming the resist film on the first conductivity type epitaxial layer, with an opening in the portion facing the formation region of the second conductivity type region. In the lamination process, the thickness of the first conductive epitaxial layer is set to 1 μm or more. In the masking process, the thickness of the resist film is set to 3.0 μm or more and 20.0 μm or less. The method for manufacturing a silicon carbide semiconductor device according to claim 3, characterized in that the first implantation step is performed using the resist film as a mask and with an acceleration energy of 1.5 MeV to 15 MeV. [Claim 5] The method for manufacturing a silicon carbide semiconductor device according to claim 3, characterized in that the second conductive impurity of the first ion implantation in the first implantation step is aluminum. [Claim 6] In the lamination process, the first conductivity type epitaxial layer having an impurity concentration lower than the design value for the impurity concentration of the first conductivity type region is epitaxially grown. The method for manufacturing a silicon carbide semiconductor device according to claim 3, characterized in that the first step further includes a second implantation step of increasing the impurity concentration of the first conductivity type epitaxial layer to the design value by implanting a first conductivity type impurity into the second ion at room temperature. [Claim 7] The method for manufacturing a silicon carbide semiconductor device according to claim 6, characterized in that the second ion implantation step is performed at room temperature without heating the semiconductor substrate.

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