Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can suppress an increase in on-resistance. [Solution] p-type base region 3 and n - Between the drift region 2 and the bottom surface of trench 6, n + A first PB region 21 for electric field relaxation is provided at a deep position on the drain region 1 side, facing the bottom surface of the trench 6. The first PB region 21 is n + It has a cross-sectional shape that narrows in width toward the drain region 1 side. Directly below the first PB region 21, n - Within the drift region 2, the tail region 21a of the first PB region 21 is formed. Ion implantation defects are introduced into the tail region 21a. The distribution shape of the tail region 21a and the ion implantation defects introduced into the tail region 21a is the most n + The maximum width W2 is in the source area, and the maximum width W2 is narrower than the maximum width W1 of the first PB area 21, and n + It has a cross-sectional shape that narrows in width towards the drain region 1 side.

Description

[Technical Field] 【0001】 This disclosure relates to silicon carbide semiconductor devices and methods for manufacturing silicon carbide semiconductor devices. [Background technology] 【0002】 Patent documents 1 to 4 below describe a SiC-MOSFET in which the pn junction between the p-type base region and the drift layer is partially brought closer to the drain side in a predetermined shape. [Prior art documents] [Patent Documents] 【0003】 [Patent Document 1] Japanese Patent Publication No. 2019-165165 [Patent Document 2] Japanese Patent Publication No. 2006-303272 [Patent Document 3] Japanese Patent Publication No. 2021-002597 [Patent Document 4] Japanese Patent Publication No. 2021-072360 [Overview of the project] [Problems that the invention aims to solve] 【0004】 In the above-mentioned Patent Documents 1-4, ion implantation is performed on the surface region of the epitaxial layer which becomes the drift layer. + When a type region is formed, the ion-implanted p-type dopants and ion-implanted defects spread isotropically in a direction parallel to the surface of the semiconductor substrate. This can lead to a decrease in the effective n-type impurity concentration in the drift region, a decrease in the majority carrier concentration, and a narrowing of the effective width of the JFET region, potentially increasing the on-resistance. 【0005】 This disclosure aims to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can suppress an increase in on-resistance. [Means for solving the problem] 【0006】 A silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A first region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first region, forming a pn junction with the first region. A third region of a first conductivity type is selectively provided between the second region and the first main surface. A trench gate structure is provided on the first main surface side. The trench gate structure has a trench that terminates on the second main surface side of the semiconductor substrate, beyond the pn junction. 【0007】 A local region of a second conductivity type is selectively provided on the second main surface side of the trench bottom surface, separated from the second region. The local region faces the trench bottom surface and is in contact with the first region. Within the first region, a fourth region of a first conductivity type having a lower carrier concentration than the first region is selectively provided in contact with the bottom surface of the local region. The first electrode is connected to the third region. The second electrode is provided on the second main surface. The maximum horizontal width of the fourth region is narrower than the maximum horizontal width of the local region. The fourth region has a cross-sectional shape that narrows toward the second main surface side. 【0008】 A method for manufacturing a silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A first masking step is performed to form a first mask on the first surface of a first conductivity type silicon carbide layer, with an opening in the portion corresponding to the formation area of ​​one half of a second conductivity type local region. Using the first mask, a first implantation step is performed to selectively form one half of the local region on the surface region of the first conductivity type silicon carbide layer by implanting a second conductivity type impurity at a predetermined first implantation angle that is acute with respect to the central axis perpendicular to the first surface of the local region using the first mask. A first removal step is performed to remove the first mask. A second masking step is performed to form a second mask on the first surface of the first conductivity type silicon carbide layer, with an opening in the portion corresponding to the formation area of ​​the other half of the local region. 【0009】 Using the second mask, a second implantation step is performed in which a second impurity of the second conductivity type is implanted at a predetermined second implantation angle that is acute with respect to the central axis perpendicular to the first surface of the local region, thereby selectively forming the other half of the local region on the surface region of the silicon carbide layer of the first conductivity type. A second removal step is performed in which the second mask is removed. A first forming step is performed in which a region of the second conductivity type is formed on the silicon carbide layer of the first conductivity type. A second forming step is performed in which a trench gate structure is formed from the region of the second conductivity type to the silicon carbide layer of the first conductivity type. The first implantation angle and the second implantation angle are angles that are symmetric with respect to the central axis perpendicular to the first surface of the local region. [Effects of the Invention] 【0010】 The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to this disclosure have the effect of suppressing an increase in on-resistance. [Brief explanation of the drawing] 【0011】 [Figure 1] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 2] This is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device according to the embodiment. [Figure 3] This is a cross-sectional view (part 1) showing the state of a silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 4] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device in the process of being manufactured according to the embodiment. [Figure 5] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device as an example. [Figure 6] This is a cross-sectional view showing the manufacturing process of a silicon carbide semiconductor device as a reference example. [Figure 7] Figure 5 is a schematic cross-sectional view showing the CL image of the tail region of the first PB region. [Figure 8] This is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device as a reference example. [Modes for carrying out the invention] 【0012】 <Summary of the embodiments of this disclosure> (1) A silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A first region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first region, forming a pn junction with the first region. A third region of a first conductivity type is selectively provided between the second region and the first main surface. A trench gate structure is provided on the first main surface side. The trench gate structure has a trench that terminates on the second main surface side of the semiconductor substrate, beyond the pn junction. 【0013】 A local region of a second conductivity type is selectively provided on the second main surface side of the trench bottom surface, separated from the second region. The local region faces the trench bottom surface and is in contact with the first region. Within the first region, a fourth region of a first conductivity type having a lower carrier concentration than the first region is selectively provided in contact with the bottom surface of the local region. The first electrode is connected to the third region. The second electrode is provided on the second main surface. The maximum horizontal width of the fourth region is narrower than the maximum horizontal width of the local region. The fourth region has a cross-sectional shape that narrows toward the second main surface side. 【0014】 According to the above disclosure, the decrease in the effective first conductivity type impurity concentration in the JFET region between adjacent local regions of the second conductivity type can be suppressed, thereby suppressing the increase in JFET resistance. Furthermore, the increase in the majority carrier concentration in the JFET region can be suppressed. As a result, the increase in on-resistance can be suppressed. 【0015】 (2) In addition, in the silicon carbide semiconductor device described herein, the local region may be composed of multiple stages that narrow in the depth direction, as described in (1) above. 【0016】 According to the disclosure described above, a localized region can be formed by performing multi-stage ion implantation under optimal ion implantation conditions as appropriate, depending on the ion implantation depth. 【0017】 (3) In addition, in the silicon carbide semiconductor device according to this disclosure, in (1) or (2) described above, the trench extends linearly in a direction parallel to the first main surface, and the local region and the second region may be selectively connected in the longitudinal direction of the trench. 【0018】 According to the disclosure described above, the electric field applied to the gate insulating film at the bottom of the trench can be relaxed. 【0019】 (4) A method for manufacturing a silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A first masking step is performed to form a first mask on the first surface of a silicon carbide layer of a first conductivity type, with an opening in the portion corresponding to the formation area of ​​one half of a local region of a second conductivity type. Using the first mask, a first implantation step is performed to selectively form one half of the local region on the surface region of the silicon carbide layer of the first conductivity type by implanting a second conductivity type impurity at a predetermined first implantation angle that is acute with respect to the central axis perpendicular to the first surface of the local region. A first removal step is performed to remove the first mask. A second masking step is performed to form a second mask on the first surface of the silicon carbide layer of the first conductivity type, with an opening in the portion corresponding to the formation area of ​​the other half of the local region. 【0020】 Using the second mask, a second implantation step is performed in which a second impurity of the second conductivity type is implanted at a predetermined second implantation angle that is acute with respect to the central axis perpendicular to the first surface of the local region, thereby selectively forming the other half of the local region on the surface region of the silicon carbide layer of the first conductivity type. A second removal step is performed in which the second mask is removed. A first forming step is performed in which a region of the second conductivity type is formed on the silicon carbide layer of the first conductivity type. A second forming step is performed in which a trench gate structure is formed from the region of the second conductivity type to the silicon carbide layer of the first conductivity type. The first implantation angle and the second implantation angle are angles that are symmetric with respect to the central axis perpendicular to the first surface of the local region. 【0021】 According to the disclosure described above, the second conductivity type impurity and ion implantation defects can be distributed towards the center of the local region. 【0022】 <Knowledge forming the basis of this disclosure> First, the structure of the reference example silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device will be described. Figure 5 is a cross-sectional view showing the structure of the reference example silicon carbide semiconductor device. Figure 6 is a cross-sectional view showing the silicon carbide semiconductor device during the manufacturing process of the reference example silicon carbide semiconductor device. Figure 7 is a schematic cross-sectional view showing the CL image of the tail region of the first PB region in Figure 5. In Figures 6 and 7, each part is illustrated in a different ratio than in Figure 5. The hatched area in Figure 7 is a cross-section image (hereinafter referred to as the CL image) obtained by analysis using the cathodeluminescence (CL) method. The CL method is a technique used to analyze the crystal structure, impurities, and defect state near the irradiation surface of an object from the emission intensity distribution of photons emitted by irradiating the irradiation surface of the object with accelerated electrons. 【0023】 The silicon carbide semiconductor device 110 shown in Figure 5 is a vertical SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field-effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) with a trench gate structure on the front side (main surface on the epitaxial layer 133 side) of a semiconductor substrate 130 using silicon carbide (SiC) as the semiconductor material. The semiconductor substrate 130 is made of n + n - The semiconductor substrate 130 is formed by sequentially epitaxially growing epitaxial layers 132 and 133, which will become the p-type drift region 102 and the p-type base region 103, respectively. The entire front surface of the semiconductor substrate 130 is covered with the interlayer insulating film 109. + The starting substrate 131 is n + This is the type drain region 101. 【0024】 The trench gate structure is a p-type base region 103, n +p-type source region 104 ++ It is composed of a p-type contact region 105, a trench 106, a gate insulating film 107, and a gate electrode 108. Between the p-type base region 103 and the n - -type drift region 102, p + -type base regions (hereinafter referred to as the first and second PB regions) 121 and 122 and an n-type current diffusion region (hereinafter referred to as the CS region) 120 are selectively provided. The first PB region 121 and the CS region 123 (120) are diffusion regions formed by ion implantation inside the n - -type epitaxial layer 132a. The second PB region 122 and the CS region 124 (120) are diffusion regions formed by ion implantation inside the n - -type epitaxial layer 132b. The portion of the n - -type epitaxial layer 132 excluding the first and second PB regions 121 and 122 and the CS region 120 is the n - -type drift region 102. 【0025】 The first PB region 121 is selectively provided at positions separated from each other at a position facing the bottom surface of the trench 106 in the depth direction Z, at a position deeper on the n + -type drain region 101 side than the bottom surface of the trench 106, and between adjacent trenches 106. The first PB region 121 directly below the trench 106 (on the n + -type drain region 101 side) is electrically connected to the p-type base region 103 at a portion not shown. The second PB region 122 is provided between the p-type base region 103 and the first PB region 121 between adjacent trenches 106 and is adjacent to these regions in the depth direction Z. The first PB region 121 has a high impurity concentration and is often formed by ion implantation 142 (see FIG. 6) with high acceleration energy. Therefore, a tail region 121a due to the ion implantation 142 for forming the first PB region 121 is formed inside the n - -type drift region 102 directly below the first PB region 121. 【0026】 The tail region 121a is the n of the acceptor (p-type dopant) concentration profile in the depth direction Z of the first PB region 121. - This is a portion with a tail extending from the inside of the drift region 102 and the CS region 123. The width of the tail region 121a is wider than the width of the first PB region 121 in the direction parallel to the front surface of the semiconductor substrate 130. The tail region 121a extends from the side and bottom (n) of the first PB region 121 within the epitaxial layer 132a. + It surrounds the side of the drain region 101. - In the type drift region 102 and CS region 123, the n-type carrier concentration is relatively low in the tail region 121a, resulting in a low effective n-type impurity concentration. The portion between adjacent first PB regions 121 and the portion between adjacent second PB regions 122 and the trench 106 constitutes the CS region 120 (123, 124). The CS region 120 is the path of the current that flows when the silicon carbide semiconductor device 110 is turned on. 【0027】 The operation of the silicon carbide semiconductor device 110 will be described. When a positive voltage is applied to the drain electrode 112 relative to the source electrode 111, and a voltage less than the gate threshold voltage is applied to the gate electrode 108, the silicon carbide semiconductor device 110 remains in the off state by being reverse-biased. When a reverse bias is applied, the silicon carbide semiconductor device 110 has a first PB region 121 and n - By extending the depletion layer from the pn junction with the drift region 102 and pinching off the JFET (Junction FET) regions between adjacent first PB regions 121, leakage current is reduced and breakdown voltage is maintained. By narrowing the spacing between adjacent first PB regions 121 (width of the JFET region), the corners of the first PB region 121 and the n region that is narrower than the first PB region 121 are reduced. + Because the electric field strength in the source region 104 side decreases, the breakdown voltage is improved. 【0028】 On the other hand, when a positive voltage is applied to the drain electrode 112 relative to the source electrode 111, and a voltage greater than or equal to the gate threshold voltage is applied to the gate electrode 108, a channel (n-type inversion layer) is formed in the portion of the p-type base region 103 along the trench 106. As a result, n + From the source region 104 to the channel, the CS region 120 and n - n through the drift region 102 + A flow of electron carriers (drain current) Id is generated toward the drain region 101, and the silicon carbide semiconductor device 110 turns on. If the spacing between adjacent first PB regions 121 is narrow, the path for the electron current Id becomes narrower, and the on-resistance increases. In other words, there is a trade-off relationship between breakdown voltage and on-resistance, which is appropriately set by the spacing between adjacent first PB regions 121. 【0029】 As shown in Figure 6, the width of the JFET region is determined by the opening pattern of the ion implantation mask 141 used in ion implantation 142 to form the first PB region 121. The first PB region 121 is formed by ion implantation 142 from a direction perpendicular to or slightly inclined to the surface of the epitaxial layer 132a. The p-type impurities (p-type dopants) implanted by ion implantation 142 spread isotropically in the vertical direction (depth direction Z) and the horizontal direction (direction parallel to the front surface of the semiconductor substrate 130) due to scattering within the crystal. Not only p-type dopants, but also ion implantation defects (crystal defects) spread horizontally in the same way as p-type dopants. As a result, a tail region 121a is formed with a width W102 that is wider than the opening width (width of the opening 141a) W101 of the ion implantation mask 141, surrounding the sides and bottom surface of the first PB region 121. 【0030】 Effective width W in the JFET region JFET1 This becomes the width between adjacent tail regions 121a, and the design width of the JFET region (the distance between adjacent first PB regions 121) W JFET2 Because it becomes narrower, the JFET resistance increases. Also, when the silicon carbide semiconductor device 110 is turned on, the electron current Id is affected by the electric field from the back side of the semiconductor substrate 130 in the CS region 123 and n -The drift region 102 is traversed by the shortest distance (i.e., the first PB region 121 and the CS region 123 and n - The current Id flows along the pn junction with the drift region 102 (perpendicular to the back surface of the semiconductor substrate 30). Therefore, the electron current Id does not flow in the relatively low-resistance center of the CS region 123, but rather in the high-resistance n surrounding the side of the first PB region 121. -- n + As the current moves towards the drain region 101, the on-resistance increases. 【0031】 Furthermore, when aluminum (Al), which acts as an acceptor, is ion-implanted into the n-type region, Al compensates for the majority carrier (electron) concentration by acting as an electron-capturing trap and recombination center, thus lowering the majority carrier concentration in the n-type region and increasing the on-resistance. Figure 7 shows the first PB region 121 and n in the cross-sectional view of Figure 5. - The CL image near the pn junction with the type drift region 102 is superimposed on the cross-sectional view. As shown in Figure 7, the CL image near the first PB region 121 of the silicon carbide semiconductor device 110 confirms that the first PB region 121 and n - The cross-sectional shape is wider laterally than that of the pn junction with the p-type drift region 102, and the CL emission intensity from ion implantation defects is large (the CL image is bright). Therefore, it was confirmed that ion implantation defects, along with the p-type dopant, diffuse and spread out in a large amount laterally, forming a tail region 121a. As a countermeasure to avoid the adverse effects of such a tail region 121a, the design width W of the JFET region was used. JFET2 One example is widening the design width W of the JFET region. JFET2 Widening the area reduces the pressure resistance. 【0032】 Therefore, the inventors have made the following inference. Figure 8 is a cross-sectional view showing another example of the structure of the silicon carbide semiconductor device of the reference example. The silicon carbide semiconductor device 150 of the reference example shown in Figure 8 differs from the silicon carbide semiconductor device 110 of the reference example shown in Figure 5 in the arrangement of the first PB region 121. In Figure 8, the first PB region 121 is provided away from the trench 106 and facing the bottom corner of the trench 106 (the boundary between the side and the bottom surface) in the depth direction Z. When the JFET region is placed directly below the trench 106 by two first PB regions 121 as shown in Figure 8, the design width W of the JFET region differs from that of the silicon carbide semiconductor device 110 of the reference example shown in Figure 5. JFET2 Even if the values ​​are the same, the electron current Id flows more easily through the side and bottom of the trench 106, and through the relatively low-resistance center of the CS region 123. + Because it moves towards the drain region 101, the increase in on-resistance can be suppressed. In the silicon carbide semiconductor device 150 of the reference example shown in Figure 8, the effective width W of the JFET region JFET1 This represents the spacing between adjacent first PB regions 121, and the design width W of the JFET region. JFET2 This is essentially the same as the previous example. From this, it can be inferred that the path of the electron current Id changes depending on the arrangement of the first PB region 121 and the tail region 121a directly beneath it. This disclosure is based on this finding. 【0033】 One of the problems to be solved in this embodiment is to suppress the increase in on-resistance. 【0034】 Preferred embodiments of the silicon carbide semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. 【0035】 (Details of the embodiment) The silicon carbide semiconductor device according to Embodiment 1, which solves the above-mentioned problems, is described below. Figure 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 2 is a cross-sectional view showing another example of the structure of the silicon carbide semiconductor device according to Embodiment 1. The silicon carbide semiconductor device 10 according to Embodiment 1 shown in Figure 1 is a vertical SiC-MOSFET having a trench gate structure on the front side of a semiconductor substrate (semiconductor chip) 30 using silicon carbide (SiC) as the semiconductor material, and has a first PB region (local region of the second conductivity type) 21 near the bottom surface of the trench 6. 【0036】 The semiconductor substrate 30 uses silicon carbide as the semiconductor material n + n - The semiconductor substrate 30 is constructed by sequentially stacking epitaxial layers 32 and 33, which form a p-type drift region (first region of the first conductivity type) 2 and a p-type base region (second region of the second conductivity type) 3. The first main surface on the epitaxial layer 33 side of the semiconductor substrate 30 is the front surface, and n + The second main surface (n) on the mold starting substrate 31 side + The back surface of the starting substrate 31 is used as the back surface. The crystal structure of the semiconductor substrate 30 may be, for example, a four-layer periodic hexagonal silicon carbide crystal (4H-SiC). + The starting substrate 31 is n + This is type drain region 1. 【0037】 The trench gate structure has a p-type base region 3, n + Type source region (third region of the first conductivity type) 4, p ++ It consists of a type contact region (not shown), a trench 6, a gate insulating film 7, and a gate electrode 8, and is located in the active region. The active region is the region through which the main current (drift current) flows when the SiC-MOSFET (silicon carbide semiconductor device 10) is in the ON state. Multiple cells (functional units of the device) of the same structure as the SiC-MOSFET are arranged adjacent to each other in the active region. Figure 1 shows two cells of the SiC-MOSFET. 【0038】 The active region is surrounded by an edge termination region (not shown). The edge termination region is the area between the active region and the edge (chip edge) of the semiconductor substrate 30, and has the function of mitigating the electric field on the front side of the semiconductor substrate 30 and maintaining the breakdown voltage. A breakdown voltage structure such as a field limiting ring (FLR), a junction termination extension (JTE) structure, or a guard ring is placed in the edge termination region. 【0039】 The p-type base region 3 is connected to the front surface of the semiconductor substrate 30 in the active region. - It is provided between the type drift region 2. + Type source region 4 and p ++ The type contact region is a diffusion region formed by ion implantation inside the p-type epitaxial layer 33. + Type source region 4 and p ++ The portion excluding the type contact region is the p-type base region 3. + Type source region 4 and p ++ The type contact regions are selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 3. 【0040】 n + Type source region 4 and p ++ The type contact region is in contact with the p-type base region 3 and is in contact with the source electrode (first electrode) 11 on the front surface of the semiconductor substrate 30. + The type source region 4 is adjacent to the trench 6. For example, n + Type source area 4 and p ++ The contact regions are arranged alternately and repeatedly in the longitudinal direction of the trench 6. ++ The contact area may be adjacent to the trench 6. ++ A type contact region does not need to be provided. In this case, p ++ Instead of the type contact region, the p-type base region 3 extends to the front surface of the semiconductor substrate 30. The p-type base region 3 and n +The thicknesses of each part of the mold source region 4 are, for example, approximately 0.85 μm and 0.45 μm, respectively. 【0041】 Trench 6 is located from the front surface of the semiconductor substrate 30 to n + The trenches penetrate the p-type source region 4 and the p-type base region 3 and terminate inside the CS region 20, which will be described later. The trenches 6 extend linearly in a direction parallel to the front surface of the semiconductor substrate 30 (the longitudinal direction of the trench), and multiple trenches are arranged adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 30 and perpendicular to the longitudinal direction of the trench (the short direction of the trench), forming a stripe shape. Inside the trenches 6, a gate electrode 8 is provided via a gate insulating film 7. 【0042】 p-type base region 3 and n - Between type drift region 2, p + A type base region (hereinafter referred to as the first PB region) 21 and an n-type current diffusion region (hereinafter referred to as the CS region) 20 are selectively provided. The first PB region 21 is n - This is a diffusion region formed by ion implantation inside the epitaxial layer 32a(32) of type n. - This is a diffusion region formed by ion implantation inside the epitaxial layer 32 of type n. - The portion of the epitaxial layer 32 of type n, excluding the first PB region 21 and the CS region 20 - This is type drift region 2. 【0043】 The first PB region 21 is n greater than the bottom surface of the trench 6. +The first PB region 21 is located deep within the drain region 1, separate from the p-type base region 3, and faces the bottom surface of the trench 6 in the depth direction Z. The first PB region 21 may be in contact with the bottom surface of the trench 6 or may be separated from the bottom surface of the trench 6. The width of the first PB region 21 (width in the short direction (horizontal direction) of the trench) is greater than or equal to the width of the trench 6. The first PB region 21 extends linearly in the longitudinal direction of the trench with a length approximately equal to the longitudinal length of the trench 6. The first PB region 21 is selectively electrically connected to the p-type base region 3 at multiple locations in the longitudinal direction of the trench 6, for example, in parts not shown. 【0044】 The first PB region 21 is formed by ion implantation 52, 54 (see Figures 3 and 4 described later) in multiple stages (multiple times) with different acceleration energies and implantation angles (tilt angles θ1, θ2). The first PB region 21 is the most n + The first stage 41 on the source region 4 side has the widest cross-sectional shape. This makes it possible to suppress the lateral spread (in the direction parallel to the front surface of the semiconductor substrate 30) of p-type dopants and ion implantation defects during ion implantation 52, 54 to form the first PB region 21. 【0045】 The first PB region 21 is n + The cross-sectional shape is such that it narrows (tapers) toward the drain region 1, for example, a roughly trapezoidal (tapered) or roughly triangular shape. Multiple stages (four stages in Figure 1) of ion implantation are formed at different widths and depths, and adjacent to each other in the depth direction Z. + The first PB region 21 may be composed of type regions (hereinafter referred to as the 1st to 4th stages) 41 to 44. + The side surface of the first PB region 21 may be stepped due to the steps created by the first to fourth stages (multiple stages narrowing in the depth direction Z) 41 to 44, which become narrower the closer they are to the type drain region 1. 【0046】 Furthermore, among the first to fourth stages 41 to 44 that constitute the first PB region 21, the most n +The width of the first stage 41 on the type source area 4 side (width in the short direction of the trench) should be wider than the widths of the other second to fourth stages 42 to 44 (width in the short direction of the trench), and the widths of the other second to fourth stages 42 to 44 can be set as appropriate. The maximum width W2 of the tail area (fourth area) 21a of the first PB area 21, which will be described later, should be at least the nth of the first PB area 21. + The width of the first stage 41 on the type source area 4 side should be narrower than the width of the first PB area 21 (the maximum width W1). The widths of the other second to fourth stages 42 to 44 should be narrower than the width of the first stage 41, and they may all be approximately the same. 【0047】 The acceptor concentration in the first PB region 21 may be a box profile, or it may reach its maximum value (peak concentration) at a predetermined depth position (peak position), and from that peak position n + Type source area 4 side and n + It may also be a Gaussian distribution that decreases at a predetermined gradient as it moves toward the drain region 1 side. - Within the drift region 2, a tail region 21a of the first PB region 21 is formed adjacent to the first PB region 21 in the depth direction Z. In addition, p-type dopants are introduced into the tail region 21a by ion implantation 52,54 to form the first PB region 21, and ion implantation defects are also introduced by the same ion implantation 52,54. 【0048】 The tail region 21a is formed by ion implantation 52, 54 of p-type dopant to form the first PB region 21, and the acceptor concentration profile in the depth direction Z is n in the depth direction Z. - This is the part with a tail drawn inside the drift region 2. The tail region 21a and the distribution shape of the ion implantation defects introduced into the tail region 21a are the most n + The maximum width W2 is on the source area 4 side, and the maximum width W2 is narrower than the maximum width W1 of the first PB area 21, n + The width (width in the trench's short direction (horizontal direction)) narrows towards the drain region 1 side (taperses), resulting in a cross-sectional shape that is approximately trapezoidal or triangular. The acceptor concentration and ion implantation defect density in the tail region 21a are n +The temperature decreases as you move towards the drain region 1 side. 【0049】 The tail region 21a is ion-implanted 52, 54 to form the first PB region 21. - The p-type dopant introduced into the drift region 2 (epitaxial layer 32) causes n - The n-type carrier concentration is lower in the part of the type drift region 2 excluding the tail region 21a. The first PB region 21, as described above, is electrically connected to the source electrode 11 via the p-type base region 3 in a part not shown in the figure and is fixed at the source potential. It has the function of depleting when the SiC-MOSFET is off (by depleting the CS region 20, or both) and mitigating the electric field applied to the gate insulating film 7 at the bottom of the trench 6. 【0050】 The area between adjacent first PB regions 21 is a CS region 23, and the area between adjacent trenches 6 is a CS region 24. CS regions 23 and 24 are connected in the depth direction Z to form a CS region 20. CS region 20 consists of a p-type base region 3 and n - It is located between the drift region 2 and adjacent first PB regions 21 and adjacent trenches 6, and is provided adjacent to these regions. The CS region 20 is n + On the drain region 1 side, at approximately the same depth as the first PB region 21, or at a position n further than the first PB region 21. + It is terminated on the drain region 1 side. 【0051】 The CS region 20 is a so-called current spreading layer (CSL). The CS region 20 is the path for the main current (electron current Id) that flows when the silicon carbide semiconductor device 10 is turned on. The thickness of the CS regions 23 and 24 is, for example, about 0.5 μm. The CS region 20 is not required. In this case, n - The type drift region 2 extends from adjacent first PB regions 21 to adjacent trenches 6 to the p-type base region 3, and from the p-type base region 3 to the first PB region 21 in the short direction of trench 6 to trench 6. 【0052】 n - The n-type drift region 2 is provided between the first PB region 21 and the CS region 20 and in contact with these regions and the n + -type starting substrate 31. The interlayer insulating film 9 is provided on the entire front surface of the semiconductor substrate 30 and covers the gate electrode 8. The source electrode 11 makes ohmic contact with the front surface of the semiconductor substrate 30 through the contact hole of the interlayer insulating film 9 and is electrically connected to the p-type base region 3, the n + -type source region 4, and the p ++ -type contact region. A drain electrode (second electrode) 12 is provided on the entire back surface of the semiconductor substrate 30 (the back surface of the n + -type starting substrate 31). The drain electrode 12 makes ohmic contact with the back surface of the semiconductor substrate 30 and is electrically connected to the n + -type drain region 1. 【0053】 As shown in FIG. 2, the first PB region 21 may be selectively provided between adjacent trenches 6, apart from the trenches 6 and the first PB region 21 on the side of the n + -type drain region 1 directly thereunder. Between adjacent trenches 6, a p + -type base region (hereinafter referred to as the second PB region) 22 is provided between the first PB region 21 and the p-type base region 3. The second PB region 22 electrically connects the first PB region 21 directly under the trench 6 to the p-type base region 3 at a portion not shown in the figure. The second PB region 22 is a diffusion region formed by ion implantation inside the n - -type epitaxial layer 32. 【0054】 In this case, a tail region 21a is also formed directly under the first PB region 21 between adjacent trenches 6, similar to the first PB region 21 directly under the trench 6. The portion of the n - -type epitaxial layer 32 excluding the first and second PB regions 21 and 22 and the CS region 20 is n -This is drift region 2. The area between the adjacent second PB region 22 and the trench 6 is CS region 24. CS region 20 is provided adjacent to these regions, between adjacent first PB regions 21 and between adjacent second PB region 22 and the trench 6. ++ The contact area 5 is away from the trench 6, n + It is adjacent to type source area 4. 【0055】 A method for manufacturing the silicon carbide semiconductor device 10 (see Figure 1) according to the embodiment will be described. Figures 3 and 4 are cross-sectional views showing the state during the manufacturing of the silicon carbide semiconductor device according to the embodiment. First, as shown in Figure 3, n made of silicon carbide + On the front surface of the starting substrate (starting wafer) 31, n - n is in the drift region 2. - A type 32a (first conductive silicon carbide layer) 32a (32) is epitaxially grown. The thickness of the epitaxial layer 32a is n - This is the sum of the thickness of the type drift region 2 and the thickness of the first PB region 21. 【0056】 Next, an ion implantation mask (first mask) 51 is formed on the surface (first surface) of the epitaxial layer 32a, with an opening corresponding to the formation area of ​​one half (left half in Figure 3) of the first PB region 21 (first mask step). Then, using the ion implantation mask 51, p-type impurities (p-type dopants (second conductivity type impurities)) such as aluminum (Al) are implanted from an oblique direction toward the center of the formation area of ​​the first PB region 21 at a predetermined implantation angle (tilt angle (first implantation angle)) θ1 that is acute with respect to the central axis (dotted vertical line in Figures 3 and 4) perpendicular to the front surface of the semiconductor substrate 30 in the formation area of ​​the first PB region 21 (first ion implantation) 52, thereby forming one half of the first stage 41, which will become the first PB region 21, on the surface area of ​​the epitaxial layer 32a (first implantation step). Finally, the ion implantation mask 51 is removed (first removal step). 【0057】 Next, as shown in Figure 4, an ion implantation mask (second mask) 53 is formed on the surface of the epitaxial layer 32a, with an opening corresponding to the formation area of ​​the other half (right half in Figure 4) of the first PB region 21 (second mask step). Next, using the ion implantation mask 53, p-type impurities such as Al (p-type dopants (second conductivity type impurities)) are ion implanted (second ion implantation) 54 from an oblique direction toward the center of the formation area of ​​the first PB region 21 at a predetermined tilt angle (second implantation angle) θ2 that is acute with respect to the central axis perpendicular to the front surface of the semiconductor substrate 30 in the formation area of ​​the first PB region 21, thereby forming the other half of the first stage 41 on the surface area of ​​the epitaxial layer 32a (second implantation step). Then, the ion implantation mask 53 is removed (second removal step). 【0058】 The tilt angles θ1 of ion implantation 52 and θ2 of ion implantation 54 are symmetrical with respect to the central axis perpendicular to the front surface of the semiconductor substrate 30 in the formation region of the first PB region 21. The two halves of the first stage 41 are connected to form the first stage 41. Then, the ion implantation mask 53 is removed. By performing ion implantation 52 and 54 at predetermined tilt angles θ1 and θ2, the p-type dopants and ion implantation defects can be distributed towards the center of the first PB region 21. This suppresses the lateral spread of p-type dopants and ion implantation defects toward the outer edges of the first PB region 21. 【0059】 The first PB region 21 is formed by performing the above-described series of steps—formation of the ion implantation mask 51, ion implantation 52 at a predetermined tilt angle θ1, removal of the ion implantation mask 51, formation of the ion implantation mask 53, ion implantation 54 at a predetermined tilt angle θ2, and removal of the ion implantation mask 53—for the number of stages of the first PB region 21 (stages 1 to 4, 41 to 44). The formation order of stages 1 to 4, 41 to 44 can be changed as appropriate. The tilt angles θ1 and θ2 of ion implantation 52 and 54 are, for example, greater than 0 degrees and less than or equal to 30 degrees. 【0060】 The higher the acceleration energy used for ion implantation 52 and 54, the greater the tilt angles θ1 and θ2 of the ion implanters 52 and 54 should be. The larger the tilt angles θ1 and θ2, the more likely the p-type dopants and ion implantation defects are to be distributed towards the center of the formation region of the first PB region 21. Each half of the first PB region 21 has a cross-sectional shape that is tilted towards the center, with approximately the same width as the openings 51a and 53a of the ion implantation masks 51 and 53, respectively. This suppresses the lateral spread of p-type dopants and ion implantation defects. 【0061】 The two halves of the first PB region 21 may overlap at their centers. In this case, the impurity concentration at the center of the first PB region 21 is relatively high, for example, about twice as high as the impurity concentration in the part away from the center of the first PB region 21. When the silicon carbide semiconductor device 10 is turned off, the first PB region 21 and n - If the depletion layer extending from the pn junction with the drift region 2 does not reach the bottom of the trench 6, then the two halves of the first PB region 21 may be positioned slightly apart, creating a gap in the center of the first PB region 21. 【0062】 Al is ion-implanted 52,54 into the epitaxial layer 32a beyond the formation region of the first PB region 21, and n - A tail region 21a is formed inside the type drift region 2. As described above, by performing ion implantation 52, 54 at predetermined tilt angles θ1, θ2, the lateral spread of the p-type dopant and ion implantation defects is suppressed, and the tail region 21a is n + From the source area 4 side, n + The cross-sectional shape is roughly triangular, narrowing towards the drain region 1 side. 【0063】 The portion of the epitaxial layer 32a excluding the first PB region 21 and the CS region 23 formed in a later step is n -This becomes the n-type drift region 2. Next, an ion implantation mask (not shown) is formed on the surface of the epitaxial layer 32a, with the entire area corresponding to the active region open. Then, using this ion implantation mask, n-type impurities such as nitrogen (N) are ion implanted to form a CS region 23 (20) over the entire surface area of ​​the epitaxial layer 32a in the active region. The CS region 23 is formed between adjacent first PB regions 21. 【0064】 Next, after removing the ion implantation mask used to form the CS region 23, n - The epitaxial layer 32b(32) of the type is epitaxially grown to increase the thickness of the epitaxial layer 32. Next, a CS region 24(20) is formed in the epitaxial layer 32b. The method for forming the CS region 24 is the same as the method for forming the CS region 23. The CS region 24 penetrates the epitaxial layer 32b in the depth direction Z, reaches and connects with the CS region 23, and covers the first PB region 21. Then, the ion implantation mask is removed. 【0065】 When forming the second PB region 22 (see Figure 2), n - An ion implantation mask is formed on the surface of the epitaxial layer 32b of the type, with an opening corresponding to the formation region of the second PB region 22. P-type impurities can then be ion implanted using this ion implantation mask. The second PB region 22 penetrates the epitaxial layer 32b in the depth direction Z in the portion other than the trench 6 formation region, reaching and connecting with the first PB region 21. In this case, the CS region 24 covers the first PB region 21 in the trench 6 formation region. Then, the ion implantation mask is removed. 【0066】 Next, a p-type epitaxial layer 33, which will become the p-type base region 3, is epitaxially grown on the epitaxial layer 32b (first formation step). This creates n +A semiconductor substrate (semiconductor wafer) 30 is fabricated by sequentially stacking epitaxial layers 32 and 33 on a mold starting substrate 31. Subsequently, a trench gate structure, interlayer insulating film 9, source electrode 11, and drain electrode 12 are formed by a general method (second formation step). Then, the semiconductor substrate 30 is cut (diced) into chip-shaped pieces to complete the silicon carbide semiconductor device 10 shown in Figure 1. 【0067】 The operation of the silicon carbide semiconductor device (SiC-MOSFET) 10 according to Embodiment 1 shown in Figure 1 will be described. When a positive voltage is applied to the drain electrode 12 relative to the source electrode 11, and a voltage greater than or equal to the gate threshold voltage is applied to the gate electrode 8, a channel (n-type inversion layer) is formed in the portion of the p-type base region 3 along the trench 6. As a result, n + From the source region 4 to the channel, CS region 20 and n - n through the drift region 2 + A flow of electron carriers (drain current) Id is generated toward the drain region 1, and the silicon carbide semiconductor device 10 turns on. 【0068】 As described above, the lateral spread of p-type dopants and ion implantation defects was suppressed during the formation of the first PB region 21, resulting in at least the most n + The width of the tail region 21a is narrower than the width of the first stage 41 on the source region 4 side. Since the tail region 21a does not exist in the JFET region, the decrease in the effective n-type carrier concentration of the JFET resistor is suppressed. Effective width W of the JFET region JFET1 The design width W of the JFET region JFET2 Similarly, this becomes the width between the first stages 41 of the adjacent first PB regions 21. 【0069】 Furthermore, the electron current Id is affected by the electric field from the back side of the semiconductor substrate 30 in the CS region 23 and n - Type drift region 2 is traversed by the shortest distance (i.e., the first PB region 21 and CS region 23 and n - Along the pn junction with the drift region 2, the n flows perpendicularly to the back surface of the semiconductor substrate 30. +It proceeds towards the drain region 1. Because the width of the tail region 21a is narrower than the width of the first PB region 21, the electron current Id is in the CS region 23 and n - Even if the electron current Id flows through the drift region 2 along the shortest path, it will not pass through the tail region 21a. 【0070】 On the other hand, when a positive voltage is applied to the drain electrode 12 relative to the source electrode 11, and a voltage less than the gate threshold voltage is applied to the gate electrode 8, the p-type base region 3 and the first PB region 21, and the CS region 20 and n - The silicon carbide semiconductor device 10 remains in the off state when the pn junction of the first PB region 21 (including the tail region 21a) is reverse-biased. - From the pn junction with the drift region 2, the depletion layer extends into the first PB region 21, the CS region 20, or both. 【0071】 By making the p-type impurity concentration in the first PB region 21 sufficiently higher than the n-type impurity concentration in the CS region 23, the first PB region 21 does not become completely depleted even when a high voltage is applied to the drain electrode 12. As a result, a high electric field is not applied to the gate insulating film 7 at the bottom of the trench 6, thus improving the breakdown voltage. In addition, the depletion layer that has spread within the CS region 20 causes the JFET regions between adjacent first PB regions 21 to be pinched off, reducing the leakage current and thus maintaining the breakdown voltage of the silicon carbide semiconductor device 10. 【0072】 The silicon carbide semiconductor device 10 according to Embodiment 1 shown in Figure 2 operates in the same manner as the silicon carbide semiconductor device 10 according to Embodiment 1 shown in Figure 1. By narrowing the width between adjacent trenches 6 and reducing the size of the silicon carbide semiconductor device 10, low on-resistance can be achieved. In the silicon carbide semiconductor device 10 according to Embodiment 1 shown in Figure 1, the first and second PB regions 21 and 22 are not arranged between adjacent trenches 6, making it easier to narrow the width between adjacent trenches 6. 【0073】 As described above, according to Embodiment 1, the lateral spread of p-type dopants and ion implantation defects during ion implantation to form the first PB region is suppressed, and the width of the tail region of the first PB region is at least the nth of the first PB region. + The width is narrower than the source region portion (first stage). Since there is no tail region in the JFET region (CS region) between adjacent first PB regions, the decrease in the effective n-type impurity concentration of the JFET region can be suppressed, and the increase in JFET resistance can be suppressed. This suppresses the increase in on-resistance. The effective width of the JFET region becomes the same as the design width of the JFET region, and is the width between the first stages of adjacent first PB regions. 【0074】 Furthermore, by suppressing the lateral spread of p-type dopants and ion implantation defects during ion implantation to form the first PB region, the amount of p-type dopants and ion implantation defects that act as traps and recombination centers for capturing electrons within the JFET region is reduced. This suppresses the increase in the majority carrier concentration in the JFET region, and thus suppresses the increase in on-resistance. Also, according to Embodiment 1, when the silicon carbide semiconductor device is turned on, the electron current is influenced by the electric field from the back side of the semiconductor substrate, affecting the CS region and n - n flows through the drift region along the shortest distance + Even when moving towards the drain region, the electron current does not flow through the tail region, thus suppressing the increase in on-resistance. 【0075】 In the foregoing, this disclosure is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of this disclosure. Furthermore, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. [Industrial applicability] 【0076】 As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to this disclosure are useful for power semiconductor devices used in power converters, power supply devices for various industrial machines, and the like. [Explanation of Symbols] 【0077】 1,101 n + Type drain region 2,102 n - Type drift region 3,103 p-type base region 4,104 n + Type source area 5,105 p ++ Type Contact Area 6,106 Trench 7,107 Gate Insulator 8,108 Grid gate 9,109 Interlayer insulating film 10,110,150 Silicon Carbide Semiconductor Devices 11,111 source electrodes 12,112 drain electrodes 20,23,24,120,123,124 CS area 21,121 1st PB area 21a,121a Tail region of the first PB region 22,122 2nd PB area 30,130 semiconductor substrates 31,131 n + Mold starting substrate 32, 32a, 32b, 33, 132, 132a, 132b, 133 Epitaxial layer 41-44 Stages in the first PB area 51, 53, 141 Ion implantation mask 51a, 53a, 141a Opening of ion implantation mask 52, 54, 142 Ion implantation W JFET1 Effective width in the JFET region W JFET2 Design width in the JFET domain W1 Maximum width of the first PB area W2 Maximum width of the tail region of the first PB area Z-direction (depth) θ1, θ2 Tilt angles for ion implantation

Claims

[Claim 1] A semiconductor substrate made of silicon carbide, A first region of a first conductivity type provided inside the semiconductor substrate, A second region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first region, and forms a pn junction with the first region, A third region of a first conductivity type is selectively provided between the second region and the first main surface, A trench gate structure having a trench provided on the first main surface side and terminating on the second main surface side of the semiconductor substrate, rather than the pn junction, A local region of second conductivity is selectively provided on the second main surface side of the trench bottom surface, separated from the second region, facing the trench bottom surface and in contact with the first region, A fourth region of a first conductivity type is selectively provided within the first region, in contact with the bottom surface of the local region, and having a carrier concentration lower than that of the first region. The first electrode connected to the third region, The second electrode provided on the second main surface, Equipped with, The maximum horizontal width of the fourth region is narrower than the maximum horizontal width of the local region. The silicon carbide semiconductor device is characterized in that the fourth region has a cross-sectional shape that narrows in width toward the second main surface side. [Claim 2] The silicon carbide semiconductor device according to claim 1, characterized in that the local region is composed of multiple stages that narrow in the depth direction. [Claim 3] The trench extends linearly in a direction parallel to the first main surface, The silicon carbide semiconductor device according to claim 1, characterized in that the local region and the second region are selectively connected in the longitudinal direction of the trench. [Claim 4] A first mask step involves forming a first mask on the first surface of a first-conductivity silicon carbide layer, with an opening in the portion corresponding to the formation area of ​​one half of the localized region of the second conductivity type. A first implantation step in which a second conductivity type impurity is implanted using the first mask at a predetermined first implantation angle that is acute with respect to the central axis perpendicular to the first surface of the local region, thereby selectively forming one half of the local region on the surface region of the first conductivity type silicon carbide layer, A first removal step of removing the first mask, A second mask step is to form a second mask on the first surface of the first conductive silicon carbide layer, with an opening in the portion corresponding to the other half of the formation region of the local area. A second implantation step in which a second conductivity type impurity is implanted using the second mask at a predetermined second implantation angle that is acute with respect to the central axis perpendicular to the first surface of the local region, thereby selectively forming the other half of the local region on the surface region of the silicon carbide layer of the first conductivity type, A second removal step of removing the second mask, A first forming step of forming a region of a second conductivity type on the silicon carbide layer of the first conductivity type, A second forming step of forming a trench gate structure that extends from the region of the second conductivity type to the silicon carbide layer of the first conductivity type, Includes, A method for manufacturing a silicon carbide semiconductor device, characterized in that the first injection angle and the second injection angle are angles that are symmetric with respect to a central axis perpendicular to the first surface of the local region.

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