Hybrid differential amplifier and hybrid differential amplification method

Abstract

This invention provides a hybrid differential amplifier and a hybrid differential amplification method that utilize multi-stage pulse modulation technology. [Solution] The hybrid amplifier according to the present invention includes first to fourth PWM circuits, a first masking frequency multiplier circuit (first processing circuit), a signal determination circuit, a signal selection circuit, and first and second power stage circuits. The first to fourth PWM circuits generate a PWM signal by comparing a triangular wave signal and a filtered signal. The first masking frequency multiplier circuit generates a pulse-width processed signal based on the polarity of the PWM signal and the input signal. The signal determination circuit generates a path selection signal based on the level range of the differential input signal. The signal selection circuit generates a switching control signal according to the selection signal and the pulse-width processed signal. The first and second power stage circuits generate a switching voltage based on the switching control signal and switch the inductor to generate an output signal.

Description

【Technical Field】 【0001】 (Cross - reference to related applications) This invention claims priority to TW113146650 (filed on December 2, 2024, access code: D741) and claims priority to US19 / 032,466 (filed on January 21, 2025, access code: 9618). 【0002】 This invention relates to a hybrid differential amplifier and its method, and more particularly, to a hybrid differential amplifier and a hybrid differential amplification method capable of reducing electromagnetic interference by increasing the pulse width. 【Background Art】 【0003】 Power factor correction (PFC) circuits and switching amplifiers using totem - pole modulation often face problems related to distortion and electromagnetic interference (EMI) near the zero - voltage crossover point. 【0004】 Figure 1 shows a prior - art hybrid differential amplifier. This prior - art hybrid differential amplifier requires an additional low - dropout regulator (LDO) under no - load conditions to reduce electromagnetic interference (EMI). During light - load operation, the pulse width may approach 0% or 100%. If the pulse is not accurately generated, the distortion may increase. To address this problem, very fast rise and fall times are often required during the high - speed driving process. 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0005】 To overcome the above problems, especially the effects of distortion and electromagnetic interference in the zero - voltage crossover region under light - load conditions, the present invention proposes a hybrid differential amplifier and method using multi - stage pulse modulation technology. This approach effectively increases the pulse width, reduces electromagnetic interference, and addresses the drawbacks of the prior art. [Means for solving the problem] 【0006】 From one perspective, the present invention provides a hybrid differential amplifier configured to generate a differential output signal based on a differential input signal to drive a load, wherein the differential input signal includes a first input signal and a second input signal, and the differential output signal includes a first output signal and a second output signal. The hybrid differential amplifier comprises a first PWM circuit, a second PWM circuit, a third PWM circuit, a fourth PWM circuit, a first masking frequency doubler circuit, a signal determination circuit, a signal selection circuit, a first power stage circuit, and a second power stage circuit. The first PWM circuit is configured to generate a first PWM signal by comparing a first triangular wave signal with a first filtered signal, the first filtered signal being related to a first input signal. The second PWM circuit is configured to generate a second PWM signal by comparing the first triangular wave signal with a second filtered signal, the second filtered signal being related to the second input signal. The third PWM circuit is configured to generate a third PWM signal by comparing the second triangular wave signal with the first filtered signal. The fourth PWM circuit is configured to generate a fourth PWM signal by comparing the second triangular wave signal with the second filtered signal. The first masking frequency doubling circuit is configured to generate a first pulse width masking frequency doubling signal and a second pulse width masking frequency doubling signal based on a first PWM signal and a second PWM signal. When the first input signal is positive, the first pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the first PWM signal; when the first input signal is negative, the first pulse width masking frequency doubling signal is 0. When the second input signal is positive, the second pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the second PWM signal; when the second input signal is negative, the second pulse width masking frequency doubling signal is 0. The signal determination circuit is configured to generate a path selection signal based on the range in which the levels of the differential input signals exist. The signal selection circuit is configured to generate a first switching control signal and a second switching control signal in response to a path selection signal, based on a first pulse width masking frequency doubling signal, a second pulse width masking frequency doubling signal, a third PWM signal, and a fourth PWM signal. The first power stage circuit includes a plurality of first transistors coupled to a first switching node, and is configured to generate a first switching voltage at the first switching node based on a first switching control signal, thereby switching a first inductor coupled to the first switching node to generate a first output signal. The second power stage circuit includes a second set of transistors and is configured to generate a second switching voltage at a second switching node based on a second switching control signal, thereby generating a second output signal. If the path selection signal indicates that the differential input signal is outside the light load range, a first switching control signal is selected as relating to a first pulse width masking frequency doubling signal having a first PWM characteristic, and controls the first switching voltage at the first switching node to toggle between the first supply voltage and ground potential. A second switching control signal is selected as approximating the fundamental frequency, and controls the second switching voltage at the second switching node to toggle between the first supply voltage and ground potential, and the differential input signal has a fundamental frequency. If the path selection signal indicates that the differential input signal is within the light load range, a first switching control signal is selected in relation to a third PWM signal to control a first switching voltage to toggle between a second supply voltage and ground potential, thereby switching the first inductor to generate a first output signal. A second switching control signal is selected in relation to a fourth PWM signal to control a second switching voltage to toggle between a second supply voltage and ground potential. The second supply voltage is lower than the first supply voltage. 【0007】 In one preferred embodiment, the first triangular wave signal and the second triangular wave signal have a common-mode offset and have a first amplitude and a second amplitude, respectively. The first amplitude is either equal to or different from the second amplitude, which has a non-zero common-mode offset. 【0008】 In one preferred embodiment, the second switching voltage switches a second inductor having a smaller inductance than the first inductor to generate a second output signal, or corresponds to a second output signal. 【0009】 In one preferred embodiment, the differential input signal has an input common-mode level, and the path selection signal includes a light load selection signal and a level selection signal. The signal determination circuit generates a light load selection signal based on whether the differential input signal is within the light load range, and generates a level selection signal based on a first pulse width masking frequency doubling signal and a second pulse width masking frequency doubling signal. The level selection signal indicates a comparison between the differential input signal and the input common-mode level. 【0010】 In one preferred embodiment, the signal decision circuit includes a flip-flop. The flip-flop is configured to reset based on the inverted signal of the second pulse width masking frequency doubling signal, and in the non-reset state, to activate the level selection signal based on the trigger of the first pulse width masking frequency doubling signal. 【0011】 In one preferred embodiment, the signal determination circuit further compares an offset triangular wave with the differential input signal to generate a fifth PWM signal and a sixth PWM signal. The offset triangular wave is obtained by superimposing a first triangular wave signal with a non-zero common-mode offset associated with the light load range, and the system is configured to periodically determine, based on the current operating cycle of the offset triangular wave, whether the fifth PWM signal and the sixth PWM signal each contain a pulse in the operating cycle immediately preceding the current operating cycle, thereby determining whether the level of the differential input signal is within the light load range. 【0012】 In one preferred embodiment, if a path selection signal indicates that the differential input signal is outside the light load range and greater than the input common-mode level, the signal selection circuit controls a first switching control signal to toggle based on a first pulse width masking frequency doubling signal and a second switching control signal to toggle based on a second pulse width masking frequency doubling signal. If the path selection signal indicates that the differential input signal is outside the light load range and is lower than the input common-mode level, the signal selection circuit controls the first switching control signal to toggle based on the inverted signal of the second pulse width masking frequency doubling signal, and controls the second switching control signal to toggle based on the inverted signal of the first pulse width masking frequency doubling signal. 【0013】 In one preferred embodiment, if a path selection signal indicates that the differential input signal is within a light load range, the signal selection circuit controls a first switching control signal to toggle based on a third PWM signal and a second switching control signal to toggle based on a fourth PWM signal. 【0014】 In one preferred embodiment, the hybrid differential amplifier further includes a second masking frequency doubling circuit configured to generate a third pulse width masking frequency doubling signal and a fourth pulse width masking frequency doubling signal based on a third PWM signal and a fourth PWM signal. When the first input signal is positive, the third pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the third PWM signal; when the first input signal is negative, the third pulse width masking frequency doubling signal is 0. When the second input signal is positive, the fourth pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the fourth PWM signal; when the second input signal is negative, the fourth pulse width masking frequency doubling signal is 0. If the path selection signal indicates that the differential input signal is within the light load range and greater than the input common-mode level, the first switching control signal is controlled to toggle based on the third pulse width masking frequency doubling signal, and the second switching control signal is controlled to toggle based on the fourth pulse width masking frequency doubling signal. If the path selection signal indicates that the differential input signal is within the light load range and is lower than the input common-mode level, the first switching control signal is controlled to toggle based on the inverted signal of the fourth pulse width masking frequency doubling signal, and the second switching control signal is controlled to toggle based on the inverted signal of the third pulse width masking frequency doubling signal. 【0015】 In one preferred embodiment, the first masking frequency doubling circuit generates a first pulse width masking frequency doubling signal by applying an AND logic operation to the first PWM signal and the inverted signal of the second PWM signal, and generates a second pulse width masking frequency doubling signal by applying an AND logic operation to the inverted signal of the first PWM signal and the second PWM signal. 【0016】 In one preferred embodiment, the first masking frequency doubling circuit generates a first pulse width masking frequency doubling signal by applying an AND logic operation to the first PWM signal and the inverted signal of the second PWM signal, and generates a second pulse width masking frequency doubling signal by applying an AND logic operation to the inverted signal of the first PWM signal and the second PWM signal. The second masking frequency doubling circuit generates a third pulse width masking frequency doubling signal by applying an AND logic operation to the third PWM signal and the inverted signal of the fourth PWM signal, and generates a fourth pulse width masking frequency doubling signal by applying an AND logic operation to the inverted signal of the third PWM signal and the fourth PWM signal. 【0017】 In one preferred embodiment, the first power stage circuit includes a first main high-side transistor, a first auxiliary high-side transistor, and a first low-side transistor. The first main high-side transistor is coupled between the first supply voltage and the first switching node. The first auxiliary high-side transistor is coupled between the second supply voltage and the first switching node. The first low-side transistor is coupled between the first switching node and the ground potential. The first power stage circuit is configured to generate a first switching voltage based on a first switching control signal to switch a first inductor, thereby converting a first supply voltage and a second supply voltage to generate a first output signal. The second power stage circuit includes a second main high-side transistor, a second auxiliary high-side transistor, and a second low-side transistor. The second main high-side transistor is coupled between the first supply voltage and the second switching node. The second auxiliary high-side transistor is coupled between the second supply voltage and the second switching node. The second low-side transistor is coupled between the second switching node and the ground potential. The second power stage circuit is configured to switch based on a second switching control signal to convert the first supply voltage and the second supply voltage to generate a second output signal. 【0018】 In one preferred embodiment, the hybrid differential amplifier further includes an error amplifier configured to generate an error amplification signal based on the difference between a feedback signal related to the second output signal and a second filtered signal. In the ultra-light load range, the signal selection circuit selects the error amplification signal to linearly control the second main high-side transistor and adjusts the second output signal to be linearly related to the second filtered signal. The ultra-light load range is a subset of the light load range and represents a state having a smaller load level than in the light load range. 【0019】 From another perspective, the present invention provides a hybrid differential amplification method for controlling a hybrid differential amplifier to generate a differential output signal based on a differential input signal to drive a load, wherein the differential input signal includes a first input signal and a second input signal, and the differential output signal includes a first output signal and a second output signal. The hybrid differential amplification method includes the following steps: A first PWM (pulse width modulation) signal is generated by comparing a first triangular wave signal with a first filtered signal, where the first filtered signal is related to the first input signal. A second PWM signal is generated by comparing the first triangular wave signal with the second filtered signal, and the second filtered signal is related to the second input signal. A step of generating a third PWM signal by comparing a second triangular wave signal with a first filtered signal. A step of generating a fourth PWM signal by comparing a second triangular wave signal with a second filtered signal. The step of generating a first pulse width masking frequency doubling signal and a second pulse width masking frequency doubling signal based on a first PWM signal and a second PWM signal, wherein if the first input signal is positive, the first pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the first PWM signal; if the first input signal is negative, the first pulse width masking frequency doubling signal is 0; if the second input signal is positive, the second pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the second PWM signal; and if the second input signal is negative, the second pulse width masking frequency doubling signal is 0. A step of generating a path selection signal based on the range in which the levels of differential input signals exist. Steps to generate a first switching control signal and a second switching control signal based on a first pulse width masking frequency doubling signal, a second pulse width masking frequency doubling signal, a third PWM signal, and a fourth PWM signal in response to a path selection signal. A step of generating a first switching voltage at a first switching node based on a first switching control signal, thereby switching a first inductor coupled to the first switching node to generate a first output signal. A step of generating a second switching voltage at a second switching node based on a second switching control signal, thereby generating a second output signal. If the path selection signal indicates that the differential input signal is outside the light load range, a first switching control signal is selected as relating to a first pulse width masking frequency doubling signal having a first PWM characteristic, and controls a first switching voltage at a first switching node to toggle between a first supply voltage and ground potential. A second switching control signal is selected as relating to a signal approximating the fundamental frequency, and controls a second switching voltage at a second switching node to toggle between the first supply voltage and ground potential. The differential input signal has a fundamental frequency. If the path selection signal indicates that the differential input signal is within the light load range, a first switching control signal is selected in relation to a third PWM signal to control a first switching voltage to toggle between a second supply voltage and ground potential. This switches the first inductor to generate a first output signal, and a second switching control signal is selected in relation to a fourth PWM signal to control a second switching voltage to toggle between a second supply voltage and ground potential. The second supply voltage is lower than the first supply voltage. 【0020】 In one preferred embodiment, the first triangular wave signal and the second triangular wave signal have a common-mode offset and have first and second amplitudes, respectively. The first amplitude is either equal to or different from the second amplitude, which has a non-zero common-mode offset. 【0021】 In one preferred embodiment, the second switching voltage switches a second inductor having a smaller inductance than the first inductor to generate a second output signal, or corresponds to a second output signal. 【0022】 In one preferred embodiment, the differential input signal has an input common-mode level, and the path selection signal includes a light load selection signal and a level selection signal. The step of generating a path selection signal includes generating a light load selection signal based on whether the differential input signal is within the light load range, and generating a level selection signal based on a first pulse width masking frequency doubling signal and a second pulse width masking frequency doubling signal. The level selection signal indicates a comparison between the differential input signal and the input common-mode level. 【0023】 In one preferred embodiment, the step of generating a level selection signal includes resetting the level selection signal based on an inverted signal of a second pulse width masking frequency doubling signal, and, in a non-reset state, enabling the level selection signal based on a trigger of a first pulse width masking frequency doubling signal. 【0024】 In one preferred embodiment, the step of generating a light load selection signal includes the following: The offset triangular wave is compared with the differential input signal to generate a fifth and a sixth PWM signal, and the offset triangular wave is obtained by superimposing the first triangular wave signal with a non-zero common-mode offset associated with the light load range. Based on the current operating cycle of the offset triangular wave, periodically determine whether the fifth PWM signal and the sixth PWM signal each contain a pulse within the operating cycle immediately preceding the current operating cycle, thereby determining whether the level of the differential input signal is within the light load range. 【0025】 In one preferred embodiment, the step of generating a level selection signal includes the following: If the path selection signal indicates that the differential input signal is outside the light load range and greater than the input common-mode level, control the first switching control signal to toggle based on a first pulse width masking frequency doubling signal, and control the second switching control signal to toggle based on a second pulse width masking frequency doubling signal. If the path selection signal indicates that the differential input signal is outside the light load range and is lower than the input common-mode level, control the first switching control signal to toggle based on the inverted signal of the second pulse width masking frequency doubling signal, and control the second switching control signal to toggle based on the inverted signal of the first pulse width masking frequency doubling signal. 【0026】 In one preferred embodiment, the step of generating a first switching control signal and a second switching control signal includes controlling the first switching control signal to toggle based on a third PWM signal and the second switching control signal to toggle based on a fourth PWM signal, if the path selection signal indicates that the differential input signal is within a light load range. 【0027】 In one preferred embodiment, the hybrid differential amplification method further includes generating a third pulse width masking frequency doubling signal and a fourth pulse width masking frequency doubling signal based on a third PWM signal and a fourth PWM signal. When the first input signal is positive, the third pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the third PWM signal; when the first input signal is negative, the third pulse width masking frequency doubling signal is 0. When the second input signal is positive, the fourth pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the fourth PWM signal; when the second input signal is negative, the fourth pulse width masking frequency doubling signal is 0. If the path selection signal indicates that the differential input signal is within the light load range and greater than the input common-mode level, the first switching control signal is controlled to toggle based on the third pulse width masking frequency doubling signal, and the second switching control signal is controlled to toggle based on the fourth pulse width masking frequency doubling signal. If the path selection signal indicates that the differential input signal is within the light load range and is lower than the input common-mode level, the first switching control signal is controlled to toggle based on the inverted signal of the fourth pulse width masking frequency doubling signal, and the second switching control signal is controlled to toggle based on the inverted signal of the third pulse width masking frequency doubling signal. 【0028】 In one preferred embodiment, the step of generating a first pulse width masking frequency doubling signal and a second pulse width masking frequency doubling signal includes: applying an AND logic operation to the first PWM signal and the inverted signal of the second PWM signal to generate the first pulse width masking frequency doubling signal; and applying an AND logic operation to the inverted signal of the first PWM signal and the second PWM signal to generate the second pulse width masking frequency doubling signal. 【0029】 In one preferred embodiment, the step of generating a first pulse width masking frequency doubling signal and a second pulse width masking frequency doubling signal includes: applying an AND logic operation to the first PWM signal and the inverted signal of the second PWM signal to generate the first pulse width masking frequency doubling signal; and applying an AND logic operation to the inverted signal of the first PWM signal and the second PWM signal to generate the second pulse width masking frequency doubling signal. 【0030】 The steps for generating a third pulse width masking frequency doubling signal and a fourth pulse width masking frequency doubling signal include: applying an AND logic operation to the third PWM signal and the inverted signal of the fourth PWM signal to generate a third pulse width masking frequency doubling signal; and applying an AND logic operation to the inverted signal of the third PWM signal and the fourth PWM signal to generate a fourth pulse width masking frequency doubling signal. 【0031】 In one preferred embodiment, the hybrid differential amplification method further includes generating an error amplified signal based on the difference between a feedback signal associated with a second output signal and a second filtered signal. In the ultra-light load range, an error amplification signal is selected to linearly control the second main high-side transistor, adjusting the second output signal to be linearly related to the second filtered signal. The ultra-light load range is a subset of the light load range, representing conditions with lower load levels than those in the light load range. 【0032】 The object, technical details, features, and effects of the present invention will be better understood with reference to the drawings and the following detailed description of embodiments. [Brief explanation of the drawing] 【0033】 [Figure 1] This diagram shows a conventional hybrid differential amplifier. [Figure 2A] This is a block diagram of a hybrid differential amplifier according to an embodiment of the present invention. [Figure 2B] This figure shows a specific embodiment of the power stage circuit and signal selection circuit (201) in a hybrid differential amplifier according to one embodiment of the present invention. [Figure 3] This figure shows signal waveforms related to a hybrid differential amplifier according to one embodiment of the present invention. [Figure 4] This figure illustrates another embodiment of the hybrid differential amplifier, specifically an embodiment of the masking frequency doubling circuit and the signal selection circuit. [Figure 5] This is a waveform diagram of the signal corresponding to the embodiment of the hybrid differential amplifier shown in Figure 4. [Figure 6] This is a schematic diagram of a signal determination circuit in a hybrid differential amplifier according to an embodiment of the present invention. [Figure 7A] This is a waveform diagram of a signal in a conventional hybrid differential amplifier. [Figure 7B] This is a waveform diagram of a signal in a hybrid differential amplifier according to one embodiment of the present invention. [Figure 7C] This is a waveform diagram of a signal in a hybrid differential amplifier according to another embodiment of the present invention. [Figure 8A] This is a magnified view of a portion of Figure 7A. [Figure 8B] This is a magnified view of a portion of Figure 7B. [Figure 8C] This is a magnified view of a portion of Figure 7C. [Figure 9] This is a schematic diagram of some specific embodiments of the signal selection circuit and power stage circuit in a hybrid differential amplifier according to the present invention. [Figure 10] This is a waveform diagram for generating the light load selection signal SEL_LL in one embodiment of the present invention. [Figure 11] Figures (a) to (d) show signal waveforms related to a hybrid differential amplifier according to an embodiment of the present invention. [Figure 12] This is a schematic diagram of an alternative embodiment of the power stage circuit of a hybrid differential amplifier according to the present invention. [Figure 13A] This figure shows a specific embodiment of a pulse width modulation circuit and a masking frequency doubling circuit in a hybrid differential amplifier according to one embodiment of the present invention. [Figure 13B] This figure shows another specific embodiment of the pulse width modulation circuit and masking frequency doubling circuit in a hybrid differential amplifier according to an alternative embodiment of the present invention. [Figure 14] These are signal waveform diagrams corresponding to the embodiments shown in Figures 13A and 13B. [Modes for carrying out the invention] 【0034】 The drawings referenced throughout this description of the present invention are for illustrative purposes only to illustrate the relationship between circuits and signal waveforms and are not drawn to the actual scale of the circuit size and signal amplitude and frequency. 【0035】 Figure 2A shows a block diagram of a hybrid differential amplifier according to an embodiment of the present invention. As shown in Figure 2A, the hybrid differential amplifier 20 generates a differential output signal Vod (the difference between output signals Vop and Von) based on a differential input signal Vid (the difference between input signals Vip and Vin) to drive a load 207. The differential input signal Vid includes input signals Vip and Vin, and the differential output signal Vod includes output signals Vop and Von. The hybrid differential amplifier 20 includes a signal selection circuit 201, a loop filter circuit 202, pulse width modulation circuits 203a to 203d, a signal determination circuit 204, a masking frequency doubler circuit (MFD Ckt 205), and power stage circuits 206a and 206b. 【0036】 The input signals Vip and Vin, and the output signals Vop and Von, correspond to positive and negative input signals and positive and negative output signals, respectively. Here, "positive" and "negative" are defined for their respective common-mode levels and phases, and are not absolute terms. Furthermore, the concepts of this invention can also be applied when "positive" and "negative" are reversed. 【0037】 The loop filter circuit 202 amplifies and filters the difference between the differential output signal Vod and the differential input signal Vid to generate filtered signals Vep and Ven. The pulse width modulation circuit 203a generates a pulse width modulated signal CMPp1 by comparing the triangular wave signal Vtr1 with the filtered signal Vep. The filtered signal Vep is related to the input signal Vip. Similarly, the pulse width modulation circuit 203b generates a pulse width modulated signal CMPn1 by comparing the triangular wave signal Vtr1 with the filtered signal Ven. The filtered signal Ven is related to the input signal Vin. 【0038】 The pulse width modulation circuit 203c generates a pulse width modulated signal CMPp2 by comparing the second triangular wave signal Vtr2 with the filtered signal Vep, and the pulse width modulation circuit 203d generates a pulse width modulated signal CMPn2 by comparing the triangular wave signal Vtr2 with the filtered signal Ven. 【0039】 Referring to Figures 11(a) to 11(d), which show signal waveforms related to a hybrid differential amplifier according to an embodiment of the present invention, triangular wave signals Vtr1 and Vtr2 are shown. As shown in Figures 11(a) to 11(d), there is a common-mode offset Vos between the triangular wave signals Vtr1 and Vtr2, with amplitudes Va1 and Va2, respectively. In one embodiment, as shown in Figures 11(a) to 11(c), amplitude Va1 is different from amplitude Va2. In one embodiment, Va1 is greater than Va2, and the common-mode offset Vos may be zero, as in Figure 11(a), or non-zero, as in Figures 11(b) and 11(c). In another embodiment, as shown in Figure 11(d), amplitudes Va1 and Va2 are equal, and the common-mode offset Vos is non-zero. 【0040】 The pulse-width modulated signals CMPp1, CMPn1, CMPp2, and CMPn2 correspond to the pulse-width modulated signals after basic Class D pulse-width modulation processing. In this invention, these pulse-width modulated signals are further processed to achieve the aforementioned functions and objectives, as will be described in detail later. 【0041】 Referring again to Figure 2A, the masking frequency doubling circuit 205 generates pulse width masking frequency doubling signals Ndp1, 1-Ndp1, Ndn1, and 1-Ndn1 based on the pulse width modulated signals CMPp1 and CMPn1. The masking frequency doubling circuit 205 performs logical operations on the pulse width modulated signals CMPp1 and CMPn1 so that when the input signal Vip is positive, the pulse width masking frequency doubling signal Ndp1 corresponds to the frequency doubling pulse width modulated signal derived from the pulse width modulated signal CMPp1, and when the input signal Vip is negative, Ndp1 is zero. Similarly, when the input signal Vin is positive, the pulse width masking frequency doubling signal Ndn1 corresponds to the frequency doubling pulse width modulated signal derived from the pulse width modulated signal CMPn1, and when the input signal Vin is negative, Ndn1 is zero. 【0042】 The signal determination circuit 204 is configured to generate a level selection signal SEL_Rb and a light load selection signal SEL_LL based on the range in which the levels of the differential input signal Vid, the pulse width masking frequency doubling signal Ndp1, and the pulse width masking frequency doubling signal Ndn1 exist. Specifically, the signal determination circuit 204 generates the light load selection signal SEL_LL based on the differential input signal Vid. In this embodiment, an effective level of the light load selection signal SEL_LL (e.g., 1) indicates that the differential input signal Vid is within the light load range. Furthermore, the signal determination circuit 204 generates a level selection signal SEL_Rb based on the pulse width masking frequency doubling signals Ndp1 and Ndn1. The level selection signal SEL_Rb indicates a comparison between the differential input signal Vid and the input common mode level Vicm. Specifically, in this embodiment, an effective level of SEL_Rb (e.g., 1) indicates that the differential input signal Vid is greater than the input common mode level Vicm. 【0043】 The signal selection circuit 201 is configured to generate switching control signals A1, A2, Ab, C1, C2, and Cb for controlling power stage circuits 206a and 206b based on the path selection signal SEL (including the level selection signal SEL_Rb and the light load selection signal SEL_LL). The signal selection circuit 201 generates the aforementioned switching control signals by selecting from pulse width masking frequency doubling signals Ndp1, 1-Ndp1, Ndn1, 1-Ndn1 and pulse width modulation signals CMPp2 and CMPn2. 【0044】 Power stage circuit 206a generates a switching voltage VLXp at switching node LXp based on switching control signals A1, A2, and Ab. This switching voltage VLXp drives an inductor Lp coupled to switching node LXp to generate an output signal Vop. Similarly, power stage circuit 206b generates a switching voltage VLXn at switching node LXn based on switching control signals C1, C2, and Cb, thereby generating an output signal Von. In this embodiment, the switching voltage VLXn corresponds to the output signal Von. 【0045】 Figure 2B shows a specific embodiment of the power stage circuits (206a and 206b) and signal selection circuit (201) in a hybrid differential amplifier according to one embodiment of the present invention. As shown in Figure 2B, the power stage circuit 206a includes a main high-side transistor QPUP, an auxiliary high-side transistor QPUA, and a low-side transistor QPL. The main high-side transistor QPUP is coupled between the supply voltage PV1 and the switching node LXp. The auxiliary high-side transistor QPUA is coupled between the supply voltage PV2 and the switching node LXp. The low-side transistor QPL is coupled between the switching node LXp and ground potential. The power stage circuit 206a generates a switching voltage VLXp based on switching control signals A1, A2, and Ab to toggle the inductor Lp and converts the supply voltages PV1 and PV2 to generate the output signal Vop. The power stage circuit 206b includes a main high-side transistor QNUP, an auxiliary high-side transistor QNUA, and a low-side transistor QNL. The main high-side transistor QNUP is coupled between the supply voltage PV1 and the switching node LXn. The auxiliary high-side transistor QNUA is coupled between the supply voltage PV2 and the switching node LXn. The low-side transistor QNL is coupled between the switching node LXn and ground potential. The circuit toggles based on the switching control signals C1, C2, and Cb, converting the supply voltages PV1 and PV2 to generate the output signal Von. 【0046】 If the path selection signal SEL indicates that the differential input signal Vid is outside the light load range, the switching control signals A1, A2, and Ab are selected as signals associated with the pulse width masking frequency doubling signals Ndp1 and Ndn1, which have a first pulse width modulation characteristic. These signals control the switching voltage VLXp at switching node LXp to toggle between the supply voltage PV1 and ground potential. The switching control signals C1, C2, and Cb are selected as signals approximating the fundamental frequency and control the switching voltage VLXn at switching node LXn to toggle between the supply voltage PV1 and ground potential. 【0047】 Note that the aforementioned fundamental frequency refers to the frequency of variation in the differential input signal Vid. The "first pulse width modulation characteristic" refers to the modulation characteristics of the pulse width masked frequency doubling signals Ndp1 and Ndn1 after frequency doubling and masking processing. 【0048】 More specifically, if the path selection signal SEL indicates that the differential input signal Vid is outside the light load range and greater than the input common-mode level Vicm, the signal selection circuit 201 controls the switching control signals A1, A2, and Ab to toggle based on the pulse width masking frequency doubling signal Ndp1, and controls the switching control signals C1, C2, and Cb to toggle based on the pulse width masking frequency doubling signal Ndn1. If the path selection signal SEL indicates that the differential input signal Vid is outside the light load range and less than the input common-mode level Vicm, the signal selection circuit 201 controls the switching control signals A1, A2, and Ab to toggle based on the inverted signal of the pulse width masking frequency doubling signal Ndn1, and controls the switching control signals C1, C2, and Cb to toggle based on the inverted signal of the pulse width masking frequency doubling signal Ndp1. 【0049】 On the other hand, if the path selection signal SEL indicates that the differential input signal Vid is within the light load range, the switching control signals A1, A2, and Ab are selected as signals associated with the pulse width modulation signal CMPp2, controlling the switching voltage VLXp to toggle between the supply voltage PV2 and ground potential, thereby switching the inductor Lp to generate the output signal Vop. Similarly, the switching control signals C1, C2, and Cb are selected as signals associated with the pulse width modulation signal CMPn2, controlling the switching voltage VLXn to toggle between the supply voltage PV2 and ground potential. In one embodiment, the supply voltage PV2 is lower than the supply voltage PV1. 【0050】 It is worth noting that the path selection signal SEL controls the signal selection circuit 201 to distinguish the operating modes of the hybrid differential amplifier based on the range of the differential input signal Vid. Specifically, it distinguishes between states within the light load range and states outside the light load range. Outside the light load range, the path selection signal further determines whether the differential input signal Vid is greater than or less than the input common-mode level and enables the corresponding control for totem-pole pulse width modulation. Outside the light load range, the signal selection circuit 201 also controls the power stage circuits 206a and 206b to operate using a higher supply voltage PV1, performing totem-pole class D PWM operation. In this mode, power stage circuit 206a drives inductor Lp to generate output signal Vop, while power stage circuit 206b can output a signal Von with a fundamental frequency directly or by switching a smaller inductor. This design reduces the overall circuit size and cost (note that totem-pole Class D PWM operation refers to toggling the switching voltage VLXp at the pulse width modulation frequency while toggling VLXn at the fundamental frequency). 【0051】 On the other hand, when the differential input signal Vid is within the light load range, power stage circuits 206a and 206b perform Class D PWM operation using a lower supply voltage PV2. In this mode, the voltage amplitudes of the switching voltages VLXp and VLXn are reduced, and the required duty cycle increases. Such a design effectively reduces distortion and electromagnetic interference near the zero-voltage crossover point. 【0052】 As shown in Figure 2B, in one particular embodiment, the signal selection circuit 201 has subcircuits 2011a and 2011b. Subcircuit 2011a includes multiplexers 20111a, 20112a, and 20113a, as well as an inverter 20114a. Multiplexer 20111a is configured to generate a switching control signal A1 in response to a level selection signal SEL_Rb and a light load selection signal SEL_LL, based on a pulse width masking frequency doubling signal Ndp1, 1-Ndn1, and a low-level signal Lw (e.g., 0). Multiplexer 20112a generates a switching control signal A2 in response to a level selection signal SEL_Rb and a light load selection signal SEL_LL, based on a pulse width modulation signal CMPp2 and a low-level signal Lw. Multiplexer 20113a generates an intermediate signal Am1 based on switching control signals A1 and A2 in response to the light load selection signal SEL_LL, and inverter 20114a then inverts Am1 to generate a switching control signal Ab. 【0053】 Continuing with the reference to Figure 2B, subcircuit 2011b functions similarly. Multiplexer 20111b is configured to generate a switching control signal C1 based on pulse width masking frequency doubling signals 1-Ndp1, Ndn1 and a low-level signal Lw in response to the level selection signal SEL_Rb and the light load selection signal SEL_LL. Multiplexer 20112b generates a switching control signal C2 based on pulse width modulated signal CMPn2 and a low-level signal Lw in response to the level selection signal SEL_Rb and the light load selection signal SEL_LL. Multiplexer 20113b generates an intermediate signal Cm1 based on switching control signals C1 and C2 in response to the light load selection signal SEL_LL, and inverter 20114b inverts Cm1 to generate a switching control signal Cb. 【0054】 Figure 3 shows signal waveforms related to a hybrid differential amplifier according to one embodiment of the present invention. The input signals Vip and Vin, output signals Vop and Von, differential output signal Vod, differential input signal Vid, input common-mode level Vicm, output common-mode level Vocm, level selection signal SEL_Rb, pulse width masking frequency doubling signals Ndp1 and Ndn1, switching control signals A1 and C1, light load selection signal SEL_LL, and switching voltages VLXp and VLXn are all shown in Figure 3. As shown in Figure 3, the differential input signal Vid has an input common-mode level Vicm. Also, as shown in Figure 3, when the light load selection signal SEL_LL indicates that the differential input signal Vid is outside the light load range and is greater than the input common-mode level Vicm (shown on the right as the "heavy load" range), the switching control signal A1 toggles based on the pulse width masking frequency doubling signal Ndp1, and the switching control signal C1 toggles based on the pulse width masking frequency doubling signal Ndn1. If the light load selection signal SEL_LL indicates that the differential input signal Vid is outside the light load range and is less than the input common-mode level Vicm (shown on the left as the "heavy load" range), the switching control signal A1 toggles based on the inverted signal of the pulse width masking frequency doubling signal Ndn1, and the switching control signal C1 toggles based on the inverted signal of the pulse width masking frequency doubling signal Ndp1. 【0055】 As shown in Figure 3, outside the light load range, the switching voltages VLXp and VLXn toggle between the supply voltage PV1 and ground potential using the aforementioned totem-pole Class D pulse width modulation (PWM). Within the light load range, the switching voltages VLXp and VLXn toggle between the supply voltage PV2 and ground potential using Class D PWM. 【0056】 Figure 4 shows another embodiment of the hybrid differential amplifier, illustrating specific embodiments of the masking frequency doubling circuit and signal selection circuit. As shown in Figure 4, this embodiment includes masking frequency doubling circuits (MFD Ckt205a and 205b). Masking frequency doubling circuit 205a is similar to masking frequency doubling circuit 205 in Figure 2A and will not be described in detail. Masking frequency doubling circuit 205b generates pulse-width masking frequency doubling signals Ndp2, 1-Ndp2, Ndn2, and 1-Ndn2 based on pulse-width modulated signals CMPp2 and CMPn2. When the input signal Vip is positive, the pulse-width masking frequency doubling signal Ndp2 corresponds to the frequency doubling of the pulse-width modulated signal CMPp2, and when the input signal Vip is negative, the pulse-width masking frequency doubling signal Ndp2 is 0. Similarly, when the input signal Vin is positive, the pulse width masking frequency doubling signal Ndn2 corresponds to the pulse width modulated signal CMPn2 with double the frequency, and when the input signal Vin is negative, the pulse width masking frequency doubling signal Ndn2 is 0. 【0057】 In this embodiment, when the path selection signal SEL indicates that the differential input signal Vid is outside the light load range, the operation is the same as in the embodiment shown in Figure 2B. The difference in this embodiment lies in the operation when the path selection signal SEL indicates that the differential input signal Vid is within the light load range. In such cases, the hybrid differential amplifier also employs a totem-pole class D pulse width modulation approach, and the switching voltages VLXp and VLXn toggle between the supply voltage PV2 (lower than the supply voltage PV1) and ground potential. 【0058】 Specifically, if the path selection signal SEL indicates that the differential input signal Vid is within the light load range and greater than the input common-mode level Vicm, the signal selection circuit 201 controls the switching control signals A1, A2, and Ab to toggle based on the pulse width masking frequency doubling signal Ndp2, and controls the switching control signals C1, C2, and Cb to toggle based on the pulse width masking frequency doubling signal Ndn2. If the path selection signal SEL indicates that the differential input signal Vid is within the light load range and less than the input common-mode level Vicm, the signal selection circuit 201 controls the switching control signals A1, A2, and Ab to toggle based on the inverted signal of the pulse width masking frequency doubling signal Ndn2, and controls the switching control signals C1, C2, and Cb to toggle based on the inverted signal of the pulse width masking frequency doubling signal Ndp2. 【0059】 As shown in Figure 4, the signal selection circuit 401 in this embodiment is similar to the signal selection circuit 201 in Figure 2B, but with some differences. Multiplexer 20112a is configured to generate a switching control signal A2 based on pulse width masking frequency doubling signals Ndp2 and 1-Ndn2 and a low-level signal Lw in response to the level selection signal SEL_Rb and the light load selection signal SEL_LL. Multiplexer 20112b is configured to generate a switching control signal C2 based on pulse width masking frequency doubling signals Ndn2 and 1-Ndp2 and a low-level signal Lw in response to the level selection signal SEL_Rb and the light load selection signal SEL_LL. 【0060】 Figure 5 shows waveform diagrams of signals corresponding to the embodiment of the hybrid differential amplifier shown in Figure 4. The signals, for example, input signals Vip and Vin, output signals Vop and Von, differential output signal Vod, differential input signal Vid, input common-mode level Vicm, output common-mode level Vocm, level selection signal SEL_Rb, pulse width masking frequency doubling signals Ndp1 and Ndn1, switching control signals A1 and C1, light load selection signal SEL_LL, and switching voltages VLXp and VLXn are shown in Figure 5. As illustrated, when the light load selection signal SEL_LL indicates that the differential input signal Vid is outside the light load range, the operating waveform is identical to that shown in Figure 3. On the other hand, when the light load selection signal SEL_LL indicates that the differential input signal Vid is within the light load range, the switching voltages VLXp and VLXn toggle between the supply voltage PV2 and ground potential using totem-pole class D pulse width modulation. The embodiments shown in Figures 4 and 5 demonstrate that reducing the voltage amplitudes of the switching voltages VLXp and VLXn near the zero-voltage intersection increases the duty cycle and effectively reduces distortion and electromagnetic interference. 【0061】 Figure 6 shows a schematic diagram of a signal decision circuit in a hybrid differential amplifier according to an embodiment of the present invention. This embodiment shows a specific embodiment of the signal decision circuit 204. The signal decision circuit 204 includes a flip-flop 2041. The flip-flop 2041 is configured to reset based on the inverted signal of the pulse width masking frequency doubling signal Ndn1, and in the non-reset state, to activate the level selection signal SEL_Rb based on a trigger (e.g., rising edge) of the pulse width masking frequency doubling signal Ndp1. 【0062】 Figure 7A shows the waveform diagram of a signal in a conventional hybrid differential amplifier, and Figure 8A shows a magnified view of a portion of Figure 7A. The signals, e.g., output signals Vop and Von, switching voltages VLXp and VLXn, and differential output signals (i.e., Vop, Von) are shown in Figures 7A and 8A. In the prior art, regardless of whether the operation is within or outside the light load range, the switching voltages VLXp and VLXn toggle at a higher level between the supply voltage PV1 and ground potential. As seen in Figure 8A, under light load conditions, the zero-voltage crossover region exhibits a very narrow pulse width, which means a very low duty cycle, and in addition, the high switching voltages cause higher electromagnetic interference. 【0063】 Figure 7B shows a waveform diagram of signals in a hybrid differential amplifier according to one embodiment of the present invention, and Figure 8B shows an enlarged view of a portion of Figure 7B. Figure 7C shows another embodiment, and Figure 8C shows an enlarged view of a portion of Figure 7C. Signals, such as output signals Vop and Von, switching voltages VLXp and VLXn, and differential output signal Vod, are shown in Figures 7B, 8B, 7C, and 8C. Figures 7B and 8B correspond to embodiments in Figures 2B and 3, and Figures 7C and 8C correspond to embodiments in Figures 4 and 5. As shown in Figure 8B, in this embodiment, within the light load range, the switching voltages VLXp and VLXn toggle between a lower supply voltage PV2 and ground potential using pulse width modulation. As shown in Figure 8C, within the light load range, the switching voltages VLXp and VLXn toggle between a lower supply voltage PV2 and ground potential using totem-pole class D pulse width modulation. The reduction in electromagnetic interference is due to both an increase in the duty cycle and a decrease in the supply voltage PV2. 【0064】 Figure 9 shows a schematic diagram of some specific embodiments of the signal selection circuit and power stage circuit in a hybrid differential amplifier according to the present invention. In this embodiment, the signal selection circuit 201 includes a signal selection subcircuit 2011c. The signal selection subcircuit 2011c includes multiplexers 20112c and 20113c, an inverter 20114c, and an error amplifier 20115c. The error amplifier 20115c generates an amplified error signal Veg based on the difference between a feedback signal VFBn related to the output signal Von and a filtered signal Ven. In the ultra-light load range, the signal selection circuit 201 selects the amplified error signal Veg and linearly controls the main high-side transistor QNUP to adjust the output signal Von to be linearly related to the filtered signal Ven. In one embodiment, the ultra-light load range is a subset of the light load range and represents a smaller load than in the light load range. In one example, the ultra-light load range may include no-load conditions. In this embodiment, the ultra-light load range shares at least one transistor with the light load or heavy load range. Specifically, in the heavy load or light load range, the main high-side transistor QNUP, the auxiliary high-side transistor QNUA, and the low-side transistor QNL are controlled to toggle by switching control signals C1, C2, and Cb, switching the output signal Von between the supply voltages PV1, PV2 and ground potential. In the ultra-light load range, at least one of QNUP, QNUA, and QNL is linearly controlled based on the error amplification signal Veg, adjusting the output signal Von to a linear voltage output that is linearly related to the input signal Vin. This linear output voltage lies between the supply voltage PV1 (or PV2) and ground potential. 【0065】 Continuing with the reference to Figure 9, in this embodiment, multiplexer 20112c selects between error amplification signal Veg and low-level signal Lw based on level selection signal SEL_Rb and light-load selection signal SEL_LL to generate switching control signals C2, C1, and / or Cb. Multiplexer 20113c selects between switching control signal C1 and high-level signal Hgh based on light-load selection signal SEL_LL to generate intermediate signal Cm3. Intermediate signal Cm3 is then inverted by inverter 20114c to generate switching control signal Cb. In this particular embodiment shown in Figure 9, during the ultra-light-load range, the main high-side transistor QNUP and low-side transistor QNL are turned off, while the auxiliary high-side transistor QNUA is linearly controlled based on error amplification signal Veg to adjust the output signal Von to a linear output voltage that is linearly related to the input signal Vin. 【0066】 Figure 10 shows a waveform diagram for generating the light load selection signal SEL_LL in one embodiment of the present invention. The signals, e.g., triangular wave signal Vtr1, offset triangular wave Vtr3, common mode offset Vos, filtered signals Vep and Ven, common mode levels Vcm1 and Vcm3, clock signal CLK, pulse width modulated signals CMPp3 and CMPn3, and the light load selection signal SEL_LL are shown in Figure 10. Referring to both Figure 10 and Figure 11, in this embodiment, the light load selection signal SEL_LL is generated by performing a logical operation between the filtered signals Vep and Ven using the triangular wave signal Vtr1 and the offset triangular wave Vtr3 to determine whether the differential input signal Vid is within the light load range. In one embodiment, the offset triangular wave Vtr3 is obtained by adding a non-zero common mode offset Vos to the triangular wave signal Vtr1, both having the same amplitudes Va1 and Va2. The pulse-width modulated signals CMPp3 and CMPn3 are generated by comparing the offset triangular wave Vtr3 with the filtered signals Vep and Ven, respectively. The signal determination circuit periodically determines, based on the current operating cycle of the offset triangular wave Vtr3, whether each of the pulse-width modulated signals CMPp3 and CMPn3 contains a pulse in the operating cycle immediately preceding the current operating cycle, thereby determining whether the level of Vid is within the light load range. In one embodiment, the common-mode offset Vos is related to the light load range. In this embodiment, the common-mode level of Vtr1 is related to the common-mode levels of the filtered signals Vep and Ven (e.g., equal to the common-mode level). 【0067】 Figure 12 shows schematic diagrams of alternative embodiments of power stage circuits 206a and 206b. These embodiments are similar to the power stage circuits shown in Figure 2B, except that the switching voltage VLXn is configured to switch inductor Ln to generate the output signal Von, and the inductance of Ln is smaller than that of Lp. According to the present invention, optionally, the switching voltage VLXn can function directly as the output signal Von, or, as in these embodiments, VLXn switches inductor Ln to generate the output signal Von. Due to the aforementioned characteristics inherent in the design of the present invention, the inductance of Ln can be reduced, or even omitted, thereby reducing size and cost. 【0068】 Figure 13A shows a specific embodiment of the pulse width modulation circuit and masking frequency doubling circuit in a hybrid differential amplifier according to one embodiment of the present invention. The pulse width modulation circuits 203a to 203d in this embodiment are the same as those in Figure 2A and will not be described in detail. As shown in Figure 13A, the masking frequency doubling circuit 205a includes AND gates 410 and 420. The AND gate 410 is configured to generate a pulse width masking frequency doubling signal Ndp1 by applying a logical AND operation to the pulse width modulation signal CMPp1 and the inverted signal of the pulse width modulation signal CMPn1. The AND gate 420 is configured to generate a pulse width masking frequency doubling signal Ndn1 by applying a logical AND operation to the inverted signal of the pulse width modulation signal CMPp1 and the pulse width modulation signal CMPn1. 【0069】 Figure 13B shows another specific embodiment of the pulse width modulation circuit and masking frequency doubling circuit in a hybrid differential amplifier according to an alternative embodiment of the present invention. The pulse width modulation circuits 203a to 203d and the masking frequency doubling circuit 205a in this embodiment are the same as those in Figure 13A and will not be described in detail. As shown in Figure 13B, the masking frequency doubling circuit 205b includes AND gates 410b and 420b. The AND gate 410b is configured to generate a pulse width masking frequency doubling signal Ndp2 by applying a logical AND operation to the pulse width modulation signal CMPp2 and the inverted signal of the pulse width modulation signal CMPn2. The AND gate 420b is configured to generate a pulse width masking frequency doubling signal Ndn2 by applying a logical AND operation to the inverted signal of the pulse width modulation signal CMPp2 and the pulse width modulation signal CMPn2. 【0070】 Figure 14 shows waveform diagrams of signals corresponding to the embodiments shown in Figures 13A and 13B. The signals, for example, triangular wave signals Vtr1 and Vtr2, filtered signals Vep and Ven, common-mode levels Vcm1 and Vcm2, clock signal CLK, pulse-width modulated signals CMPp1, CMPp2, CMPn1, and CMPn2, and pulse-width masking frequency doubling signals Ndp1, Ndp2, Ndn1, and Ndn2 are shown in Figure 14. As illustrated, when the filtered signal Vep exceeds its common-mode level, the pulse-width masking frequency doubling signal Ndp1 exhibits a frequency doubling characteristic of the pulse-width modulated signal CMPp1. When the filtered signal Vep falls below its common-mode level, the pulse-width masking frequency doubling signal Ndp1 is masked to 0. The pulse-width masking frequency doubling signal Ndp1 exhibits a symmetrical waveform. The pulse-width masking frequency doubling signals Ndp2 and Ndn2 exhibit similar characteristics. 【0071】 The present invention has been described in considerable detail with reference to certain preferred embodiments. It should be understood that this description is illustrative and not intended to limit the broadest scope of the invention. Embodiments or claims of the invention do not need to achieve all the objectives or advantages of the invention. The title and abstract are provided to aid in searching and are not intended to limit the scope of the invention. Those skilled in the art will readily recall variations and modifications within the spirit of the invention. For example, performing an action "according to" a particular signal as described in the context of the invention is not strictly limited to performing an action according to the signal itself, but can also be performed according to a transformed or augmented or reduced form of the signal. That is, the signal can be processed before the action is performed by voltage-to-current conversion, current-to-voltage conversion, and / or ratio conversion, etc. Each of the embodiments described herein is not limited to being used alone. In accordance with the spirit of the invention, two or more of the embodiments described herein can be used in combination. For example, two or more embodiments can be configured together, or parts of one embodiment can be configured to replace corresponding parts of another embodiment. In light of the foregoing, the spirit of the present invention encompasses all such and other modifications and variations, which should be interpreted as falling within the scope of the claims and their equivalents. [Explanation of Symbols] 【0072】 2. Pulse width masking frequency 20 Hybrid Differential Amplifiers 201 Signal Selection Circuit 202 Loop filter circuit 203a Pulse width modulation circuit 203b Pulse width modulation circuit 203c pulse width modulation circuit 203d Pulse Width Modulation Circuit 204 Signal judgment circuit 206a power stage circuit 206b power stage circuit 207 load 401 Signal Selection Circuit 410 AND Gate 410b AND gate 420 And Gate 420b AND gate 2011a Sub-circuit 2011b Sub-circuit 2011c Signal Selection Subcircuit 2041 Flip-Flop 20111a Multiplexer 20111b Multiplexer 20112a Multiplexer 20112b Multiplexer 20112c Multiplexer 20113a Multiplexer 20113b Multiplexer 20113c Multiplexer 20114a Inverter 20114b Inverter 20114c Inverter 20115c Error Amplifier A1 Switching control signal A2 Switching control signal Ab switching control signal Am1 intermediate signal C1 Switching control signal C2 Switching Control Signal CLK clock signal CMPn1 pulse width modulated signal CMPn2 pulse width modulated signal CMPp1 pulse width modulated signal CMPp2 pulse width modulated signal CMPp3 pulse width modulated signal Cb switching control signal Cm1 intermediate signal Cm3 intermediate signal D Totem Pole Hgh High-level signal LXn Switching Node LXp Switching Node Ln Inductor Lp Inductor Lw Low-level signal Ndp1 multiplied signal NDP2 doubled signal PV1 supply voltage PV2 supply voltage QNL Low-Side Transistor QNUA Auxiliary High-Side Transistor QNUP Main High-Side Transistor QPL Low-Side Transistor QPUA Auxiliary High-Side Transistor QPUP Main High-Side Transistor SEL route selection signal SEL_LL Light load selection signal SEL_Rb level selection signal VFBn Feedback Signal VLXn Switching Voltage VLXp Switching Voltage Va1 amplitude Va2 amplitude Vcm1 Common Mode Level Veg error amplification signal Ven signal Vep signal Vicm Input Common Mode Level Vid differential input signal Vin Input Signal VIP input signal Vocm output common mode level VOD differential output signal Von output signal Vop output signal Vos Common Mode Offset Vtr1 Triangular wave signal Vtr2 triangle wave signal Vtr3 Offset Triangular Wave

Claims

[Claim 1] A hybrid differential amplifier configured to generate a differential output signal based on a differential input signal to drive a load, wherein the differential input signal includes a first input signal and a second input signal, the differential output signal includes a first output signal and a second output signal, the differential input signal has an input common-mode level, and the hybrid differential amplifier is A first PWM (pulse width modulation) circuit is configured to generate a first PWM signal by comparing a first triangular wave signal with a first filtered signal, wherein the first filtered signal is related to the first input signal. A second PWM circuit configured to generate a second PWM signal by comparing the first triangular wave signal with a second filtered signal, wherein the second filtered signal is related to the second input signal, A third PWM circuit is configured to generate a third PWM signal by comparing a second triangular wave signal with the first filtered signal, A fourth PWM circuit is configured to generate a fourth PWM signal by comparing the second triangular wave signal with the second filtered signal, A first masking frequency doubling circuit is configured to generate a first pulse width masking frequency doubling signal and a second pulse width masking frequency doubling signal based on the first PWM signal and the second PWM signal, When the first input signal is positive, the first pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the first PWM signal; when the first input signal is negative, the first pulse width masking frequency doubling signal is 0. A first masking frequency doubling circuit, wherein when the second input signal is positive, the second pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the second PWM signal, and when the second input signal is negative, the second pulse width masking frequency doubling signal is 0. A signal determination circuit configured to generate a path selection signal based on the range in which the level of the differential input signal exists, A signal selection circuit is configured to generate a first switching control signal and a second switching control signal based on the first pulse width masking frequency doubling signal, the second pulse width masking frequency doubling signal, the third PWM signal, and the fourth PWM signal in response to the path selection signal. A first power stage circuit comprising a plurality of first transistors coupled to a first switching node, configured to generate a first switching voltage at the first switching node based on a first switching control signal, thereby switching a first inductor coupled to the first switching node to generate a first output signal; A second power stage circuit comprising a second plurality of transistors, configured to generate a second switching voltage at a second switching node based on the second switching control signal, thereby generating the second output signal; It has, If the path selection signal indicates that the differential input signal is outside the light load range, The first switching control signal is selected as relating to the first pulse width masking frequency doubling signal having a first PWM characteristic, and controls the first switching voltage at the first switching node to toggle between the first supply voltage and ground potential. The second switching control signal is selected to approximate the fundamental frequency and controls the second switching voltage at the second switching node to toggle between the first supply voltage and the ground potential, and the differential input signal has the fundamental frequency. If the path selection signal indicates that the differential input signal is within the light load range, The first switching control signal is selected as relating to the third PWM signal and controls the first switching voltage to toggle between the second supply voltage and the ground potential, thereby switching the first inductor and generating the first output signal. The second switching control signal is selected as relating to the fourth PWM signal and controls the second switching voltage to toggle between the second supply voltage and the ground potential. A hybrid differential amplifier characterized in that the second supply voltage is lower than the first supply voltage. [Claim 2] The first triangular wave signal and the second triangular wave signal have a common-mode offset and have a first amplitude and a second amplitude, respectively. The hybrid differential amplifier according to claim 1, wherein the first amplitude is equal to or different from the second amplitude having a non-zero common-mode offset. [Claim 3] The hybrid differential amplifier according to claim 1, wherein the second switching voltage generates the second output signal by switching a second inductor having a smaller inductance than the first inductor, or corresponds to the second output signal. [Claim 4] The aforementioned path selection signal includes a light load selection signal and a level selection signal. The signal determination circuit generates the light load selection signal based on whether the differential input signal is within the light load range, and generates the level selection signal based on the first pulse width masking frequency doubling signal and the second pulse width masking frequency doubling signal. The hybrid differential amplifier according to claim 2, wherein the level selection signal indicates a comparison between the differential input signal and the input common-mode level. [Claim 5] The aforementioned signal determination circuit includes a flip-flop, The hybrid differential amplifier according to claim 4, wherein the flip-flop is configured to be reset based on the inverted signal of the second pulse width masking frequency doubling signal, and in a non-reset state, is configured to activate the level selection signal based on the trigger of the first pulse width masking frequency doubling signal. [Claim 6] The signal determination circuit further compares the offset triangular wave with the differential input signal to generate a fifth PWM signal and a sixth PWM signal. The offset triangular wave is configured to be obtained by superimposing the first triangular wave signal with a non-zero common-mode offset associated with the light load range. The hybrid differential amplifier according to claim 4, configured to periodically determine whether the fifth PWM signal and the sixth PWM signal each contain a pulse in the operating cycle immediately preceding the current operating cycle, based on the current operating cycle of the offset triangular wave, thereby determining whether the level of the differential input signal is within the light load range. [Claim 7] If the path selection signal indicates that the differential input signal is outside the light load range and greater than the input common-mode level, the signal selection circuit controls the first switching control signal to toggle based on the first pulse width masking frequency doubling signal, and controls the second switching control signal to toggle based on the second pulse width masking frequency doubling signal. The hybrid differential amplifier according to claim 4, wherein if the path selection signal indicates that the differential input signal is outside the light load range and is less than the input common-mode level, the signal selection circuit controls the first switching control signal to toggle based on the inverted signal of the second pulse width masking frequency doubling signal, and controls the second switching control signal to toggle based on the inverted signal of the first pulse width masking frequency doubling signal. [Claim 8] The hybrid differential amplifier according to claim 4, wherein, when the path selection signal indicates that the differential input signal is within the light load range, the signal selection circuit controls the first switching control signal to toggle based on the third PWM signal, and controls the second switching control signal to toggle based on the fourth PWM signal. [Claim 9] The system further includes a second masking frequency doubling circuit configured to generate a third pulse width masking frequency doubling signal and a fourth pulse width masking frequency doubling signal based on the third PWM signal and the fourth PWM signal. When the first input signal is positive, the third pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the third PWM signal; when the first input signal is negative, the third pulse width masking frequency doubling signal is 0. When the second input signal is positive, the fourth pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the fourth PWM signal; when the second input signal is negative, the fourth pulse width masking frequency doubling signal is 0. If the path selection signal indicates that the differential input signal is within the light load range and greater than the input common-mode level, the signal selection circuit controls the first switching control signal to toggle based on the third pulse width masking frequency doubling signal, and controls the second switching control signal to toggle based on the fourth pulse width masking frequency doubling signal. The hybrid differential amplifier according to claim 1, wherein, when the path selection signal indicates that the differential input signal is within the light load range and is less than the input common-mode level, the signal selection circuit controls the first switching control signal to toggle based on the inverted signal of the fourth pulse width masking frequency doubling signal, and controls the second switching control signal to toggle based on the inverted signal of the third pulse width masking frequency doubling signal. [Claim 10] The hybrid differential amplifier according to claim 1, wherein the first masking frequency doubling circuit generates a first pulse width masking frequency doubling signal by applying an AND logic operation to the inverted signal of the first PWM signal and the second PWM signal, and generates a second pulse width masking frequency doubling signal by applying an AND logic operation to the inverted signal of the first PWM signal and the second PWM signal. [Claim 11] The first masking frequency doubling circuit generates a first pulse width masking frequency doubling signal by applying an AND logic operation to the inverted signal of the first PWM signal and the second PWM signal, and generates a second pulse width masking frequency doubling signal by applying an AND logic operation to the inverted signal of the first PWM signal and the second PWM signal, The hybrid differential amplifier according to claim 9, wherein the second masking frequency doubling circuit generates a third pulse width masking frequency doubling signal by applying an AND logic operation to the inverted signal of the third PWM signal and the fourth PWM signal, and generates a fourth pulse width masking frequency doubling signal by applying an AND logic operation to the inverted signal of the third PWM signal and the fourth PWM signal. [Claim 12] The first power stage circuit includes a first main high-side transistor, a first auxiliary high-side transistor, and a first low-side transistor. The first main high-side transistor is coupled between the first supply voltage and the first switching node. The first auxiliary high-side transistor is coupled between the second supply voltage and the first switching node. The first low-side transistor is coupled between the first switching node and the ground potential. The first power stage circuit is configured to generate a first switching voltage based on a first switching control signal, thereby switching the first inductor, and converting the first supply voltage and the second supply voltage to generate the first output signal. The second power stage circuit includes a second main high-side transistor, a second auxiliary high-side transistor, and a second low-side transistor. The second main high-side transistor is coupled between the first supply voltage and the second switching node. The second auxiliary high-side transistor is coupled between the second supply voltage and the second switching node. The second low-side transistor is coupled between the second switching node and the ground potential. The hybrid differential amplifier according to claim 9, wherein the second power stage circuit is configured to switch based on the second switching control signal to convert the first supply voltage and the second supply voltage to generate the second output signal. [Claim 13] The system further includes an error amplifier configured to generate an error amplified signal based on the difference between a feedback signal associated with the second output signal and the second filtered signal. In the ultra-light load range, the signal selection circuit selects the error amplification signal and linearly controls the second main high-side transistor, adjusting the second output signal to be linearly related to the second filtered signal. The hybrid differential amplifier according to claim 12, wherein the ultra-light load range is a subset of the light load range and represents a state having a load level smaller than that in the light load range. [Claim 14] A hybrid differential amplification method for controlling a hybrid differential amplifier to generate a differential output signal based on a differential input signal to drive a load, wherein the differential input signal includes a first input signal and a second input signal, the differential output signal includes a first output signal and a second output signal, the differential input signal has an input common-mode level, and the hybrid differential amplification method is A first PWM (pulse width modulation) signal is generated by comparing a first triangular wave signal with a first filtered signal, and the first filtered signal is related to the first input signal and steps are performed. A second PWM signal is generated by comparing the first triangular wave signal with a second filtered signal, and the second filtered signal is related to the second input signal. A step of generating a third PWM signal by comparing a second triangular wave signal with the first filtered signal, A step of generating a fourth PWM signal by comparing the second triangular wave signal with the second filtered signal, Based on the first PWM signal and the second PWM signal, a first pulse width masking frequency doubling signal and a second pulse width masking frequency doubling signal are generated. When the first input signal is positive, the first pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the first PWM signal; when the first input signal is negative, the first pulse width masking frequency doubling signal is 0. The step is that when the second input signal is positive, the second pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the second PWM signal, and when the second input signal is negative, the second pulse width masking frequency doubling signal is 0. The steps include generating a path selection signal based on the range in which the level of the differential input signal exists, The steps of generating a first switching control signal and a second switching control signal based on the first pulse width masking frequency doubling signal, the second pulse width masking frequency doubling signal, the third PWM signal, and the fourth PWM signal in response to the path selection signal, The steps include generating a first switching voltage at a first switching node based on the first switching control signal, thereby switching a first inductor coupled to the first switching node to generate the first output signal, The steps include generating a second switching voltage at a second switching node based on the second switching control signal, thereby generating the second output signal, Includes, If the path selection signal indicates that the differential input signal is outside the light load range, the first switching control signal is selected as relating to the first pulse width masking frequency doubling signal having a first PWM characteristic, and controls the first switching voltage at the first switching node to toggle between the first supply voltage and ground potential; the second switching control signal is selected as relating to a signal approximating the fundamental frequency, and controls the second switching voltage at the second switching node to toggle between the first supply voltage and ground potential; and the differential input signal has the fundamental frequency. If the path selection signal indicates that the differential input signal is within the light load range, the first switching control signal is selected as relating to the third PWM signal and controls the first switching voltage to toggle between the second supply voltage and ground potential, thereby switching the first inductor and generating the first output signal; the second switching control signal is selected as relating to the fourth PWM signal and controls the second switching voltage to toggle between the second supply voltage and ground potential; A hybrid differential amplification method characterized in that the second supply voltage is lower than the first supply voltage. [Claim 15] The first triangular wave signal and the second triangular wave signal have a common-mode offset and have a first amplitude and a second amplitude, respectively. The hybrid differential amplifier method according to claim 14, wherein the first amplitude is equal to or different from the second amplitude having a non-zero common-mode offset. [Claim 16] The hybrid differential amplifier method according to claim 14, wherein the second switching voltage generates the second output signal by switching a second inductor having a smaller inductance than the first inductor, or corresponds to the second output signal. [Claim 17] The aforementioned path selection signal includes a light load selection signal and a level selection signal. The step of generating the path selection signal includes generating the light load selection signal based on whether the differential input signal is within the light load range, and generating the level selection signal based on the first pulse width masking frequency doubling signal and the second pulse width masking frequency doubling signal. The hybrid differential amplification method according to claim 15, wherein the level selection signal indicates a comparison between the differential input signal and the input common-mode level. [Claim 18] The step of generating the level selection signal is: The level selection signal is reset based on the inverted signal of the second pulse width masking frequency doubling signal, In the non-reset state, the level selection signal is activated based on the trigger of the first pulse width masking frequency doubling signal, The hybrid differential amplification method according to claim 17, including the method described in claim 17. [Claim 19] The step of generating the light load selection signal is: The offset triangular wave is compared with the differential input signal to generate a fifth PWM signal and a sixth PWM signal, and the offset triangular wave is obtained by superimposing the first triangular wave signal with a non-zero common-mode offset associated with the light load range. Based on the current operating cycle of the offset triangular wave, it is periodically determined whether each of the fifth PWM signal and the sixth PWM signal contains a pulse in the operating cycle immediately preceding the current operating cycle, thereby determining whether the level of the differential input signal is within the light load range. The hybrid differential amplification method according to claim 17, including the method described in claim 17. [Claim 20] The step of generating the level selection signal is: When the path selection signal indicates that the differential input signal is outside the light load range and greater than the input common-mode level, the first switching control signal is controlled to toggle based on the first pulse width masking frequency doubling signal, and the second switching control signal is controlled to toggle based on the second pulse width masking frequency doubling signal. When the path selection signal indicates that the differential input signal is outside the light load range and is smaller than the input common-mode level, the first switching control signal is controlled to toggle based on the inverted signal of the second pulse width masking frequency doubling signal, and the second switching control signal is controlled to toggle based on the inverted signal of the first pulse width masking frequency doubling signal. The hybrid differential amplification method according to claim 17, including the method described in claim 17. [Claim 21] The hybrid differential amplifier method according to claim 17, wherein the step of generating the first switching control signal and the second switching control signal includes controlling the first switching control signal to toggle based on the third PWM signal and controlling the second switching control signal to toggle based on the fourth PWM signal when the path selection signal indicates that the differential input signal is within the light load range. [Claim 22] The method further includes generating a third pulse width masking frequency doubling signal and a fourth pulse width masking frequency doubling signal based on the third PWM signal and the fourth PWM signal, When the first input signal is positive, the third pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the third PWM signal; when the first input signal is negative, the third pulse width masking frequency doubling signal is 0. When the second input signal is positive, the fourth pulse width masking frequency doubling signal corresponds to the frequency doubling signal of the fourth PWM signal; when the second input signal is negative, the fourth pulse width masking frequency doubling signal is 0. If the path selection signal indicates that the differential input signal is within the light load range and greater than the input common-mode level, the first switching control signal is controlled to toggle based on the third pulse width masking frequency doubling signal, and the second switching control signal is controlled to toggle based on the fourth pulse width masking frequency doubling signal. The hybrid differential amplifier method according to claim 14, wherein when the path selection signal indicates that the differential input signal is within the light load range and is less than the input common-mode level, the first switching control signal is controlled to toggle based on the inverted signal of the fourth pulse width masking frequency doubling signal, and the second switching control signal is controlled to toggle based on the inverted signal of the third pulse width masking frequency doubling signal. [Claim 23] The step of generating the first pulse width masking frequency doubling signal and the second pulse width masking frequency doubling signal is: The first pulse width masking frequency doubling signal is generated by applying an AND logic operation to the inverted signals of the first PWM signal and the second PWM signal, The second pulse width masking frequency doubling signal is generated by applying an AND logic operation to the inverted signal of the first PWM signal and the second PWM signal, The hybrid differential amplification method according to claim 14, including the method described in claim 14. [Claim 24] The step of generating the first pulse width masking frequency doubling signal and the second pulse width masking frequency doubling signal is: The first pulse width masking frequency doubling signal is generated by applying an AND logic operation to the inverted signals of the first PWM signal and the second PWM signal, The second pulse width masking frequency doubling signal is generated by applying an AND logic operation to the inverted signal of the first PWM signal and the second PWM signal, Includes, The step of generating the third pulse width masking frequency doubling signal and the fourth pulse width masking frequency doubling signal is: The third pulse width masking frequency doubling signal is generated by applying an AND logic operation to the third PWM signal and the inverted signal of the fourth PWM signal, The inverted signal of the third PWM signal and the fourth PWM signal are subjected to an AND logic operation to generate the fourth pulse width masking frequency doubling signal, The hybrid differential amplification method according to claim 22, including the method described in claim 22. [Claim 25] The method further includes generating an error amplification signal based on the difference between the feedback signal associated with the second output signal and the second filtered signal, In the ultra-light load range, the error amplification signal is selected to linearly adjust the second output signal so that it is linearly related to the second filtered signal. The hybrid differential amplifier method according to claim 22, wherein the ultra-light load range is a subset of the light load range and represents a state having a load level smaller than that in the light load range.

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