Semiconductor device and method for manufacturing the same

Abstract

To suppress the decrease in field-effect mobility in a semiconductor device containing an oxide semiconductor layer. [Solution] The semiconductor device includes a first gate electrode, a first insulating layer on the first gate electrode, a first oxide semiconductor layer on the first insulating layer, a second oxide semiconductor layer on the first oxide semiconductor layer that is in contact with the first oxide semiconductor layer, a source electrode and a drain electrode that are in contact with the respective end faces of the first oxide semiconductor layer and the second oxide semiconductor layer, and a second insulating layer that covers the source electrode and the drain electrode, wherein the second oxide semiconductor layer includes a first region having a first film thickness and a second region having a second film thickness smaller than the first film thickness, and the upper surface of the first region is in contact with one of the source electrode and the drain electrode.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device using an oxide semiconductor. [Background technology]

[0002] In recent years, the development of semiconductor devices using oxide semiconductor films has progressed as an alternative to silicon semiconductor films using amorphous silicon, low-temperature polysilicon, and single-crystal silicon (see, for example, Patent Documents 1 to 6). Semiconductor devices containing oxide semiconductor films have a simple structure and can be manufactured using low-temperature processes, similar to semiconductor devices containing amorphous silicon films. Furthermore, semiconductor devices containing oxide semiconductor films are known to have higher field-effect mobility than semiconductor devices containing amorphous silicon films. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-141338 [Patent Document 2] Japanese Patent Publication No. 2014-099601 [Patent Document 3] Japanese Patent Publication No. 2021-153196 [Patent Document 4] Japanese Patent Publication No. 2018-006730 [Patent Document 5] Japanese Patent Publication No. 2016-184771 [Patent Document 6] Japanese Patent Publication No. 2021-108405 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In semiconductor devices having a so-called channel etch structure, where an oxide semiconductor layer is etched during the formation of the source and drain electrodes, the desired electrical characteristics may not be obtained due to the influence of the etched back channel. Therefore, it is desirable to suppress the decrease in field-effect mobility in semiconductor devices containing an oxide semiconductor layer and having a channel etch structure.

[0005] In view of the above-mentioned problems, one embodiment of the present invention aims to suppress a decrease in field-effect mobility in a semiconductor device that includes an oxide semiconductor layer and has a channel etch structure. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a first gate electrode, a first insulating layer on the first gate electrode, a first oxide semiconductor layer on the first insulating layer, a second oxide semiconductor layer on the first oxide semiconductor layer that is in contact with the first oxide semiconductor layer, a source electrode and a drain electrode that are in contact with the respective end faces of the first oxide semiconductor layer and the second oxide semiconductor layer, and a second insulating layer that covers the source electrode and the drain electrode, wherein the second oxide semiconductor layer includes a first region having a first film thickness and a second region having a second film thickness smaller than the first film thickness, the upper surface of the first region is in contact with one of the source electrode and the drain electrode, and the upper surface of the second region is in contact with the second insulating layer.

[0007] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming a first gate electrode on a substrate, forming a first insulating layer on the first gate electrode, depositing a first oxide semiconductor layer on the first insulating layer, depositing a second oxide semiconductor layer in contact with the first oxide semiconductor layer, patterning the first oxide semiconductor layer and the second oxide semiconductor layer together so that they have island shapes of substantially the same size, performing heat treatment on the first oxide semiconductor layer and the second oxide semiconductor layer to form source electrodes and drain electrodes in contact with the respective end faces of the first oxide semiconductor layer and the second oxide semiconductor layer, thereby forming a first region having a first film thickness and a second region having a second film thickness smaller than the first film thickness in the second oxide semiconductor layer, and forming a second insulating layer so as to cover the source electrodes and drain electrodes, wherein the upper surface of the first region is in contact with one of the source electrodes and drain electrodes, and the upper surface of the second region is in contact with the second insulating layer. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic cross-sectional view showing the configuration of a semiconductor device relating to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional enlargement view showing the configuration of a semiconductor device relating to one embodiment of the present invention. [Figure 3] This is a schematic plan view showing the configuration of a semiconductor device relating to one embodiment of the present invention. [Figure 4] This is a schematic plan view showing the configuration of a semiconductor device relating to one embodiment of the present invention. [Figure 5] This is a schematic plan view showing the configuration of a semiconductor device relating to one embodiment of the present invention. [Figure 6] This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configurations of the embodiments while maintaining the gist of the invention are naturally included in the scope of the present invention. For the sake of clarity in the explanation, the drawings may be schematically represented in terms of the width, thickness, shape, etc. of the components compared to the actual aspect. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and the drawings, components similar to those described above with respect to the previously presented drawings may be denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upward." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." Thus, for the sake of explanation, the terms "up" and "downward" are used, but the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in the opposite direction to that shown in the illustration. Also, the expression "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer, and other components may be placed between the substrate and the oxide semiconductor layer. Up and down refer to the stacking order in a structure in which multiple layers are stacked, and when we say "pixel electrode above the semiconductor device," the semiconductor device and the pixel electrode may not overlap in a plan view. On the other hand, when we say "pixel electrode vertically above the semiconductor device," it means that the semiconductor device and the pixel electrode overlap in a plan view. A plan view refers to viewing from a direction perpendicular to the surface of the substrate.

[0011] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise explicitly stated. Furthermore, these expressions do not exclude cases where α includes other components.

[0012] In this specification, "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are included as forms of semiconductor devices. The semiconductor devices of the embodiments shown below may be, for example, integrated circuits (ICs) such as display devices and microprocessors (MPUs), or transistors used in memory circuits.

[0013] In this specification, "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, in the embodiments, liquid crystal display devices including a liquid crystal layer and organic EL display devices including an organic EL layer are described as examples. However, the structures described in the embodiments can be applied to other display devices including electro-optical layers as described above.

[0014] In this specification, the terms "membrane" and "layer" may be interchangeable as appropriate.

[0015] The source and drain electrodes of a transistor may have their functions reversed depending on the voltage supplied to each electrode. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchangeable as needed. Similarly, in this specification, the terms "source region" and "drain region" may be interchangeable as needed.

[0016] Furthermore, the following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0017] [1. Configuration of semiconductor device 10] Figure 1 is a schematic cross-sectional view showing the configuration of a semiconductor device 10 according to one embodiment of the present invention.

[0018] As shown in Figure 1, the semiconductor device 10 includes a substrate 100, a first gate electrode 110, a first insulating layer 120, a first oxide semiconductor layer 130, a second oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a second insulating layer 170, and a second gate electrode 180. The first gate electrode 110 is provided on the substrate 100. The first insulating layer 120 covers the first gate electrode 110 and is provided on the substrate 100. The first oxide semiconductor layer 130 is superimposed on the first gate electrode 110 and is provided on the first insulating layer 120. The second oxide semiconductor layer 140 is superimposed on the first gate electrode 110 and is provided on the first oxide semiconductor layer 130. The source electrode 150 and the drain electrode 160 are in contact with the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 and are provided on the first insulating layer 120. The second insulating layer 170 covers the first oxide semiconductor layer 130, the second oxide semiconductor layer 140, the source electrode 150, and the drain electrode 160, and is provided on top of the first insulating layer 120. The second gate electrode 180 is provided on top of the second insulating layer 170, superimposed on the first gate electrode 110, the first oxide semiconductor layer 130, and the second oxide semiconductor layer 140.

[0019] The first insulating layer 120 and the second insulating layer 170 can function as gate insulating layers. In the semiconductor device 10, the first gate electrode 110 is located below the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 via the first insulating layer 120, and the second gate electrode 180 is located above the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 via the second insulating layer 170. That is, the semiconductor device 10 is a so-called dual-gate transistor. Different voltages may be applied to the first gate electrode 110 and the second gate electrode 180, or the first gate electrode 110 and the second gate electrode 180 may be electrically connected and the same voltage may be applied to them.

[0020] Although the semiconductor device 10 shown in FIG. 1 is a dual-gate transistor, in this embodiment, a so-called bottom-gate transistor in which only the first gate electrode 110 is located via the first insulating layer 120 below the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 can also be applied as the semiconductor device 10.

[0021] [2. Components of the semiconductor device 10] [2-1. Substrate 100] As the substrate 100, for example, a rigid substrate having translucency such as a glass substrate, a quartz substrate, or a sapphire substrate can be used. Also, as the substrate 100, a rigid substrate having no translucency such as a silicon substrate can be used. Further, as the substrate 100, a flexible substrate having translucency such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate can be used. In order to improve the heat resistance of the substrate 100, impurities may be introduced into the above-described flexible substrate. Note that a substrate on which an oxide insulating film or a nitride insulating film is formed on the above-described rigid substrate or flexible substrate can also be used as the substrate 100. As the oxide insulating film, silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ) etc. can be used. Also, as the nitride insulating film, silicon nitride (SiN x ) or silicon oxynitride (SiN x O y ) etc. can be used. Here, SiO x N y is a silicon compound containing nitrogen (N) in a ratio (x>y) less than that of oxygen (O). SiN x O y is a silicon compound containing oxygen in a ratio (x>y) less than that of nitrogen.

[0022] [2-2. The first gate electrode 110 and the second gate electrode 180] For each of the first gate electrode 110 and the second gate electrode 180, a metallic material such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys thereof, can be used. The alloy is, for example, molybdenum tungsten (MoW), but is not limited thereto. The first gate electrode 110 and the second gate electrode 180 may have a single-layer structure or a multilayer structure.

[0023] The first gate electrode 110 or the second gate electrode 180 can also function as a light-shielding film. In this case, in a plan view, it is preferable that the first gate electrode 110 or the second gate electrode 180 overlaps the entirety of the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140.

[0024] [2-3. First insulating layer 120 and second insulating layer 170] Each of the first insulating layer 120 and the second insulating layer 170 may have a single-layer structure, but it is preferable that they have a laminated structure. The first insulating layer 120 preferably has a laminated structure in which an oxide insulating film 124 is laminated on a nitride insulating film 122. In this case, the nitride insulating film 122 is in contact with the first gate electrode 110, and the oxide insulating film 124 is in contact with the first oxide semiconductor layer 130. The second insulating layer 170 preferably has a laminated structure in which a nitride insulating film 174 is laminated on an oxide insulating film 172. In this case, the oxide insulating film 172 is in contact with the end face of the first oxide semiconductor layer 130 and the end face and top surface of the second oxide semiconductor layer 140, and the nitride insulating film 174 is in contact with the second gate electrode 180. As the oxide insulating films 124 and 172, silicon oxide (SiO₂) is used. x ) or silicon oxide nitride (SiO x N y ) and the like can be used. Also, silicon nitride (SiN) can be used as nitride insulating film 122 and 174. x ) or silicon nitride (SiN x O y) and the like can be used. For example, the film thickness of the first insulating layer 120 is 100 nm or more and 900 nm or less, preferably 200 nm or more and 600 nm or less. When the first insulating layer 120 has such a large film thickness, the carrier concentration induced in the first oxide semiconductor layer 130 by the gate voltage of the first gate electrode 110 becomes small.

[0025] [2-4. Source electrode 150 and drain electrode 160] The same metallic materials as those used for the first gate electrode 110 and the second gate electrode 180 can be used for the source electrode 150 and the drain electrode 160. The source electrode 150 and the drain electrode 160 may have a single-layer structure or a multilayer structure. The source electrode 150 and the drain electrode 160 are in contact not only with the first oxide semiconductor layer 130 but also with the second oxide semiconductor layer 140.

[0026] [2-5. First oxide semiconductor layer 130 and second oxide semiconductor layer 140] The semiconductor device 10 includes a stacked structure in which a second oxide semiconductor layer 140 is stacked on top of a first oxide semiconductor layer 130. Details of the stacked structure will be explained with reference to Figure 2.

[0027] Figure 2 is a schematic enlarged cross-sectional view showing the configuration of a semiconductor device 10 according to one embodiment of the present invention. Specifically, Figure 2 is an enlarged cross-sectional view of the semiconductor device 10, showing region A in Figure 1.

[0028] At least a portion of the respective end faces of the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 is covered by the source electrode 150 or the drain electrode 160. A recess is formed on the upper surface of the second oxide semiconductor layer 140, and the second oxide semiconductor layer 140 includes a first region 142 and a second region 144 with different film thicknesses. The first region 142 and the second region 144 have a first film thickness t1 and a second film thickness t2, respectively. The second film thickness t2 is smaller than the first film thickness t1. The upper surface of the first region 142 is in contact with the source electrode 150 or the drain electrode 160 and is covered by the source electrode 150 or the drain electrode 160. The upper surface of the second region 144 is in contact with the second insulating layer 170 (more specifically, the oxide insulating film 172) and is covered by the second insulating layer 170. In other words, the first region 142 overlaps with the source electrode 150 or the drain electrode 160, while the second region 144 does not overlap with the source electrode 150 or the drain electrode 160.

[0029] As will be described in detail later, when the source electrode 150 and drain electrode 160 are patterned, the upper surface of the second oxide semiconductor layer 140 is etched, and a recess is formed. As a result, the second region 144 has a second film thickness t2 that is smaller than the first film thickness t1. For example, the first film thickness t1 corresponds to the film thickness of the second oxide semiconductor layer 140 when it is deposited. The first film thickness t1 is 20 nm or more and 200 nm or less, preferably 20 nm or more and 150 nm or less, and more preferably 20 nm or more and 100 nm or less. If the first film thickness t1 is too small, when the source electrode 150 and drain electrode 160 are patterned, the second region 144 will disappear, and the first oxide semiconductor layer 130 will be exposed. If the first film thickness t1 is too large, not only will the deposition of the second oxide semiconductor layer 140 take longer, but the patterning of the second oxide semiconductor layer 140 will also take longer. The second film thickness t2 can be controlled by the over-etching time during patterning of the source electrode 150 and the drain electrode 160. The second film thickness t2 should be sufficient to adequately cover the upper surface of the first oxide semiconductor layer 130. For example, the second film thickness t2 is greater than 0 nm and less than or equal to 100 nm, preferably between 5 nm and 70 nm, and more preferably between 5 nm and 50 nm. If the second film thickness t2 is too large, oxygen vacancies in the second region 144 cannot be adequately repaired, and the conductivity of the second region 144 becomes high.

[0030] Figures 3 to 5 are schematic plan views showing the configuration of a semiconductor device according to one embodiment of the present invention. Specifically, Figures 3 to 5 show a second oxide semiconductor layer 140, as well as a source electrode 150 and a drain electrode 160 superimposed on the second oxide semiconductor layer 140.

[0031] Each of the source electrode 150 and the drain electrode 160 may be formed to completely cover one side of the second oxide semiconductor layer 140 (see Figure 3). In this case, the second region 144 is formed between the source electrode 150 and the drain electrode 160 (i.e., between the two first regions 142). Alternatively, each of the source electrode 150 and the drain electrode 160 may be formed to cover a portion of one side of the second oxide semiconductor layer 140 (see Figure 4). In this case, the second region 144 is formed not only between the source electrode 150 and the drain electrode 160 (i.e., between the two first regions 142) but also around the source electrode 150 and the drain electrode 160. Furthermore, the source electrode 150 and the drain electrode 160 can be formed so that multiple second regions 144-1 and 144-2 are formed (see Figure 5). In this case, a second region 144-1 is formed between the source electrode 150 and the drain electrode 160 (i.e., between the two first regions 142), and a second region 144-2 is formed outside the source electrode 150 and the drain electrode, respectively.

[0032] The first oxide semiconductor layer 130 contains indium (In).

[0033] The second oxide semiconductor layer 140 preferably also contains indium. However, the ratio of indium to all metal elements in the second oxide semiconductor layer 140 is smaller than the ratio of indium to all metal elements in the first oxide semiconductor layer 130. Furthermore, the second oxide semiconductor layer 140 preferably contains metal elements not included in the first oxide semiconductor layer.

[0034] The third film thickness t3 of the first oxide semiconductor layer 130 is not particularly limited. For example, the third film thickness t3 is 15 nm or more and 150 nm or less, preferably 15 nm or more and 125 nm or less, and more preferably 15 nm or more and 100 nm or less. If the third film thickness t3 is too large, oxygen vacancies in the first oxide semiconductor layer 130 may not be reduced, and the desired electrical properties may not be obtained.

[0035] The third film thickness t3 is preferably greater than the second film thickness t2. When the third film thickness t3 is greater than the second film thickness t2, the main channels are formed in the first oxide semiconductor layer 130, thus increasing the field-effect mobility. Alternatively, the third film thickness t3 may be smaller than the first film thickness t1. Or, the third film thickness t3 may be greater than or equal to the difference in film thickness between the first film thickness t1 and the second film thickness t2. In this case, the number of electrons injected from the source electrode 150 into the first region 142 increases and flows through the first oxide semiconductor layer 130, thus increasing the field-effect mobility.

[0036] A transistor in which the upper surface of an oxide semiconductor layer (sometimes called the back channel) is etched is called a channel-etched transistor. In other words, the semiconductor device 10 can suppress the decrease in field-effect mobility by reducing the effect of the back channel by providing a second oxide semiconductor layer 140 with a lower indium content than the first oxide semiconductor layer 130 on the back channel side of the first oxide semiconductor layer 130.

[0037] [3. Method for manufacturing semiconductor device 10] Figure 6 is a flowchart illustrating a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. Figures 7 to 14 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. Below, each step of the flowchart shown in Figure 6 will be described in order.

[0038] In step S100, a first gate electrode 110 is formed on the substrate 100 (see Figure 7). The first gate electrode 110 is formed by depositing a conductive film by sputtering, and then patterning it into a predetermined shape using photolithography.

[0039] In step S110, a first insulating layer 120 is formed on the first gate electrode 110 (see Figure 8). If the first insulating layer 120 has a multilayer structure, the first insulating layer 120 is formed by depositing a nitride insulating film 122 and an oxide insulating film 124 by CVD.

[0040] In step S120, a first oxide semiconductor layer 130 is deposited on the first insulating layer 120 (see Figure 9). The first oxide semiconductor layer 130 is deposited by sputtering.

[0041] When a film is deposited on an object by sputtering, ions generated in the plasma and atoms recoiling from the sputtering target collide with the object, causing the temperature of the object to rise during the deposition process.

[0042] In the sputtering process, a first oxide semiconductor layer 130 having an amorphous structure is formed under conditions where the oxygen partial pressure is 10% or less.

[0043] In step S120, a second oxide semiconductor layer 140 is deposited on the first oxide semiconductor layer 130 (see Figure 10). The second oxide semiconductor layer 140 is deposited by sputtering.

[0044] In step S130, the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 are patterned together (see Figure 11). The first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 are formed using photolithography to have an island-shaped stacked structure. For example, a resist mask (not shown) is formed on the second oxide semiconductor layer 140, and the second oxide semiconductor layer 140 and the first oxide semiconductor layer 130 are etched sequentially using the resist mask. As a result, the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 have island shapes of approximately the same size. Wet etching or dry etching may be used for etching the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140. For wet etching, etching can be performed using an acidic etching solution. For example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid can be used as the etching solution.

[0045] In step S150, the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 are subjected to heat treatment (OS annealing) (see Figure 12). During OS annealing, the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 are held at a predetermined temperature for a predetermined time. The predetermined temperature is 300°C or higher and 500°C or lower, preferably 350°C or higher and 450°C or lower. The holding time at the temperature is 15 minutes or higher and 120 minutes or lower, preferably 30 minutes or higher and 60 minutes or lower.

[0046] The proportion of indium to all metal elements in the second oxide semiconductor layer 140 is smaller than the proportion of indium to all metal elements in the first oxide semiconductor layer 130.

[0047] In step S160, the source electrode 150 and the drain electrode 160 are formed so as to be in contact with the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 (see Figure 13). The source electrode 150 and the drain electrode 160 are formed by depositing a conductive film by sputtering and then patterning it into a predetermined shape using photolithography. Wet etching or dry etching may be used for etching the source electrode 150 and the drain electrode 160. When the source electrode 150 and the drain electrode 160 are etched, the upper surface of the second oxide semiconductor layer 140 is also etched, and a recess is formed. That is, the second oxide semiconductor layer 140 is formed with a first region 142 that overlaps with the source electrode 150 or the drain electrode 160 and a second region 144 that does not overlap with the source electrode 150 and the drain electrode 160. Since the second region 144 corresponds to the region where the recess is formed, the second film thickness t2 in the second region 144 is smaller than the first film thickness t1 in the first region 142 (see Figure 2).

[0048] Many defects are generated on the upper surface of the second region 144 by etching the source electrode 150 and the drain electrode 160. This is more pronounced when dry etching is used. The resist mask formed during patterning of the source electrode 150 and the drain electrode 160 is removed by the stripping solution. At this time, the upper surface of the second region 144 is exposed to the stripping solution. The oxide semiconductor contained in the second oxide semiconductor layer 140 can be etched near the surface by the stripping solution. Therefore, in step S160, even if many defects are generated on the upper surface of the second region 144, the area near the surface containing many defects can be etched by the stripping solution. As a result, the semiconductor device 10 can reduce defects on the upper surface of the second region 144, i.e., the back channel.

[0049] In step S170, a second insulating layer 170 is formed on the source electrode 150 and the drain electrode 160 (see Figure 14). If the second insulating layer 170 has a laminated structure, the second insulating layer 170 is formed by depositing an oxide insulating film 172 and a nitride insulating film 174 by CVD.

[0050] In step S170, it is preferable that the heat treatment (oxidation annealing) is performed with the second insulating layer 170 covering the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140. Oxidation annealing can repair oxygen vacancies in the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140. In particular, in oxidation annealing, if the oxide insulating film 172 is in contact with the second region 144 of the second oxide semiconductor layer 140, oxygen is supplied from the oxide insulating film 172 to the second region 144, and oxygen vacancies in the back channel can be efficiently repaired. In step S170, oxidation annealing may be performed after the oxide insulating film 172 is formed, and then the nitride insulating film 174 may be formed.

[0051] The oxide annealing may be performed with a metal oxide film deposited on the oxide insulating film 172. The deposition of the metal oxide film suppresses the release of oxygen from the oxide insulating film 172 to the outside. The metal oxide film is removed after the oxide annealing. As the metal oxide film, aluminum oxide (AlO) x ), indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO) can be used. For example, the thickness of the metal oxide film is 1 nm to 50 nm, preferably 1 nm to 30 nm.

[0052] In step S180, a second gate electrode 180 is formed on the second insulating layer 170. The second gate electrode 180 is formed by depositing a conductive film by sputtering and then patterning it into a predetermined shape using photolithography.

[0053] By following the steps described above, the semiconductor device 10 shown in Figure 1 can be manufactured.

[0054] According to this embodiment, when the semiconductor device 10 having a channel etch structure includes an oxide semiconductor layer having a polycrystalline structure, the decrease in field-effect mobility can be suppressed. Furthermore, variations in the electrical characteristics of the semiconductor device 10 can be reduced, and the manufacturing yield of the semiconductor device 10 can be improved.

[0055] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on these embodiments, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0056] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0057] 100: Circuit board 110: First gate 120: First insulating layer 122: Nitride insulating film 124: Oxide insulating film 130: First oxide semiconductor layer 140: Second oxide semiconductor layer 142: The First Domain 144: The Second Domain 150: Source electrode 160: Drain electrode 170: Second insulating layer 172: Oxide insulating film 174: Nitride insulating film 180: Second gate electrode

Claims

1. The first gate electrode and A first insulating layer on the first gate electrode, The first oxide semiconductor layer on the first insulating layer, On the first oxide semiconductor layer, a second oxide semiconductor layer in contact with the first oxide semiconductor layer, Source electrodes and drain electrodes in contact with the respective end faces of the first oxide semiconductor layer and the second oxide semiconductor layer, It includes a second insulating layer covering the source electrode and the drain electrode, The second oxide semiconductor layer includes a first region having a first film thickness and a second region having a second film thickness smaller than the first film thickness. The upper surface of the first region is in contact with one of the source electrode and the drain electrode, The upper surface of the second region is in contact with the second insulating layer, and the semiconductor device.

2. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer has an amorphous structure.

3. The first oxide semiconductor layer has a third film thickness, The semiconductor device according to claim 1, wherein the third film thickness is greater than the second film thickness.

4. The semiconductor device according to claim 3, wherein the third film thickness is smaller than the first film thickness.

5. The semiconductor device according to claim 3, wherein the third film thickness is greater than or equal to the difference in film thickness between the first film thickness and the second film thickness.

6. Each of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium, The semiconductor device according to claim 1, wherein the ratio of indium to all metal elements in the second oxide semiconductor layer is smaller than the ratio of indium to all metal elements in the first oxide semiconductor layer.

7. Furthermore, the semiconductor device according to claim 1, further comprising a second gate electrode on the second insulating layer.

8. The second insulating layer has a laminated structure in which an oxide insulating film and a nitride insulating film are stacked. The oxide insulating film is in contact with the second oxide semiconductor layer, The semiconductor device according to claim 7, wherein the nitride insulating film is in contact with the second gate electrode.

9. A first gate electrode is formed on the substrate. A first insulating layer is formed on the first gate electrode, A first oxide semiconductor layer is formed on the first insulating layer. A second oxide semiconductor layer is formed so as to be in contact with the first oxide semiconductor layer. The first oxide semiconductor layer and the second oxide semiconductor layer are patterned together such that they have island shapes of substantially the same size. The first oxide semiconductor layer and the second oxide semiconductor layer are subjected to heat treatment. Source electrodes and drain electrodes are formed in contact with the respective end faces of the first oxide semiconductor layer and the second oxide semiconductor layer, thereby forming a first region having a first film thickness and a second region having a second film thickness smaller than the first film thickness in the second oxide semiconductor layer. This includes forming a second insulating layer so as to cover the source electrode and the drain electrode, The upper surface of the first region is in contact with one of the source electrode and the drain electrode, A method for manufacturing a semiconductor device, wherein the upper surface of the second region is in contact with the second insulating layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the second oxide semiconductor layer has an amorphous structure.

11. The first oxide semiconductor layer has a third film thickness, The method for manufacturing a semiconductor device according to claim 9, wherein the third film thickness is greater than the second film thickness.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the third film thickness is smaller than the first film thickness.

13. The method for manufacturing a semiconductor device according to claim 11, wherein the third film thickness is greater than or equal to the difference in film thickness between the first film thickness and the second film thickness.

14. Each of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium, The method for manufacturing a semiconductor device according to claim 9, wherein the ratio of indium to all metal elements in the second oxide semiconductor layer is smaller than the ratio of indium to all metal elements in the first oxide semiconductor layer.

15. Furthermore, the method for manufacturing a semiconductor device according to claim 9, wherein a second gate electrode is formed on the second insulating layer.

16. The second insulating layer has a laminated structure in which an oxide insulating film and a nitride insulating film are stacked. The oxide insulating film is in contact with the second oxide semiconductor layer, The method for manufacturing a semiconductor device according to claim 15, wherein the nitride insulating film is in contact with the second gate electrode.

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