Memory device and method for manufacturing the same

Abstract

The present invention provides a memory device and a method for manufacturing the same that improve the support effect of the support structure and simplify the manufacturing process of the support structure. [Solution] A memory device according to an embodiment of the present invention includes contacts and support structures disposed around the contacts, each of the support structures may have a configuration in which support holes overlap. The support structures may include insulating films embedded inside the support holes that overlap each other. The support structures can be formed by expanding each of the first openings and causing them to overlap each other. Three or more support structures may be disposed around any one of the contacts.

Description

Technical Field

[0001] The present invention relates to a memory device and a method for manufacturing the same, and more particularly, to a memory device including a support structure and a method for manufacturing the same.

Background Art

[0002] The memory device can include a nonvolatile memory device in which data stored is maintained even when the power supply is cut off. The nonvolatile memory device can be classified into a two-dimensional structure or a three-dimensional structure according to the structure in which memory cells are arranged. The memory cells of the nonvolatile memory device having a two-dimensional structure can be arranged in a single layer on a substrate, and the memory cells of the nonvolatile memory device having a three-dimensional structure can be stacked vertically on the substrate. Recently, electronic devices using nonvolatile memory devices having a three-dimensional structure have increased because the integration degree of nonvolatile memory devices having a three-dimensional structure is higher than that of nonvolatile memory devices having a two-dimensional structure.

[0003] On the other hand, as the integration degree of the nonvolatile memory device having a three-dimensional structure increases, the necessity of a support structure for supporting the vertically stacked material films so as not to bend has become apparent.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a memory device and a method for manufacturing the same that can improve the supporting effect of a support structure and simplify the process of manufacturing the support structure.

Means for Solving the Problems

[0005] The memory device according to an embodiment of the present invention includes a contact and a support structure disposed around the contact, and each of the support structures can have a form in which support holes overlap.

[0006] A method for manufacturing a memory device according to an embodiment of the present invention may include the steps of: forming a laminate including sacrificial films and interlayer insulating films alternately stacked along a first direction; forming a first opening penetrating the laminate; forming a contact opening in the sacrificial film that extends from the first sacrificial film in the first direction; forming support holes around the contact openings by expanding each of the first openings so that they overlap each other; and filling the interiors of the overlapping support holes with insulating films to form a support structure. [Effects of the Invention]

[0007] This technology improves the support effect of support structures and simplifies the manufacturing process by improving the manufacturing process and structure of the support structure. [Brief explanation of the drawing]

[0008] [Figure 1] This is a diagram illustrating a memory device according to an embodiment of the present invention. [Figure 2] This is a diagram illustrating a memory device according to an embodiment of the present invention. [Figure 3a] This is a diagram illustrating a memory device including a support structure according to an embodiment of the present invention. [Figure 3b] This is a diagram illustrating a memory device including a support structure according to an embodiment of the present invention. [Figure 4a] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4b] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4c] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4d] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4e]This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4f] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4g] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4h] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4i] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4j] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4k] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4l] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 4m] This figure illustrates a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. [Figure 5a] This figure illustrates a memory device including a support structure and support columns according to an embodiment of the present invention. [Figure 5b] This figure illustrates a memory device including a support structure and support columns according to an embodiment of the present invention. [Figure 6a] This figure illustrates a method for manufacturing a memory device including a support structure and support columns according to an embodiment of the present invention. [Figure 6b] This figure illustrates a method for manufacturing a memory device including a support structure and support columns according to an embodiment of the present invention. [Figure 6c] This figure illustrates a method for manufacturing a memory device including a support structure and support columns according to an embodiment of the present invention. [Figure 6d]A diagram for explaining a method of manufacturing a memory device including a support structure and support pillars according to an embodiment of the present invention. [Figure 6e] A diagram for explaining a method of manufacturing a memory device including a support structure and support pillars according to an embodiment of the present invention. [Figure 6f] A diagram for explaining a method of manufacturing a memory device including a support structure and support pillars according to an embodiment of the present invention. [Figure 6g] A diagram for explaining a method of manufacturing a memory device including a support structure and support pillars according to an embodiment of the present invention. [Figure 7a] A diagram for explaining the forms and arrangements of support structures according to various embodiments of the present invention. [Figure 7b] A diagram for explaining the forms and arrangements of support structures according to various embodiments of the present invention. [Figure 7c] A diagram for explaining the forms and arrangements of support structures according to various embodiments of the present invention. [Figure 7d] A diagram for explaining the forms and arrangements of support structures according to various embodiments of the present invention. [Figure 7e] A diagram for explaining the forms and arrangements of support structures according to various embodiments of the present invention. [Figure 7f] A diagram for explaining the forms and arrangements of support structures according to various embodiments of the present invention. [Figure 8] A diagram for explaining a memory card system to which the memory device of the present invention is applied. [Figure 9] A diagram for explaining an SSD (Solid State Drive) system to which the memory device of the present invention is applied.

Mode for Carrying Out the Invention

[0009] The specific structural or functional descriptions of embodiments of the concept of the present invention disclosed herein or in the application are illustrative only for the purpose of illustrating embodiments of the concept of the present invention, and embodiments of the concept of the present invention can be carried out in various forms and should not be construed as being limited to the embodiments described herein or in the application.

[0010] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to explain in detail to the extent that a person with ordinary skill in the art to which the present invention pertains can implement the technical idea of ​​the present invention.

[0011] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present invention.

[0012] Referring to Figure 1, the memory device 100 may include a memory cell array 110, a peripheral circuit 170, and a control circuit 180.

[0013] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may contain a memory cell capable of storing data. Each of the first to i-th memory blocks BLK1 to BLKi may be connected to a drain selection line DSL, a word line WL, a source selection line SSL, and a source line SL, and a bit line BL may be connected to all of the first to i-th memory blocks BLK1 to BLKi in common.

[0014] The first to i-th memory blocks BLK1 to BLKi can be formed in a three-dimensional structure. A memory block having a three-dimensional structure may include memory cells stacked perpendicular to the substrate.

[0015] Memory cells can store one bit or two or more bits of data, depending on the programming method. For example, a method in which one bit of data is stored in a single memory cell is called a single-level cell method, and a method in which two bits of data are stored is called a multi-level cell method. A method in which three bits of data are stored in a single memory cell is called a triple-level cell method, and a method in which four bits of data are stored is called a quad-level cell method. In addition, it is also possible to store five bits or more of data in a single memory cell.

[0016] The peripheral circuit 170 can be configured to perform a program operation to store data in the memory cell array 110, a read operation to output the data stored in the memory cell array 110, and an erase operation to erase the data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0017] The voltage generator 120 can generate various operating voltages Vop used for program, read, or erase operations in response to the operation code OPCD. For example, the voltage generator 120 can be configured to generate program voltages, turn-on voltages, turn-off voltages, negative voltages, precharge voltages, verify voltages, read voltages, pass voltages, or erase voltages in response to the operation code OPCD. The operating voltages Vop generated by the voltage generator 120 can be applied to the drain selection line DSL, word line WL, source selection line SSL, and source line SL of the selected memory block via the row decoder 130.

[0018] The program voltage is a voltage applied to a selected word line WL during a program operation and can be used to increase the threshold voltage of the memory cell connected to the selected word line. The turn-on voltage can be applied to the drain selection line DSL or source selection line SSL and can be used to turn on the drain selection transistor or source selection transistor. The turn-off voltage can be applied to the drain selection line DSL or source selection line SSL and can be used to turn off the drain selection transistor or source selection transistor. For example, the turn-off voltage can be set to 0V. The precharge voltage is a voltage higher than 0V and can be applied to the bit line during a read operation. The verification voltage can be used during a verification operation to determine whether the threshold voltage of the selected memory cell has risen to a target level. The verification voltage can be set to various levels depending on the target level and can be applied to the selected word line.

[0019] The read voltage can be applied to the selected word line during a read operation of the selected memory cell. For example, the read voltage can be set to various levels depending on the programming method of the selected memory cell. The pass voltage is a voltage applied to the unselected word line WL during a program or read operation and can be used to turn on the memory cell connected to the unselected word line. The erase voltage can be used during an erase operation to erase the memory cells contained in the selected memory block and can be applied to the source line SL.

[0020] The row decoder 130 can be configured to transmit an operating voltage Vop to a drain selection line DSL, a word line WL, a source selection line SSL, and a source line SL connected to a memory block selected according to the row address RADD. For example, the row decoder 130 can be connected to a voltage generator 120 via global lines, and can be connected to the first to i-th memory blocks BLK1 to BLKi via the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0021] The page buffer group 140 may include page buffers (not shown) connected to the first to i-th memory blocks BLK1 to BLKi, respectively. Each of the page buffers (not shown) may be connected to the first to i-th memory blocks BLK1 to BLKi via a bit line BL. During a read operation, the page buffer (not shown) can sense the current or voltage of a bit line that varies according to the threshold voltage of a selected memory cell in response to the page buffer control signal PBSIG, and temporarily store the sensed data.

[0022] The column decoder 150 can be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 can be connected to the page buffer group 140 via column lines CL, and an enable signal can be transmitted via column lines CL. The page buffer (not shown) included in the page buffer group 140 can receive or output data via data lines DL in response to the enable signal.

[0023] The input / output circuit 160 can be configured to receive or output commands CMD, addresses ADD, or data via input / output line I / O. For example, the input / output circuit 160 can transmit commands CMD and addresses ADD received from an external controller via input / output line I / O to the control circuit 180, and can transmit data received from an external controller via input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 can output data transmitted from the page buffer group 140 to an external controller via input / output line I / O.

[0024] The control circuit 180 can output at least one of the following in response to a command CMD and an address ADD: an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, or a column address CADD. For example, if the command CMD input to the control circuit 180 corresponds to a program operation, the control circuit 180 can control the peripheral circuit 170 to execute a program operation on the memory block selected by address ADD. If the command CMD input to the control circuit 180 corresponds to a read operation, the control circuit 180 can control the peripheral circuit 170 to execute a read operation on the memory block selected by address and output the read data. If the command CMD input to the control circuit 180 corresponds to an erase operation, the control circuit 180 can control the peripheral circuit 170 to execute an erase operation on the selected memory block.

[0025] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present invention.

[0026] Referring to Figure 2, the memory device 100 may include a peripheral circuit structure PC and memory blocks BLK1 to BLKi arranged on a substrate SUB. The memory blocks BLK1 to BLKi can be superimposed on the peripheral circuit structure PC.

[0027] The substrate SUB can be a single-crystal semiconductor film. For example, the substrate SUB can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth.

[0028] The peripheral circuit structure PC may include a row decoder 130, a column decoder 150, a page buffer group 140, and a control circuit 180, which constitute a circuit for controlling the operation of memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors that are electrically connected to memory blocks BLK1 to BLKi. The peripheral circuit structure PC can be placed between the substrate SUB and the memory blocks BLK1 to BLKi.

[0029] Each of the memory blocks BLK1 to BLKi may include a source structure, a bit line, a cell string electrically connected to the source structure and bit line, a word line electrically connected to the cell string, and a selection line electrically connected to the cell string. Each cell string may include a memory cell and a selection transistor connected in series by a cell plug. Each selection line may be used as the gate electrode of its corresponding selection transistor, and each word line may be used as the gate electrode of its corresponding memory cell.

[0030] In another embodiment, the substrate SUB, peripheral circuit structure PC, and memory blocks BLK1 to BLKi can be stacked in the reverse order of the order shown in Figure 2. For example, the peripheral circuit structure PC can be placed on top of the memory blocks BLK1 to BLKi.

[0031] In another embodiment, unlike that shown in Figure 2, the peripheral circuit structure PC can also be arranged on a portion of the substrate SUB that does not overlap with the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC and the memory blocks BLK1 to BLKi can be arranged on separate, non-overlapping regions of the substrate SUB.

[0032] Figures 3a and 3b are diagrams illustrating a memory device including a support structure according to an embodiment of the present invention. Figure 3a is a plan view showing the layout of the memory device according to an embodiment of the present invention. Figure 3b is a cross-sectional view showing the section A-A' in Figure 3a.

[0033] Referring to Figure 3a, the memory device 100 may include a cell area CR and a contact area CTR. The contact area CTR may be located in the X direction of the cell area CR. The contact area CTR may extend from the cell area CR in the X direction. Unlike the illustration in Figure 3a, the contact area CTR may extend from the cell area CR in the Y direction, or in both the X and Y directions. In addition, the cell area CR and the contact area CTR can be arranged in various ways.

[0034] Cell plugs (CPLs) can be located in the cell area CR. Cell plugs (CPLs) can be arranged along the X and Y directions. Cell plugs (CPLs) can be spaced apart from each other in the X and Y directions. Each cell plug (CPL) can extend in the Z direction. Each cell plug (CPL) can be electrically connected to a bit line (e.g., bit line BL in Figure 1) and a source line (e.g., source line SL in Figure 1) via a wiring structure.

[0035] Each cell plug CPL may include a memory membrane ML, a channel membrane CH, and a gap fill membrane GF. The memory membrane ML may have a cylindrical shape. The memory membrane ML may enclose the periphery of the channel membrane CH. Although not shown, the memory membrane ML may include a blocking membrane, a charge trapping membrane, and a tunneling membrane. The channel membrane CH may be formed along the inner wall of the memory membrane ML. The gap fill membrane GF may fill the interior of the channel membrane CH. The gap fill membrane GF may have a cylindrical shape surrounded by the channel membrane CH.

[0036] The blocking and tunneling films included in the memory film ML can be formed from oxide films (e.g., silicon oxide films) or oxidnitride films (e.g., silicon oxidnitride films), or a combination thereof. The charge trap film included in the memory film ML may include nitride films or variable resistive materials. The channel film CH can be formed from undoped silicon films or doped silicon films. The gap fill film GF can be formed from insulating films (e.g., oxide films).

[0037] A contact CT can be located in the contact region CTR. Multiple contacts can be arranged within the contact region CTR, and only some of these contact CTs are shown in Figure 3a. A contact CT can extend in the Z direction. A contact CT can contain conductive material. A contact CT can also be called a contact plug.

[0038] The spacer SPA can surround the sides of the contact CT. The contact CT can fill the interior of the spacer SPA. The spacer SPA can be formed from an insulating film. For example, the spacer SPA can include an oxide film.

[0039] The support structure SS can be located in the contact area CTR. The support structure SS can be positioned around the contact CT. For example, the support structure SS can be positioned in the X direction, Y direction, opposite direction to the X direction, and opposite direction to the Y direction of the contact CT. The support structures SS can be spaced apart from each other. The support structures SS can be positioned in contact with the spacer STA. Each portion of the support structure SS can be superimposed on the contact CT in the Z direction. The support structure SS can contain insulating material.

[0040] Each of the support structures SS may have a configuration in which support holes SH are superimposed. Any one of the support structures SS may have a configuration in which two or more support holes SH are superimposed on each other. For example, in Figure 3a, each of the support structures SS may have a configuration in which four support holes SH are superimposed. Each of the support structures SS may include an insulating film (e.g., an oxide film) embedded inside the superimposed support holes SH.

[0041] In this disclosure, the superimposed form of support holes SH can mean a state in which the support holes are connected to each other by removing the side walls between them. Alternatively, the superimposed form of support holes SH can mean that there is a region in the xy plane that each support hole SH has in common. In Figure 3a, four support holes SH forming a rectangle are shown to be superimposed, but this is just one example and the scope of rights of this disclosure is not limited to this. For example, a support structure SS can have a form in which two, three, or five or more support holes SH are superimposed. This will be discussed later with reference to Figures 7a to 7f. To give another example, a support structure SS can have a form in which four support holes SH are superimposed, but two of the four support holes SH in a particular combination may not be superimposed. This will be discussed later with reference to Figures 7e and 7f. To give yet another example, a support structure SS can have a form in which support holes SH are not rectangular but arranged in a row.

[0042] Referring to Figure 3b, the memory device 100 may include a laminate STK. The laminate STK may include a conductive film CD and an interlayer insulating film IIL. The conductive film CD and the interlayer insulating film IIL may be alternately laminated along the Z direction. The laminate STK may further include an upper insulating film UIL. The conductive film CD may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (poly-Si). The conductive film CD may correspond to gate lines (e.g., drain selection line DSL, word line WL, source selection line SSL in Figure 1). The interlayer insulating film IIL may be formed of an oxide film (e.g., silicon oxide film). The upper insulating film UIL may be formed of the same material as the interlayer insulating film IIL.

[0043] Cell plugs (CPLs) can penetrate the cell regions (CR) of the stacked material (STK). Each cell plug (CPL) may contain a memory film (ML), a channel film (CH), and a gap fill film (GF). Memory cells and selection transistors can be formed where the cell plugs (CPLs) and the conductive film (CD) intersect, respectively. Cell plugs (CPLs) can be used as channel regions in cell strings.

[0044] The support structure SS can penetrate the contact region CTR of the laminate STK. The support structure SS can extend in the Z direction. The support structure SS can have a configuration in which support holes SH overlap each other. Figure 3b corresponds to the A-A' section of Figure 3a, and shows the two support holes SH contained in each support structure SS. Since the two support holes SH contained in each support structure SS overlap each other, there can be no side walls between the support holes SH. Contrary to the illustration in Figure 3b, there may be side walls (e.g., part of the laminate STK) between the two support holes SH contained in each support structure SS. For example, if the distance between the support holes SH is greater than that shown in Figure 3b, part of the laminate STK may remain between the support holes SH. This will be discussed later with reference to Figure 7e. To give another example, there may be no side walls at the top of the support holes SH, and there may be side walls at the bottom of the support holes SH. The support structure SS can fill the support holes SH that overlap each other.

[0045] The contact CT can extend in the Z direction within the contact region CTR of the laminate STK. The contact CT can extend in the Z direction from the first conductive film CD1 among the conductive films CD contained in the laminate STK. The lower surface of the contact CT can be in contact with a portion of the upper surface of the first conductive film CD1. The contact CT can be electrically connected to the first conductive film CD1. Figure 3b shows the A-A' section of Figure 3a, and is shown not to extend into the cell region CR in contact with the contact CT. However, referring to Figure 3a as well, the first conductive film CD1 connected to the contact CT can be connected to the cell region CR via an electrical path located between the support structures SS.

[0046] The sides of the contact CT may include an uneven surface. The contact CT may include protrusions that project toward the conductive film CD. The protrusions of the contact CT may be positioned at a level corresponding to the conductive film CD.

[0047] The spacer SPA can surround the sides of the contact CT. The spacer SPA can extend along the protrusions of the contact CT. The spacer SPA can have a recessed structure corresponding to the shape of the contact CT. The spacer SPA can include protrusions and recesses. The protrusions of the spacer SPA can be located at a level corresponding to the conductive film CD, and the recesses can be located at a level corresponding to the interlayer insulating film ILL. The spacer SPA can insulate the contact CT from other conductive films CD other than the first conductive film CD1. For example, the spacer SPA can separate the contact CT from a conductive film CD located above the first conductive film CD1.

[0048] The support structure SS can contact a portion of the outer surface of the spacer SPA. Referring to Figures 3a and 3b, the support structure SS can contact a portion of the outer surface of the spacer SPA located in the X direction, the Y direction, the opposite direction of the X direction, and the opposite direction of the Y direction, respectively. For example, the support structure SS can contact a portion of the outer side surface of the spacer SPA and a portion of the bottom surface.

[0049] The support structure SS can contact a portion of the lower surface of the contact CT. A portion of the lower surface of the contact CT can contact the first conductive film CD1, and the remaining portion can contact the support structure SS. When viewed from the Z direction, the support structure SS can be superimposed on the contact CT.

[0050] The shape of the support hole SH that is positioned closest to the contact CT can be determined by the shapes of the contact CT and the spacer SPA. Details regarding the shapes of the support structure SS and the support holes SH will be described later with reference to Figures 4a to 4m.

[0051] Figures 4a to 4m illustrate a method for manufacturing a memory device including a support structure according to an embodiment of the present invention. Figures 4a to 4m show a plan view from the Z direction and a cross-sectional view corresponding to the A-A' section of each plan view at each stage of the manufacturing process of the memory device 100.

[0052] Referring to Figure 4a, a pre-laminate pSTK can be formed, comprising alternately stacked interlayer insulating films IIL and sacrificial films SF. An upper insulating film UIL can be stacked on top of the interlayer insulating films IIL and sacrificial films SF. The interlayer insulating film IIL can be formed from an insulating material. For example, the interlayer insulating film IIL can be formed from an oxide film (e.g., silicon oxide film). The upper insulating film UIL may contain the same material as the interlayer insulating film IIL. The sacrificial film SF can be formed from a material that can be selectively removed in a subsequent process. The sacrificial film SF can be formed from a material with a different etching selectivity ratio than the interlayer insulating film IIL. For example, the sacrificial film SF can be formed from a nitride film.

[0053] Next, a channel opening CHH and a first opening OP1 can be formed that penetrate the pre-laminated pSTK. The channel opening CHH can penetrate the cell region CR of the pre-laminated pSTK. The first opening OP1 can penetrate the contact region CTR of the pre-laminated pSTK. The channel opening CHH and the first opening OP1 can have a hole shape. For example, the planar shape of the channel opening CHH and the first opening OP1 can be circular or elliptical.

[0054] The channel opening CHH and the first opening OP1 can be formed simultaneously. For example, instead of forming the channel opening CHH and the first opening OP1 in separate etching processes, they can be formed together through either one of the etching processes. The first opening OP1 can be formed simultaneously with the channel opening CHH through a process in which openings with a high aspect ratio are etched simultaneously. By etching openings with a high aspect ratio simultaneously, the cost and time required for the etching process can be reduced. An anisotropic dry etching process can be performed to form the channel opening CHH and the first opening OP1 at specific locations.

[0055] In one embodiment, the channel opening CHH and the first opening OP1 may have equal planar areas. In another embodiment, the channel opening CHH and the first opening OP1 may have different planar areas.

[0056] Referring to Figure 4b, a first sacrificial column SFP1 can be formed inside the channel opening CHH and the first opening OP1. The first sacrificial column SFP1 can fill the channel opening CHH and the first opening OP1. The first sacrificial column SFP1 may include a carbon film. For example, the first sacrificial column SFP1 may be formed of a carbon film, include a carbon film and polysilicon, or include a carbon film and a metal nitride (e.g., TiN).

[0057] Referring to Figure 4c, the first sacrificial column SFP1 inside the channel opening CHH can be removed. Next, a cell plug CPL can be formed inside the channel opening CHH. Along the inner surface of the channel opening CHH, the memory film ML, the channel film CH, and the gap fill film GF can be formed sequentially.

[0058] Referring to Figure 4d, a contact opening CTH can be formed within the contact region CTR of the pre-laminate pSTK. The contact opening CTH can expose the first sacrificial film SF of the sacrificial film SF. The contact opening CTH can extend in the Z direction from the first sacrificial film SF. The contact opening CTH can expose the upper surface of the first sacrificial film SF.

[0059] To form the contact opening CTH, a process of alternately removing the interlayer insulating film IIL and the sacrificial film SF can be performed. A process of sequentially etching the oxide film and nitride film can be performed so that the contact opening CTH is formed to a specific depth (e.g., the depth corresponding to the first sacrificial film SF1). Because the etching process is performed in multiple stages, the planar area of ​​the contact opening CTH can be larger than that of the channel opening CHH or the first opening OP1.

[0060] The contact opening CTH can be separated from the first opening OP1. The first sacrificial column SFP1 inside the first opening OP1 can not be exposed through the contact opening CTH.

[0061] Referring to Figure 4e, a portion of the sacrificial film SF can be etched through the contact opening CTH. A portion of the side surface of the sacrificial film SF exposed through the contact opening CTH can be etched to form a recess RC. The sacrificial film SF exposed by the contact opening CTH can be recessed to prevent defects in which the conductive films CD, which are arranged in the Z direction in a subsequent process, become linked to each other. Unlike the illustration in Figure 4e, a portion of the upper surface of the first sacrificial film SF1 can be further etched.

[0062] Referring to Figure 4f, a liner film LL can be formed along the inner surface of the contact opening CTH. The liner film LL can extend along the side and bottom surfaces of the contact opening CTH. The liner film LL can be formed on the side surface of the pre-laminate pSTK exposed through the contact opening CTH. The liner film LL can be formed conformally along the recess RC of the sacrificial film SF. The liner film LL may contain at least one material from TiN, SiCN, or polysilicon.

[0063] Referring to Figure 4g, a second sacrificial column SFP2 can be formed inside the contact opening CTH. The second sacrificial column SFP2 can fill the contact opening CTH. The second sacrificial column SFP2 can be surrounded by a liner film LL. The second sacrificial column SFP2 can be separated from the pre-laminate pSTK by the liner film LL. The second sacrificial column SFP2 may contain at least one of a carbon film or polysilicon.

[0064] Next, the first sacrificial column SFP1 inside the first opening OP1 can be removed. By removing the first sacrificial column SFP1, the first opening OP1 can be opened again. The first opening OP1 can be located around the contact opening CTH.

[0065] Referring to Figure 4h, each of the first openings OP1 can be expanded to form support holes SH. A portion of the interlayer insulating film IIL and sacrificial film SF of the pre-laminate pSTK can be removed through the first openings OP1. The sides of the interlayer insulating film IIL and sacrificial film SF exposed through the first openings OP1 can be etched to expand the first openings OP1. To expand the volume of the first openings OP1, a wet etching process or a dry etching process can be performed.

[0066] When the first opening OP1 is expanded, the support holes SH can overlap each other. For example, the sidewalls between the support holes SH can be removed by gradually etching the interlayer insulating film IIL and sacrificial film SF located between the first openings OP1. The support holes SH can overlap each other to form a single space. For example, the support holes SH formed by the expansion of four first openings OP1 located in the X direction of the contact opening CTH can form a single space. Therefore, the planar shape of the overlapping support holes SH can be in the form of multiple circles or ellipses overlapping each other. The degree of expansion of the first openings OP1 (e.g., time, etchant concentration, etc.) can be controlled so that the support holes SH can overlap each other. For example, the degree of expansion of the first openings OP1 can be determined such that the support holes SH located in the X direction of the contact opening CTH overlap each other, but the support holes SH located in the X direction and the support holes SH located in the Y direction of the contact opening CTH do not overlap each other.

[0067] While the first opening OP1 is expanding, the liner film LL can be used as an etching stop film. The liner film LL prevents the support hole SH from expanding into the interior of the contact opening CTH. Therefore, a portion of the side surface of the liner film LL can be exposed by the support hole SH. To separate the contact opening CTH from the support hole SH, the liner film LL can be formed on the inner surface of the contact opening CTH.

[0068] The first opening OP1 can be expanded to such an extent that the support hole SH exposes the lower surface of the contact opening CTH. The support hole SH can extend toward the bottom of the contact opening CTH. A portion of the support hole SH can overlap the contact opening CTH in the Z direction. That is, the distance between the support hole SH tangent to the contact opening CTH in the X direction and the support hole SH tangent to the contact opening CTH in the Y direction can be smaller than the width of the contact opening CTH in the X direction. To improve the support performance of the support structure embedded inside the support hole SH (e.g., the support structure SS in Figures 3a and 3b), the support hole SH can extend toward the bottom of the contact opening CTH. Thus, a portion of the lower surface of the liner film LL can be exposed by the support hole SH.

[0069] Referring to Figure 4i, support structures SS can be formed inside the superimposed support holes SH. The support structures SS may include insulating films embedded inside the superimposed support holes SH. Each of the support structures SS can be formed by depositing an oxide material inside the superimposed support holes SH using a thermal ALD (atomic layer deposition) method.

[0070] Referring to Figure 4j, the second sacrificial column SFP2 and the liner film LL can be removed from inside the contact opening CTH. Next, a spacer film SPL can be formed along the inner surface of the contact opening CTH. The spacer film SPL can extend along the sides and bottom surfaces of the contact opening CTH. The spacer film SPL may contain an insulating material. For example, the spacer film SPL may contain an oxide film. Next, a third sacrificial column SFP3 can be formed within the contact opening CTH. The third sacrificial column SFP3 can be separated from the pre-laminate pSTK by the spacer film SPL. The third sacrificial column SFP3 may contain a carbon film.

[0071] Referring to Figure 4k, the sacrificial film SF of the pre-laminate pSTK can be removed. The sacrificial film SF can be etched through a slit (not shown) penetrating the pre-laminate pSTK. By removing the sacrificial film SF, a gap can be formed between the interlayer insulating films IIL. According to this disclosure, since the support structure SS supports the interlayer insulating films IIL which are separated from each other, bending of the interlayer insulating films IIL can be reduced. In particular, the larger the planar area of ​​the contact opening CTH, the greater the risk of bending of the interlayer insulating films IIL located below the contact opening CTH. However, according to this disclosure, since the support structure SS extends below the contact opening CTH, the support performance of the support structure SS can be improved.

[0072] Next, a conductive film CD can be formed in the space where the sacrificial film SF was removed. The conductive film CD can fill the space located between the interlayer insulating film IIL. Therefore, the sacrificial film SF can be replaced by the conductive film CD. For example, the first sacrificial film SF1 can be replaced by the first conductive film CD1.

[0073] Referring to Figure 4l, the third sacrificial column SFP3 inside the contact opening CTH can be removed. Next, the lower surface of the spacer film SPL can be removed to form the spacer SPA. The spacer SPA can extend along the inner side surface of the contact opening CTH. By removing the lower surface of the spacer film SPL, the upper surface of the first conductive film CD1 can be exposed through the contact opening CTH. Also, a portion of the support structure SS can be exposed through the contact opening CTH.

[0074] Referring to Figure 4m, a contact CT can be formed inside the contact opening CTH. For example, a contact CT can be formed by embedding a conductive material inside the contact opening CTH. The contact CT can be electrically connected to the first conductive film CD1.

[0075] Figures 5a and 5b are diagrams illustrating a memory device including a support structure and support columns according to an embodiment of the present invention. Figure 5a is a plan view showing the layout of the memory device according to an embodiment of the present invention. Figure 5b is a cross-sectional view showing the section B-B' in Figure 5a.

[0076] With regard to Figures 5a and 5b, the configuration described in Figures 3a and 3b can be briefly explained or omitted.

[0077] Referring to Figures 5a and 5b, the memory device 100 may include cell plugs CPL. The cell plugs CPL can be placed in the cell region CR. The cell plugs CPL can penetrate the cell region CR of the laminate STK. Each of the cell plugs CPL may include a memory film ML, a channel film CH, and a gap fill film GF.

[0078] The memory device 100 may include a contact CT and a spacer SPA arranged in a contact area CTR. The contact CT can contact the first conductive film CD1 of the conductive film CD of the laminate STK. The contact CT can be electrically connected to the first conductive film CD1. The spacer SPA can insulate the contact CT from other conductive films CD other than the first conductive film CD1.

[0079] The memory device 100 may include a support structure SS positioned around the contact CT. The support structure SS may penetrate the contact area CTR of the laminate STK. The support structure SS may be in contact with the outer surface of the spacer SPA. The support structure SS may be in contact with a portion of the lower surface of the contact CT.

[0080] In one embodiment, three support structures SS can be arranged around the contact CT. Each of the support structures SS may have a configuration in which two or more support holes SH overlap. Each of the support structures SS may include an insulating film embedded inside the overlapping support holes SH. The configuration of each of the support structures SS is not limited by the illustrations in Figures 5a and 5b.

[0081] When three support structures SS are arranged around a contact CT, the spacing between them can be wider compared to when four or more support structures SS are arranged around a contact CT. When three support structures SS are arranged around a contact CT, support columns SP can be placed between each of the support structures SS. For example, three support columns SP can be placed between each of the three support structures SS.

[0082] The support column SP can be positioned in the contact area CTR. The support column SP can extend in the Z direction within the laminate STK. The support column SP can penetrate the contact area CTR of the laminate STK. The support column SP can be separated from the contact CT, spacer SPA, and support structure SS. The support column SP can have the same planar area as the cell plug CPL.

[0083] The support column SP may have a structure similar to that of the cell plug CPL. The support column SP may include a dummy memory film DML, a dummy channel film DCH, and a dummy gap fill film DGF. The dummy memory film DML may have a cylindrical shape. The dummy memory film DML may enclose the periphery of the dummy channel film DCH. Although not shown, the dummy memory film DML may include a dummy blocking film, a dummy charge trap film, and a dummy tunnel insulating film. The dummy channel film DCH may be formed along the inner wall of the dummy memory film DML. The dummy gap fill film DGF may fill the interior of the dummy channel film DCH. The dummy gap fill film DGF may have a cylindrical shape surrounded by the dummy channel film DCH.

[0084] The dummy blocking film, dummy charge trap film, and dummy tunnel insulating film included in the dummy memory film DML may contain the same materials as the blocking film, charge trap film, and tunnel insulating film included in the memory film ML, respectively. The dummy channel film DCH may contain the same materials as the channel film CH. The dummy gap fill film DGF may contain the same materials as the gap fill film GF.

[0085] Figures 6a to 6g illustrate a method for manufacturing a memory device including a support structure and support columns according to an embodiment of the present invention. Figures 6a to 6g show a plan view from the Z direction and a cross-sectional view corresponding to the B-B' section of each plan view at each stage of the manufacturing process of the memory device 100.

[0086] With regard to Figures 6a to 6g, the configuration described in Figures 4a to 4m can be briefly explained or omitted.

[0087] Referring to Figure 6a, a pre-laminate pSTK can be formed, which includes alternately stacked interlayer insulating films IIL and sacrificial films SF. An upper insulating film UIL can then be stacked on top of the interlayer insulating films IIL and sacrificial films SF.

[0088] Next, a channel opening CHH, a first opening OP1, and a second opening OP2 can be formed, penetrating the pre-laminated pSTK. The channel opening CHH can penetrate the cell region CR of the pre-laminated pSTK. The first opening OP1 and the second opening OP2 can penetrate the contact region CTR of the pre-laminated pSTK. The channel opening CHH, the first opening OP1, and the second opening OP2 can have a hole shape. For example, the planar shapes of the channel opening CHH, the first opening OP1, and the second opening OP2 can be circular or elliptical.

[0089] The channel opening CHH, the first opening OP1, and the second opening OP2 can be formed simultaneously. For example, instead of forming the channel opening CHH, the first opening OP1, and the second opening OP2 in separate etching steps, they can be formed together through any one of the etching steps. The first opening OP1 and the second opening OP2 can be formed simultaneously with the channel opening CHH through a process in which openings with a high aspect ratio are etched simultaneously. By etching openings with a high aspect ratio simultaneously, the cost and time required for the etching process can be reduced. An anisotropic dry etching process can be performed to form the channel opening CHH, the first opening OP1, and the second opening OP2 at specific locations.

[0090] In one embodiment, the channel opening CHH, the first opening OP1, and the second opening OP2 may have equal planar areas. In another embodiment, the channel opening CHH, the first opening OP1, and the second opening OP2 may have different planar areas.

[0091] The spacing between the second openings OP2 can be greater than the spacing between the channel openings CHH. Similarly, the spacing between the second openings OP2 can be greater than the spacing between the first openings OP1.

[0092] Referring to Figure 6b, a first sacrificial column SFP1 can be formed inside the channel opening CHH, the first opening OP1, and the second opening OP2. The first sacrificial column SFP1 can fill the channel opening CHH, the first opening OP1, and the second opening OP2, respectively. The first sacrificial column SFP1 may include a carbon film. For example, the first sacrificial column SFP1 may be formed of a carbon film, include a carbon film and polysilicon, or include a carbon film and a metal nitride (e.g., TiN).

[0093] Referring to Figure 6c, the first sacrificial column SFP1 inside the channel opening CHH can be removed. Similarly, the first sacrificial column SFP1 inside the second opening OP2 can be removed. The process of removing the first sacrificial column SFP1 from the channel opening CHH and the second opening OP2 can be performed simultaneously. For example, the first sacrificial column SFP1 can be etched by an isotropic wet etching process.

[0094] Next, a cell plug CPL and a support column SP can be formed in the channel opening CHH and the second opening OP2, respectively. While the cell plug CPL is being formed inside the channel opening CHH, the support column SP can be formed inside the second opening OP2.

[0095] For example, a memory film ML can be formed on the inner surface of the channel opening CHH. A dummy memory film DML can also be formed on the inner surface of the second opening OP2. The dummy memory film DML may contain the same material as the memory film ML. The dummy memory film DML can be formed simultaneously with the memory film ML. For example, after a preliminary blocking film, a preliminary charge trap film, and a preliminary tunnel insulating film are formed on the preliminary laminate pSTK, a portion of the preliminary blocking film, a portion of the preliminary charge trap film, and a portion of the preliminary tunnel insulating film located on the preliminary laminate pSTK can be removed. Therefore, a portion of the preliminary blocking film, a portion of the preliminary charge trap film, and a portion of the preliminary tunnel insulating film remaining inside the channel opening CHH can constitute the memory film ML. Similarly, a portion of the preliminary blocking film, a portion of the preliminary charge trap film, and a portion of the preliminary tunnel insulating film remaining inside the second opening OP2 can constitute the dummy memory film DML.

[0096] Next, a channel membrane CH can be formed inside the channel opening CHH. A dummy channel membrane DCH can also be formed inside the second opening OP2. The channel membrane CH can be formed on the inner surface of the memory membrane ML, and the dummy channel membrane DCH can be formed on the inner surface of the dummy memory membrane DML. The dummy channel membrane DCH may contain the same material as the channel membrane CH (e.g., silicon). The dummy channel membrane DCH can be formed simultaneously with the formation of the channel membrane CH. For example, after polysilicon is formed on a pre-laminate pSTK on which the first opening OP1 and the second opening OP2 are formed, a portion of the polysilicon located on the pre-laminate pSTK can be removed. Therefore, a portion of the polysilicon remaining inside the channel opening CHH can constitute the channel membrane CH, and a portion of the polysilicon remaining inside the second opening OP2 can constitute the dummy channel membrane DCH.

[0097] Next, a gap fill membrane GF can be formed inside the channel opening CHH, and a dummy gap fill membrane DGF can be formed inside the second opening OP2. The gap fill membrane GF can be surrounded by the channel membrane CH. The dummy gap fill membrane DGF can be surrounded by the dummy channel membrane DCH. The memory membrane ML, the channel membrane CH, and the gap fill membrane GF can constitute a cell plug CPL. The dummy memory membrane DML, the dummy channel membrane DCH, and the dummy gap fill membrane DGF can form a support column SP.

[0098] The steps from Figure 6c onward can correspond to the steps described in Figures 4d to 4m. Therefore, explanations that overlap with those described in Figures 4d to 4m can be omitted.

[0099] Referring to Figure 6d, a contact opening CTH can be formed within the contact region CTR of the pre-laminated laminate pSTK. The contact opening CTH can expose the first sacrificial film SF of the sacrificial film SF. The planar area of ​​the contact opening CTH can be larger than that of the channel opening CHH, the first opening OP1, and the second opening OP2. The contact opening CTH can be spaced apart from the first opening OP1 and the support column SP.

[0100] Referring to Figure 6e, a portion of the sacrificial film SF can be etched through the contact opening CTH. Then, a liner film LL can be formed along the inner surface of the contact opening CTH. Also, a second sacrificial column SFP2 can be formed inside the contact opening CTH. Then, the first sacrificial column SFP1 inside the first opening OP1 can be removed. By removing the first sacrificial column SFP1, the first opening OP1 can be opened again.

[0101] Referring to Figure 6f, each of the first openings OP1 can be expanded to form support holes SH. Part of the interlayer insulating film IIL and sacrificial film SF of the pre-laminate pSTK can be removed through the first openings OP1. When the first openings OP1 are expanded, the support holes SH can be superimposed on each other. While the first openings OP1 are being expanded, the liner film LL can be used as an etching stop film. The first openings OP1 can be expanded to the extent that the support holes SH expose the lower surface of the contact opening CTH. The support holes SH can extend toward the bottom of the contact opening CTH.

[0102] Referring to Figure 6g, support structures SS can be formed inside the overlapping support holes SH. Next, the second sacrificial column SFP2 and liner film LL can be removed from inside the contact opening CTH, and a spacer film (e.g., spacer film SPL in Figure 4j) can be formed. Then, a third sacrificial column (e.g., third sacrificial column SFP3 in Figure 4j) can be formed inside the contact opening CTH.

[0103] Next, the sacrificial film SF of the pre-laminate pSTK can be removed. By removing the sacrificial film SF, a gap can be formed between the interlayer insulating films IIL. According to this disclosure, since the support structure SS and support column SP support the interlayer insulating films IIL which are separated from each other, the bending of the interlayer insulating films IIL can be reduced.

[0104] Next, a conductive film CD can be formed in the space where the sacrificial film SF was removed. For example, the first sacrificial film SF1 can be replaced by the first conductive film CD1.

[0105] Next, the third sacrificial column inside the contact opening CTH can be removed, and the lower surface of the spacer film SPL can be removed. Then, a contact CT surrounded by spacer SPA can be formed inside the contact opening CTH. The contact CT can be electrically connected to the first conductive film CD1.

[0106] Figures 7a to 7f illustrate the form and arrangement of support structures according to various embodiments of the present invention.

[0107] Figures 7a and 7c show various forms of the support structure SS when four support structures SS are arranged around the contact CT, as in Figure 3a. Figures 7b and 7d show various forms of the support structure SS when three support structures SS are arranged around the contact CT, as in Figure 5a. Figure 7e shows various forms that a support structure SS can have when four support holes SH overlap, as in Figures 3a and 5a. Figure 7f shows another embodiment in which four support holes SH included in the support structure SS overlap each other.

[0108] Referring to Figures 7a and 7b, each support structure SS can have a configuration in which two support holes SH are superimposed. The two support holes SH contained in each support structure SS can superimpose each other. For example, the support holes SH can form a single space that is connected to each other. The support holes SH can be formed by expanding the first opening (e.g., the first opening OP1 in Figures 4a and 6a). No laminate STK can remain between the two support holes SH.

[0109] Support holes SH can be arranged away from contact CT. Two overlapping support holes SH can be arranged in a line. For example, two support holes SH located in the X direction of contact CT can be arranged along the X direction. Also, two support holes SH located in the Y direction of contact CT can be arranged along the Y direction.

[0110] Referring to Figures 7c and 7d, each support structure SS can have a configuration in which three support holes SH are superimposed. The three support holes SH contained in each support structure SS can superimpose on each other. For example, there can be a region in which two arbitrarily selected support holes SH from the three support holes SH are commonly contained. Also, there can be a region in which all three support holes SH are commonly contained.

[0111] The support holes SH can be arranged to form a triangle. Three overlapping support holes SH can be arranged in the form of a triangle with one vertex close to the contact CT and two vertices away from the contact CT. In another embodiment, three overlapping support holes SH can also be arranged in the form of a triangle with two vertices close to the contact CT and one vertex away from the contact CT.

[0112] However, the illustrations in Figures 7c and 7d are illustrative and do not limit the scope of the rights of this disclosure. For example, of the three support holes SH included in each support structure SS, two support holes SH in one combination may overlap with each other, while two support holes SH in another combination may not overlap with each other. Another example is that each support structure SS may have a configuration in which three support holes SH arranged in a row overlap.

[0113] Figure 7e shows various ways in which the support holes SH are superimposed when the support structure SS has a configuration in which four support holes SH are superimposed.

[0114] In one embodiment, as shown in Figures 3a and 5a, the support structure SS can have a configuration in which four support holes SH overlap each other. For example, there can be a region in which two arbitrarily selected support holes SH from the four support holes SH are included in common. Also, there can be a region in which three arbitrarily selected support holes SH from the four support holes SH are included in common. Furthermore, there can be a region in which all four support holes SH are included in common.

[0115] In another embodiment, the support structure SS' may have a configuration in which parts of the four support holes SH overlap each other. For example, in one combination of the four support holes SH, there may be a region that all three support holes SH have in common, while in another combination of the three support holes SH, there may be no region that all three support holes SH have in common. Even in the case of the support structure SS', at least two of the support holes SH included in the support structure SS' overlap, and therefore it can be included within the scope of the rights of this specification.

[0116] In yet another embodiment, the support structure SS'' may have a configuration in which some of the four support holes SH overlap each other. For example, of the four support holes SH, two support holes SH in one combination may overlap each other, while two support holes SH in another combination may not overlap. Even in the case of the support structure SS'', ​​at least two of the support holes SH included in the support structure SS'' overlap, and therefore it can be included in the scope of the present invention.

[0117] Figure 7f shows yet another way in which the support holes SH overlap when the support structure SS has a configuration in which four support holes SH overlap. Referring to Figure 7f, the support holes SH can be arranged in a configuration surrounding the contact CT. Of the support holes SH, adjacent support holes SH may overlap each other, while non-adjacent support holes SH may not overlap each other. In addition to the illustration in Figure 7f, the support structure SS may be included in the scope of this disclosure as long as it has a configuration in which the support holes SH overlap.

[0118] Figure 8 is a diagram illustrating a memory card system to which the memory device of the present invention is applied.

[0119] Referring to Figure 8, the memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0120] The controller 3100 can be connected to the memory device 3200. The controller 3100 can be configured to access the memory device 3200. For example, the controller 3100 can be configured to control the program, read, or erase operations of the memory device 3200, or to control background operations. The controller 3100 can be configured to provide an interface between the memory device 3200 and the host. The controller 3100 can be configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0121] The controller 3100 can communicate with an external device via the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 is configured to communicate with an external device via at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, or NVMe. For example, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0122] The memory device 3200 may include multiple memory cells and can be configured similarly to the memory device 100 shown in Figure 1.

[0123] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to constitute a memory card such as a PC card (PCMCIA, personal computer memory card international association), CompactFlash® card (CF), SmartMedia card (SM, SMC), Memory Stick, Multimedia card (MMC, RS-MMC, MMCmicro, eMMC), SD card (SD, miniSD, microSD, SDHC), or Universal Flash Storage (UFS).

[0124] Figure 9 is a diagram illustrating an SSD (Solid State Drive) system to which the memory device of the present invention is applied.

[0125] Referring to Figure 9, the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 via a signal connector 4001 and can receive power via a power connector 4002. The SSD 4200 may include a controller 4210, multiple memory devices 4221-422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0126] The controller 4210 can control multiple memory devices 4221-422n in response to signals received from the host 4100. For example, the signals may be based on the interface between the host 4100 and the SSD 4200. For example, the signals may be defined by at least one of the following interfaces: USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, or NVMe.

[0127] The multiple memory devices 4221-422n may include multiple memory cells configured to store data. Each of the multiple memory devices 4221-422n can be configured similarly to the memory device 100 shown in Figure 1. The multiple memory devices 4221-422n can communicate with the controller 4210 via channels CH1-CHn.

[0128] The auxiliary power supply unit 4230 can be connected to the host 4100 via the power connector 4002. The auxiliary power supply unit 4230 can receive power voltage input from the host 4100 and be charged. The auxiliary power supply unit 4230 can provide power voltage to the SSD 4200 if the power supply from the host 4100 is not smooth. For example, the auxiliary power supply unit 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply unit 4230 can be located on the main board and provide auxiliary power to the SSD 4200.

[0129] The buffer memory 4240 can operate as a buffer memory for the SSD 4200. For example, the buffer memory 4240 can temporarily store data received from the host 4100 or data received from multiple memory devices 4221-422n, or it can temporarily store metadata (e.g., mapping tables) of the memory devices 4221-422n. The buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, or non-volatile memory such as FRAM®, ReRAM, STT-MRAM, or PRAM. [Explanation of Symbols]

[0130] 100 memory devices STK Laminate CD conductive film IIL Interlayer Insulation Film CR cell area CTR Contact Area CPL Cellplug ML memory membrane CH channel membrane GF gap fill membrane CT Contact SPA Spacer SS support structure SH Support Hole

Claims

1. Contact and; The contact includes a support structure arranged around the contact, Each of the aforementioned support structures has a configuration in which support holes are superimposed, in a memory device.

2. Each of the aforementioned support structures is The memory device according to claim 1, comprising an insulating film embedded inside the superimposed support holes.

3. Each of the aforementioned support structures is The two support holes are arranged in a manner that overlaps each other. The memory device according to claim 1, wherein the two support holes are arranged in a direction away from the contact.

4. Each of the aforementioned support structures is The three support holes are arranged in a manner that overlaps each other. The memory device according to claim 1, wherein the three support holes are arranged to form a triangle.

5. Each of the aforementioned support structures is At least two of the four support holes are arranged in a manner that overlaps, The memory device according to claim 1, wherein the four support holes are arranged to form a square.

6. Each of the aforementioned support structures is At least two of the four support holes are arranged in a manner that overlaps, The memory device according to claim 1, wherein the four support holes are arranged to surround the contact.

7. The laminate further includes conductive films and interlayer insulating films that are alternately stacked along a first direction, The contact extends from the first conductive film in the first direction among the conductive films, The memory device according to claim 1, wherein the support structure penetrates the laminate in the first direction.

8. The lower surface of the contact is in contact with the first conductive film, as described in claim 7.

9. The invention further includes a spacer that surrounds the side surface of the contact, The memory device according to claim 7, wherein the spacer separates the contact from the conductive film disposed on the first conductive film among the conductive films.

10. The aforementioned support structure is A portion of the outer surface of the spacer is in contact with it, The memory device according to claim 9, which is in contact with a part of the lower surface of the contact.

11. The memory device according to claim 1, wherein four or more of the support structures are arranged around the contact.

12. Three of the support structures are arranged around the contact. The memory device according to claim 1, further comprising support columns disposed between each of the aforementioned support structures.

13. A laminate comprising conductive films and interlayer insulating films alternately stacked along a first direction; The laminate further includes a cell plug that penetrates in the first direction, The memory device according to claim 12, wherein the support column includes a dummy material film corresponding to the material film contained in the cell plug.

14. Each of the cell plugs includes a memory film, a channel film, and a gap fill film. The memory device according to claim 13, wherein each of the support columns includes a dummy memory film corresponding to the memory film, a dummy channel film corresponding to the channel film, and a dummy gap fill film corresponding to the gap fill film.

15. The aforementioned support column is The memory device according to claim 12, which is separated from the contact and the support structure.

16. A step of forming a laminate including sacrificial films and interlayer insulating films that are alternately stacked along a first direction; The step of forming a first opening that penetrates the laminate; The steps include forming a contact opening extending in the first direction from the first sacrificial film among the sacrificial films; The steps include: expanding each of the first openings around the contact opening to form support holes that overlap each other; A method for manufacturing a memory device, comprising the step of forming a support structure by embedding an insulating film inside the superimposed support holes.

17. In the step of forming the first opening, The method for manufacturing a memory device according to claim 16, wherein the step of forming a channel opening that penetrates the laminate is performed simultaneously.

18. After the step of forming the first opening, The step of filling the first opening with the first sacrificial column; A method for manufacturing a memory device according to claim 17, further comprising the step of forming a cell plug inside each of the channel openings.

19. In the step of forming the first opening, The method for manufacturing a memory device according to claim 17, wherein the step of forming a second opening that penetrates the laminate is performed simultaneously.

20. After the step of forming the first opening, The step of filling the first opening with the first sacrificial column; The steps include forming cell plugs inside each of the channel openings; A method for manufacturing a memory device according to claim 19, further comprising the step of forming a support column inside each of the second openings.

21. In the step of forming the contact opening, The method for manufacturing a memory device according to claim 16, wherein the contact opening is formed to be spaced apart from the first opening.

22. After the step of forming the contact opening, The steps include: etching a portion of the side surface of the sacrificial film exposed through the contact opening to form a recess; The steps include forming a liner film that extends along the inner surface of the contact opening; A method for manufacturing a memory device according to claim 16, further comprising the step of forming a second sacrificial column that fills the contact opening.

23. In the step of forming the support holes that overlap each other, The method for manufacturing a memory device according to claim 22, wherein the liner film is used as an etching stop film while each of the first openings is expanded.

24. In the step of forming the support holes that overlap each other, The method for manufacturing a memory device according to claim 22, wherein a portion of the side surface and a portion of the bottom surface of the liner film are exposed by the support holes.

25. After the step of forming the support structure, The step of removing the second sacrificial column and the liner film from inside the contact opening; The step of forming a spacer on the inner surface of the contact opening; A method for manufacturing a memory device according to claim 22, further comprising the step of forming a contact inside the contact opening.

26. The step of forming the spacer is, The steps include forming a spacer film that extends along the inner surface of the contact opening; A method for manufacturing a memory device according to claim 25, comprising the step of removing the lower surface of the spacer film to form the spacer.

27. After the step of forming the spacer film, The steps include forming a third sacrificial column to fill the contact opening; The steps include replacing the sacrificial film of the laminate with a conductive film; A method for manufacturing a memory device according to claim 26, further comprising the step of removing the third sacrificial column.

Images