Semiconductor equipment

Abstract

The present invention provides a semiconductor device that includes an RC-IGBT having an IGBT and a diode, enabling improved performance. [Solution] The semiconductor device of the embodiment comprises a transistor region and a diode region. It also comprises a semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type between the first semiconductor region and a first surface, a third semiconductor region between the second semiconductor region and the first surface having a lower second conductivity type impurity concentration than the second semiconductor region, and a sixth semiconductor region between the second semiconductor region and a second surface having a higher second conductivity type impurity concentration than the second semiconductor region. The second semiconductor region includes a first region and a second region, the first region is located between the sixth semiconductor region and the third semiconductor region, the second region is located between the first semiconductor region and the third semiconductor region, the impurity concentration of the first region is 80% to 120% of that of the second region, and the carrier concentration of the first region is lower than that of the second region.

Description

[Technical Field] 【0001】 Embodiments of the present invention relate to semiconductor devices. [Background technology] 【0002】 An example of a power semiconductor device is an Insulated Gate Bipolar Transistor (IGBT). In an IGBT, for example, a p-type collector region, an n-type drift region, and a p-type base region are provided on the collector electrode. A gate electrode is provided in a trench that penetrates the p-type base region and reaches the n-type drift region, with a gate insulating film in between. Furthermore, an n-type emitter region, connected to the emitter electrode, is provided in a region adjacent to the trench on the surface of the p-type base region. 【0003】 In recent years, reverse-conducting IGBTs (RC-IGBTs), which integrate IGBTs and freewheeling diodes on the same semiconductor chip, have been widely developed and commercialized. RC-IGBTs are used, for example, as switching elements in inverter circuits. The freewheeling diode has the function of allowing current to flow in the opposite direction to the IGBT's on-current. Integrating IGBTs and freewheeling diodes on the same semiconductor chip offers many advantages, such as simplified assembly and dispersion of heat-generating points. [Prior art documents] [Patent Documents] 【0004】 [Patent Document 1] Japanese Patent Publication No. 2024-58718 [Overview of the project] [Problems that the invention aims to solve] 【0005】 The problem that this invention aims to solve is to provide a semiconductor device that includes an RC-IGBT having an IGBT and a diode, and that enables improved characteristics. [Means for solving the problem] 【0006】 The semiconductor device of the embodiment comprises a transistor region and a diode region, the transistor region being a semiconductor layer having a first surface and a second surface facing the first surface, the semiconductor layer including a first semiconductor region of a first conductivity type in contact with the second surface, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, a third semiconductor region of a second conductivity type provided between the second semiconductor region and the first surface and having a lower concentration of second conductivity type impurities than the second semiconductor region, a fourth semiconductor region of a first conductivity type provided between the third semiconductor region and the first surface, and a fifth semiconductor region of a second conductivity type provided between the fourth semiconductor region and the first surface and in contact with the first surface, the semiconductor layer comprising a gate electrode facing the fourth semiconductor region, a gate insulating film provided between the gate electrode and the fourth semiconductor region, a first electrode in contact with the fifth semiconductor region, and a second electrode in contact with the first semiconductor region, the diode The oxide region is a semiconductor layer comprising: the second semiconductor region, the third semiconductor region, a sixth semiconductor region of a second conductivity type provided between the second semiconductor region and the second surface and in contact with the second surface, having a second conductivity type impurity concentration higher than that of the second conductivity type impurity concentration of the second semiconductor region, and a seventh semiconductor region of a first conductivity type provided between the third semiconductor region and the first surface and in contact with the first surface; the first electrode in contact with the seventh semiconductor region; and the sixth semiconductor layer. The semiconductor region includes the second electrode in contact with the body region, the second semiconductor region includes a first region and a second region, the first region is provided between the sixth semiconductor region and the third semiconductor region, the second region is provided between the first semiconductor region and the third semiconductor region, the second conductivity type impurity concentration in the first region is 80% to 120% of the second conductivity type impurity concentration in the second region, and the carrier concentration in the first region is lower than the carrier concentration in the second region. [Brief explanation of the drawing] 【0007】 [Figure 1] Schematic diagram of the semiconductor device according to the first embodiment. [Figure 2] Schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. [Figure 3] Schematic cross-sectional view showing an example of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 4] Schematic cross-sectional view showing an example of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 5] Schematic cross-sectional view showing an example of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 6] Schematic cross-sectional view showing an example of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] Schematic cross-sectional view showing an example of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 8] Schematic cross-sectional view showing an example of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 9] Schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. [Figure 10] Schematic cross-sectional view showing an example of the manufacturing method of the semiconductor device according to the second embodiment. [Figure 11] Explanatory diagram of the operation and effect of the semiconductor device according to the second embodiment. [Figure 12] Explanatory diagram of the operation and effect of the semiconductor device according to the second embodiment. [Figure 13] Schematic cross-sectional view of a part of the semiconductor device according to a modified example of the second embodiment. [Figure 14] Schematic cross-sectional view of a part of the semiconductor device according to the third embodiment. [Figure 15] Schematic cross-sectional view of a part of the semiconductor device according to a modified example of the third embodiment. 【Embodiments for Carrying Out the Invention】 【0008】 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate. 【0009】 In this specification, n+ shape, n shape, n - When the notation "shape" is used, n + shape, n shape, n - This means that the concentration of n-type impurities decreases in the order of their shapes. Also, p + shape, p shape, p - If there is a notation for the shape, p + shape, p shape, p - This means that the concentration of p-type impurities decreases in the order of their shapes. 【0010】 In this specification, the n-type impurity concentration refers to the effective n-type impurity concentration after compensation, not the actual n-type impurity concentration. Similarly, the p-type impurity concentration refers to the effective p-type impurity concentration after compensation, not the actual p-type impurity concentration. For example, if the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the n-type impurity concentration is calculated by subtracting the p-type impurity concentration from the actual n-type impurity concentration. The same applies to the p-type impurity concentration. 【0011】 In this specification, the n-type impurity concentration and p-type impurity concentration refer to the atomic concentration of physically present impurity atoms, not the concentration of activated impurities. 【0012】 In this specification, carrier concentration means the concentration of activated impurities. 【0013】 The distribution and absolute values ​​of impurity concentrations in the semiconductor region can be measured, for example, using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX). 【0014】 The relative magnitudes and absolute values ​​of carrier concentrations in semiconductor regions can be measured, for example, using scanning capacitance microscopy (SCM) or spreading resistance analysis (SRA). 【0015】 For example, SCM can be used to evaluate the planar distribution of semiconductor regions. For example, SCM can be used to measure the depth of semiconductor regions and the distance between semiconductor regions. 【0016】 Unless otherwise specified in the specification, the impurity concentration or carrier concentration in the semiconductor region shall be represented by the concentration near the center of that semiconductor region. 【0017】 The relative magnitudes of crystal defect densities in semiconductor regions can be measured, for example, using transmission electron microscopy (TEM) or photoluminescence (PL). 【0018】 (First Embodiment) The semiconductor device of the first embodiment comprises a transistor region and a diode region. The transistor region is a semiconductor layer having a first surface and a second surface facing the first surface, and includes a first semiconductor region of a first conductivity type in contact with the second surface, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, a third semiconductor region of a second conductivity type provided between the second semiconductor region and the first surface and having a lower concentration of second conductivity type impurities than the second semiconductor region, a fourth semiconductor region of a first conductivity type provided between the third semiconductor region and the first surface, and a fifth semiconductor region of a second conductivity type provided between the fourth semiconductor region and the first surface and in contact with the first surface; a gate electrode facing the fourth semiconductor region, a gate insulating film provided between the gate electrode and the fourth semiconductor region, a first electrode in contact with the fifth semiconductor region, and a second electrode in contact with the first semiconductor region; and the diode region is a second semiconductor The semiconductor layer includes a region, a third semiconductor region, a second semiconductor region, a second surface, a sixth semiconductor region of a second conductivity type provided between the second surface and in contact with the second surface, having a second conductivity type impurity concentration higher than that of the second semiconductor region, and a seventh semiconductor region of a first conductivity type provided between the third semiconductor region and the first surface and in contact with the first surface; the semiconductor layer also includes a first electrode in contact with the seventh semiconductor region and a second electrode in contact with the sixth semiconductor region, wherein the second semiconductor region includes a first region and a second region, the first region is provided between the sixth semiconductor region and the third semiconductor region, the second region is provided between the first semiconductor region and the third semiconductor region, the second conductivity type impurity concentration of the first region is 80% to 120% of the second conductivity type impurity concentration of the second region, and the carrier concentration of the first region is lower than the carrier concentration of the second region. 【0019】 The semiconductor device of the first embodiment is an RC-IGBT100 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The RC-IGBT100 has a trench-gate type IGBT with a gate electrode located in a trench formed in the semiconductor layer. The following explanation will be given using the case where the first conductivity type is p-type and the second conductivity type is n-type as an example. 【0020】 FIG. 1 is a schematic diagram of a semiconductor device according to the first embodiment. 【0021】 As shown in FIG. 1, the RC-IGBT 100 has a transistor region 101, a diode region 102, and a termination region 103. The transistor region 101 and the diode region 102 are alternately arranged in a first direction. The transistor region 101 and the diode region 102 extend in a second direction perpendicular to the first direction. The termination region 103 surrounds the transistor region 101 and the diode region 102. 【0022】 The transistor region 101 operates as an IGBT. The diode region 102 operates as a freewheeling diode. The freewheeling diode is, for example, a Fast Recovery Diode (FRD). 【0023】 When the RC-IGBT 100 is in the off state, the termination region 103 relaxes the strength of the electric field applied to the end portions of the pn junctions of the transistor region 101 and the diode region 102. The termination region 103 has a function of improving the breakdown voltage characteristics of the RC-IGBT 100. 【0024】 A gate electrode pad 104 is provided in the termination region 103. 【0025】 The RC-IGBT 100 of the first embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate insulating film 41, a dummy gate insulating film 42, a gate electrode 51, a dummy gate electrode 52, an interlayer insulating layer 60, and a gate electrode pad 104. The dummy gate electrode 52 is connected to the emitter electrode and does not form an inversion layer in the p-type anode region 38. 【0026】 The semiconductor layer 10 includes a gate trench 21, a dummy trench 22, a p-type collector region 26 (first semiconductor region), an n-type first buffer region 28 (second semiconductor region), an n [[ID=2)] - type drift region 30 (third semiconductor region), a p-type base region 32 (fourth semiconductor region), an n + type emitter region 34 (fifth semiconductor region), an n+ It includes a type contact region 36 (sixth semiconductor region) and a p-type anode region 38 (seventh semiconductor region). The first buffer region 28 includes a first region 28a and a second region 28b. 【0027】 The semiconductor layer 10 has a first surface F1 and a second surface F2 facing the first surface F1. The semiconductor layer 10 is, for example, single-crystal silicon. The thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less. 【0028】 In this specification, a direction parallel to the first surface F1 is referred to as the first direction. A direction parallel to the first surface F1 and perpendicular to the first direction is referred to as the second direction. A direction connecting the first surface F1 and the second surface F2 is referred to as the third direction. 【0029】 Figure 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 2 is a schematic cross-sectional view of the boundary between the diode region 102 and the transistor region 101. Figure 2 is a cross-sectional view AA' of Figure 1. 【0030】 The transistor region 101 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate insulating film 41, a gate electrode 51, and an interlayer insulating layer 60. 【0031】 The semiconductor layer 10 of the transistor region 101 consists of a gate trench 21, a p-type collector region 26 (first semiconductor region), and n - The drift region 30 (third semiconductor region) of the p-shape, the base region 32 (fourth semiconductor region) of the p-shape, and the n-shape. + It includes the emitter region 34 (the fifth semiconductor region). 【0032】 The upper electrode 12 is provided on the side of the first surface F1 of the semiconductor layer 10. At least a portion of the upper electrode 12 is in contact with the first surface F1 of the semiconductor layer 10. 【0033】 The upper electrode 12 functions as the emitter electrode of the IGBT in the transistor region 101. The upper electrode 12 is made of, for example, metal. 【0034】 The upper electrode 12 is in contact with the emitter region 34. The upper electrode 12 is electrically connected to the emitter region 34. 【0035】 The lower electrode 14 is provided on the side of the second surface F2 of the semiconductor layer 10. The lower electrode 14 is in contact with the second surface F2 of the semiconductor layer 10. 【0036】 The lower electrode 14 functions as the collector electrode of the IGBT in the transistor region 101. The lower electrode 14 is made of, for example, metal. 【0037】 The lower electrode 14 is in contact with the collector region 26 in the transistor region 101. The lower electrode 14 is electrically connected to the collector region 26 in the transistor region 101. 【0038】 The collector region 26 is a p-type semiconductor region. The collector region 26 is in contact with the second surface F2. The collector region 26 is electrically connected to the lower electrode 14. The collector region 26 is in contact with the lower electrode 14. The collector region 26 is a hole source when the IGBT is ON. 【0039】 The first buffer region 28 is an n-type semiconductor region. The first buffer region 28 is provided between the collector region 26 and the first surface F1. The second region 28b of the first buffer region 28 is provided between the collector region 26 and the first surface F1. 【0040】 The first buffer region 28 has the function of suppressing the elongation of the depletion layer extending from the first surface F1 side when the IGBT is off, thereby maintaining the IGBT's breakdown voltage. 【0041】 The drift region 30 is n - This is a semiconductor region of a certain shape. The drift region 30 is provided between the first buffer region 28 and the first surface F1. The n-type impurity concentration in the drift region 30 is lower than the n-type impurity concentration in the first buffer region 28. 【0042】 The drift region 30 serves as the path for the on-current when the IGBT is on. The drift region 30 depletes when the IGBT is off, thus maintaining the IGBT's breakdown voltage. 【0043】 The base region 32 is a p-type semiconductor region. The base region 32 is provided between the drift region 30 and the first surface F1. 【0044】 An n-type inversion layer is formed in the region of the base region 32 opposite the gate electrode 51 when the IGBT is in the ON state. The base region 32 functions as the channel region of the transistor. 【0045】 The emitter region 34 is n + This is a semiconductor region of a certain shape. The emitter region 34 is provided between the base region 32 and the first surface F1. The emitter region 34 is in contact with the first surface F1. 【0046】 The n-type impurity concentration in the emitter region 34 is higher than the n-type impurity concentration in the drift region 30. 【0047】 The emitter region 34 is in contact with the upper electrode 12. The emitter region 34 is electrically connected to the upper electrode 12. The emitter region 34 is an electron source when the transistor is in the ON state. 【0048】 The gate trench 21 is provided on the side of the first surface F1 of the semiconductor layer 10. The gate trench 21 is a groove provided in the semiconductor layer 10. The gate trench 21 is part of the semiconductor layer 10. 【0049】 The gate electrode 51 is provided in the gate trench 21. The gate electrode 51 is, for example, a semiconductor or a metal. The gate electrode 51 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities. 【0050】 The gate electrode 51 is electrically connected to the gate electrode pad 104. 【0051】 The gate insulating film 41 is provided between the gate electrode 51 and the semiconductor layer 10. The gate insulating film 41 is provided between the gate electrode 51 and the base region 32. The gate insulating film 41 is, for example, silicon oxide. 【0052】 The interlayer insulating layer 60 is provided between the gate electrode 51 and the upper electrode 12. The interlayer insulating layer 60 electrically isolates the gate electrode 51 and the upper electrode 12. The interlayer insulating layer 60 is, for example, silicon oxide. 【0053】 The diode region 102 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a dummy gate insulating film 42, a dummy gate electrode 52, and an interlayer insulating layer 60. 【0054】 The semiconductor layer 10 of the diode region 102 is a dummy trench 22, n + Type 1 contact region 36 (6th semiconductor region), n type 1 buffer region 28 (2nd semiconductor region), n - It includes a p-shaped drift region 30 (third semiconductor region) and a p-shaped anode region 38 (seventh semiconductor region). 【0055】 The upper electrode 12 functions as the anode electrode of the diode in the diode region 102. The upper electrode 12 is in contact with the anode region 38. 【0056】 The lower electrode 14 functions as the cathode electrode of the diode in the diode region 102. The lower electrode 14 is in contact with the contact region 36. 【0057】 Contact area 36 is n + This is a semiconductor region of a certain shape. The contact region 36 is in contact with the second surface F2. The contact region 36 is an electron source when the diode is in the ON state. The contact region 36 is in contact with the lower electrode 14. 【0058】 The first buffer region 28 is an n-type semiconductor region. The first buffer region 28 is provided between the contact region 36 and the first surface F1. The first region 28a of the first buffer region 28 is provided between the contact region 36 and the first surface F1. 【0059】 The drift region 30 is n - This is a semiconductor region of a certain shape. The drift region 30 is provided between the first buffer region 28 and the first surface F1. 【0060】 The drift region 30 is the path of the on-current when the diode is in the ON state. 【0061】 The anode region 38 is a p-type semiconductor region. The anode region 38 is located between the drift region 30 and the first surface F1. 【0062】 The anode region 38 is the source of holes when the diode is ON. 【0063】 The anode region 38 is in contact with the upper electrode 12. The anode region 38 is electrically connected to the upper electrode 12. 【0064】 The dummy trench 22 is provided on the side of the first surface F1 of the semiconductor layer 10. The dummy trench 22 is a groove provided in the semiconductor layer 10. The dummy trench 22 is part of the semiconductor layer 10. 【0065】 The dummy gate electrode 52 is provided in the dummy trench 22. The dummy gate electrode 52 is, for example, a semiconductor or a metal. The dummy gate electrode 52 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities. 【0066】 The dummy gate electrode 52 is electrically connected to, for example, the upper electrode 12. 【0067】 The dummy gate insulating film 42 is provided between the dummy gate electrode 52 and the semiconductor layer 10. 【0068】 The first buffer region 28 includes the first region 28a and the second region 28b. 【0069】 The first region 28a is provided between the contact region 36 and the drift region 30. The first region 28a is in contact with the contact region 36 and the drift region 30. The first region 28a is provided directly above the contact region 36. The first region 28a is provided in a third direction of the contact region 36. 【0070】 The second region 28b is provided between the collector region 26 and the drift region 30. The second region 28b is in contact with the collector region 26 and the drift region 30. The second region 28b is provided directly above the collector region 26. The second region 28b is provided in a third direction of the collector region 26. 【0071】 The concentration of n-type impurities in the first region 28a is 80% to 120% of the concentration of n-type impurities in the second region 28b. For example, the concentration of n-type impurities in the first region 28a is 90% to 110% of the concentration of n-type impurities in the second region 28b. For example, the concentration of n-type impurities in the first region 28a is substantially the same as the concentration of n-type impurities in the second region 28b. 【0072】 The carrier concentration in the first region 28a is lower than the carrier concentration in the second region 28b. For example, the carrier concentration in the first region 28a is between 1 / 1000 and 1 / 2 of the carrier concentration in the second region 28b. 【0073】 The n-type impurity concentration and carrier concentration in the first region 28a are measured, for example, at the position of the first point P1 in Figure 2. Similarly, the n-type impurity concentration and carrier concentration in the second region 28b are measured, for example, at the position of the second point P2 in Figure 2. The distance in the third direction from the second surface F2 to the first point P1 is equal to the distance in the third direction from the second surface F2 to the second point P2. 【0074】 The first region 28a contains crystal defects. These crystal defects in the first region 28a function as lifetime killers. By having these crystal defects in the first region 28a function as lifetime killers, for example, the switching characteristics of the freewheeling diode are improved. 【0075】 The second region 28b may or may not contain crystal defects. The crystal defect density of the second region 28b is, for example, lower than that of the first region 28a. The crystal defect density of the first region 28a is, for example, higher than that of the second region 28b. 【0076】 Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described. 【0077】 Figures 3, 4, 5, 6, 7, and 8 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 3 to 8 correspond to Figure 2. 【0078】 First, n - On the side of the first surface F1 of the semiconductor layer 10, which includes the p-shaped drift region 30, there is a gate trench 21, a dummy trench 22, a p-shaped base region 32, and n + A p-shaped emitter region 34, a p-shaped anode region 38, a gate insulating film 41, a dummy gate insulating film 42, a gate electrode 51, a dummy gate electrode 52, an interlayer insulating layer 60, and an upper electrode 12 are formed using known process techniques (Figure 3). 【0079】 Next, the first ion implantation is performed. In the first ion implantation, n-type impurities are implanted into the semiconductor layer 10 using the ion implantation method from the side of the second surface F2 (Figure 4). The n-type impurities are, for example, phosphorus (P). The implantation of n-type impurities forms the first n-type region 71. A portion of the first n-type region 71 eventually becomes the first buffer region 28. Crystal defects 71x are formed in the first n-type region 71 due to ion implantation. 【0080】 Next, a second ion implantation is performed. In the second ion implantation, p-type impurities are implanted into the semiconductor layer 10 using the ion implantation method from the side of the second surface F2 (Figure 5). The p-type impurities are, for example, boron (B). By implanting the p-type impurities, a p-type region 72 is formed between the first n-type region 71 and the second surface F2. A portion of the p-type region 72 eventually becomes the collector region 26. 【0081】 Next, a resist layer 61 is formed on a portion of the second surface F2. Then, a third ion implantation is performed. In the third ion implantation, n-type impurities are implanted into the semiconductor layer 10 using the ion implantation method from the side of the second surface F2, with the resist layer 61 as a mask (Figure 6). The dose of n-type impurities in the third ion implantation is higher than the dose of n-type impurities in the first ion implantation. The n-type impurities are, for example, phosphorus (P). The implantation of n-type impurities forms a second n-type region 73. A portion of the second n-type region 73 eventually becomes a contact region 36. The second n-type region 73 becomes amorphous due to the high dose of ion implantation. 【0082】 Next, the resist layer 61 is peeled off. Then, an infrared laser IR is irradiated onto the semiconductor layer 10 from the side of the second surface F2 (Figure 7). By using a long-wavelength infrared laser IR, the laser light can reach a position far from the second surface F2. 【0083】 Irradiation with an infrared laser (IR) activates the n-type impurities in the first n-type region 71 directly above the p-type region 72. In addition, crystal defects formed in the first n-type region 71 directly above the p-type region 72 due to ion implantation are restored and disappear. 【0084】 On the other hand, the activation of n-type impurities in the first n-type region 71 directly above the second n-type region 73 is suppressed. The recovery and annihilation of crystal defects formed in the first n-type region 71 directly above the second n-type region 73 are suppressed. This is because the infrared laser IR irradiated onto the second n-type region 73 is absorbed by the amorphous state of the second n-type region 73, and its arrival in the first n-type region 71 is suppressed. 【0085】 Next, the semiconductor layer 10 is irradiated with a green laser GR from the side of the second surface F2 (Figure 8). By using a green laser GR with a shorter wavelength than the infrared laser IR, the laser light is effectively irradiated to the vicinity of the second surface F2. Because the green laser GR has a shorter wavelength, it is difficult for it to reach positions far from the second surface F2. 【0086】 Irradiation with a green laser GR activates the p-type impurities in the p-type region 72 and the n-type impurities in the second n-type region 73. 【0087】 By the above manufacturing method, the RC-IGBT100 of the first embodiment shown in Figure 2 can be manufactured. 【0088】 Next, the operation and effects of the semiconductor device according to the first embodiment will be described. 【0089】 In RC-IGBTs, lifetime control is sometimes implemented by introducing a lifetime killer to improve the switching characteristics of the freewheeling diode. However, lifetime control can increase leakage current at high temperatures, potentially causing thermal runaway and destruction of the RC-IGBT. 【0090】 In the RC-IGBT100 of the first embodiment, a lifetime killer is introduced only in the first buffer region 28 of the diode region 102. That is, a lifetime killer is introduced only in the first region 28a, which is the first buffer region 28 of the diode region 102. 【0091】 A lifetime killer is not introduced in the first buffer region 28 of the transistor region 101. In other words, a lifetime killer is not introduced in the second region 28b, which is the first buffer region 28 of the transistor region 101. 【0092】 Therefore, since defects are sufficiently reduced in the transistor region 101 compared to the first region 28a, leakage current at high temperatures is not a problem. Consequently, according to the RC-IGBT100 of the first embodiment, thermal runaway at high temperatures is suppressed compared to a structure in which lifetime killers are introduced in both the transistor region and the diode region. 【0093】 In particular, the RC-IGBT100 of the first embodiment, as described above, uses an infrared laser IR and a green laser GR to activate impurities, and a lifetime killer can be formed self-aligned only on the contact region 36 of the diode region 102. In other words, a lifetime killer can be formed self-aligned at the boundary between the diode region 102 and the transistor region 101. The RC-IGBT100 of the first embodiment makes it possible to manufacture RC-IGBTs with suppressed thermal runaway at high temperatures using a simple process. 【0094】 From the viewpoint of increasing the crystal defect density and effectively controlling the lifetime, the carrier concentration in the first region 28a is preferably half or less of the carrier concentration in the second region 28b, more preferably one-fifth or less, and even more preferably one-tenth or less. 【0095】 As described above, according to the first embodiment, a semiconductor device can be realized that includes an RC-IGBT having an IGBT and a diode, and in which thermal runaway at high temperatures is suppressed, thereby enabling improved performance. 【0096】 (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the second semiconductor region further includes a third region, the third region is in contact with the second surface, the third region is located between the sixth semiconductor region and the first semiconductor region, and the carrier concentration of the first region is lower than that of the third region. Hereafter, some descriptions that overlap with the first embodiment may be omitted. 【0097】 The semiconductor device of the second embodiment is an RC-IGBT200 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. 【0098】 Figure 9 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment. Figure 9 corresponds to Figure 2 of the first embodiment. 【0099】 The first buffer area 28 of the RC-IGBT200 includes a first area 28a and a second area 28b, as well as a third area 28c. 【0100】 The third region 28c is provided between the contact region 36 and the collector region 26. The third region 28c is in contact with the second surface F2. 【0101】 The n-type impurity concentration in the first region 28a is 80% to 120% of the n-type impurity concentration in the third region 28c. For example, the n-type impurity concentration in the first region 28a is 90% to 110% of the n-type impurity concentration in the third region 28c. For example, the n-type impurity concentration in the first region 28a is substantially the same as the n-type impurity concentration in the third region 28c. 【0102】 The carrier concentration in the first region 28a is lower than the carrier concentration in the third region 28c. The carrier concentration in the first region 28a is, for example, between 1 / 1000 and 1 / 2 of the carrier concentration in the third region 28c. The carrier concentration in the third region 28c is higher than the carrier concentration in the first region 28a. 【0103】 The n-type impurity concentration and carrier concentration in the third region 28c are measured, for example, at the position of the third point P3 in Figure 9. The distance in the third direction from the second plane F2 to the first point P1 and the distance in the third direction from the second plane F2 to the second point P2 are equal to the distance in the third direction from the second plane F2 to the third point P3. 【0104】 The third region 28c may or may not contain crystal defects. The crystal defect density of the third region 28c is, for example, lower than that of the first region 28a. The crystal defect density of the first region 28a is, for example, higher than that of the third region 28c. 【0105】 The contact region 36 and the collector region 26 are separated in a first direction, with a third region 28c in between. The distance between the contact region 36 and the collector region 26 in the first direction (d1 in Figure 9) is, for example, greater than or equal to the distance between the collector region 26 and the drift region 30 in the third direction (d2 in Figure 9). The distance d1 between the contact region 36 and the collector region 26 in the first direction is, for example, less than or equal to five times the distance d2 between the collector region 26 and the drift region 30 in the third direction. 【0106】 Figure 10 is a schematic cross-sectional view showing an example of a semiconductor device manufacturing method according to the second embodiment. Figure 10 corresponds to Figure 5, which shows the semiconductor device manufacturing method according to the first embodiment. 【0107】 For example, before performing the second ion implantation, a resist layer 61 is formed on a portion of the second surface F2. In the second ion implantation, p-type impurities are implanted into the semiconductor layer 10 using the ion implantation method from the side of the second surface F2, with the resist layer 61 as a mask. The p-type impurities are, for example, boron (B). The implantation of p-type impurities forms a p-type region 72 in a portion between the first n-type region 71 and the second surface F2. The p-type region 72 eventually becomes the collector region 26. 【0108】 Subsequently, by performing the same manufacturing method as the semiconductor device manufacturing method of the first embodiment, the RC-IGBT200 of the second embodiment shown in Figure 9 can be manufactured. 【0109】 Next, the operation and effects of the semiconductor device according to the second embodiment will be described. 【0110】 Figure 11 is an explanatory diagram of the operation and effects of the semiconductor device of the second embodiment. Figure 11 is a diagram showing the problems of the semiconductor device of the first embodiment. Figure 11 is a diagram corresponding to Figure 2 of the first embodiment. 【0111】 Figure 11 shows the state where the RC-IGBT100 is off and the depletion layer extends into the drift region 30. In Figure 11, the edge of the depletion layer is shown by a dotted line. 【0112】 The carrier concentration in the first region 28a of the first buffer region 28 of the diode region 102 is lower than the carrier concentration in the second region 28b of the first buffer region 28 of the transistor region 101. Therefore, the depletion layer is more likely to extend in the first region 28a compared to the second region 28b. 【0113】 In this case, the distance between the depletion layer edge in the first region 28a and the collector region 26 decreases, making it easier for holes to be injected from the collector region 26 into the depletion layer. Consequently, the leakage current at high temperatures increases, and thermal runaway may occur at high temperatures. 【0114】 Figure 12 is an explanatory diagram of the operation and effects of the semiconductor device of the second embodiment. Figure 12 corresponds to Figure 9 of the second embodiment. 【0115】 Figure 12 shows the state where the RC-IGBT200 is off and the depletion layer extends into the drift region 30. In Figure 12, the edge of the depletion layer is shown by a dotted line. 【0116】 In the RC-IGBT200, the contact region 36 and the collector region 26 are separated in the first direction, with a third region 28c in between. The carrier concentration in the third region 28c is higher than the carrier concentration in the first region 28a. 【0117】 Therefore, compared to the RC-IGBT100, the distance between the depletion layer edge in the first region 28a and the collector region 26 is increased. Consequently, the injection of holes from the collector region 26 into the depletion layer is suppressed. Thus, leakage current at high temperatures is further suppressed, and thermal runaway at high temperatures is further suppressed. 【0118】 From the viewpoint of suppressing hole injection from the collector region 26 into the depletion layer, it is preferable that the distance d1 in the first direction between the contact region 36 and the collector region 26 is less than or equal to the distance d2 in the third direction between the collector region 26 and the drift region 30. 【0119】 (modified version) The semiconductor device of the modified second embodiment differs from the semiconductor device of the second embodiment in that the third region has a first portion in contact with the second surface and a second portion between the first portion and the third semiconductor region, and the concentration of the second conductivity type impurity in the first portion is higher than that of the second conductivity type impurity in the second portion. 【0120】 A modified semiconductor device of the second embodiment is an RC-IGBT210 in which the IGBT and the freewheeling diode are formed on the same semiconductor chip. 【0121】 Figure 13 is a schematic cross-sectional view of a part of a semiconductor device of a modified example of the second embodiment. Figure 13 corresponds to Figure 9 of the second embodiment. 【0122】 The first buffer region 28 of the RC-IGBT210 has a third region 28c which includes a first portion 28c1 and a second portion 28c2. 【0123】 The first portion 28c1 is in contact with the second surface F2. The second portion 28c2 is provided between the first portion 28c1 and the drift region 30. 【0124】 The concentration of n-type impurities in the first portion 28c1 is higher than that of n-type impurities in the second portion 28c2. The concentration of n-type impurities in the first portion 28c1 is higher than that of n-type impurities in the second region 28b. 【0125】 In the RC-IGBT210, the presence of a first portion 28c1 with a high concentration of n-type impurities further increases the distance between the depletion layer edge in the first region 28a and the collector region 26. Therefore, leakage current at high temperatures is further suppressed, and thermal runaway at high temperatures is further suppressed. 【0126】 As described above, according to the second embodiment and its modifications, a semiconductor device can be realized that includes an RC-IGBT having an IGBT and a diode, and in which thermal runaway at high temperatures is suppressed, thereby enabling improved performance. 【0127】 (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the second embodiment in that the semiconductor layer further includes an eighth semiconductor region of a second conductivity type, which is provided between the second semiconductor region and the third semiconductor region, and whose concentration of the second conductivity type impurity is lower than that of the sixth semiconductor region and higher than that of the third semiconductor region. Hereafter, some descriptions that overlap with the second embodiment may be omitted. 【0128】 The semiconductor device of the third embodiment is an RC-IGBT300 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. 【0129】 Figure 14 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment. Figure 14 corresponds to Figure 9 of the second embodiment. 【0130】 In the RC-IGBT300, the semiconductor layer 10 further includes an n-type second buffer region 29 (eighth semiconductor region). 【0131】 The second buffer region 29 is an n-type semiconductor region. The second buffer region 29 is located between the first buffer region 28 and the drift region 30. 【0132】 The n-type impurity concentration in the second buffer region 29 is lower than that in the contact region 36. The n-type impurity concentration in the second buffer region 29 is higher than that in the drift region 30. 【0133】 The carrier concentration in the second buffer region 29 is higher than the carrier concentration in the first region 28a of the first buffer region 28. The crystal defect density in the second buffer region 29 is lower than the crystal defect density in the first region 28a of the first buffer region 28. 【0134】 The formation of the second buffer region 29 is performed, for example, in the manufacturing method of the first embodiment, by ion implanting n-type impurities in a region closer to the first surface F1 than the first n-type region 71, before performing the first ion implantation to form the first n-type region 71. Then, an infrared laser IR is irradiated onto the semiconductor layer 10 from the side of the second surface F2 to activate the n-type impurities in the n-type region and to recover crystal defects. 【0135】 The RC-IGBT300, by providing a second buffer region 29 with a high carrier concentration, can suppress the depletion layer extending from the first surface F1 side from hitting defects in the first region 28a. By preventing an electric field from being applied to the defects, the generated current can be suppressed. On the other hand, when the diode is operating, the first region 28a contributes to the annihilation of residual carriers, thus improving the trade-off relationship between the diode's switching characteristics and leakage current. 【0136】 (modified version) The semiconductor device of the modified third embodiment differs from the semiconductor device of the third embodiment in that the second semiconductor region does not include the third region. 【0137】 A modified semiconductor device of the third embodiment is the RC-IGBT310, in which the IGBT and the freewheeling diode are formed on the same semiconductor chip. 【0138】 Figure 15 is a schematic cross-sectional view of a part of a semiconductor device of a modified example of the third embodiment. Figure 15 corresponds to Figure 14 of the third embodiment. 【0139】 The first buffer area 28 of the RC-IGBT310 does not include the third area 28c. The contact area 36 and the collector area 26 are in contact. 【0140】 As described above, according to the third embodiment and its modifications, a semiconductor device can be realized that includes an RC-IGBT having an IGBT and a diode, and in which thermal runaway at high temperatures is suppressed, thereby enabling improved performance. 【0141】 In the first to third embodiments, the case where the semiconductor layer is single-crystal silicon was described as an example, but the semiconductor layer is not limited to single-crystal silicon. For example, it may be other single-crystal semiconductors such as single-crystal silicon carbide. 【0142】 In the first to third embodiments, the case where the first conductivity type is p-type and the second conductivity type is n-type was described as an example, but it is also possible to have the first conductivity type be n-type and the second conductivity type be p-type. 【0143】 In the first to third embodiments, an RC-IGBT having a trench gate type IGBT was described as an example, but an RC-IGBT having a planar gate type IGBT may also be used. 【0144】 While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols] 【0145】 10 Semiconductor layer 12 Upper electrode (first electrode) 14. Lower electrode (second electrode) 26 p-type collector region (first semiconductor region) 28 n-type first buffer region (second semiconductor region) 28a First area 28b Second area 28c Third area 28c1 Part 1 28c2 Second part 29. n-type second buffer region (eighth semiconductor region) 30 n - Shape drift region (third semiconductor region) 32 p-type base region (fourth semiconductor region) 34 n + Shape of the emitter region (fifth semiconductor region) 36 n + Type contact region (sixth semiconductor region) 38. p-type anode region (7th semiconductor region) 41 Gate insulating film 51 Guard Station 100 RC-IGBT (Semiconductor Device) 101 Transistor Region 102 Diode region 200 RC-IGBT (Semiconductor Device) 210 RC-IGBT (Semiconductor Equipment) 300 RC-IGBT (Semiconductor Device) 310 RC-IGBT (Semiconductor Device) F1 First Side F2 Second side

Claims

[Claim 1] The transistor region and A diode region and, The aforementioned transistor region is A semiconductor layer having a first surface and a second surface facing the first surface, A first semiconductor region of the first conductivity type that is in contact with the second surface, A second semiconductor region of a second conductivity type is provided between the first semiconductor region and the first surface, A third semiconductor region of the second conductivity type is provided between the second semiconductor region and the first surface, and has a lower concentration of second conductivity type impurities than the second semiconductor region. A fourth semiconductor region of a first conductivity type is provided between the third semiconductor region and the first surface, A fifth semiconductor region of a second conductivity type is provided between the fourth semiconductor region and the first surface and is in contact with the first surface, A semiconductor layer including, The gate electrode facing the semiconductor region of the fourth reference, A gate insulating film is provided between the gate electrode and the fourth semiconductor region, The first electrode in contact with the fifth semiconductor region, A second electrode in contact with the first semiconductor region, Includes, The diode region is The second semiconductor region described above, The above-mentioned third semiconductor region, A sixth semiconductor region of a second conductivity type is provided between the second semiconductor region and the second surface, is in contact with the second surface, and has a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the second semiconductor region. A seventh semiconductor region of a first conductivity type is provided between the third semiconductor region and the first surface and is in contact with the first surface, The semiconductor layer includes, The first electrode in contact with the seventh semiconductor region, The second electrode in contact with the sixth semiconductor region, Includes, The second semiconductor region includes the first region and the second region. The first region is provided between the sixth semiconductor region and the third semiconductor region. The second region is provided between the first semiconductor region and the third semiconductor region. A semiconductor device wherein the concentration of a second conductivity type impurity in the first region is 80% or more and 120% or less of the concentration of a second conductivity type impurity in the second region, and the carrier concentration in the first region is lower than the carrier concentration in the second region. [Claim 2] The semiconductor device according to claim 1, wherein the crystal defect density of the first region is higher than the crystal defect density of the second region. [Claim 3] The aforementioned second semiconductor region further includes a third region, The semiconductor device according to claim 1, wherein the third region is in contact with the second surface, the third region is provided between the sixth semiconductor region and the first semiconductor region, and the carrier concentration of the first region is lower than the carrier concentration of the third region. [Claim 4] The semiconductor device according to claim 3, wherein the third region has a first portion in contact with the second surface and a second portion between the first portion and the third semiconductor region, and the concentration of the second conductivity type impurity in the first portion is higher than the concentration of the second conductivity type impurity in the second portion. [Claim 5] The semiconductor device according to claim 3, wherein the semiconductor layer further includes an eighth semiconductor region of a second conductivity type, provided between the second semiconductor region and the third semiconductor region, the second conductivity type impurity concentration being lower than that of the sixth semiconductor region and higher than that of the third semiconductor region. [Claim 6] The semiconductor device according to claim 1, further comprising an eighth semiconductor region of a second conductivity type, provided between the second semiconductor region and the third semiconductor region, wherein the concentration of the second conductivity type impurity is lower than that of the second conductivity type impurity in the sixth semiconductor region and higher than that of the second conductivity type impurity in the third semiconductor region. [Claim 7] The semiconductor device according to claim 1, wherein the carrier concentration in the first region is half or less of the carrier concentration in the second region.

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