Memory device

Abstract

To prevent process defects that occur during the manufacturing of memory devices. [Solution] The memory device according to the embodiment of the present disclosure includes a gate capping layer 221 which is embedded in a substrate 200 and includes a word line 120 extending in a first direction, a first capping portion 221a positioned between the word lines and in contact with the active area 110 of the substrate, and in contact with the upper surface of a bit line contact hole CNT having at least a portion of its side surface recessed toward the center in a second direction perpendicular to the first direction, and a second capping portion 221b located on the first capping portion and overlapping with at least a portion of the side surface of the bit line contact in a second direction, and having a width different from the width of the first capping portion.

Description

【Technical Field】 【0001】 Embodiments of the present disclosure relate to a memory device. 【0002】 (Cross - reference to related applications) This application claims priority under 35 U.S.C.§ 119(a) to Korean Patent Application No. 10 - 2024 - 0177281, filed on December 3, 2024, the entire contents of which are incorporated herein by reference. 【Background Art】 【0003】 Due to characteristics such as miniaturization, multi - functionality, and / or low manufacturing cost, memory devices have been in the spotlight as important elements in the electronics industry. As the electronics industry develops highly, memory devices are becoming more and more highly integrated. For the high integration of memory devices, the line width of the wiring included in the memory device is gradually decreasing, and the size of the memory cell is also shrinking. As a result, the difficulty of the process of forming the memory cell is increasing. 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0004】 Embodiments of the present disclosure can provide a memory device capable of preventing process defects occurring in the manufacturing process of the memory device. 【0005】 The problems of the embodiments of the present disclosure are not limited to the problems mentioned in this specification, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. 【Means for Solving the Problems】 【0006】 Embodiments of the present disclosure can provide a memory device including a gate capping layer comprising: word lines embedded in a substrate and extending in a first direction; bit line contacts positioned between the word lines and in contact with the active area of ​​the substrate, with at least a portion of their sides recessed toward the center in a second direction perpendicular to the first direction; a first capping portion in contact with the upper surface of the word lines; and a second capping portion located on the first capping portion, overlapping with at least a portion of the sides of the bit line contacts in the second direction, and having a width different from the width of the first capping portion. 【0007】 Embodiments of the present disclosure can provide a memory device comprising: word lines embedded in a substrate and extending in a first direction; bit line contacts positioned between the word lines and in contact with the active region of the substrate, with at least a portion of their sides recessed toward the center in a second direction perpendicular to the first direction; a gate capping layer overlapping the word lines and at least a portion of which overlaps with at least a portion of the sides of the bit line contacts in the second direction; and a buffer layer positioned on the gate capping layer and surrounding the bit line contacts. 【0008】 Embodiments of the present disclosure can provide a memory device comprising a word line embedded in a substrate and extending in a first direction, a bit line contact positioned between the word line and in contact with an active area of ​​the substrate, a first capping portion in contact with the upper surface of the word line, a second capping portion located on the first capping portion, the lower surface of the second capping portion being higher than the upper surface of the substrate, and a buffer layer covering the second capping portion of the gate capping layer and surrounding the bit line contact. [Effects of the Invention] 【0009】 According to embodiments of this disclosure, process defects that occur during the manufacturing process of memory devices can be prevented. 【0010】 The effects of the embodiments of this disclosure are not limited to those described above, and other effects not mentioned will be clearly understood by those skilled in the art from the claims. [Brief explanation of the drawing] 【0011】 This disclosure will be better understood from the detailed description and accompanying drawings provided below. The detailed description and accompanying drawings are provided for illustrative purposes only and do not limit the content of this disclosure. 【0012】 [Figure 1] This figure shows an example of a planar structure of a memory device according to an embodiment of the present disclosure. [Figure 2] This figure shows an example of the cross-sectional structure of part II' in Figure 1. [Figure 3] This figure shows an example of the cross-sectional structure of section II-II' in Figure 1. [Figure 4] This figure shows an example of the cross-sectional structure of section III-III' in Figure 1. [Figure 5] These are enlarged views of Figure 1, item 10 and Figure 2, item 20. [Figure 6] These are enlarged views of Figure 1, item 10 and Figure 2, item 20. [Figure 7] These are enlarged views of Figure 1, item 10 and Figure 2, item 20. [Figure 8] This figure shows another example of the cross-sectional structure of part II' in Figure 1. [Figure 9] This figure shows another example of the cross-sectional structure of section II-II' in Figure 1. [Figure 10] These are enlarged views of Figure 8, part 30 and Figure 9, part 40. [Figure 11] These are enlarged views of Figure 8, part 30 and Figure 9, part 40. [Figure 12] This figure shows an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. [Figure 13] This figure shows an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. [Figure 14]It is a diagram showing an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. [Figure 15] It is a diagram showing an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. [Figure 16] It is a diagram showing an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. [Figure 17] It is a diagram showing an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. [Figure 18] It is a diagram showing an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. [Figure 19] It is a diagram showing an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. [Figure 20] It is a diagram showing an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. [Figure 21] It is a diagram showing an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. [Figure 22] It is a diagram showing another example of a method for manufacturing a memory device according to an embodiment of the present disclosure. 【Embodiments for Carrying Out the Invention】 【0013】 Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, for the same components, even if they are shown on other drawings, they may be given the same reference numerals as much as possible. In describing the present invention, when it is determined that a specific description of related known configurations or functions may obscure the gist of the present disclosure, the detailed description thereof will be omitted. When terms such as "including", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it can include the case of including a plurality unless there are specific descriptions. 【0014】 Furthermore, in describing the components of this disclosure, terms such as 1, 2, A, B, (a), (b), etc., may be used. These terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of such components. 【0015】 In descriptions of the positional relationships of components, when it is stated that two or more components are “linked,” “joined,” or “connected,” it should be understood that while two or more components can be directly “linked,” “joined,” or “connected,” it is also possible for two or more components to be further “interposed” with other components before being “linked,” “joined,” or “connected.” Here, the other components may be included in one or more of the two or more components that are “linked,” “joined,” or “connected” to each other. 【0016】 In descriptions of temporal relationships concerning constituent elements, operating methods, or manufacturing methods, when temporal order or sequential relationships are described using phrases such as "after," "following," "next," or "before," unless "immediately" or "directly" is used, this can include cases that are not continuous. 【0017】 On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.). 【0018】 Various embodiments of this disclosure will be described in detail below with reference to the attached drawings. 【0019】 In the attached drawings, the three directions parallel to the top surface of the substrate are defined as the first direction FD, the second direction SD, and the third direction TD, respectively, and the direction projecting perpendicularly from the top surface of the substrate is defined as the fourth direction VD. The first direction FD and the second direction SD may be substantially perpendicular to each other. The fourth direction VD is perpendicular to the first direction FD, the second direction SD, and the third direction TD. In the following specification, "perpendicular" or "perpendicular direction" is used with substantially the same meaning as the fourth direction VD. The direction indicated by the arrow in the figures and its reverse direction indicate the same direction. 【0020】 Figure 1 shows an example of a planar structure of a memory device according to an embodiment of the present disclosure. 【0021】 Referring to Figure 1, a memory device according to an embodiment of the present disclosure includes an active region 110, a word line 120, and a bit line structure 130. The word line 120 extends in a first direction FD and crosses the active region 110. The word lines 120 are arranged parallel to each other in a second direction SD. In one embodiment, two corresponding word lines 120 may cross one active region 110. 【0022】 The bit line structures 130 extend in a second direction SD and traverse the active region 110. The bit line structures 130 are arranged parallel to each other in a first direction FD. The bit line structures 130 traverse the word line 120. The bit line structures 130 can be orthogonal to the word line 120. In one embodiment, one corresponding bit line structure 130 may traverse one active region 110. 【0023】 The bit line contact holes CNTs are positioned to overlap with each of the active regions 110. A single bit line contact hole CNT can correspond to one active region 110. The bit line contact hole CNTs can be located near the center of the active region 110. The bit line contact hole CNTs are located between the word lines 120. In one embodiment, at least a portion of the bit line contact hole CNTs can overlap with the word line 120 in a second direction SD. The bit line contact hole CNTs overlap with each of the bit line structures 130. In Figure 1, the bit line contact hole CNTs are shown as ellipses in plan view, but the shape of the bit line contact hole CNTs is not limited thereto. 【0024】 Figure 2 shows an example of the cross-sectional structure of section II' in Figure 1. Figure 3 shows an example of the cross-sectional structure of section II-II' in Figure 1. Figure 4 shows an example of the cross-sectional structure of section III-III' in Figure 1. Figures 5 to 7 are enlarged views of section 10 in Figure 1 and section 20 in Figure 2. 【0025】 Referring to Figures 2 and 5, the memory device according to the embodiment of the present disclosure includes a substrate 200, an element isolation layer 203, a gate structure 210, a first insulating layer 202, a gate capping layer 221, a buffer layer 222, a first spacer 231, a bit line contact 230, a bit line structure 130, and a bit line spacer 251. 【0026】 The substrate 200 may include a semiconductor substrate such as a silicon wafer or an SOI (Silicon On Insulator) wafer. The substrate 200 may include a III-V semiconductor substrate, such as a compound semiconductor substrate such as GaAs. The substrate 200 may include single-crystal silicon, polysilicon, amorphous silicon, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof. 【0027】 An element isolation layer 203 defining an active region 110 is disposed within the substrate 200. The active region 110 can be separated from each other by the element isolation layer 203 along a first direction FD, a second direction SD, and a third direction TD. The active region 110 and the element isolation layer 203 can be formed using trench element isolation techniques such as STI (Shallow Trench Isolation). In one embodiment, the active region 110 may include single-crystal silicon having p-type impurities. The p-type impurities may include B, BF, BF2, or a combination thereof. The element isolation layer 203 may be a single layer or a multilayer. The element isolation layer 203 may include at least two selected from the group consisting of Si, O, N, C, and H. The element isolation layer 203 may include silicon oxide, silicon nitride, silicon oxynitride, low-K dielectrics, high-K dielectrics, or a combination thereof. 【0028】 A gate structure 210 is embedded within the substrate 200. The gate structure 210 includes a gate insulating layer 211 and a word line 120. The gate insulating layer 211 surrounds the sides and bottom of the word line 120. The top surface of the gate insulating layer 211 may be located higher than the top surface of the word line 120. However, it is not limited to this, and the top surface of the gate insulating layer 211 may be located at the same height as the top surface of the word line 120, or at a lower height than the top surface of the word line 120. The word line 120 may include an upper word line 213 and a lower word line 212. The word line 120 may be located lower vertically than the top surface of the active region 110. 【0029】 The gate insulating layer 211 may include silicon oxide, silicon nitride, silicon oxynitride, high-silicon dielectric, or a combination thereof. The word line 120 may include conductive materials such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. The upper word line 213 may be made of a different material from the material constituting the lower word line 212. In one embodiment, the upper word line 213 may include a low work function material, and the lower word line 212 may include a high work function material. For example, the upper word line 213 may include doped polysilicon, and the lower word line 212 may include titanium nitride. 【0030】 A first insulating layer 202 is placed on the active region 110. In one embodiment, the first insulating layer 202 may include a material such as ULTO (Ultra low temperature oxide). 【0031】 A gate capping layer 221 is positioned on the word line 120. The gate capping layer 221 overlaps with the word line 120. In one embodiment, each of the gate capping layers 221 can correspond to one word line 120. The gate capping layer 221 includes a first capping portion 221a and a second capping portion 221b. 【0032】 The first capping portion 221a contacts the upper surface of the upper word line 213. In one embodiment, the first capping portion 221a can fill the space between the inner surfaces of the gate insulating layer 211. 【0033】 In another embodiment, the first capping portion 221a can be positioned on the gate insulating layer 211. For example, if the upper surface of the gate insulating layer 211 is at the same height as the upper surface of the upper word line 213, the first capping portion 221a can be positioned on the gate insulating layer 211 and the upper word line 123. In this case, the first capping portion 221a can fill the space between the active regions 110 and the space between the inner surfaces of the first insulating layer 202. 【0034】 In one embodiment, the lower surface of the first capping portion 221a can be positioned higher than the upper surface of the substrate 200. 【0035】 The second capping portion 221b is positioned on the first capping portion 221a. The second capping portion 221b is continuous with the first capping portion 221a. The width of the second capping portion 221b may differ from the width of the first capping portion 221a. The width of the second capping portion 221b will be described later with reference to Figure 3. In one embodiment, the lower surface of the second capping portion 221b can contact the upper surface of the gate insulating layer 211. In one embodiment, the lower surface of the second capping portion 221b can contact the upper surface of the first insulating layer 202. 【0036】 The gate capping layer 221 may include silicon oxide, silicon nitride, silicon oxynitride, low-K dielectrics, high-K dielectrics, or a combination thereof. In one embodiment, the gate capping layer 221 may include silicon nitride. 【0037】 The buffer layer 222 is placed on the first insulating layer 202, the element isolation layer 203, the gate insulating layer 211, and the gate capping layer 221. The buffer layer 222 fills the space between the gate capping layers 221 corresponding to different word lines 120. The buffer layer 222 can contact the upper surface of the first insulating layer 202. The buffer layer 222 covers the second capping portion 221b of the gate capping layer 221. The buffer layer 222 contacts the upper and side surfaces of the second capping portion 221b of the gate capping layer 221. 【0038】 The buffer layer 222 may include silicon oxide, silicon nitride, silicon oxynitride, low-K dielectrics, high-K dielectrics, or combinations thereof. For example, the buffer layer 222 may include SiCOH, SiCO, SiO2, SiCN, or combinations thereof. Alternatively, depending on the deposition method, the buffer layer 222 may include materials such as ULTO (Ultra low temperature oxide) or SOD (Spin On Dielectric). In one embodiment, the buffer layer 222 may include a material having an etching selectivity ratio with respect to the gate capping layer 221 and the first bit line 241. 【0039】 Referring to Figures 1, 2, and 5, bit line contact holes CNTs are positioned between the word lines 120. The bit line contact holes CNTs may be spaces formed by etching the buffer layer 222, the first insulating layer 202, and the gate insulating layer 211. In one embodiment, the bit line contact holes CNTs can be superimposed on the gate capping layer 221 and the word lines 120. The bit line contact holes CNTs expose the active region 110 of the substrate 200 between the word lines 120. 【0040】 A first spacer 231 is positioned along the side surface of the bit line contact hole CNT. In one embodiment, the first spacer 231 can conformally cover the side surface of the bit line contact hole CNT. The first spacer 231 surrounds the side surface of the bit line contact 230. The first spacer 231 may contain silicon nitride. 【0041】 The bit line contact 230 penetrates the buffer layer 222 and the first insulating layer 202 to contact the active region 110 of the substrate 200. In one embodiment, the side surface of the bit line contact 230 facing the word line 120 may have a shape that is recessed toward the center of the bit line contact 230. The side surface of the bit line contact 230 may be recessed toward the second capping portion 221b of the gate capping layer 221. In one embodiment, the width of the bit line contact 230 may be smallest in the region adjacent to the lower surface of the second capping portion 221b. The bit line contact 230 may include conductive materials such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. The detailed structure of the bit line contact 230 will be described later with reference to Figure 3. 【0042】 A bit line structure 130 is placed on the bit line contact 230. The bit line structure 130 includes a first bit line 241, a second bit line 242, a third bit line 243, and a bit line capping layer 244. The first bit line 241, the second bit line 242, the third bit line 243, and the bit line capping layer 244 are stacked sequentially from the vertical direction. The first bit line 241, the second bit line 242, and the third bit line 243 can constitute a single bit line. The first bit line 241, the second bit line 242, and the third bit line 243 can include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The bit line capping layer 244 can include silicon oxide, silicon nitride, silicon oxynitride, low-silicon dielectric, high-silicon dielectric, or combinations thereof. In one embodiment, the first bit line 241 may be polysilicon, the second bit line 242 may be metal silicide, and the third bit line 243 may be metal. In one embodiment, the bit line capping layer 244 may be silicon nitride. 【0043】 Bit line spacers 251 are positioned on the sides of the bit line contact 230 and the bit line structure 130. The bit line spacers 251 may include silicon nitride. The space between the bit line spacers 251 and the first spacers 231 may be filled with insulating material. 【0044】 Referring to Figures 1, 3, and 5, the gate capping layers 221 can extend along a first direction FD. The gate capping layers 221 may be spaced apart from each other in a second direction SD. 【0045】 In one embodiment, the width W2 in the second direction SD of the second capping portion 221b of the gate capping layer 221 can decrease as it moves away from the upper surface of the substrate 200 in the vertical direction. For example, the cross-section of the second capping portion 221b may be a trapezoid where the width of the lower surface is greater than the width of the upper surface. However, the shape of the cross-section of the second capping portion 221b is not limited to this, and the cross-section of the second capping portion 221b may have various shapes such as a rectangle or a semicircle. 【0046】 In one embodiment, the second capping portion 221b has a maximum width W2 on its lower surface. max It can have the following: In one embodiment, the maximum width W2 of the second capping portion 221b max The width W1 of the first capping portion 221a in the second direction SD may be greater than the width W1 of the first capping portion 221a. That is, the second capping portion 221b may protrude further in the second direction SD than the first capping portion 221a. The second capping portion 221b may extend toward the recessed side surface of the bit line contact 230 in the second direction SD. 【0047】 Referring to Figures 3 and 5, the bit line contact 230 includes a first contact portion 230a, a second contact portion 230b, and a third contact portion 230c. 【0048】 The first contact portion 230a contacts the active region of the substrate 200. The first contact portion 230a overlaps with the first capping portion 221a of the gate capping layer 221 in a second direction SD. The width W3 of the first contact portion 230a in the second direction SD may be constant. For example, the width of the lower surface of the first contact portion 230a may be the same as the width of the upper surface. 【0049】 The second contact portion 230b is positioned on the first contact portion 230a. The second contact portion 230b is continuous with the first contact portion 230a. The second contact portion 230b overlaps with the second capping portion 221b of the gate capping layer 221 in the second direction SD. In one embodiment, the width W4 of the lower surface of the second contact portion 230b may be smaller than the width W3 of the upper surface of the first contact portion 230a. In one embodiment, the width of the second contact portion 230b may be smallest at the lower surface. In one embodiment, the shape of the second contact portion 230b may vary depending on the shape of the second capping portion 221b of the gate capping layer 221. 【0050】 The third contact portion 230c is positioned on the second contact portion 230b. The third contact portion 230c is continuous with the second contact portion 230b. The third contact portion 230c may be positioned higher than the second capping portion 221b of the gate capping layer 221. In one embodiment, the lower surface of the third contact portion 230c may be positioned higher than the upper surface of the second capping portion 221b. In one embodiment, the width W6 in the second direction SD of the lower surface of the third contact portion 230c may be greater than the width W5 in the second direction SD of the upper surface of the second contact portion 230b. 【0051】 In one embodiment, the second capping portion 221b of the gate capping layer 221 can be superimposed on the first contact portion 230a and the third contact portion 230c of the bit line contact 230 in the vertical direction. 【0052】 Referring to Figure 4, the memory device according to an embodiment of the present disclosure further includes a second spacer 532, a third spacer 533, and a contact plug 540. The contact plug 540 includes a lower contact plug 541 and an upper contact plug 542 positioned on the lower contact plug. The lower contact plug 541 and the upper contact plug 542 may include conductive materials such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. 【0053】 The contact plug 540 contacts the active region 110. In one embodiment, two contact plugs 540 can be positioned between the bit line contacts 230 in a first direction FD. Between the contact plugs 540, a first insulating layer 202 and a buffer layer 222 are positioned beneath the bit line structure 130. In one embodiment, in the first direction FD, the buffer layer 222 can be positioned between the bit line contacts 230. The second insulating layer 202 and buffer layer 222 can overlap perpendicularly with one element isolation layer 203. The lower surface of the first bit line 241 can contact the upper surface of the buffer layer 222. The bit line structure 130 and the contact plugs 540 may be arranged alternately with each other in the first direction FD. A bit line spacer 251 can be positioned between the bit line structure 130 and the contact plugs 540. 【0054】 The second spacer 532 is positioned on the side surface of the lower contact plug 541. The third spacer 533 is positioned in the space enclosed by the first spacer 231, the second spacer 532, and the bit line spacer 251. The first spacer 231 can be extended between the element isolation layer 203 and the third spacer 533. The bit line spacer 251 can be extended between the buffer layer 222 and the third spacer 533. 【0055】 The second spacer 532 and the third spacer 533 may include dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, low-silicon dielectric, high-silicon dielectric, or combinations thereof. 【0056】 Referring to Figures 2 and 6, in one embodiment, at least a portion of the side surface of the second contact portion 230b of the bit line contact 230 can be separated from the inner surface of the first spacer 231. In one embodiment, the bit line spacer 251 can be positioned on the side surfaces of the second contact portion 230b and the third contact portion 230c. 【0057】 In a direction different from the second direction SD (for example, the third direction TD or the direction extending parallel to the top surface of the substrate 200 between the first direction FD and the third direction TD), the width of the third contact portion 230c of the bit line contact 230 may be smaller than the width of the third contact portion 230c of the bit line contact 230 shown in Figure 5. In a direction different from the second direction SD (for example, the third direction TD or the direction extending parallel to the top surface of the substrate 200 between the first direction FD and the third direction TD), the width of the top surface of the second contact portion 230b of the bit line contact 230 may be substantially the same as the width of the bottom surface of the third contact portion 230c. The area between the bit line spacer 251 and the first spacer 231 may be filled with insulating material. 【0058】 Referring to Figures 3 and 6, in the second direction SD, the width of the third contact portion 230c of the bit line contact 230 may be substantially the same as the width of the third contact portion 230c of the bit line contact 230 shown in Figure 5. In the second direction SD, the width of the upper surface of the second contact portion 230b of the bit line contact 230 may be smaller than the width of the lower surface of the third contact portion 230c. 【0059】 Referring to Figures 2 and 7, in one embodiment, the side surfaces of the second contact portion 230b and the first contact portion 230a of the bit line contact 230 can be separated from the inner surface of the first spacer 231. In one embodiment, the bit line spacer 251 can be positioned on the side surfaces of the first contact portion 230a, the second contact portion 230b, and the third contact portion 230c. 【0060】 In a direction different from the second direction SD (for example, the third direction TD or the direction extending parallel to the top surface of the substrate 200 between the first direction FD and the third direction TD), the widths of the first contact portion 230a, the second contact portion 230b, and the third contact portion 230c of the bit line contact 230 may be substantially the same. The area between the bit line spacer 251 and the first spacer 231 can be filled with insulating material. 【0061】 Referring to Figures 3 and 7, in the second direction SD, the widths of the first contact portion 230a, the second contact portion 230b, and the third contact portion 230c of the bit line contact 230 may be substantially the same as the widths of the first contact portion 230a, the second contact portion 230b, and the third contact portion 230c described with reference to Figure 5. 【0062】 Figure 8 shows another example of the cross-sectional structure of section II' in Figure 1. Figure 9 shows another example of the cross-sectional structure of section II-II' in Figure 1. Figures 10 and 11 are enlarged views of section 30 in Figure 8 and section 40 in Figure 9. 【0063】 Referring to Figures 8 and 10, the memory device according to the embodiment of the present disclosure includes a substrate 200, an element isolation layer 203, a gate structure 210, a first insulating layer 202, a gate capping layer 221, a buffer layer 222, a first spacer 231, a bit line contact 230, a bit line structure 130, and a bit line spacer 251. 【0064】 A gate capping layer 221 is positioned on the word line 120. The gate capping layer 221 overlaps with the word line 120. In one embodiment, each of the gate capping layers 221 can correspond to one word line 120. The gate capping layer 221 includes a first capping portion 221a and a second capping portion 221b. 【0065】 The first capping portion 221a may be substantially identical to the first capping portion 221a described with reference to Figure 2. 【0066】 The second capping portion 221b is positioned on the first capping portion 221a. The second capping portion 221b is continuous with the first capping portion 221a. The width of the second capping portion 221b may differ from the width of the first capping portion 221a. The width of the second capping portion 221b will be described later with reference to Figure 9. In one embodiment, the lower surface of the second capping portion 221b can contact the upper surface of the gate insulating layer 211. In one embodiment, the lower surface of the second capping portion 221b can contact the upper surface of the first insulating layer 202. 【0067】 Referring to Figures 1, 8, and 10, bit line contact hole CNTs are positioned between the word lines 120. In one embodiment, the bit line contact hole CNTs can be superimposed on the gate capping layer 221 and the word lines 120. The bit line contact hole CNTs expose the active region 110 of the substrate 200 between the word lines 120. 【0068】 A first spacer 231 is positioned along the side surface of the bit line contact hole CNT. In one embodiment, the first spacer 231 can conformally cover the side surface of the bit line contact hole CNT. The first spacer 231 surrounds the side surface of the bit line contact 230. The first spacer 231 may contain silicon nitride. 【0069】 The bit line contact 230 penetrates the buffer layer 222 and the first insulating layer 202 to contact the active region 110 of the substrate 200. In one embodiment, the side surface of the bit line contact 230 facing the word line 120 may have a shape that is recessed toward the center of the bit line contact 230. The side surface of the bit line contact 230 may be recessed in the direction facing the second capping portion 221b of the gate capping layer 221. In one embodiment, the width of the bit line contact 230 may be smallest at the bottom surface of the bit line contact 230. 【0070】 Referring to Figures 1, 9, and 10, the gate capping layers 221 may extend along a first direction FD. The gate capping layers 221 may be spaced apart from each other in a second direction SD. 【0071】 In one embodiment, the width W3 in the second direction SD of the second capping portion 221b of the gate capping layer 221 can decrease as it moves away from the upper surface of the substrate 200 in the vertical direction. For example, the cross-section of the second capping portion 221b may have a configuration in which the width of the lower surface is greater than the width of the upper surface. However, the configuration of the cross-section of the second capping portion 221b is not limited thereto. 【0072】 In one embodiment, the second capping portion 221b has a maximum width W3 in the second direction SD on its lower surface. max It can have. In one embodiment, the maximum width W3 of the second capping portion 221b in the second direction SD max The width W1 of the first capping portion 221a in the second direction SD may be substantially the same as the width W1 of the first capping portion 221a. That is, the second capping portion 221b does not have to protrude more than the first capping portion 221a in the second direction SD. The second capping portion 221b can extend toward the recessed side surface of the bit line contact 230 in the second direction SD. 【0073】 Referring to Figures 8 and 11, in one embodiment, the side surface of the bit line contact 230 can be separated from the inner surface of the first spacer 231. In one embodiment, the bit line spacer 251 can be placed on all sides of the bit line contact 230. 【0074】 In a direction different from the second direction SD (for example, the third direction TD or the direction extending parallel to the top surface of the substrate 200 between the first direction FD and the third direction TD), the width of the bit line contact 230 may be smaller than the width of the bit line contact 230 shown in Figure 10. In a direction different from the second direction SD (for example, the third direction TD or the direction extending parallel to the top surface of the substrate 200 between the first direction FD and the third direction TD), the width of the bit line contact 230 may be constant. For example, the widths of the top and bottom surfaces of the bit line contact 230 may be substantially the same. The area between the bit line spacer 251 and the first spacer 231 can be filled with insulating material. 【0075】 Referring to Figures 9 and 11, in the second direction SD, the width of the bit line contact 230 may be substantially the same as the width of the bit line contact 230 shown in Figure 10. For example, in the second direction SD, the width of the upper surface of the bit line contact 230 may be greater than the width of the lower surface. 【0076】 Figures 12 to 21 show an example of a method for manufacturing a memory device according to an embodiment of the present disclosure. 【0077】 Referring to Figure 12, a substrate 200 is prepared in which an element isolation layer 203 defining the active region 110 of the substrate 200, a (buried) gate structure 210 embedded within the substrate 200, and a first insulating layer 202 are formed. 【0078】 The first insulating layer 202 can be formed before the gate structure 210. For example, after the first insulating layer 202 is formed on the substrate 200, the first insulating layer 202 and the upper part of the substrate 200 can be removed to form a trench in which the gate structure 210 will be placed. In one embodiment, the thickness of the first insulating layer 202 may be 100 angstroms or more and 300 angstroms or less. 【0079】 Subsequently, a gate structure 210 can be formed on the sides and bottom of the trench. The gate structure 210 can be formed within the active region of the element isolation layer 203 or the substrate 200. Figure 12 shows, but is not limited to, a gate insulating layer 211 also being formed on the sides of the first insulating layer 202 and the sides of the element isolation layer 203. For example, the upper surface of the gate insulating layer 211 may be formed to be below the upper surface of the upper word line 213. 【0080】 Referring to Figure 13, a first gate-capping material 1300 can be formed on the word line 120. The first gate-capping material 1300 is formed to correspond to each of the word lines 120. The process of forming the first gate-capping material 1300 may include an etchback process. In one embodiment, the upper surface of the first gate-capping material 1300 may be located lower than the upper surface of the first insulating layer 202. In one embodiment, the upper surface of the first gate-capping material 1300 may be located higher than the upper surface of the substrate 200. The first gate-capping material 1300 may include silicon nitride. 【0081】 Referring to Figure 14, a portion of the first insulating layer 202, the element isolation layer 203, and the gate insulating layer 211 may be removed, exposing the side surface of the first gate capping material 1300. The step of removing a portion of the first insulating layer 202, the element isolation layer 203, and the gate insulating layer 211 may include an etching step. 【0082】 In one embodiment, the thickness of the first insulating layer 202 after etching may be between 50 angstroms and 100 angstroms. The upper surface of the first insulating layer 202 may be positioned lower than the upper surface of the first gate capping material 1300. 【0083】 Referring to Figure 15, a second gate-capping material 1500 is formed on the first insulating layer 202 and the first gate-capping material 1300. The second gate-capping material 1500 can be formed along the step of the lower layer. For example, in the region where the first gate-capping material 1300 is placed, the upper surface of the second gate-capping material 1500 can be positioned higher than the upper surface of the second gate-capping material 1500 in the region where the first gate-capping material 1300 is not placed. 【0084】 Referring to Figure 16, at least a portion of the first gate capping material 1300 and the second gate capping material 1500 is removed to form a gate capping layer 221. The step of forming the gate capping layer 221 may include an etching step. At least a portion of the first gate capping material 1300 and the second gate capping material 1500 can be removed to expose the upper surface of the first insulating layer 202. 【0085】 In one embodiment, the maximum width of the second capping portion 221b of the gate capping layer 221 may be greater than the width of the first capping portion 221a. 【0086】 Referring to Figure 17, a buffer layer 222 is formed on the gate capping layer 221. The buffer layer 222 can contact the upper surface of the first insulating layer 202. The buffer layer 222 can contact the upper and side surfaces of the second capping portion 221b of the gate capping layer 221. 【0087】 Referring to Figure 18, the buffer layer 222, the first insulating layer 202, and the top of the substrate 200 are removed to form bit line contact hole CNTs. The bit line contact hole CNTs expose the active region 110 of the substrate 200. The process of forming the bit line contact hole CNTs includes an etching process. In embodiments of this disclosure, the process of forming the bit line contact hole CNTs may include a self-align contact etching process using an etching selectivity ratio between the buffer layer 222 and the gate capping layer 221. 【0088】 The gas used in the etching process may include a substance that can increase the etching selectivity ratio between the gate capping layer 221 and the buffer layer 222. In one embodiment, the gas used in the etching process may include a material from the CxFy (where x and y are natural numbers) family, where the value of y divided by x may be 1.5 or greater. In one embodiment, the gas used in the dry etching process may be C4F6. 【0089】 During the process of forming the bit line contact hole CNT, the gate capping layer 221 may remain unetched. For example, after the bit line contact hole CNT is formed, the second capping portion 221b of the gate capping layer 221 may protrude outward beyond the buffer layer 222. That is, the width of the upper surface of the second capping portion 221b of the gate capping layer 221 may be substantially the same as the width of the upper surface of the capping portion 221b before the bit line contact hole CNT is formed. 【0090】 Referring to Figure 19, a first spacer 231 is formed on the side and bottom surfaces of the bit line contact hole CNT. In one embodiment, the first spacer 231 can be conformally formed on the side and bottom surfaces of the bit line contact hole CNT. Subsequently, the first spacer 231 located on the bottom surface of the bit line contact hole CNT can be removed to expose the active region 110 of the substrate 200. 【0091】 Referring to Figure 20, a bit line contact 230 is formed within the bit line contact hole CNT. The process of forming the bit line contact 230 may include a process of depositing a conductive material and an etch-back process. The upper surface of the bit line contact 230 can form a substantially the same plane as the upper surface of the buffer layer 222. The lower surface of the bit line contact 230 is in contact with the active region 110 of the substrate 200. 【0092】 Referring to Figure 21, a first bit line 241, a second bit line 242, a third bit line 243, and a bit line capping layer 244 are formed sequentially on the bit line contact 230 and the buffer layer 222. The process of forming the first bit line 241, the second bit line 242, the third bit line 243, and the bit line capping layer 244 may include an etching process. In one embodiment, the etching process may etch at least a portion of the bit line contact 230 together. Referring back to Figure 5, in one embodiment, at least a portion of the side surface of the third contact portion 230c of the bit line contact 230 may be separated from the first spacer 231. 【0093】 Bit line spacers 251 are formed on the first bit line 241, the second bit line 242, the third bit line 243, and the side surface of the bit line capping layer 244. In one embodiment, the bit line spacers 251 may extend below the upper surface of the buffer layer 222. The space between the first spacer 231 and the bit line spacers 251 may be filled with insulating material. 【0094】 Figure 22 shows another example of a method for manufacturing a memory device according to an embodiment of the present disclosure. 【0095】 The memory device shown in Figure 22 can be formed using the same method as the manufacturing method for the memory device described with reference to Figures 12 to 15. 【0096】 Referring to Figures 15 and 22, at least a portion of the first gate capping material 1300 and the second gate capping material 1500 is removed to form a gate capping layer 221. The step of forming the gate capping layer 221 may include an etching step. At least a portion of the first gate capping material 1300 and the second gate capping material 1500 can be removed to expose the upper surface of the first insulating layer 202. 【0097】 In one embodiment, the maximum width of the second capping portion 221b of the gate capping layer 221 may be the same as the width of the first capping portion 221a. 【0098】 Referring again to Figure 8, a buffer layer 222, a first spacer 231, a bit line contact 230, a bit line structure 130, and a bit line spacer 251 are formed on the gate capping layer 221. The process of forming the buffer layer 222, the first spacer 231, the bit line contact 230, the bit line structure 130, and the bit line spacer 251 may be substantially the same as the process of forming the buffer layer 222, the first spacer 231, the bit line contact 230, the bit line structure 130, and the bit line spacer 251 described with reference to Figures 17 to 21. 【0099】 Referring again to Figures 2, 3, and 5, the gate capping layer 221 includes a first capping portion 221a positioned on the word line 120 and a second capping portion 221b positioned on the first capping portion 221a and extending toward the recessed side surface of the bit line contact 230, having a different width from the first capping portion 221a. Of the side surfaces of the bit line contact 230, the side facing the word line 120 may be recessed toward the center of the bit line contact 230. In one embodiment, the process of forming the bit line contact hole CNT may include a self-align contact etching process using an etching selectivity ratio between the buffer layer 222 and the gate capping layer 221. In one embodiment, the gate capping layer 221 may contain a nitride, and the buffer layer 222 may contain an oxide. 【0100】 According to embodiments of this disclosure, when bit line contact hole CNTs are formed, an etching process is used that increases the etching selectivity ratio between the gate capping layer 221 and the buffer layer 222, so that only the buffer layer 222 can be selectively etched. In other words, the gate capping layer 221 around the bit line contact hole CNT may not be etched. Therefore, if the gate capping layer 221 is etched when bit line contact hole CNTs are formed, the bit line contact 230 and the word line 120 will come into close proximity, preventing the bit line contact 230 and the word line 120 from short-circuiting each other. 【0101】 Referring again to Figure 4, the buffer layer 222 is located beneath the bit line structure 130. The buffer layer 222 may include SiCOH, SiCO, SiO2, SiCN, or a combination thereof. Alternatively, depending on the deposition method, the buffer layer 222 may include materials such as ULTO (Ultra low temperature oxide) or SOD (Spin On Dielectric). The buffer layer 222 may include materials having etching selectivity ratios for the first bit line 241, the second bit line 242, and the third bit line 243. 【0102】 According to embodiments of this disclosure, the buffer layer 222 contains a material having an etching selectivity ratio for the first bit line 241, the second bit line 242, and the third bit line 243. Therefore, when forming the first bit line 241, the second bit line 242, and the third bit line 243, the buffer layer 222 may not be etched together. Consequently, when forming the first bit line 241, the second bit line 242, and the third bit line 243, defects in which the area where the contact plug 540 is landed is not opened due to etching residue can be prevented. 【0103】 Furthermore, the buffer layer 222 has higher insulating performance than the gate capping layer 221. Since the buffer layer 222 is placed around the bit line contact 230, when an ion implantation process is performed to improve the conductivity of the bit line contact 230, it is possible to prevent the bit line contact 230 and the surrounding structures (e.g., contact plug 540) from short-circuiting each other. 【0104】 The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments of this disclosure are for illustrative purposes only, and not to limit the technical concept of this disclosure, and the scope of the technical concept of this disclosure is not limited by such embodiments.

Claims

[Claim 1] A word line embedded within the substrate and extending in a first direction; A bit line contact positioned between the word lines, in contact with the active region of the substrate, and having at least a portion of its side surface recessed toward the center in a second direction perpendicular to the first direction; and A memory device including a gate capping layer comprising a first capping portion that contacts the upper surface of the word line, and a second capping portion located on the first capping portion, overlapping with at least a portion of the side surface of the bit line contact in the second direction, and having a width different from the width of the first capping portion. [Claim 2] The memory device according to claim 1, wherein the maximum width of the second capping portion of the gate capping layer is greater than the width of the first capping portion. [Claim 3] The aforementioned bit line contact is A first contact portion that contacts the active region of the substrate; A second contact portion located on the first contact portion and overlapping the second capping portion of the gate capping layer in the second direction; and Including a third contact portion located on the second contact portion, The memory device according to claim 2, wherein the width of the upper surface of the first contact portion is greater than the width of the lower surface of the second contact portion. [Claim 4] The memory device according to claim 3, wherein the width of the upper surface of the second contact portion of the bit line contact is smaller than the width of the lower surface of the third contact portion. [Claim 5] The memory device according to claim 3, wherein the second capping portion of the gate capping layer overlaps with the first contact portion and the third contact portion of the bit line contact. [Claim 6] The memory device according to claim 1, wherein the maximum width of the second capping portion of the gate capping layer is substantially the same as the width of the first capping portion. [Claim 7] The bit line spacer further includes the bit line contact surrounding the bit line contact, The memory device according to claim 1, wherein the bit line spacer contacts the upper surface of the second capping portion of the gate capping layer. [Claim 8] The memory device according to claim 1, wherein the lower surface of the second capping portion of the gate capping layer is located higher than the upper surface of the substrate. [Claim 9] The system further includes a buffer layer disposed on the gate capping layer, The memory device according to claim 1, wherein the buffer layer surrounds the bit line contact. [Claim 10] The memory device according to claim 9, wherein the buffer layer comprises an oxide and the gate capping layer comprises a nitride. [Claim 11] A word line embedded within the substrate and extending in a first direction; A bit line contact positioned between the word lines, in contact with the active region of the substrate, and having at least a portion of its side surface recessed toward the center in a second direction perpendicular to the first direction; A gate capping layer that overlaps with the word line and at least a portion of which overlaps with at least a portion of the side surface of the bit line contact in the second direction; and A memory device comprising a buffer layer disposed on the gate capping layer and surrounding the bit line contacts. [Claim 12] The aforementioned bit line contact is A first contact portion that contacts the active region of the substrate; A second contact portion located on the first contact portion and overlapping with at least a portion of the gate capping layer in the second direction; and Including a third contact portion located on the second contact portion, The memory device according to claim 11, wherein the width of the upper surface of the first contact portion is greater than the width of the lower surface of the second contact portion. [Claim 13] The memory device according to claim 12, wherein the width of the upper surface of the second contact portion of the bit line contact is smaller than the width of the lower surface of the third contact portion. [Claim 14] The memory device according to claim 11, wherein the gate capping layer includes a first capping portion that contacts the upper surface of the word line, and a second capping portion located on the first capping portion, overlapping with at least a portion of the side surface of the bit line contact in the second direction, and having a width different from the width of the first capping portion. [Claim 15] The memory device according to claim 14, wherein the maximum width of the second capping portion of the gate capping layer is greater than the width of the first capping portion. [Claim 16] The memory device according to claim 14, wherein the maximum width of the second capping portion of the gate capping layer is substantially the same as the width of the first capping portion. [Claim 17] The memory device according to claim 14, wherein the lower surface of the second capping portion of the gate capping layer is located higher than the upper surface of the substrate. [Claim 18] The bit line spacer further includes the bit line contact surrounding the bit line contact, The memory device according to claim 11, wherein the bit line spacer is in contact with the side surface of the buffer layer and the upper surface of the gate capping layer. [Claim 19] The memory device according to claim 11, wherein the buffer layer contains an oxide and the gate capping layer contains a nitride. [Claim 20] A word line embedded within the substrate and extending in a first direction; Bit line contacts positioned between the word lines and in contact with the active region of the substrate; A gate capping layer comprising a first capping portion that contacts the upper surface of the word line and a second capping portion located on the first capping portion, wherein the lower surface of the second capping portion is positioned higher than the upper surface of the substrate; and A memory device including a buffer layer that covers the second capping portion of the gate capping layer and surrounds the bit line contact.

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