Non-volatile memory device and electronic system including the same

Abstract

The present invention provides a non-volatile memory device with reduced overall size and an electronic system including the same. [Solution] The non-volatile memory device of the present invention comprises a first substrate, a plurality of memory cell structures located on the first substrate, a second substrate facing a first direction perpendicular to one surface of the first substrate, a first circuit element located on the second substrate, a third substrate located between the first substrate and the second substrate, a second circuit element located on the third substrate, and a through-structure including a dummy semiconductor pattern separated from the third substrate within the third substrate and a through-electrode penetrating the dummy semiconductor pattern in a first direction, wherein one end of the through-electrode is connected to the first circuit element and the other end is connected to at least one of the plurality of memory cell structures or the second circuit element.

Description

【Technical Field】 【0001】 The present invention relates to a non-volatile memory device and an electronic system including the same. 【Background Art】 【0002】 Semiconductor memory elements are broadly classified into volatile memory elements and non-volatile memory elements. A volatile memory element is a memory element in which stored data is lost when the power supply is interrupted, and examples thereof include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and the like. A non-volatile memory element is a memory element in which stored data is not lost even when the power supply is interrupted, and examples thereof include PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), flash memory devices, and the like. Recently, in line with the trend of high performance and low power consumption of semiconductor memory elements, next-generation semiconductor memory elements having non-volatility, such as MRAM (Magnetic Random Access Memory), PRAM (Phase-Change Random Access Memory), and FeRAM (Ferroelectric Random Access Memory), have been developed. As higher integration and higher performance of non-volatile memory devices are required, various studies have been conducted using non-volatile memory devices having different characteristics. 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0003】 The present invention has been made in view of the above prior art, and an object of the present invention is to provide a non-volatile memory device with a reduced overall size and an electronic system including the same. 【Means for Solving the Problems】 【0004】 A non-volatile memory device according to one aspect of the present invention, made to achieve the above objective, comprises a first substrate, a plurality of memory cell structures located on the first substrate, a second substrate facing a first direction perpendicular to one surface of the first substrate, a first circuit element located on the second substrate, a third substrate located between the first substrate and the second substrate, a second circuit element located on the third substrate, and a through-structure including a dummy semiconductor pattern separated from the third substrate within the third substrate and a through-electrode penetrating the dummy semiconductor pattern in a first direction, wherein one end of the through-electrode is connected to the first circuit element and the other end is connected to at least one of the plurality of memory cell structures or the second circuit element. 【0005】 To achieve the above objective, another aspect of the present invention provides a non-volatile memory device comprising: a first substrate; a gate stack structure including interlayer insulating layers and gate electrodes alternately stacked on the lower surface of the first substrate; a channel structure penetrating the gate stack structure in a first direction perpendicular to the lower surface of the first substrate; a first joint located below the channel structure and connected to at least one of the channel structures; a second substrate facing the first substrate in the first direction; a first circuit element located on the upper surface of the second substrate 210; and a position located between the first substrate and the second substrate. The device comprises a third substrate, a second circuit element located on the third substrate, a second junction located on the second circuit element and in contact with the first junction, a through-structure including a dummy semiconductor pattern separated from the third substrate within the third substrate and a through-electrode extending toward the upper surface of the second substrate through the dummy semiconductor pattern in a first direction, and a barrier pattern that penetrates the third substrate in a first direction and surrounds the side surface of the through-structure, wherein one end of the through-electrode is connected to the first circuit element and the other end is connected to at least one of the second junctions or the second circuit element. 【0006】 An electronic system according to one aspect of the present invention, made to achieve the above objective, comprises a main board, a non-volatile memory device on the main board, and a controller electrically connected to the non-volatile memory device on the main board, wherein the non-volatile memory device includes a first board, a plurality of memory cell structures located on the first board, a second board facing a first direction perpendicular to the first board, a first circuit element located on the second board, a third board located between the first and second boards, a second circuit element located on the third board, and a through-structure including a dummy semiconductor pattern separated from the third board within the third board and a through-electrode penetrating the dummy semiconductor pattern in a first direction, wherein one end of the through-electrode is connected to the first circuit element and the other end is connected to at least one of the plurality of memory cell structures or the second circuit element. [Effects of the Invention] 【0007】 According to the present invention, it is possible to provide a non-volatile memory device and an electronic system including the same that can improve reliability and reduce overall size. [Brief explanation of the drawing] 【0008】 [Figure 1] This is a cross-sectional view showing a first example of a non-volatile memory device according to one embodiment. [Figure 2] Figure 1 is a cross-sectional view showing an enlarged example of a channel structure included in a non-volatile memory device. [Figure 3] This is an enlarged cross-sectional view showing the "A" portion of Figure 1. [Figure 4] This is an enlarged cross-sectional view showing the first example of section "B" in Figure 3. [Figure 5] This is a plan view showing a first example of a partial area of ​​a non-volatile memory device according to one embodiment. [Figure 6] This is an enlarged cross-sectional view showing a second example of section "B" in Figure 3. [Figure 7] This is an enlarged cross-sectional view showing the third example of section "B" in Figure 3. [Figure 8]This is an enlarged cross-sectional view showing the fourth example of section "B" in Figure 3. [Figure 9] This is an enlarged cross-sectional view showing the fifth example of section "B" in Figure 3. [Figure 10] This is a plan view showing a second example of a partial area of ​​a non-volatile memory device according to one embodiment. [Figure 11] This is a plan view showing a third example of a partial area of ​​a non-volatile memory device according to one embodiment. [Figure 12] This is a plan view of a fourth example of a partial region of a non-volatile memory device according to one embodiment. [Figure 13] This is a cross-sectional view taken along the line I3-I3' in Figure 12. [Figure 14] This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to one embodiment. [Figure 15] This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to one embodiment. [Figure 16] This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to one embodiment. [Figure 17] This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to one embodiment. [Figure 18] This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to one embodiment. [Figure 19] This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to one embodiment. [Figure 20] This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to one embodiment. [Figure 21] This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to one embodiment. [Figure 22] This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to one embodiment. [Figure 23] This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to one embodiment. [Figure 24] It is a process cross-sectional view for explaining a method of manufacturing a non-volatile memory device according to an embodiment. [Figure 25] It is a partial cross-sectional view schematically showing a second example of a non-volatile memory device according to an embodiment. [Figure 26] It is a partial cross-sectional view schematically showing a third example of a non-volatile memory device according to an embodiment. [Figure 27] It is a partial cross-sectional view schematically showing a fourth example of a non-volatile memory device according to an embodiment. [Figure 28] It is a diagram schematically showing an electronic system including a non-volatile memory device according to an embodiment. [Figure 29] It is a perspective view schematically showing an electronic system including a non-volatile memory device according to an embodiment. [Figure 30] It is a cross-sectional view schematically showing a semiconductor package according to an embodiment. 【MODE FOR CARRYING OUT THE INVENTION】 【0009】 Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail while referring to the drawings. The present invention can be embodied in various different forms and is not limited to the embodiments described here. 【0010】 For the sake of clarity in explaining the present invention, parts that are unnecessary for the explanation are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification. 【0011】 Also, the sizes and thicknesses of each configuration shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to what is shown in the drawings. The thickness is enlarged to clearly represent a plurality of layers and regions in the drawings. And, in the drawings, for convenience of explanation, the thicknesses of some layers and regions are exaggeratedly shown. 【0012】 Furthermore, when a part such as a layer, membrane, region, or plate is said to be "on top of" another part, this includes not only the case where it is "directly above" the other part, but also the case where the other part is in between. Conversely, when one part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on top of" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the opposite direction of gravity. 【0013】 Furthermore, when a specification states that a part of it "includes" a certain component, unless otherwise stated, this does not mean that it excludes other components, but rather that it may include other components. 【0014】 Furthermore, throughout the specification, "plan view" refers to a view of the subject from above, and "cross-sectional view" refers to a view of a cross-section of the subject, obtained by cutting it vertically, from the side. 【0015】 Figures 1 to 3 are plan views and cross-sectional views illustrating a non-volatile memory device according to one embodiment. 【0016】 Figure 1 is a cross-sectional view showing a first example of a non-volatile memory device according to one embodiment; Figure 2 is an enlarged cross-sectional view showing an example of a channel structure included in the non-volatile memory device shown in Figure 1; and Figure 3 is an enlarged cross-sectional view showing portion "A" in Figure 1. For clear understanding, both the gate contact portion 184 and the connecting structure 188 are shown in Figure 1, but the positions of the gate contact portion 184 and the connecting structure 188 can be varied. 【0017】 Referring to Figures 1 to 3, the non-volatile memory device according to this embodiment includes a cell region 100 containing a memory cell structure and a circuit region 200 containing a peripheral circuit structure that controls the operation of the memory cell structure. In this embodiment, the circuit region 200 includes a first circuit region 201 and a second circuit region 202. 【0018】 In this embodiment, the cell region 100 and the circuit region 200 are bonded to each other to constitute a non-volatile memory device. The cell region 100 or the circuit region 200 corresponds to a semiconductor chip for a bonded semiconductor device included in the non-volatile memory device. In other words, the non-volatile memory device according to this embodiment is composed of a bonding vertical NAND flash memory (BV NAND), but this embodiment is not limited to this. The following description assumes that the non-volatile memory device according to this embodiment is a bonding vertical NAND flash memory, but this embodiment is not necessarily applicable only to bonding vertical NAND flash memory and can be applied to non-volatile memory devices of various structures. 【0019】 In this embodiment, the circuit region 200 and the cell region 100 correspond to the first structure 1100F and the second structure 1100S of the non-volatile memory device 1100 included in the electronic system 1000 shown in Figure 28, respectively. Alternatively, the circuit region 200 and the cell region 100 correspond to the first structure 4100 and the second structure 4200 of the semiconductor chip 2200 shown in Figure 30, respectively. 【0020】 The non-volatile memory device according to this embodiment includes a first substrate 110, a plurality of memory cells located on the first substrate 110, a second substrate 210, a first circuit element 220 located on the second substrate 210, a third substrate 310, a second circuit element 320 located on the third substrate 310, and a through-structure 370 penetrating the third substrate 310. In this embodiment, the first substrate 110 and the plurality of memory cells are located in a cell region 100, the second substrate 210 and the first circuit element 220 are located in a first circuit region 201, and the third substrate 310, the second circuit element 320, and the through-structure 370 are located in a second circuit region 202. 【0021】 In this embodiment, the cell region 100 is located on the circuit region 200. This eliminates the need to separately reserve the area corresponding to the circuit region 200 from the cell region 100, thus reducing the area of ​​the non-volatile memory device. 【0022】 In one embodiment, the non-volatile memory device is formed by bonding the cell region 100 to the circuit region 200 after the cell region 100 has been formed separately from the circuit region 200. For example, the cell region 100 is bonded to the circuit region 200 by a hybrid bonding method, such as a chip-to-chip (C2C) bonding process, a chip-to-wafer bonding process, or a wafer-to-wafer bonding process. When the cell region 100 and the circuit region 200 are formed in separate processes in this way, it is possible to prevent the formation of the cell region 100 from affecting the circuit region 200. 【0023】 The cell region 100 includes a first substrate 110, a gate stacked structure 120, a channel structure CH, a first wiring section 180, and a first bonding section 190 located on the first wiring section 180. Thus, the cell region 100, which corresponds to a semiconductor chip for a bonded semiconductor device, includes a first substrate 110 corresponding to a substrate, a first wiring section 180 corresponding to a wiring section located on the substrate, and a first bonding section 190 corresponding to a bonding section located on the wiring section. 【0024】 At least a portion of the first substrate 110 functions as a common source line. Although not clearly shown in Figure 1, in one embodiment, the source contact portion is electrically connected to the common source line. Unlike the one shown in Figure 1, a source connection portion is provided that is connected to the first substrate 110 by through vias that penetrate the outer insulating layer 110c from the outer surface side of the first substrate 110. In this case, the source contact portion is connected to the source connection portion either via through vias or directly. However, this embodiment is not limited thereto, and the electrical connection structure between the source contact portion and the common source line can be modified in various ways. 【0025】 The cell region 100 includes a cell array region 102 and a linking region 104. The cell region 100 includes at least a gate stack structure 120 and a channel structure CH located in the cell array region 102 as memory cell structures. Structures for linking the memory cell structures to a circuit region 200 or an external circuit are located in the cell array region 102 and / or the linking region 104. 【0026】 In one embodiment, the first substrate 110 includes a semiconductor layer containing a semiconductor material. For example, the first substrate 110 is a semiconductor substrate made of a semiconductor material, with a semiconductor layer formed on a base substrate. As an example, the first substrate 110 is composed of silicon, germanium, silicon-germanium, silicon-on-insulator, or germanium-on-insulator. Here, the first substrate 110 includes an n-type semiconductor layer doped with an n-type dopant such as phosphorus (P) or arsenic (As), and / or a p-type semiconductor layer doped with a p-type dopant such as boron (B) or gallium (Ga). As another example, the first substrate 110 includes an insulating layer or a support member containing an insulating material. In this case, after joining the cell region 100 to the circuit region 200, the semiconductor substrate provided in the cell region 100 is removed, and then the support member containing the insulating layer or insulating material is formed. This embodiment is not limited to the material of the first substrate 110, the conductivity type or material of the dopant doped into the semiconductor layer, etc. 【0027】 The gate stack structure 120 includes cell insulating layers 132 and gate electrodes 130 that are alternately stacked on one surface (the lower surface in Figure 1) of the first substrate 110. The channel structure CH penetrates the gate stack structure 120 and extends in an extension direction intersecting the first substrate 110. For example, the extension direction of the channel structure CH is the direction intersecting the first substrate 110 (for example, the vertical direction perpendicular to the first substrate 110), which corresponds to the Z-axis direction in the figure. 【0028】 The gate electrode 130 contains a variety of conductive materials. For example, the gate electrode 130 contains metallic materials such as tungsten (W), copper (Cu), and aluminum (Al), polycrystalline silicon, metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or combinations thereof. The cell insulating layer 132 contains a variety of insulating materials. For example, the cell insulating layer 132 contains silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant materials with a dielectric constant lower than that of silicon oxide, or combinations thereof. 【0029】 The channel structure CH includes a channel layer 140 and a gate dielectric layer 150 located on the channel layer 140 between the gate electrode 130 and the channel layer 140. The gate dielectric layer 150 located between the gate electrode 130 and the channel layer 140 includes a tunneling layer 152, a charge storage layer 154, and a blocking layer 156 that are sequentially formed on the channel layer 140. 【0030】 The channel structure CH further includes a core insulating layer 142 located inside the channel layer 140, although in an alternative example, the core insulating layer 142 may be omitted. The channel structure CH further includes a channel pad 144 disposed on the channel layer 140 and / or the gate dielectric layer 150. The channel pad 144 covers the upper surface (lower surface in Figure 1) of the core insulating layer 142 and is arranged to be electrically connected to the channel layer 140. 【0031】 Each channel structure CH forms a single memory cell string, and in a plan view, multiple channel structures CH are arranged in rows and columns, spaced apart from one another. For example, in a plan view, multiple channel structures CH can be arranged in various configurations such as a grid or a zigzag pattern. The channel structures CH have a columnar shape. As an example, in a cross-sectional view, the channel structures CH have sides that are inclined such that the width narrows as they approach the first substrate 110, depending on the aspect ratio. However, this embodiment is not limited thereto, and the arrangement, structure, and form of the channel structures CH can be varied in various ways. 【0032】 The channel layer 140 contains a semiconductor material, such as polycrystalline silicon. The core insulating layer 142 contains a variety of insulating materials. For example, the core insulating layer 142 contains silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The channel pad 144 contains a conductive material, such as polycrystalline or monocrystalline silicon doped with impurities. 【0033】 The tunneling layer 152 includes an insulating material (e.g., silicon oxide, silicon oxynitride) that allows charge tunneling. The charge storage layer 154 is used as a data storage area and includes polycrystalline silicon, silicon nitride, etc. The blocking layer 156 includes an insulating material that can prevent unwanted charge flow into the gate electrode 130. For example, the blocking layer 156 includes silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. In one embodiment, the blocking layer 156 includes a first blocking layer 156a that extends horizontally along the gate electrode 130, and a second blocking layer 156b that extends vertically between the first blocking layer 156a and the charge storage layer 154. 【0034】 However, this embodiment is not limited to the materials, structures, etc., of the channel layer 140, core insulating layer 142, channel pad 144, or gate dielectric layer 150. 【0035】 In one embodiment, the gate stacking structure 120 includes a plurality of gate stacking portions (121, 122) sequentially stacked on the first substrate 110. This allows for an increase in the number of stacked gate electrodes 130, thus enabling an increase in the number of memory cells with a stable structure. Figure 1 illustrates a gate stacking structure 120 that includes first and second gate stacking portions (121, 122). However, this embodiment is not limited to this, and the gate stacking structure 120 may include one or three or more gate stacking portions. 【0036】 As described above, when multiple gate stacking portions (121, 122) are provided, the channel structure CH can have multiple channel portions (CH1, CH2) that penetrate through the multiple gate stacking portions (121, 122) and are connected to each other. Each of the multiple channel portions (CH1, CH2) has a slanted side surface in cross-sectional view such that the width becomes narrower as it approaches the first substrate 110 in terms of aspect ratio, and a bent portion due to the width difference is provided at the connection portion of the multiple channel portions (CH1, CH2). As another example, the multiple channel portions (CH1, CH2) can have slanted side surfaces that are continuously connected without a bent portion. Figure 2 illustrates a case in which the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of the multiple channel portions (CH1, CH2) extend to each other and have an integral structure. As another example, the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of multiple channel portions (CH1, CH2) may be formed separately and electrically connected to each other, or separate channel pads may be further provided at the connecting portions of the multiple channel portions (CH1, CH2). Thus, this embodiment is not limited to the form of multiple channel portions (CH1, CH2). 【0037】 A connecting area 104 and a first wiring section 180 are provided to connect the gate stacking structure 120 and channel structure CH provided in the cell array area 102 to the circuit area 200 or an external circuit. The connecting area 104 is located around the cell array area 102, and a part of the first wiring section 180 is located therein. 【0038】 In one embodiment, the first wiring section 180 includes a gate electrode 130, a channel structure CH, and a member that electrically connects the first substrate 110 to a circuit region 200 or an external circuit. For example, the first wiring section 180 includes a bit line 182, a gate contact section 184, a connecting structure 188, contact vias 180a connected to these, and connecting wiring 180b connecting them. 【0039】 The bit line 182 extends in a second direction (Y-axis direction in the figure) that intersects the first direction (X-axis direction in the figure) (in the claims, "Z-axis direction" is described as the first direction) in which the gate electrode 130 extends, and is electrically connected to a channel structure CH, for example, a channel pad 144. 【0040】 Multiple gate electrodes 130 extend in the first direction (X-axis direction in the figure) within the connecting region 104, and the length of the extension of the multiple gate electrodes 130 in the connecting region 104 decreases sequentially as it moves further away from the first substrate 110. For example, the multiple gate electrodes 130 have a stepped shape in one or more directions within the connecting region 104. Multiple gate contact portions 184 in the connecting region 104 penetrate the interlayer insulating layer 138 and are electrically connected to the multiple gate electrodes 130 extending into the connecting region 104. 【0041】 Although not clearly shown in Figure 1, the source contact portion is electrically connected to the first substrate 110, which constitutes at least a part of the common source line. The connecting structure 188 is electrically connected to the input / output pads 198 provided in the cell region 100. Unlike in Figure 1, a separate input / output pad 198 may be provided in the circuit region 200. 【0042】 The connecting wiring 180b is located in the cell array region 102 and / or the connecting region 104. The bit line 182, gate contact portion 184, source contact portion, and / or connecting structure 188 are electrically connected to the connecting wiring 180b. For example, the bit line 182, gate contact portion 184, source contact portion, and / or connecting structure 188 are electrically connected to the connecting wiring 180b through contact vias 180a. The connecting wiring 180b includes a plurality of connecting wiring layers that are separated by an interlayer insulating layer 138 and connected by contact vias to form a desired path. 【0043】 Figure 1 illustrates that the connecting wiring 180b is provided as a single layer located on the same plane as the bit line 182, with the cell insulation layer 132 located in the portion other than the first wiring section 180. However, this is merely a simplified representation for convenience. Therefore, the connecting wiring 180b includes multiple wiring layers for electrical connection with the bit line 182 and / or the gate contact section 184, and further includes contact vias. 【0044】 The first circuit region 201 contains a second substrate 210 and first circuit elements 220 located on the second substrate 210. In this embodiment, the first circuit region 201 contains a plurality of first circuit elements 220 located on the second substrate 210. The second substrate 210 further contains element isolation patterns STI for separating each of the first circuit elements 220 from other first circuit elements 220. 【0045】 The second substrate 210 is a semiconductor substrate containing a semiconductor material. For example, the second substrate 210 is a semiconductor substrate made of a semiconductor material, and is a semiconductor substrate in which a semiconductor layer is formed on a base substrate. As an example, the second substrate 210 is composed of single crystal or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. 【0046】 In this embodiment, the first circuit element 220 formed on the second substrate 210 includes various circuit elements that control the operation of the second circuit element 320 provided in the second circuit region 202, or the memory cell structure provided in the cell region 100. In one embodiment, the first circuit element 220 includes a low-voltage element. When the non-volatile memory device according to this embodiment is in operation, the first circuit element 220 is subjected to a lower operating voltage compared to the second circuit element 320. In this embodiment, the first circuit element 220 is connected to an external first power supply, which has a relatively low voltage. For example, the first power supply has a lower voltage than the second power supply connected to the second circuit element 320. 【0047】 In this embodiment, the first circuit element 220 has a lower breakdown voltage compared to the second circuit element 320. As an example, the first circuit element 220 constitutes at least a part of the peripheral circuit structure of a logic circuit (reference numeral 1130 in Figure 24) or a page buffer (reference numeral 1120 in Figure 28). 【0048】 The first circuit element 220 includes, for example, multiple transistors, but this embodiment is not limited thereto. The first circuit element 220 includes not only active elements such as transistors, but also passive elements such as capacitors, resistors, and inductors. 【0049】 The non-volatile memory device according to this embodiment further includes a second wiring section 280 located on a second substrate 210, and interlayer insulating layers (261, 263) and an interface insulating layer 265 covering the second wiring section 280. 【0050】 A second wiring section 280 located on a second substrate 210 is electrically connected to a first circuit element 220. In one embodiment, the second wiring section 280 includes a plurality of wiring layers 286 separated by a wiring insulation layer 282 and connected by contact vias 284 to form a desired path. The wiring layers 286 or contact vias 284 include a variety of conductive materials, and the wiring insulation layer 282 includes a variety of insulating materials. For example, the wiring insulation layer 282 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. 【0051】 The interlayer insulating layers (261, 263) are located on the second wiring section 280. The interlayer insulating layers (261, 263) cover at least a portion of the wiring insulating layer 282, the contact via 284, and the wiring layer 286. The interlayer insulating layers (261, 263) contain insulating material. The interlayer insulating layers (261, 263) contain silicon oxide (SiO2), silicon nitride (SiN XThe material comprises at least one of the following: ), and silicon oxynitride (SiON). The interlayer insulating layers (261, 263) contain different insulating materials or the same insulating material. 【0052】 The interfacial insulating layer 265 is located on top of the interlayer insulating layer 263. The interfacial insulating layer 265 is located at the interface between the first circuit region 201 and the second circuit region 202. The interfacial insulating layer 265 contains an insulating material. The interfacial insulating layer 265 contains silicon oxide (SiO2), silicon nitride (SiN X ), and at least one of silicon oxynitride (SiON). 【0053】 The second circuit region 202 contains a third substrate 310, a second circuit element 320 formed on one surface of the third substrate 310, and a through-structure 370 that penetrates the third substrate 310. In this embodiment, the second circuit region 202 contains a plurality of second circuit elements 320 located on the third substrate 310. The third substrate 310 further contains element isolation patterns STI for separating each of the second circuit elements 320 from other second circuit elements 320. In this embodiment, at least a portion of the through-structure 370 is located in the first circuit region 201. Specifically, referring to Figures 1 and 3, one end of the through-electrode 371 extends toward the upper surface of the second substrate 210, so that a portion of the lower part of the through-electrode 371 is located in the first circuit region 201. 【0054】 The third substrate 310 is a semiconductor substrate. Since the composition and materials of the third substrate 310 are the same as or similar to those of the second substrate 210 described above, a detailed explanation is omitted. 【0055】 The second circuit element 320 formed on the third substrate 310 includes various circuit elements that control the operation of the memory cell structure provided in the cell region 100. In this embodiment, the second circuit element 320 includes a high-voltage element. The high-voltage element is an element designed to have a relatively high breakdown voltage. When the non-volatile memory device according to this embodiment is in operation, a higher operating voltage is applied to the second circuit element 320 compared to the first circuit element 220. In this embodiment, the second circuit element 320 is connected to an external second power supply, which has a relatively high voltage. For example, the second power supply has a higher voltage than the first power supply connected to the first circuit element 220. 【0056】 In this embodiment, the second circuit element 320 has a higher breakdown voltage compared to the first circuit element 220. As an example, the second circuit element 320 constitutes at least a part of the peripheral circuit structure of the decoder circuit (reference numeral 1110 in Figure 28) and / or the page buffer (reference numeral 1120 in Figure 28). 【0057】 The second circuit element 320 includes, for example, multiple transistors, but this embodiment is not limited thereto. The second circuit element 320 includes not only active elements such as transistors, but also passive elements such as capacitors, resistors, and inductors. 【0058】 The non-volatile memory device according to this embodiment further includes a third wiring section 380 located on the upper surface of the third substrate 310, an interface insulating layer 369 and a second bonding section 290 located on the third wiring section 380, and an interlayer insulating layer 361 and an interface insulating layer 367 located on the lower surface of the third substrate 310. 【0059】 The third wiring section 380, located on the third substrate 310, is electrically connected to the second circuit element 320. In one embodiment, the third wiring section 380 includes a plurality of wiring layers 386 that are separated by a wiring insulation layer 382 and connected by contact vias 384 to form a desired path. The wiring layers 386 or contact vias 384 include a variety of conductive materials, and the wiring insulation layer 382 includes a variety of insulating materials. For example, the wiring insulation layer 382 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. 【0060】 Since the interlayer insulating layer 361 and the interface insulating layers (367, 369) are similar to the interlayer insulating layers (261, 263) and interface insulating layer 265 described above, a detailed explanation will be omitted. 【0061】 In this embodiment, the non-volatile memory device has a first junction 190 and an interface insulating layer 193 located in a cell region 100 adjacent to a circuit region 200, and a second junction 290 and an interface insulating layer 369 located in a circuit region 200 adjacent to the cell region 100. In this embodiment, the cell region 100 and the circuit region 200 are joined by the joining of the first junction 190 and the second junction 290, thereby forming the non-volatile memory device. At least a portion of the first junction 190 is electrically connected to the first wiring portion 180. 【0062】 Specifically, the first joint 190 is connected to at least one of the bit line 182 and the connecting wiring 180b. The first joint 190 is connected to the channel structure CH via the bit line 182, or to the gate contact portion 184 or the connecting structure 188 via the connecting wiring 180b. Unlike in Figure 1, the first joint 190 may be connected to the bit line 182 via the connecting wiring 180b. 【0063】 The second junction 290 is connected to the first circuit element 220. Specifically, the second junction 290 is connected to a through-electrode 371 that penetrates the third substrate 310 through a contact via 384 or a wiring layer 386, and the through-electrode 371 is connected to the first circuit element 220 through the second wiring portion 280. 【0064】 The second junction 290 is connected to the second circuit element 320. Specifically, the second junction 290 is connected to the second circuit element 320 through a contact via 384 or a wiring layer 386. 【0065】 In this embodiment, the bit line 182, gate electrode 130, and first substrate 110 connected to the channel structure CH are electrically connected to the first circuit element 220 of the first circuit region 201 or the second circuit element 320 of the second circuit region 202 by the first wiring portion 180, the first joint portion 190, the second joint portion 290, the second wiring portion 280, the through electrode 371, and the third wiring portion 380. 【0066】 The through-structure 370 is located within the third substrate 310. The through-structure 370 includes a dummy semiconductor pattern 373 surrounded by the third substrate 310 and located away from the third substrate 310, and a through-electrode 371 that penetrates the dummy semiconductor pattern 373 in a third direction Z (in the claims, the "Z-axis direction" is described as the first direction). The through-structure 370 electrically connects a first circuit element 220 located on the second substrate 210 to a configuration located on the first substrate 110 and / or the third substrate 310 through the through-electrode 371. For example, referring to Figures 1 and 3, the first circuit element 220 is connected to a second circuit element 320 located on the third substrate 310 through the through-electrode 371. For example, the first circuit element 220 is connected to a second junction 290 located in the second circuit region 202 via a through electrode 371, and is connected to a channel structure CH, a gate contact portion 184, a connecting structure 188, and / or a source contact portion within the cell region 100 via the first junction 190 connected to the second junction 290. 【0067】 The through-electrode 371 is surrounded by the third substrate 310 and extends toward the upper surface of the second substrate 210, penetrating a dummy semiconductor pattern 373 located away from the third substrate 310 in the third direction Z. One end of the through-electrode 371 extending toward the upper surface of the second substrate 210 is connected to a contact via 284 or a wiring layer 286. The through-electrode 371 is connected to the first circuit element 220 through the contact via 284 or the wiring layer 286. The other end of the through-electrode 371 located on the third substrate 310 is connected to a wiring layer 386 or a contact via 384. The through-electrode 371 is connected to the second circuit element 320 via the wiring layer 386 or the contact via 384. Alternatively, the through-electrode 371 is connected to at least one of a plurality of memory cells located in the cell region 100 through junctions (190, 290) connected to the wiring layer 386 or the contact via 384. Specifically, the through electrode 371 is connected to the gate stack structure 120 and / or channel structure CH located in the cell region 100 through joints (190, 290) connected to the wiring insulation layer 382 or contact via 384. 【0068】 The through electrode 371 contains a conductive material. For example, the through electrode 371 includes metallic materials such as tungsten (W), copper (Cu), and aluminum (Al), polycrystalline silicon, metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or combinations thereof. 【0069】 The dummy semiconductor pattern 373 is located within the third substrate 310, but separated from the third substrate 310. The dummy semiconductor pattern 373 is electrically isolated from the third substrate 310. The dummy semiconductor pattern 373 does not have any portion in contact with the third substrate 310. In this embodiment, the dummy semiconductor pattern 373 has substantially the same thickness as the third substrate 310. The upper surface of the dummy semiconductor pattern 373 is located at substantially the same level as the upper surface of the third substrate 310. The lower surface of the dummy semiconductor pattern 373 is located at substantially the same level as the lower surface of the third substrate 310. 【0070】 A portion of the dummy semiconductor pattern 373 is penetrated by the through-electrode 371. Referring to Figures 1 and 3, the dummy semiconductor pattern 373 is penetrated by the through-electrode 371 in the third direction Z. The dummy semiconductor pattern 373 surrounds at least a portion of the side surface of the through-electrode 371. The dummy semiconductor pattern 373 surrounds the side surface of the through-electrode 371 in the region where the third substrate 310 and the through-electrode 371 overlap horizontally (for example, in the first direction X or the second direction Y). The inner surface of the dummy semiconductor pattern 373 is in contact with the through-electrode 371 in the region where the third substrate 310 and the through-electrode 371 overlap horizontally. The outer surface of the dummy semiconductor pattern 373 is in contact with the barrier pattern 330, which will be described later. 【0071】 The dummy semiconductor pattern 373 contains a semiconductor material. For example, the dummy semiconductor pattern 373 is composed of single-crystal or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. In this embodiment, the dummy semiconductor pattern 373 contains the same material as the third substrate 310. This is due to the process characteristics in which the dummy semiconductor pattern 373 is formed by etching a portion of the third substrate 310 and separating it from the third substrate 310. However, it is not limited to this, and the dummy semiconductor pattern 373 may contain other materials different from the third substrate 310. 【0072】 The non-volatile memory device according to this embodiment further includes a barrier pattern 330 located between the third substrate 310 and the dummy semiconductor pattern 373. The barrier pattern 330 surrounds the outer surface of the dummy semiconductor pattern 373 between the third substrate 310 and the dummy semiconductor pattern 373. The barrier pattern 330 is formed, for example, by etching a portion of the third substrate 310 so that it penetrates in the third direction Z, forming the dummy semiconductor pattern 373, and then filling the space between the dummy semiconductor pattern 373 and the third substrate 310 with an insulating material. The dummy semiconductor pattern 373 and the third substrate 310 are separated from each other in the horizontal direction by the barrier pattern 330. In this embodiment, the distance between the dummy semiconductor pattern 373 and the third substrate 310 in the horizontal direction (e.g., the first direction X or the second direction Y) is greater than 0 and less than about 500 nm, or is equal to 500 nm. Alternatively, the horizontal distance (e.g., in the first direction X or the second direction Y) between the dummy semiconductor pattern 373 and the third substrate 310 is greater than 0, less than approximately 200 nm, or equal to 0. 【0073】 In this embodiment, the barrier pattern 330 includes an insulating material. For example, the barrier pattern 330 may include silicon oxide (SiO2), silicon nitride (SiN X ), and silicon oxynitride (SiON) are included. In this embodiment, the barrier pattern 330 contains the same insulating material as the wiring insulating layer 382, ​​but is not limited thereto. 【0074】 In the non-volatile memory device according to this embodiment, the through-electrode 371 is electrically isolated from the third substrate 310 by a barrier pattern 330 surrounding the dummy semiconductor pattern 373. In this case, it is possible to prevent electrical signals flowing through the through-electrode 371 from flowing to the second circuit element 320 through the third substrate 310, thereby improving the reliability of the non-volatile memory device. 【0075】 Furthermore, according to this embodiment, the through-electrode 371 penetrating the third substrate 310 can be formed in a small area in a single step, thereby improving the reliability of the manufacturing process for the non-volatile memory device and reducing the size of the memory device. This will be discussed later. 【0076】 The non-volatile memory device according to this embodiment further includes an outer region 106 located on one side of the linked region 104. The outer region 106 is a region that does not exist in the final product of the non-volatile memory device according to this embodiment. For example, in the final stage of the manufacturing process of the non-volatile memory device, the outer region 106 is separated from other regions (e.g., the cell array region 102 and the linked region 104) by a scribing process. 【0077】 In this embodiment, the outer region 106 contains a plurality of alignment keys 288 and 388. Alignment keys are patterns used in the manufacturing process of the non-volatile memory device according to this embodiment when alignment is required between substrates (110, 210, and 310) during the bonding process or photoprocessing, or when alignment is required between the photomask and the substrates (110, 210, and 310). Figure 1 shows alignment keys (288 and 388) located in the circuit region 200, but this is shown illustratively for the sake of explanation, and alignment keys may also be located in the cell region 100. 【0078】 Referring to Figure 1, the first alignment key 288 is located in a portion of the outer region 106 on the second substrate 210, and the second alignment key 388 is located in a portion of the outer region 106 on the third substrate 310. The first alignment key 288 and the second alignment key 388 overlap each other in the third direction Z. An alignment window WD is located between the first alignment key 288 and the second alignment key 388. The alignment window WD is a region where a portion of the substrate has been removed and filled with an insulating material for alignment between the two substrates. In Figure 1, the alignment window WD is the region where a portion of the third substrate 310 has been removed by the etching process. In this embodiment, the portion of the third substrate 310 that has been removed is filled with a wiring insulating layer 382. In this embodiment, the second substrate 210 and the third substrate 310 can be aligned by positioning the first alignment key 288 and the second alignment key 388 to overlap through the alignment window WD. 【0079】 Figures 4 and 5 are diagrams for specifically illustrating the through-structure 370 according to this embodiment. Specifically, Figure 4 is an enlarged cross-sectional view showing a first example of portion "B" in Figure 3, and Figure 5 is a plan view showing a first example of a part of a non-volatile memory device according to one embodiment. Figure 5 is a plan view at the level of the line I1-I1' in Figure 4. 【0080】 In the non-volatile memory device according to this embodiment, the through-structure 370 includes a plurality of through-electrodes 371 located adjacent to each other in the horizontal direction. Referring to Figures 4 and 5, four through-electrodes 371 are shown, but the number of adjacent through-electrodes 371 is not limited. Figures 4 and 5 show a plurality of through-electrodes 371 aligned spaced apart from each other along a second direction Y, but the position, direction, or arrangement of the plurality of through-electrodes 371 is not limited. For example, the through-electrodes 371 may be aligned in a first direction X, or spaced apart from each other in a diagonal direction between the first direction X and the second direction Y. For example, the through-electrodes 371 may be arranged in a matrix or a hexagonal shape within the third substrate 310. 【0081】 In this embodiment, the through-structure 370 includes a plurality of dummy semiconductor patterns 373 and a through-electrode 371 that penetrates each of the plurality of dummy semiconductor patterns 373 in the third direction Z. Each of the dummy semiconductor patterns 373 surrounds a portion of the side surface of the through-electrode 371 that penetrates itself in the third direction Z. The inner surface of each of the dummy semiconductor patterns 373 is in contact with the through-electrode 371 that penetrates itself in the third direction Z. 【0082】 Referring to Figure 5, the through electrode 371 is shown to have a circular planar shape, but this is illustrative, and the through electrode 371 can have a variety of planar shapes. For example, the through electrode 371 may have an elliptical or polygonal planar shape such as a triangle or quadrilateral. 【0083】 The dummy semiconductor pattern 373 is positioned horizontally separated from other adjacent dummy semiconductor patterns 373. In this embodiment, a barrier pattern 330 is located between two adjacent dummy semiconductor patterns 373. Multiple dummy semiconductor patterns 373 are electrically isolated from each other by the barrier pattern 330. Multiple through electrodes 371 are electrically isolated from each other by the barrier pattern 330 located between the dummy semiconductor patterns 373. 【0084】 Referring to Figure 5, the dummy semiconductor pattern 373 is shown to have a square planar shape, but this is illustrative, and the dummy semiconductor pattern 373 can have a variety of planar shapes. For example, the through-electrode 371 may be circular or elliptical, or have a planar shape of other polygons such as a rectangle, triangle, or pentagon. 【0085】 Figure 6 shows a portion of a non-volatile memory device according to one embodiment. Specifically, Figure 6 is an enlarged cross-sectional view showing a second example of portion "B" in Figure 3. The non-volatile memory device shown in Figure 6 has many similarities to the embodiment described above, so the following explanation will focus on the differences from the embodiment described above. The non-volatile memory device shown in Figure 6 differs from the embodiment described above in that it includes an air gap. 【0086】 Referring to Figure 6, in the non-volatile memory device according to this embodiment, an air gap AG is located between the dummy semiconductor pattern 373 and the third substrate 310. The air gap AG refers to the empty space located between one film and another. For example, the air gap AG includes air or gas used in the manufacturing process of the non-volatile memory device. In this embodiment, the air gap AG is located between the third substrate 310 and the dummy semiconductor pattern 373 in the region where the third substrate 310 and the dummy semiconductor pattern 373 overlap horizontally. The third substrate 310 and the dummy semiconductor pattern 373 are separated from each other by the air gap AG. The air gap AG surrounds the sides of the dummy semiconductor pattern 373. In other words, in the non-volatile memory device according to this embodiment, the barrier pattern 330 described with reference to Figures 1 to 5 is replaced by the air gap AG. 【0087】 Figures 7 and 8 show a portion of a non-volatile memory device according to one embodiment. Specifically, Figures 7 and 8 are enlarged cross-sectional views showing the third and fourth examples of portion "B" in Figure 3. Since the non-volatile memory device shown in Figures 7 and 8 has many similarities to the embodiment described above, the following explanation will focus on the differences from the embodiment described above. The non-volatile memory device shown in Figures 7 and 8 differs from the embodiment described above in that it includes voids formed inside the barrier pattern 330. 【0088】 Referring to Figures 7 and 8, in the non-volatile memory device according to this embodiment, a void is located between the dummy semiconductor pattern 373 and the third substrate 310. That is, unlike the one described with reference to Figure 6, in the non-volatile memory device according to this embodiment, a portion of the area between the third substrate 310 and the barrier pattern 330 is filled with the barrier pattern 330, and a void is located in the remaining portion. 【0089】 Figures 7 and 8 exemplify the locations where voids are formed within the barrier pattern 330. Referring to Figures 7 and 8, the barrier pattern 330 is located along the outer surface of the dummy semiconductor pattern 373 and the inner surface of the third substrate 310, with voids located between them, and a portion of the barrier pattern 330 also located above and below the voids. As shown in Figure 7, in cross-sectional view, the void has a trapezoidal shape within the barrier pattern 330, with its width gradually narrowing along the horizontal direction (for example, the first direction X or the second direction Y in Figures 7 and 8) as it approaches the second substrate 210. As shown in Figure 8, in cross-sectional view, the void has an elongated elliptical shape along the third direction Z within the barrier pattern 330. 【0090】 However, Figures 7 and 8 are illustrative examples of void formation locations within the barrier pattern 330, and voids can be formed at various locations between the third substrate 310 and the dummy semiconductor pattern 373. For example, voids are formed during the process of forming the barrier pattern 330. For instance, voids are formed at various locations between the dummy semiconductor pattern 373 and the third substrate 310 depending on the process equipment and conditions used to form the barrier pattern 330. 【0091】 For example, the aspect ratio of the formed film changes depending on the process equipment or process conditions used in the process of forming the barrier pattern 330. In this case, if the aspect ratio of the formed film is small compared to the space between the third substrate 310 and the dummy semiconductor pattern 373, the barrier pattern 330 will be formed only in a portion of the area between the third substrate 310 and the dummy semiconductor pattern 373, and voids will be located in the remaining portion. For example, even if the aspect ratio of the formed film is sufficiently high, voids will be formed between the dummy semiconductor pattern 373 and the third substrate 310 due to process time differences or the density of the formed film. For example, voids are intentionally formed to be located in a specific area within the barrier pattern 330. 【0092】 Figures 9 and 10 show a portion of a non-volatile memory device according to one embodiment. Specifically, Figure 9 is an enlarged cross-sectional view showing a fifth example of portion "B" in Figure 3, and Figure 10 is a plan view showing a second example of a portion of a non-volatile memory device according to one embodiment. Figure 10 is a plan view at the level of line II-II' in Figure 9. The non-volatile memory device shown in Figures 9 and 10 has many similarities to the embodiment described above, so the following explanation will focus on the differences from the embodiment described above. The non-volatile memory device shown in Figures 9 and 10 differs in part from the embodiment described above in that it further includes an insulating liner 335 surrounding the through electrode 371. 【0093】 Referring to Figures 9 and 10, the non-volatile memory device according to this embodiment includes an insulating liner 335 surrounding the side surface of the through-electrode 371. The insulating liner 335 is conformally positioned along the side surface of the through-electrode 371. The insulating liner 335 is positioned between the through-electrode 371 and the dummy semiconductor pattern 373 in the region where the through-electrode 371 and the dummy semiconductor pattern 373 overlap horizontally. In the region where the through-electrode 371 and the dummy semiconductor pattern 373 overlap horizontally, the insulating liner 335's outer surface is surrounded by the dummy semiconductor pattern 373. 【0094】 The insulating liner 335 contains an insulating material. For example, the insulating liner 335 contains silicon oxide (SiO2), silicon nitride (SiN X ), and at least one of silicon oxynitride (SiON), are included, but are not limited to. 【0095】 Figure 11 is a diagram showing a portion of a non-volatile memory device according to one embodiment. Specifically, Figure 11 is a plan view showing a third example of a portion of a non-volatile memory device according to one embodiment. Figure 11 is a plan view at the level of line II-II' in Figure 9. The non-volatile memory device shown in Figure 11 has many similarities to the embodiment described above, so the following explanation will focus on the differences from the embodiment described above. The non-volatile memory device shown in Figure 11 differs from the embodiment described above in that multiple through-electrodes 371 penetrate a single dummy semiconductor pattern 373 which is integrally formed. 【0096】 Referring to Figure 11, the non-volatile memory device according to this embodiment includes an insulating liner 335 surrounding the side surface of the through electrode 371. Since the insulating liner 335 is the same as the insulating liner 335 described with reference to Figures 9 and 10, a detailed explanation is omitted. 【0097】 As shown in Figure 11, in a non-volatile memory device, when multiple through-electrodes 371 are located adjacent to each other in the horizontal direction, the insulating liner 335 surrounds each side of the multiple through-electrodes 371. Unlike the embodiments described above, in the non-volatile memory device according to this embodiment, one dummy semiconductor pattern 373 is penetrated by multiple through-electrodes 371. Referring to Figure 11, when multiple through-electrodes 371 are located adjacent to each other, the adjacent multiple through-electrodes 371 penetrate a single dummy semiconductor pattern 373 formed as a single unit in the third direction Z. 【0098】 In this embodiment, the barrier pattern 330 surrounds the outer surface of the dummy semiconductor pattern 373. In this embodiment, the barrier pattern 330 is not located between two adjacent through electrodes 371. In this embodiment, even if the barrier pattern 330 is not located between two adjacent through electrodes 371, each of the through electrodes 371 is electrically isolated from each other by the insulating liner 335. 【0099】 Figures 12 and 13 show a portion of a non-volatile memory device according to one embodiment. Figure 12 is a plan view of a fourth example of a portion of a non-volatile memory device according to one embodiment, and Figure 13 is a cross-sectional view taken along the line I3-I3' in Figure 12. The non-volatile memory device shown in Figures 12 and 13 has many similarities to the embodiment described above, so the following explanation will focus on the differences from the embodiment described above. The non-volatile memory device shown in Figures 12 and 13 differs in part from the embodiment described above in that a semiconductor pattern is included in a portion of the barrier pattern 330. 【0100】 Referring to Figures 12 and 13, in the non-volatile memory device according to this embodiment, the barrier pattern 330 includes a first barrier pattern 331 surrounding the outer casing of the through-structure 370 and a second barrier pattern 343 located between a plurality of dummy semiconductor patterns 373 contained within a single through-structure 370. 【0101】 Specifically, as shown in Figures 12 and 13, in the non-volatile memory device according to this embodiment, when a plurality of through-electrodes 371 and dummy semiconductor patterns 373 surrounding each of them are located adjacent to each other in the through-structure 370, the first barrier pattern 331 surrounds the outer casing of the through-structure 370, and the second barrier pattern 343 is located between the dummy semiconductor patterns 373. 【0102】 In this embodiment, the first barrier pattern 331 includes an insulating material. The specific structure and materials contained in the first barrier pattern 331 are the same as those of the barrier pattern 330 described in the above embodiment, so a detailed explanation is omitted. 【0103】 In this embodiment, the second barrier pattern 343 includes a plurality of semiconductor patterns (343a, 343b), each containing a semiconductor material. In this embodiment, the first semiconductor pattern 343b and the second semiconductor pattern 343a are doped with different types of impurities. In this embodiment, the first semiconductor pattern 343b is doped with a first conductivity type impurity, and the second semiconductor pattern 343a is doped with a second conductivity type impurity of a different type from the first conductivity type impurity. For example, the first semiconductor pattern 343b is doped with a p-type impurity, and the second semiconductor pattern 343a is doped with an n-type impurity. Exemplarily, each of the plurality of semiconductor patterns (343a, 343b) is formed by an ion implantation process (IIP), but is not limited thereto. 【0104】 Specifically, referring to Figures 12 and 13, each of the multiple semiconductor patterns (343a, 343b) extends in the first direction X and the third direction Z between the dummy semiconductor pattern 373. The upper surface of each of the multiple semiconductor patterns (343a, 343b) is at the same level as the upper surface of the dummy semiconductor pattern 373, and the lower surface of each of the multiple semiconductor patterns (343a, 343b) is at the same level as the lower surface of the dummy semiconductor pattern 373. 【0105】 Referring to Figures 12 and 13, the multiple semiconductor patterns (343a, 343b) are arranged alternately among the multiple second barrier patterns 343 along the direction in which the through-electrodes 371 are arranged (for example, the second direction Y in Figures 12 and 13). Referring to Figures 12 and 13, the second barrier pattern 343 includes one first semiconductor pattern 343b and two second semiconductor patterns 343a located on either side of the first semiconductor pattern 343b. Referring to Figures 12 and 13, the two second semiconductor patterns 343a are spaced apart from each other with the first semiconductor pattern 343b in between. 【0106】 In the structure shown in Figures 12 and 13, the second barrier pattern 343 located between the two through electrodes 371 prevents charge from moving across the second barrier pattern 343 to the adjacent through electrode 371 due to the potential barrier located at the boundary between the p-type semiconductor region and the n-type semiconductor region, thereby electrically isolating the adjacent through electrodes 371. 【0107】 Figures 14 to 23 are cross-sectional process views illustrating a method for manufacturing a non-volatile memory device according to one embodiment. 【0108】 Figure 14 shows the first circuit region 201 as described with reference to Figures 1 to 3. As shown in Figure 14, the first circuit element 220 and the second wiring section 280 are formed on the second substrate 210. 【0109】 First, an element isolation pattern (STI) is formed around the region on the second substrate 210 where the first circuit element 220 is formed, to separate it from the first circuit element 220. Then, a plurality of first circuit elements 220 are formed on the second substrate 210. In this embodiment, the first circuit element 220 includes source / drain electrodes, a gate insulating film, a gate electrode, and a gate spacer, respectively. Photo-etching and ion implantation processes are performed to form the first circuit elements 220 on the second substrate 210. 【0110】 Next, a second wiring section 280 is formed on the first circuit element 220. First, a wiring insulation layer 282 covering the first circuit element 220 is formed on the second substrate 210. After this, a portion of the wiring insulation layer 282 is etched by a photo-etching process, and then a conductive material is deposited to form contact vias 284 and a wiring layer 286. In Figure 14, the wiring insulation layer 282 is shown as a single layer, but the wiring insulation layer 282 consists of multiple layers. For example, after depositing the wiring insulation layer 282, the process of patterning it to form contact vias 284 and a wiring layer 286 is repeated multiple times to form the second wiring section 280 as shown in Figure 14. Next, multiple interlayer insulation layers (261, 263) and an interface insulation layer are formed on the wiring insulation layer 282. In this embodiment, some of the steps for forming the interlayer insulation layers (261, 263) and the interface insulation layer 265 can be omitted. During the process of forming the second wiring section 280, the interlayer insulating layers (261, 263), and the interface insulating layer 265, a chemical mechanical polishing (CMP) process is performed to flatten the upper surface. 【0111】 Figures 15 to 18 sequentially show the process of forming the second circuit region 202, as described with reference to Figures 1 to 3, in the manufacturing process of a non-volatile memory device according to one embodiment. In this embodiment, the order in which the process of forming the first circuit region 201 and the process of forming the second circuit region 202 are performed is not limited. For example, the first circuit region 201 and the second circuit region 202 are formed on separate lines, and then connected to each other in the process of joining the second substrate 210 and the third substrate 310. However, this is not limited to this, and the first circuit region 201 and the second circuit region 202 may be formed sequentially within a single process. 【0112】 First, as shown in Figure 15, a portion of the third substrate 310 is etched to form the element isolation pattern STI and the isolation trench DTI. For example, a mask pattern is formed on a portion of the third substrate 310 that exposes the area where the element isolation pattern STI and the isolation trench DTI are to be formed, and then a dry etching process is performed to form the element isolation pattern STI and the isolation trench DTI. 【0113】 The element isolation pattern STI is formed around the region where the first circuit element 220 is formed. The isolation trench DTI is formed in the region where the barrier pattern 330, described with reference to Figures 1 to 3, is located. In this embodiment, the isolation trench DTI is formed to a deeper depth than the element isolation pattern STI. In this embodiment, the isolation trench DTI is formed to a narrower width than the element isolation pattern STI. However, it is not limited to this, and the isolation trench DTI and the element isolation pattern STI may have substantially the same width. 【0114】 As shown in Figure 16, a second circuit element 320 and a third wiring section 380 are formed on a third substrate 310 on which an element isolation pattern STI and isolation trench DTI are formed. First, the inside of the element isolation pattern STI and isolation trench DTI are filled with an insulating material. In this embodiment, the isolation trench DTI has a relatively large aspect ratio. For example, the isolation trench DTI has a larger aspect ratio than the element isolation pattern STI. As an example, the depth of the isolation trench DTI is greater than or equal to about 4 μm, and the width is less than or equal to about 200 nm. 【0115】 In this embodiment, the step of filling the interior of the isolation trench DTI with insulating material is performed by selecting a method that ensures good film formation even inside trenches with a relatively large aspect ratio. As an example, the step of filling the interior of the isolation trench DTI with insulating material is performed by atomic layer deposition (ALD). In the case of atomic layer deposition, the material is formed conformally on the substrate in units of one atomic layer, so a uniform film can be formed inside trenches with a large aspect ratio, such as the isolation trench DTI in this embodiment. 【0116】 In this embodiment, the step of filling the inside of the element isolation pattern STI with insulating material is performed together with the step of filling the inside of the isolation trench DTI with insulating material, or is performed separately. 【0117】 Next, a plurality of second circuit elements 320 are formed on the third substrate 310, and a third wiring portion 380 and an interface insulating layer 365 are formed to cover the second circuit elements 320. The process of forming the second circuit elements 320, the third wiring portion 380, and the interface insulating layer 365 on the third substrate 310 is similar to the process of forming the first circuit element 220, the second wiring portion 280, the interlayer insulating layers (261, 263), and the interface insulating layer 265 described above, so a detailed explanation is omitted. 【0118】 Next, a process of etching a portion of the lower region of the third substrate 310 is performed. First, as shown in Figure 17, the carrier substrate 312 is attached to the upper surface of the third substrate 310. First, the upper surface of the interface insulating layer 365 is positioned so that it faces one surface of the carrier substrate 312, and then the surface of the carrier substrate 312 and the upper surface of the interface insulating layer 365 are attached to each other. At this time, the third substrate 310 is rotated so that the upper surface of the interface insulating layer 365 and the upper surface of the carrier substrate 312 face each other. Although not clearly shown in Figure 17, an adhesive member is further positioned between the interface insulating layer 365 and the carrier substrate 312. 【0119】 Next, as shown in Figure 18, a portion of the lower region of the third substrate 310 is removed. The process of removing a portion of the third substrate 310 is carried out by grinding and / or chemical mechanical polishing. 【0120】 In this embodiment, the step of removing the lower part of the third substrate 310 is performed to have an appropriate thickness considering the operating voltage of the second circuit element 320 and the breakdown voltage of the third substrate 310. During the step of removing the lower part of the third substrate 310, the third substrate 310 is controlled to have a thickness greater than or equal to approximately 4 μm. 【0121】 In this embodiment, the step of removing a portion of the third substrate 310 is performed using the isolation trench DTI as the etching stop film. In other words, the step of removing a portion of the third substrate 310 is performed until the isolation trench DTI is completely exposed on the etched lower surface of the third substrate 310. 【0122】 In this embodiment, the separation trench DTI is exposed on the lower surface of the third substrate 310 by the step of removing a portion of the third substrate 310, thereby forming a dummy semiconductor pattern 373 separated from the third substrate 310, and a barrier pattern 330 located between the dummy semiconductor pattern 373 and the third substrate 310. After this, an interlayer insulating layer 361 and an interface insulating layer 367 are sequentially formed on the lower surface of the third substrate 310. 【0123】 As shown in Figure 19, the second substrate 210 and the third substrate 310 are joined together. Specifically, the interface insulating layer 367 located on the lower surface of the third substrate 310 and the interface insulating layer 265 located on the upper surface of the second substrate 210 are positioned facing each other, and then the opposing surfaces of the two interface insulating layers (367, 265) are attached to each other. Although not clearly shown in Figure 19, an adhesive member is further positioned between the two interface insulating layers (367, 265). 【0124】 In the process of joining the second substrate 210 and the third substrate 310 to each other, a further step is taken to align the two substrates (210, 310). As an example, the second substrate 210 and the third substrate 310 are positioned so that the first alignment key 288 (see Figure 1) and the second alignment key 388 (see Figure 1), as described with reference to Figure 1, overlap each other vertically, and then the opposing surfaces of the two interface insulating layers (367, 265) are attached. 【0125】 As shown in Figure 20, the carrier substrate 312 is removed from the third substrate 310, and the interface insulating layer 365 and a portion of the upper part of the wiring insulating layer 382 are removed. When a portion of the wiring insulating layer 382 is etched, the etching process is controlled so that the contact vias 384 or the wiring layer 386 are not exposed to the outside. 【0126】 Next, through-electrodes 371 are formed that penetrate the dummy semiconductor pattern 373 in the third direction Z. First, as shown in Figure 21, through-holes TH are formed that penetrate the wiring insulating layer 282, the dummy semiconductor pattern 373, and the insulating layers (261, 263, 265, 361, 367) in the third direction Z by photo-etching processes. In this embodiment, the wiring insulating layer 282, the dummy semiconductor pattern 373, and the insulating layers (261, 263, 265, 361, 367) are sequentially etched by a dry etching process. 【0127】 When forming through-holes TH, if the substrate is exposed to metal contained in wiring, etc., the substrate may be contaminated by the metal, which may degrade the characteristics of the circuit elements formed on the substrate. According to this embodiment, in the process of forming through-holes TH, the third substrate 310 is separated from the dummy semiconductor pattern 373 and the wiring layer 286 exposed by the through-holes TH by the barrier pattern 330, thereby improving the reliability of the non-volatile memory device according to this embodiment. Furthermore, according to this embodiment, in the process of forming through-electrodes 371, there is no need to perform additional steps to protect the third substrate 310 (for example, a step of covering the through-hole sidewalls with an insulating material to protect the substrate), so the process of manufacturing the non-volatile memory device according to this embodiment can be carried out efficiently. 【0128】 Next, as shown in Figure 22, the through-hole TH is filled with a conductive material to form the through-electrode 371. At this time, a conductive material is also formed in a portion of the upper surface of the wiring insulation layer 382, ​​and a chemical-mechanical polishing process is further performed to remove the conductive material formed on the upper surface of the wiring insulation layer 382. In this embodiment, one end of the through-electrode 371 is connected to the wiring layer 286 or contact via 284 connected to the first circuit element 220. 【0129】 As shown in Figure 23, a photo-etching process is performed on the third substrate 310 to further form a wiring insulation layer 382, ​​contact vias 384, and wiring layer 386, and then a second junction 290 and an interface insulation layer 369 are formed. The second junction 290 is connected to a through electrode 371 or a second circuit element 320 through the contact vias 384 and / or wiring layer 386. Referring to Figure 23, the other end of the through electrode 371 is shown connected to the second junction 290, but the other end of the through electrode 371 can be connected to the second circuit element 320 (see Figure 1). 【0130】 Next, as shown in Figure 24, the first substrate 110 on which the cell region 100 is formed is bonded to the third substrate 310. A gate stacking structure 120, a channel structure CH, a first wiring section 180, and a first bonding section 190 are formed on the first substrate 110. The process of forming the cell region 100 is performed separately from the process of forming the circuit region 200. In this embodiment, after forming a gate stack structure 120, a channel structure CH, a first wiring section 180, and a first joint section 190 on a first substrate 110, the first substrate 110 and the third substrate 310 are positioned so that the upper surfaces of the first joint section 190 and the interface insulating layer 193 are in contact with the upper surfaces of the second joint section 290 and the interface insulating layer 369. Then, the upper surfaces of the first joint section 190 and the interface insulating layer 193 are attached to the upper surfaces of the second joint section 290 and the interface insulating layer 369, respectively, thereby manufacturing the non-volatile memory device described with reference to Figures 1 to 5. 【0131】 According to this embodiment, as described with reference to Figures 15 to 23, a relatively narrow isolation trench DTI is formed around the region where the through-electrode 371 is formed, and this is used to form a dummy semiconductor pattern 373 separated from the third substrate 310 and a through-electrode 371 penetrating it. The through-electrode 371 is electrically isolated from the third substrate 310 by the dummy semiconductor pattern 373. 【0132】 In contrast, when forming the through-electrode 371, a separation trench DTI having a width wider than the horizontal width of the through-electrode 371 may be formed first, and then filled with an insulating layer to form the through-electrode 371 so as to penetrate a portion of the insulating layer. In this case, forming the insulating layer inside the wide separation trench DTI by atomic evaporation may result in excessively long process times and increased process costs. The insulating layer may also be deposited inside the wide separation trench DTI by chemical vapor deposition, which has a faster deposition rate compared to atomic evaporation. However, in this case, the insulating layer filling the separation trench DTI may have lower step coverage compared to the insulating layer formed by atomic evaporation, which may result in the formation of voids inside the separation trench DTI. The width of the separation trench DTI may be made sufficiently larger to prevent the formation of voids inside the separation trench DTI. However, in this case, the size of the non-volatile memory device according to this embodiment may become excessively large. 【0133】 As described in this embodiment with reference to Figures 14 to 24, when a separation trench DTI is formed around the region where the through-electrode 371 is formed, with a relatively narrow width, the through-electrode 371 can be efficiently formed in a smaller area compared to when the separation trench DTI is formed wider (for example, wider than the width along the horizontal direction of the through-electrode 371). This improves the reliability of the manufacturing process for non-volatile memory devices and reduces the size of the memory device. 【0134】 Figure 25 is a schematic partial cross-sectional view showing a second example of a non-volatile memory device according to one embodiment. The non-volatile memory device shown in Figure 25 has many similarities to the embodiment described above, so the following explanation will focus on the differences from the embodiment described above. The non-volatile memory device according to this embodiment differs in part from the embodiment described above in that it further includes a fourth substrate 410 located in the cell region 100 and a through-structure 470 located in the circuit region 200 and penetrating the second substrate 210. 【0135】 The non-volatile memory device shown in Figure 25 has a shape similar to that of the non-volatile memory device shown in Figure 1, in which the non-volatile memory device is positioned so that the upper surface of the external insulating layer 110c faces the upper surface of the fourth substrate 410, and then the upper surface of the external insulating layer 110c and the upper surface of the fourth substrate 410 are attached to each other. In this embodiment, the fourth substrate 410 includes a semiconductor layer containing a semiconductor material. As an example, the fourth substrate 410 is composed of silicon, germanium, silicon-germanium, silicon-on-insulator, germanium-on-insulator, etc. An interlayer insulating layer 461 is located between the upper surface of the fourth substrate 410 and the external insulating layer 110c. The interlayer insulating layer 461 is made of silicon oxide (SiO2), silicon nitride (SiN X ), and at least one of silicon oxynitride (SiON). Although not clearly shown in Figure 25, an adhesive member is further positioned between the interlayer insulating layer 461 and the outer insulating layer 110c. 【0136】 In the non-volatile memory device according to this embodiment, the second substrate 210 includes a first surface 211s on which a plurality of first circuit elements 220 are located, and a second surface 212s opposite to the first surface 211s. The first surface 211s includes an active area. The first surface is located even more adjacent to the cell area 100 than the second surface 212s. In this embodiment, the fourth wiring section 480 is located on the second surface 212s of the second substrate 210. Unlike those described with reference to Figures 1 to 24, in the non-volatile semiconductor device according to this embodiment, the input / output pads 198 are located in the circuit area 200, not the cell area 100. Specifically, the input / output pads 198 are located on the second surface 212s of the second substrate 210. 【0137】 The fourth wiring section 480 includes a wiring layer 486, contact vias 484, and a wiring insulation layer 482 surrounding them. The input / output pad 198 is connected to a through electrode 471 (described later) via the wiring layer 486 and contact vias 484. The input / output pad 198 is partially surrounded by the wiring insulation layer 482. At least a portion of the upper surface of the input / output pad 198 is exposed to the outside. 【0138】 The through-structure 470 is located within the second substrate 210. The through-structure 470 includes a dummy semiconductor pattern 473 surrounded by the second substrate 210 and located away from the second substrate 210, and a through-electrode 471 that penetrates the dummy semiconductor pattern 473 in the third direction Z. The non-volatile memory device according to this embodiment further includes a barrier pattern 430 located between the second substrate 210 and the dummy semiconductor pattern 473. The specific structure and function of the dummy semiconductor pattern 473 and the barrier pattern 430 are the same as or similar to those of the dummy semiconductor pattern 373 and the barrier pattern 330 described with reference to Figures 1 to 24, so a detailed explanation therein is omitted. 【0139】 In this embodiment, the through-electrode 471 extends along the third direction Z. In this embodiment, the through-electrode 471 extends along the third direction Z, penetrating the dummy semiconductor pattern 473. One end of the through-electrode 471 is connected to the input / output pad 198 through a contact via 484 and / or a wiring layer 486. The other end of the through-electrode 471 is connected to the first circuit element 220 through a contact via 284 and / or a wiring layer 286. The through-electrode 471 penetrates the dummy semiconductor pattern 473 and electrically connects the first circuit element 220, located on the first surface 211s of the second substrate 210, to the input / output pad 198, located on the second surface 212s of the second substrate 210. In this embodiment, the dummy semiconductor pattern 473 is electrically isolated from the second substrate 210 by a barrier pattern 430, and the through-electrode 471 is surrounded by the dummy semiconductor pattern 473. Therefore, the through electrode 471 is electrically isolated and insulated from the second substrate 210. 【0140】 Regarding the structure and function of the through-electrode 471, other than what has been described above, it is the same as or similar to the through-electrode 371 described with reference to Figures 1 to 24, so a detailed explanation of it will be omitted. 【0141】 Figure 26 is a schematic partial cross-sectional view showing a third example of a non-volatile memory device according to one embodiment. The non-volatile memory device shown in Figure 26 has many similarities to the embodiments described above, so the following explanation will focus on the differences from the embodiments described above. The non-volatile memory device according to this embodiment differs from the embodiments described above in that the circuit region 200 includes a single substrate. In the embodiments described above, circuit elements are located on two substrates, but in this embodiment, the circuit elements are located on a single substrate. 【0142】 Specifically, referring to Figure 26, the non-volatile memory device according to this embodiment includes a first substrate 110 on which a plurality of memory cell structures are located, and a second substrate 210 on which a first circuit element 220 is located. A third substrate 310, as described with reference to Figures 1 to 25, is not located between the first substrate 110 and the second substrate 210. 【0143】 In this embodiment, the input / output pad 198 is located on the second surface 212s of the second substrate 210. In this embodiment, the fact that the through electrode 471 penetrates the second substrate 210 and electrically connects the first circuit element 220 and the input / output pad 198 is the same as described with reference to Figure 25, so a detailed explanation of this is omitted. 【0144】 Figure 27 is a schematic partial cross-sectional view showing a fourth example of a non-volatile memory device according to one embodiment. The non-volatile memory device shown in Figure 27 has many similarities to the embodiments described above, so the following explanation will focus on the differences from the embodiments described above. In the non-volatile memory device according to this embodiment, the position of the first circuit element 220 is slightly different from that of the embodiments described above. 【0145】 Referring to Figure 27, in the non-volatile memory device according to this embodiment, the second substrate 210 includes a first surface 211s and a second surface 212s facing the first surface 211s, and the plurality of first circuit elements 220 are located on the second surface 212s of the second substrate 210. The second surface 212s is located further from the cell region 100 compared to the first surface 211s. That is, unlike the non-volatile memory device described with reference to Figures 25 and 26, in which the plurality of first circuit elements 220 are located on the first surface 211s, in this embodiment, the first circuit elements 220 are located on the second surface 212s. 【0146】 In this embodiment, the through-electrode 471 extends along the third direction Z. In this embodiment, the through-electrode 471 extends along the third direction Z, penetrating the dummy semiconductor pattern 473. One end of the through-electrode 471 is connected to the first circuit element 220 through contact via 284 and / or wiring layer 286. The other end of the through-electrode 471 is connected to at least one of a plurality of memory cells located in the cell region 100 through contact via 180a and / or connecting wiring 180b. Specifically, the other end of the through-electrode 371 is connected to the gate stack structure 120 and / or channel structure CH located in the cell region 100 through contact via 180a and / or connecting wiring 180b. 【0147】 Unlike the embodiments described with reference to Figures 25 and 26, in which the input / output pad 198 is connected to the first circuit element 220 through through electrodes 471, in this embodiment, the input / output pad 198 is connected to the first circuit element 220 through contact vias 284 and / or wiring layers 286. An example of an electronic system including the non-volatile memory device described above is described in detail below. 【0148】 Figure 28 is a schematic diagram showing an electronic system including a non-volatile memory device according to one embodiment. 【0149】 Referring to Figure 28, the electronic system 1000 according to this embodiment includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The semiconductor device 1110 in Figure 28 is a non-volatile memory device as described with reference to Figures 1 to 24. The electronic system 1000 is a storage device or an electronic device including one or more semiconductor devices 1100. For example, the electronic system 1000 is an SSD (solid state drive device), a USB (Universal Serial Bus), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100. 【0150】 The semiconductor device 1100 is a non-volatile memory device, and is a NAND flash memory device as described with reference to Figures 1 to 24, for example. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL. 【0151】 In the second structure 1100S, each memory cell string CSTR includes lower transistors (LT1, LT2) adjacent to the common source line CSL, upper transistors (UT1, UT2) adjacent to the bit line BL, and a plurality of memory cell transistors MCT arranged between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) can vary depending on the embodiment. 【0152】 In one embodiment, the lower transistors (LT1, LT2) include ground selection transistors, and the upper transistors (UT1, UT2) include string selection transistors. The first and second gate lower lines (LL1, LL2) are gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the gate upper lines (UL1, UL2) are gate electrodes of the upper transistors (UT1, UT2), respectively. 【0153】 The common source line CSL, the first and second gate lower lines (LL1, LL2), the word line WL, and the first and second gate upper lines (UL1, UL2) are electrically connected to the decoder circuit 1110 via a first connecting wire 1115 extending from within the first structure 1100F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via a second connecting wire 1125 extending from within the first structure 1100F to the second structure 1100S. 【0154】 In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 perform control operations on at least one memory cell transistor selected from among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 are controlled by the logic circuit 1130. The semiconductor device 1100 communicates with the controller 1200 through input / output pads 1101 which are electrically connected to the logic circuit 1130. The input / output pads 1101 are electrically connected to the logic circuit 1130 through input / output coupling wiring 1135 which extends from within the first structure 1100F to the second structure 1100S. The input / output coupling wiring 1135 consists of the coupling structure 188 of the non-volatile memory device (see Figure 1), as described with reference to Figures 1 to 24. 【0155】 The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 includes a plurality of semiconductor devices 1100, in which case the controller 1200 controls the plurality of semiconductor devices 1100. 【0156】 The processor 1210 controls the operation of the entire electronic system 1000, including the controller 1200. The processor 1210 operates with predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that handles communication with the semiconductor device 1100. Through the NAND interface 1221, control commands for controlling the semiconductor device 1100, data to be recorded in the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100 are transmitted. The host interface 1230 provides communication functionality between the electronic system 1000 and an external host. When the processor 1210 receives a control command from an external host through the host interface 1230, it controls the semiconductor device 1100 in response to the control command. 【0157】 Figure 29 is a schematic perspective view showing an electronic system including a non-volatile memory device according to one embodiment. 【0158】 Referring to Figure 29, the electronic system 2000 according to this embodiment includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by wiring patterns 2005 formed on the main board 2001. 【0159】 The main board 2001 includes a connector 2006 which has multiple pins that connect to an external host. The number and arrangement of the multiple pins on the connector 2006 vary depending on the communication interface between the electronic system 2000 and the external host. In one embodiment, the electronic system 2000 communicates with the external host via one of the following interfaces: USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), or M-Phy for UFS (Universal Flash Storage). In one embodiment, the electronic system 2000 operates on power supplied from the external host through the connector 2006. The electronic system 2000 may further include a PMIC (Power Management Integrated Circuit) that distributes the power supplied from the external host to a controller 2002 and a semiconductor package 2003. 【0160】 The controller 2002 records data to or reads data from the semiconductor package 2003 to improve the operating speed of the electronic system 2000. 【0161】 DRAM2004 is a buffer memory that mitigates the speed difference between the semiconductor package 2003, which is the data storage space, and the external host. The DRAM2004 included in the electronic system 2000 also functions as a type of cache memory, providing a space for temporarily storing data during control operations on the semiconductor package 2003. When the electronic system 2000 includes DRAM2004, the controller 2002 further includes a DRAM controller for controlling DRAM2004, in addition to the NAND controller for controlling the semiconductor package 2003. 【0162】 The semiconductor package 2003 includes first and second semiconductor packages (2003a, 2003b) that are spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) are each semiconductor packages containing a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages (2003a, 2003b) includes a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, adhesive layers 2300 disposed on the lower surface of each semiconductor chip 2200, connecting structures 2400 that electrically connect the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chips 2200 and the connecting structures 2400 on the package substrate 2100. 【0163】 The package substrate 2100 is a printed circuit board including the package upper pad 2130. Each semiconductor chip 2200 includes an input / output pad 2210. The input / output pad 2210 corresponds to the input / output pad 1101 in Figure 28. Each semiconductor chip 2200 includes a gate stack structure 4210 and a channel structure 4220. Each semiconductor chip 2200 includes a non-volatile memory device as described with reference to Figures 1 to 24. 【0164】 In one embodiment, the connecting structure 2400 is a bonding wire that electrically connects the input / output pads 2210 and the package upper pads 2130. Therefore, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 are electrically connected to each other by bonding wires and electrically connected to the package upper pads 2130 of the package substrate 2100. In this embodiment, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 may be electrically connected by a connecting structure including through silicon vias (TSVs) instead of the bonding wire connecting structure 2400. 【0165】 In one embodiment, the controller 2002 and the semiconductor chip 2200 are contained in a single package. For example, the controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer board different from the main board 2001, and the controller 2002 and the semiconductor chip 2200 are connected to each other by wiring formed on the interposer board. 【0166】 Figure 30 is a schematic cross-sectional view showing a semiconductor package according to one embodiment. Figure 30 illustrates an exemplary embodiment of the semiconductor package 2003 of Figure 29 and conceptually shows the region obtained by cutting the semiconductor package 2003 of Figure 29 along the cutting line I-I'. 【0167】 Referring to Figure 30, in the semiconductor package 2003, the package substrate 2100 is a printed circuit board. The package substrate 2100 includes a package substrate body 2120, an upper package pad 2130 located on the upper surface of the package substrate body 2120, a lower package pad 2125 located on or exposed through the lower surface of the package substrate body 2120, and internal wiring 2135 that electrically connects the upper package pad 2130 and the lower package pad 2125 inside the package substrate body 2120. The upper package pad 2130 is electrically connected to a connecting structure 2400. The lower package pad 2125 is connected to the wiring pattern 2005 of the main substrate 2010 of the electronic system 2000 via a conductive connecting portion 2800, as shown in Figure 29. 【0168】 In the semiconductor package 2003, each semiconductor chip 2200 includes a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 by wafer bonding. Each semiconductor chip 2200 includes a non-volatile memory device as described with reference to Figures 1 to 24. 【0169】 The first structure 4100 includes a peripheral circuit region including peripheral wiring 4110 and a first bonding structure 4150. Although not clearly shown in Figure 30, in the semiconductor package 2003 according to this embodiment, the peripheral circuit region includes two or more circuit regions located vertically, such as the first circuit region 201 (see Figure 1) and the second circuit region 202 described with reference to Figures 1 to 24. In this embodiment, the two or more vertically located circuit regions are bonded to each other by a wafer bonding method or are formed sequentially in a single process. The second structure 4200 includes a common source line 4205, a gate stacking structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 and a separation structure 4230 penetrating the gate stacking structure 4210, and a second bonding structure 4250 electrically connected to the word lines (reference numeral WL in Figure 28, hereinafter the same) of the channel structure 4220 and the gate stacking structure 4210, respectively. For example, the second joint structure 4250 is electrically connected to the channel structure 4220 and the word line WL, respectively, through a bit line 4240 which is electrically connected to the channel structure 4220 and a gate connection wiring which is electrically connected to the word line WL. The first joint structure 4150 of the first structure 4100 and the second joint structure 4250 of the second structure 4200 are joined in contact with each other. The joined portions of the first joint structure 4150 and the second joint structure 4250 are formed of, for example, copper (Cu). 【0170】 The non-volatile memory device according to this embodiment includes a first circuit region 201 in which a circuit region 200 is formed on a second substrate 210, and a second circuit region 202 formed on a third substrate 310. The non-volatile memory device according to this embodiment includes a through-electrode 371 that penetrates the third substrate 310, and a first circuit element 220 included in the first circuit region 201 is connected to a second circuit element 320 included in the second circuit region 202 or a memory cell included in the cell region 100 through the through-electrode 371. 【0171】 In this embodiment, the through-electrode 371 is electrically isolated from the third substrate 310 by the dummy semiconductor pattern 373 and the barrier pattern 330 surrounding it. In this case, it is possible to prevent electrical signals flowing through the through-electrode 371 from flowing to the second circuit element 320 through the third substrate 310, thereby improving the reliability of the non-volatile memory device. 【0172】 Furthermore, according to this embodiment, the through-electrode 371 penetrating the third substrate 310 can be formed in a small area in a single step, thereby improving the reliability of the manufacturing process for the non-volatile memory device and reducing the size of the memory device. 【0173】 Each semiconductor chip 2200 further includes an input / output pad 2210 and an input / output coupling wiring 4265 located below the input / output pad 2210. The input / output coupling wiring 4265 is electrically connected to a portion of the second junction structure 4250. The input / output coupling wiring 4265 consists of the coupling structure 188 of the non-volatile memory device (see Figure 1), as described with reference to Figures 1 to 24. 【0174】 In one embodiment, multiple semiconductor chips 2200 in a semiconductor package 2003 are electrically connected to each other by a bonding wire-type connecting structure 2400. In another example, multiple semiconductor chips 2200 or multiple parts comprising them may be electrically connected by a connecting structure including through electrodes. 【0175】 Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of symbols] 【0176】 100 cell area 102 Cell array area 104 Consolidation area 106 Outer area 110, 210, 310, 410 1st to 4th boards 110c outer insulating layer 120, 4210 Gate stacked structure 121, 122 Gate stacking section 130 gates 132 Cell Insulation Layer 138, 261, 263, 361, 461 Interlayer insulating layer 140 channel layer 142 Core insulating layer 144 Channel Pad 150 Gate Dielectric Layer 152 Tunneling layer 154 Charge Storage Layer 156 Blocking Layers 180, 280, 380, 480 1st to 4th wiring section 180a, 284, 384, 484 contact vias 180b connection wiring 182, 183 bit lines 184 Gate Contact Section 186 Source Contact Section 188 Connected structures 190, 290 1st and 2nd joint 193, 265, 365, 367, 369 Interfacial insulating layer 198 Input / Output Pads 200 circuit areas 201, 202 1st and 2nd circuit area 211s, 212s 1st, 2nd side 220, 320 First and second circuit elements 282, 382, ​​482 Wiring insulation layer 286, 386, 486 wiring layer 288, 388 First and Second Align Keys 312 Carrier board 330, 430 barrier patterns 331, 343 First and second barrier patterns 335 Insulating Liner 343a, 343b Second and first semiconductor patterns 370, 470 penetration structure 371, 471 Through electrode 373, 473 Dummy semiconductor patterns 1000, 2000 Electronic Systems 1100 Semiconductor 1100F, 4100 1st structure 1100S, 4200 2nd structure 1101, 2210 Input / Output Pads 1110 Decoder Circuit 1115, 1125 1st and 2nd connection wiring 1120 page buffer 1130 Logic Circuit 1135, 4265 input / output connection wiring 1200 Controllers 1210 Processor 1220 NAND Controller 1221 NAND Interface 1230 Host Interface 2001 Main board 2002 Controller 2003 Semiconductor Packages 2003a, 2003b First and second semiconductor packages 2004 DRAM 2005 Wiring Pattern 2006 Connector 2100 Package Substrate 2120 Package substrate body 2125 Package bottom pad 2130 Package top pad 2135 Internal Wiring 2200 semiconductor chips 2300 Adhesive layer 2400 Connected structures 2500 Molding Layers 2800 Conductive connection part 4150, 4250 1st and 2nd joint structure 4205 Common Source Line 4220 Channel Structure 4230 Separation Structure 4240 bit lines AG Air Gap BL Bitline CH channel structure CH1, CH2 channel section CSL Common Sourceline CSTR Memory Cell String DTI Separation Trench LL1, LL2 Lower lines of gates 1 and 2 LT1, LT2 lower transistors MCT Memory Cell Transistor STI element isolation pattern TH Through Hole UL1, UL2 Upper line of the 1st and 2nd gates UT1, UT2 Upper transistors WD Align Window WL Wardline

Claims

[Claim 1] First circuit board and Multiple memory cell structures located on the first substrate, A second substrate facing a first direction perpendicular to one surface of the first substrate, A first circuit element located on the second substrate, A third substrate located between the first substrate and the second substrate, A second circuit element located on the third substrate, The third substrate comprises a through-structure including a dummy semiconductor pattern separated from the third substrate and a through-electrode penetrating the dummy semiconductor pattern in a first direction, The non-volatile memory device is characterized in that one end of the through electrode is connected to the first circuit element and the other end is connected to at least one of the plurality of memory cell structures or the second circuit element. [Claim 2] The non-volatile memory device according to claim 1, characterized in that the through electrode has a side surface in contact with the dummy semiconductor pattern in a region that horizontally overlaps with the third substrate. [Claim 3] The non-volatile memory device according to claim 1, characterized in that the dummy semiconductor pattern has the same thickness as the third substrate and contains the same semiconductor material as the semiconductor material contained in the third substrate. [Claim 4] The non-volatile memory device according to claim 1, characterized in that an air gap is located between the third substrate and the through-structure. [Claim 5] The non-volatile memory device according to claim 1, further comprising a barrier pattern located between the third substrate and the through-structure. [Claim 6] The non-volatile memory device according to claim 5, characterized in that the third substrate and the through-structure are separated by the barrier pattern. [Claim 7] The non-volatile memory device according to claim 5, characterized in that the barrier pattern includes an insulating material located between the inner surface of the third substrate and the outer surface of the dummy semiconductor pattern, and a void surrounded by the insulating material. [Claim 8] The through-structure includes a plurality of through-electrodes arranged along a second direction parallel to one surface of the third substrate and a dummy semiconductor pattern surrounding each of the sides of the plurality of through-electrodes. The non-volatile memory device according to claim 1, characterized in that the dummy semiconductor patterns are spaced apart from each other. [Claim 9] First circuit board and A gate stack structure including interlayer insulating layers and gate electrodes alternately stacked on the lower surface of the first substrate, The gate stacked structure includes a channel structure that penetrates the first substrate in a first direction perpendicular to the lower surface, A first joint located below the channel structure and connected to at least one of the channel structures, The first substrate is connected to a second substrate facing the first direction, A first circuit element located on the upper surface of the second substrate, A third substrate located between the first substrate and the second substrate, A second circuit element located on the third substrate, A second junction located on the second circuit element and in contact with the first junction, A through-structure including a dummy semiconductor pattern separated from the third substrate within the third substrate and a through-electrode that penetrates the dummy semiconductor pattern in a first direction and extends toward the upper surface of the second substrate, The third substrate comprises a barrier pattern that penetrates the third substrate in a first direction and surrounds the side surface of the through-structure, The non-volatile memory device is characterized in that one end of the through electrode is connected to the first circuit element and the other end is connected to at least one of the second junctions or the second circuit element. [Claim 10] Main board and The non-volatile memory device on the main board, The main board includes a controller electrically connected to the non-volatile memory device, The aforementioned non-volatile memory device is First circuit board and Multiple memory cell structures located on the first substrate, A second substrate facing a first direction perpendicular to the first substrate, A first circuit element located on the second substrate, A third substrate located between the first substrate and the second substrate, A second circuit element located on the third substrate, The third substrate includes a dummy semiconductor pattern separated from the third substrate and a through-structure including a through-electrode that penetrates the dummy semiconductor pattern in a first direction, The electronic system is characterized in that one end of the through electrode is connected to the first circuit element, and the other end is connected to at least one of the plurality of memory cell structures or the second circuit element.

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