A capacitor containing a dielectric layer made of a high dielectric constant material, an electronic device containing the same, and a method for manufacturing a capacitor.

Abstract

The present invention provides a capacitor containing a dielectric layer made of a high dielectric constant material, and an electronic device containing the same. [Solution] The capacitor includes a first electrode; a second electrode provided opposite the first electrode; a dielectric layer provided between the first electrode and the second electrode; and a conductive interface layer provided between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material in the rutile crystal phase, and the dielectric layer includes a first insertion film and a second insertion film inserted within the dielectric layer. The first insertion film includes a metal oxide having p-type properties, and the second insertion film may include a group IV metal element oxide having a rutile crystal phase.

Description

[Technical Field] 【0001】 The present invention relates to a capacitor including a dielectric layer made of a high dielectric constant material, an electronic device including the same, and a method for manufacturing a capacitor. [Background technology] 【0002】 As the integration density of electronic devices such as memory increases, the electronic elements within these devices are becoming even more miniaturized. However, since the capacitance of a capacitor is proportional to its area, miniaturization of capacitors can lead to a decrease in capacitance. Therefore, methods are being studied to further increase the dielectric constant of the dielectric layer in order to compensate for the decrease in capacitor size and ensure the desired capacitance. In addition, methods are being studied to suppress the increase in leakage current caused by the miniaturization of capacitors. [Overview of the Initiative] [Problems that the invention aims to solve] 【0003】 The problem that this invention aims to solve is to provide a capacitor including a dielectric layer made of a high dielectric constant material and an electronic device including the same. 【0004】 Furthermore, the objective is to provide a capacitor with improved leakage current characteristics and an electronic device including the same. [Means for solving the problem] 【0005】 A capacitor according to one embodiment includes a first electrode; a second electrode provided opposite the first electrode; a dielectric layer provided between the first electrode and the second electrode and containing a dielectric material in a rutile crystal phase; and a conductive interface layer provided between the first electrode and the dielectric layer, wherein the dielectric layer includes a first insertion film and a second insertion film inserted into the dielectric material, the first insertion film containing an oxide of a metal selected from at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc), and the second insertion film may contain an oxide of a group IV metal element having a rutile crystal phase. 【0006】 For example, the dielectric layer may contain titanium oxide (TiO2) in a rutile crystalline phase. 【0007】 The metal content of the first insertion film within the dielectric layer is, for example, greater than 0 at% and 20 at% or less. 【0008】 The second insertion film may contain, for example, at least one oxide of germanium (Ge), silicon (Si), and tin (Sn). 【0009】 The metal content of the second insertion film within the dielectric layer is, for example, 0.1 at% or more and 10 at% or less. 【0010】 The thickness of the second insertion film is, for example, 0.1 nm or more and 0.5 nm or less. 【0011】 The thickness of the second insertion film is thinner than the thickness of the first insertion film. 【0012】 The distance between the conductive interface layer and the second insertion film is, for example, 0.5 nm or more. 【0013】 The second insertion film may be provided within the dielectric layer between the first insertion film and the conductive interface layer. 【0014】 The first insertion film can be provided between the second insertion film and the conductive interface layer within the dielectric layer. 【0015】 The conductive interface layer includes a first conductive interface layer provided between the first electrode and the dielectric layer and a second conductive interface layer provided between the first conductive interface layer and the dielectric layer. The first conductive interface layer includes a conductive metal oxide material having a crystal structure stable in a rutile crystal phase. The conduction band offset between the second conductive interface layer and the dielectric layer is larger than the conduction band offset between the first conductive interface layer and the dielectric layer. 【0016】 The first conductive interface layer can include, for example, molybdenum oxide (MoO2) doped with tin (Sn). 【0017】 The doping concentration of tin in the first conductive interface layer is, for example, 0.1 at% or more and 10 at% or less. 【0018】 The thickness of the first conductive interface layer is, for example, also 0.3 nm or more and 4 nm or less. 【0019】 The second conductive interface layer can include, for example, tin oxide (SnO2), germanium oxide (GeO2), or a mixture of tin oxide and germanium oxide (Sn x Ge 1-x )(O2, 0 < x < 1). 【0020】 The thickness of the second conductive interface layer is, for example, also 0.3 nm or more and 1 nm or less. 【0021】 The first electrode can include, for example, at least one conductive metal nitride such as titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN), and cobalt nitride (CoN) or a combination thereof. 【0022】 A memory device according to another embodiment includes a transistor; and a capacitor electrically connected to the transistor, the capacitor including: a first electrode; a second electrode provided opposite to the first electrode; and a dielectric layer provided between the first electrode and the second electrode, the dielectric layer including a first metal oxide, a second metal oxide, and a third metal oxide, the first metal oxide being a titanium oxide having a rutile crystal phase, the second metal oxide including an oxide of at least one metal selected from aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc), and may include an oxide of at least one metal selected from germanium (Ge), silicon (Si), and tin (Sn). 【0023】 The content of the second metal oxide and the content of the third metal oxide in the dielectric layer may be different. 【0024】 Also, a method for manufacturing a capacitor according to another embodiment includes forming a conductive interface layer on a first electrode; forming a dielectric layer including a first metal oxide, a second metal oxide, and a third metal oxide on the conductive interface layer; and forming a second electrode on the dielectric layer, the first metal oxide being a titanium oxide having a rutile crystal phase, the second metal oxide including an oxide of at least one metal selected from aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc), and may include an oxide of at least one metal selected from germanium (Ge), silicon (Si), and tin (Sn). 【Advantages of the Invention】 【0025】 In the disclosed capacitor, a conductive interface layer having a multilayer structure is first formed on the first electrode, and then a dielectric layer is formed on the conductive interface layer, thereby forming a dielectric material in the rutile crystalline phase with a high dielectric constant. Therefore, the disclosed capacitor can be miniaturized and have high capacitance. Furthermore, according to the disclosed embodiment, leakage current can be reduced by utilizing a conductive interface layer having a multilayer structure. 【0026】 Furthermore, since the dielectric layer of the capacitor according to this embodiment includes an insertion film capable of capturing oxygen vacancies within the dielectric layer, leakage current can be further reduced by suppressing Fermi-level pinning. [Brief explanation of the drawing] 【0027】 [Figure 1] This is a cross-sectional view showing the schematic structure of a capacitor according to one embodiment. [Figure 2] Figure 1 is a schematic energy band diagram illustrating the conduction band offset (CBO) between the second conductive interface layer and the dielectric layer of the capacitor shown. [Figure 3A] Figure 1 is a schematic cross-sectional view showing the process of forming the conductive interface layer of the capacitor shown. [Figure 3B] Figure 1 is a schematic cross-sectional view showing the process of forming the conductive interface layer of the capacitor shown. [Figure 3C] Figure 1 is a schematic cross-sectional view showing the process of forming the conductive interface layer of the capacitor shown. [Figure 3D] Figure 1 is a schematic cross-sectional view showing the process of forming the conductive interface layer of the capacitor shown. [Figure 4] The image shows an HR-TEM photograph of a capacitor based on an actual fabricated embodiment. [Figure 5]This graph illustrates the UPS spectrum obtained through UV photoelectron spectroscopy (UPS) measurements of the first conductive interface layer. [Figure 6] This graph compares the leakage current characteristics of a capacitor containing a conductive interface layer according to the embodiment and a capacitor containing a conductive interface layer according to the comparative example. [Figure 7] This graph compares the leakage current characteristics of capacitors based on the tin (Sn) content in the first conductive interface layer. [Figure 8] This section illustrates GI-XRD (grazing incidence X-ray diffraction) measurement results that compare the crystallinity of dielectric layers grown with diverse layer structures. [Figure 9] This graph compares the leakage current characteristics of capacitors at various concentrations of the materials in the first and second insertion layers. [Figure 10] This graph compares the leakage current characteristics of capacitors based on the thickness of the second insertion film. [Figure 11] This graph compares the leakage current characteristics of the capacitor depending on the position of the second insertion film. [Figure 12] This is a cross-sectional view showing the schematic structure of a capacitor according to another embodiment. [Figure 13] This is a circuit diagram illustrating the general circuit configuration and operation of an electronic device employing a capacitor according to an embodiment. [Figure 14] This is a schematic diagram showing an electronic device according to an exemplary embodiment. [Figure 15] This is a schematic diagram showing an electronic device according to another exemplary embodiment. [Figure 16] This is a plan view showing an electronic device according to yet another exemplary embodiment. [Figure 17] This is a cross-sectional view along the line A-A' in Figure 16. [Figure 18] This is a cross-sectional view showing an electronic device according to yet another exemplary embodiment. [Figure 19]This is a conceptual diagram illustrating a schematic element architecture that may be applied to a device according to an exemplary embodiment. [Figure 20] This is a conceptual diagram illustrating a schematic element architecture that may be applied to a device according to an exemplary embodiment. [Modes for carrying out the invention] 【0028】 The following description details capacitors and electronic devices including a dielectric layer made of a high dielectric constant material, based on the attached drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings is exaggerated for clarity and convenience of explanation. Furthermore, the embodiments described below are merely illustrative, and various modifications are possible from such embodiments. In addition, expressions such as “approximately” or “substantially” used with numerical and / or geometric terms mean numerical values ​​including manufacturing tolerances (e.g., ±10%) near the numerical value mentioned. Furthermore, regardless of expressions such as “approximately” or “substantially,” numerical values ​​should be understood to include manufacturing or operating tolerances (e.g., ±10%) near that numerical value. 【0029】 In the following, the terms "top" or "upper," or "bottom" or "lower," may include not only those directly above / below / left / right upon contact, but also those above / below / left / right without direct contact. Furthermore, spatially relative expressions such as "upper" or "lower" are based on the direction shown in the drawing, and may be expressed differently if the orientation of the object changes. That is, spatially relative expressions encompass other directions of the element during use or operation in addition to the direction shown in the drawing, and therefore, if the elements are arranged in different directions, the spatially relative expressions may be interpreted accordingly. A singular expression includes multiple expressions unless the context clearly indicates otherwise. Also, when a part "includes" a component, this means that it includes other components, not excludes them, unless otherwise stated. 【0030】 The use of the term "the foregoing" and similar referential terms can be singular or plural. Unless otherwise explicitly stated, the steps constituting a method are performed in any order, but are not necessarily limited to the order stated. 【0031】 Furthermore, terms such as "...part" and "module" as used in this specification refer to a unit that processes at least one function or operation, which may be embodied by hardware or software, or by a combination of hardware and software. For example, a processing circuit includes, but is not limited to, a CPU (central processing unit), AP (application processor), ALU (arithmetic logic unit), GPU (graphic processing unit), digital signal processor, microcomputer, FPGA (field programmable gate array), SoC (System-on-Chip), PLC (programmable logic unit), microprocessor, or ASIC (application-specific integrated circuit). 【0032】 The lines or connecting members between components shown in the drawings exemplify functional and / or physical or circuit connections, and in actual devices, they may be substituted or represent a variety of additional functional, physical, or circuit connections. 【0033】 All use of examples or illustrative terms is solely for the purpose of detailing the technical idea and is not limited by the scope of the claims unless otherwise specified. 【0034】 Figure 1 is a cross-sectional view showing a schematic structure of a capacitor according to one embodiment. Referring to Figure 1, the capacitor 100 according to the embodiment may include a first electrode 110, a second electrode 140 provided opposite the first electrode 110, a dielectric layer 130 provided between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 provided between the first electrode 110 and the dielectric layer 130. That is, the dielectric layer 130 may be located between the first electrode 110 and the second electrode 140 which are opposite to each other. In the manufacturing process of the capacitor 100, the conductive interface layer 120 may be formed on the upper surface of the first electrode 110, the dielectric layer 130 may be formed on the upper surface of the conductive interface layer 120, and the second electrode 140 may be formed on the upper surface of the dielectric layer 130. 【0035】 The dielectric layer 130 may contain a dielectric material in the rutile crystalline phase. Here, the fact that the dielectric layer 130 contains a dielectric material in the rutile crystalline phase means that it contains a dielectric material in which the rutile crystalline phase is dominant. In other words, the entire dielectric material does not need to be in the rutile crystalline phase; either most of the dielectric material is in the rutile crystalline phase, or the rutile crystalline phase constitutes the largest portion of the crystalline phase of the material constituting the dielectric material. In the following, "material in the rutile crystalline phase" means a material in which the rutile crystalline phase is dominant. 【0036】 For example, the dielectric layer 130 may contain titanium oxide (TiO2) in the rutile crystalline phase. Titanium oxide has different dielectric constants depending on its phase. For example, titanium oxide in the anatase crystalline phase has a dielectric constant of about 40, while titanium oxide in the rutile crystalline phase can have a large dielectric constant value ranging from about 80 to 170 depending on the growth direction. Therefore, the dielectric layer 130 containing titanium oxide in the rutile crystalline phase may have a dielectric constant of about 80 to about 170. According to the embodiment, because the dielectric layer 130 has a high dielectric constant, the thickness of the dielectric layer 130 can be reduced, and the capacitor 100 can be further miniaturized. For example, the thickness of the dielectric layer 130 may be about 3 nm to about 7 nm. 【0037】 The first electrode 110 may contain a conductive metal nitride. In particular, the first electrode 110 may contain a metal nitride that is not easily reduced to metal in the heat treatment process. That is, the metal nitride is also thermally stable within the higher temperature range applied in the heat treatment process described later. For example, the first electrode 110 may contain at least one conductive metal nitride or a combination thereof from among titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN), and cobalt nitride (CoN). The thickness of the first electrode 110 is also about 5 nm to about 10 nm. 【0038】 The second electrode 140 includes a conductive material and is not particularly limited. The second electrode 140 may have a single-layer or multi-layer structure including a metal, metal nitride, metal oxide, or a combination thereof. The second electrode 140 may include, for example, titanium nitride (TiN), molybdenum nitride (MoN), cobalt nitride (CoN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), platinum oxide (PtO), SrBaRuO3, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCO ((La,Sr)CoO3), or a combination thereof. 【0039】 The conductive interface layer 120 may be configured to allow the growth of a dielectric layer 130 of the rutile crystal phase on it (for example, by inducing the dielectric layer 130 of the rutile crystal phase through lattice growth via lattice deformation and / or determined alignment) and to reduce leakage current. According to the embodiment, the conductive interface layer 120 may include a first conductive interface layer 121 provided on the upper surface of the first electrode 110 and a second conductive interface layer 122 provided on the upper surface of the first conductive interface layer 121. The dielectric layer 130 may be provided on the upper surface of the second conductive interface layer 122. Thus, the first conductive interface layer 121 may be provided between the first electrode 110 and the dielectric layer 130, particularly between the first electrode 110 and the second conductive interface layer 122, and the second conductive interface layer 122 may be provided between the first conductive interface layer 121 and the dielectric layer 130. 【0040】 The first conductive interface layer 121 may contain a conductive metal oxide material having a stable crystal structure in the rutile crystal phase, so that a dielectric layer 130 in the rutile crystal phase can grow on the conductive interface layer 120. Furthermore, the first conductive interface layer 121 may contain a conductive metal oxide material that is not easily reduced to metal during the heat treatment process. Additionally, the first conductive interface layer 121 may contain a conductive metal oxide material that exhibits minimal degradation of film quality during the crystallization process (e.g., at temperatures above 450°C) and has a relatively large work function. For example, the first conductive interface layer 121 may contain tin (Sn)-doped molybdenum oxide (MoO2). That is, the first conductive interface layer 121 may contain both molybdenum oxide (MoO2) and tin oxide (SnO2). Therefore, the first conductive interface layer 121 is located between one of the two electrodes 110 and 140, that is, between the first electrode 110 and the dielectric layer 130, and is also called a "tin (Sn) doped molybdenum oxide (MoO2) layer". 【0041】 The second conductive interface layer 122 may include a conductive metal oxide material having a crystal structure stabilized in a rutile crystal phase, similar to the first conductive interface layer 121. Also, the second conductive interface layer 122 may include a conductive metal oxide material having a relatively large conduction band offset (CBO) with the dielectric layer 130 in order to reduce leakage current. For example, the material of the second conductive interface layer 122 may be selected such that the conduction band offset CBO between the second conductive interface layer 122 and the dielectric layer 130 is larger than the conduction band offset CBO between the first conductive interface layer 121 and the dielectric layer 130. The second conductive interface layer 122 may include, for example, tin oxide (SnO2), germanium oxide (GeO2), or a mixture of tin oxide and germanium oxide ((Sn x Ge 1-x )O2, 0 < x < 1). Therefore, the second conductive interface layer 122 is located between the "molybdenum oxide (MoO2) layer doped with tin (Sn)" and the dielectric layer 130, and is also referred to as an "interface layer containing tin (Sn) oxide and / or germanium (Ge) oxide". 【0042】 Figure 2 is a schematic energy band diagram illustrating the conduction band offset (CBO) between the second conductive interface layer and the dielectric layer of the capacitor shown in Figure 1. In Figure 2, (a) illustrates the conduction band offset CBO between the second conductive interface layer 122 and the dielectric layer 130, and (b) illustrates the conduction band offset CBO between the first conductive interface layer 121 and the dielectric layer 130 when the second conductive interface layer 122 is absent, for comparison. In Figure 2, the conduction band of the first conductive interface layer 121 is shown as a thick solid line. Referring to Figure 2, the conduction band offset CBO between the second conductive interface layer 122 and the dielectric layer 130 can be greater than approximately 1 eV. For example, the conduction band offset CBO between the second conductive interface layer 122 and the dielectric layer 130 can be approximately 1.4 eV, or between approximately 1.4 eV and approximately 1.5 eV. On the other hand, the conduction band offset CBO between the first conductive interface layer 121 and the dielectric layer 130 is about 1 eV, which is smaller than the conduction band offset CBO between the second conductive interface layer 122 and the dielectric layer 130. 【0043】 Figures 3A to 3D are schematic cross-sectional views illustrating the process of forming the conductive interface layer 120 of the capacitor 100 shown in Figure 1. 【0044】 Referring to Figure 3A, amorphous molybdenum oxide (MoO) is found on the upper surface of the first electrode 110. x A first material layer 121' containing ) can be formed. The first material layer 121' can be formed, for example, by pulsed laser deposition (PLD) or atomic layer deposition (ALD). Alternatively, the first material layer 121' can be formed by other deposition methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). 【0045】 Referring to Figure 3B, a second material layer 121'' containing tin oxide (SnO2) can be formed on the upper surface of the first material layer 121'. For example, the second material layer 121'' can be formed by the ALD method. 【0046】 Thereafter, referring to FIG. 3C, the first material layer 121' can be crystallized through a post metallization annealing (PMA) process. The heat treatment process can be performed, for example, at a temperature of about 450°C or higher and about 600°C or lower. Then, amorphous molybdenum oxide (MoO x ) can be crystallized to form crystalline molybdenum oxide (MoO2). In this process, tin oxide (SnO2) of the second material layer 121" on the first material layer 121' can be mixed into the crystal structure of the crystalline molybdenum oxide (MoO2). Thereby, a first conductive interface layer 121 including crystalline molybdenum oxide (MoO2) doped with tin (Sn) or including both crystalline molybdenum oxide (MoO2) and crystalline tin oxide (SnO2) can be formed on the upper surface of the first electrode 110. The first conductive interface layer 121 formed in this way can have a thickness of about 0.3 nm or more and about 4 nm or less, or about 0.3 nm or more and about 3 nm or less. 【0047】 Referring to FIG. 3D, the conductive interface layer 120 can be completed by forming a second conductive interface layer 122 on the first conductive interface layer 121. For example, by growing crystalline tin oxide (SnO2), crystalline germanium oxide (GeO2) or a mixture of crystalline tin oxide and crystalline germanium oxide ((Sn x Ge 1-x )O2, 0 < x < 1) on the first conductive interface layer 121 by an ALD method, a second conductive interface layer 122 can be formed on the first conductive interface layer 121. The second conductive interface layer 122 formed in this way can have a thickness of about 0.3 nm or more and about 1 nm or less, or about 0.3 nm or more and about 0.6 nm or less. For example, in at least some embodiments, the thickness of the second conductive interface layer 122 can be such that the lattice structure of the first conductive interface layer 121 restricts the lattice structure of the second conductive interface layer 122, so that the structure of the first conductive interface layer 121 can affect the structure of the dielectric layer 130 through the second conductive interface layer 122. 【0048】 After the process of FIG. 3D, a capacitor 100 can be manufactured by forming a dielectric layer 130 on the conductive interface layer 120, particularly the second conductive interface layer 122, and subsequently forming a second electrode 140 on the dielectric layer 130. The dielectric layer 130 can be formed, for example, by depositing titanium oxide (TiO2) by an ALD method. By depositing titanium oxide (TiO2) by an ALD method on the conductive interface layer 120 having a crystal structure stable in a rutile crystal phase, a dielectric layer 130 containing titanium oxide (TiO2) in a rutile crystal phase can be realized. 【0049】 According to an embodiment, in the process of forming the first conductive interface layer 121, when crystallizing amorphous molybdenum oxide (MoO x ), doping with tin (Sn) can mitigate the film quality degradation of the crystallized molybdenum oxide (MoO2). Thereby, the conductive interface layer 120 has a relatively uniform thickness of about 4 nm or less, and the surface roughness of the conductive interface layer 120 is relatively small. In this case, a dielectric layer 130 is formed homogeneously on the conductive interface layer 120, and the leakage current becomes low. 【0050】 Figure 4 shows a high-resolution transmission electron microscope (HR-TEM) image of a capacitor 100 according to an actual fabricated embodiment. The first electrode 110 is made of titanium nitride (TiN), the conductive interface layer 120 is made of tin (Sn)-doped molybdenum oxide (MoO2) and tin oxide (SnO2), the dielectric layer 130 is made of rutile crystalline titanium oxide (TiO2), and the second electrode 140 is made of platinum (Pt). Although not clearly separated in the image, the conductive interface layer 120 may include both the first conductive interface layer 121 and the second conductive interface layer 122. The conductive interface layer 120 and the dielectric layer 130 were grown using the atomic layer deposition (ALD) method. The second electrode 140 was formed through deposition. Referring to Figure 4, it can be confirmed that the conductive interface layer 120 according to the embodiment has a relatively uniform thickness. Therefore, in the case of the conductive interface layer 120 according to the embodiment, it can be seen that the degradation of the molybdenum oxide (MoO2) film quality is mitigated by the tin (Sn) doped with molybdenum oxide (MoO2). As a result, the dielectric layer 130 on the conductive interface layer 120 can also have a relatively uniform thickness. 【0051】 Figure 5 is a graph illustrating an example of a UPS spectrum obtained by UV photoelectron spectroscopy (UPS) measurement of the first conductive interface layer 121. The UPS spectrum shown in Figure 5 was obtained by forming a 3 nm thick first conductive interface layer 121 on a 10 nm thick first electrode 110 made of titanium nitride (TiN), and irradiating the first conductive interface layer 121 with UV light of approximately 21.22 eV perpendicularly. In the graph in Figure 5, the horizontal axis represents the binding energy, and the vertical axis represents the intensity or kinetic energy of the electrons ejected by the photoelectric effect. The work function of the sample can be determined from the difference between the X-intercept value of the derivative of the UPS spectrum graph shown in Figure 5 and 21.22 eV. 【0052】 Referring to Figure 5, the work function of the first conductive interface layer in the comparative example that is not doped with tin (Sn) is approximately 5.12 eV. Furthermore, the work function of the first conductive interface layer 121 in the embodiment doped with tin (Sn) at a concentration of approximately 1.5 at% is approximately 5.02 eV, and the work function of the first conductive interface layer 121 in the embodiment doped with tin (Sn) at a concentration of approximately 3.0 at% is approximately 5.03 eV. Therefore, it can be seen that the work function of the first conductive interface layer 121 in the tin (Sn) doped embodiment is slightly smaller than the work function of the first conductive interface layer 221 in the comparative example that is not doped. 【0053】 Figure 6 is a graph comparing the leakage current characteristics of a capacitor 100 including a conductive interface layer 120 according to an embodiment and a capacitor including a conductive interface layer according to a comparative example. In Figure 6, the horizontal axis shows the equivalent oxide thickness of the dielectric layer, and the vertical axis shows the leakage current of the capacitor. In the graphs in Figure 6 and Figures 7, 9, 10, and 11 described later, the numerical values ​​of equivalent oxide thickness and leakage current displayed on the horizontal and vertical axes have been normalized to show only relative characteristics. Referring to Figure 6, it can be seen that the capacitor of Comparative Example 1 (▲), which includes only a first conductive interface layer made of MoO2 doped with tin (Sn) at a concentration of approximately 1.5 at%, and does not include a second conductive interface layer, has the largest leakage current and the largest equivalent oxide thickness. The leakage current of the capacitor of Comparative Example 2 (■), which includes a first conductive interface layer made of undoped MoO2 and a second conductive interface layer made of SnO2, is lower than that of the capacitor of Comparative Example 1 in terms of leakage current and equivalent oxide thickness. Furthermore, it can be seen that the leakage current and equivalent oxide thickness of the capacitor 100 in embodiment (●), which includes both a first conductive interface layer 121 made of MoO2 doped with tin (Sn) at a concentration of approximately 1.5 at%, and a second conductive interface layer 122 made of SnO2, are the smallest. 【0054】 Figure 7 is a graph comparing the leakage current characteristics of capacitor 100 based on the tin (Sn) content in the first conductive interface layer 121. Referring to Figure 7, the leakage current and equivalent oxide thickness of capacitor 100 were smallest when the tin (Sn) doping concentration in the first conductive interface layer 121 was approximately 1.5 at% (●). The leakage current and equivalent oxide thickness of capacitor 100 with a tin (Sn) doping concentration of approximately 3.0 at% in the first conductive interface layer 121 (◆) are slightly larger than those of capacitor 100 with a tin (Sn) doping concentration of approximately 1.5 at%, but are smaller than those of the capacitor in the comparative example (■). On the other hand, the leakage current and equivalent oxide thickness of capacitor 100(▲), in which the tin (Sn) doping concentration in the first conductive interface layer 121 is approximately 4.5 at%, are even greater than those of the capacitor in the comparative example. 【0055】 When comprehensively considering the various property changes due to changes in the tin (Sn) doping concentration in the first conductive interface layer 121, as explained based on Figures 5 to 7, the tin (Sn) doping concentration in the first conductive interface layer 121 is approximately 0.1 at% to approximately 5.0 at%. Alternatively, the tin (Sn) doping concentration in the first conductive interface layer 121 is approximately 0.1 at% to approximately 4.0 at% or approximately 0.1 at% to approximately 3.0 at% or approximately 0.5 at% to approximately 3.0 at% or approximately 1.5 at% to approximately 3.0 at%. Here, the tin (Sn) doping concentration in the first conductive interface layer 121 is also the ratio of the number of tin (Sn) atoms to the total number of metal atoms in the first conductive interface layer 121. In other words, the doping concentration of tin (Sn) in the first conductive interface layer 121 is also "100 × number of Sn atoms / (number of Sn atoms + number of Mo atoms)". 【0056】 As described above, in the case of the capacitor 100 according to the embodiment, by utilizing the first conductive interface layer 121 doped with tin (Sn), a dielectric layer 130 containing a rutile crystalline dielectric material can be formed by atomic layer deposition (ALD). Therefore, the disclosed capacitor 100 can be miniaturized and have high capacitance. Furthermore, since the material of the first electrode 110 is chemically stable, the possibility of reduction to metal in subsequent processes is low. In addition, by utilizing the second conductive interface layer 122 which has a sufficiently large conduction band offset with the dielectric layer 130, leakage current is reduced. 【0057】 Referring again to Figure 1, the dielectric layer 130 may include a first insertion film 131 and a second insertion film 132 inserted within the dielectric layer 130. Titanium oxide (TiO2) having a rutile crystalline phase has a relatively high dielectric constant but has a relatively small band gap of about 3.0 eV and has n-type electrical characteristics, so leakage current can occur. The first insertion film 131 may include an oxide of a dopant metal having p-type electrical characteristics. For example, the first insertion film 131 may include an oxide of at least one metal from among aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc). The first insertion film 131 having p-type characteristics can lower the Fermi level of the dielectric layer 130 and reduce leakage current. However, since the first insertion film 131 does not have a rutile crystal phase, if the amount of the first insertion film increases, the titanium oxide (TiO2) in the dielectric layer 130 may grow into an anatase crystal phase, not a rutile crystal phase. Taking this into consideration, the dopant metal content of the first insertion film 131 in the dielectric layer 130 is, for example, greater than 0 at% and less than or equal to about 20 at%. Here, the dopant metal content is also the ratio of the number of dopant metal atoms to the total number of metal atoms in the dielectric layer 130 containing the metal of the second insertion film 132, which will be described later. 【0058】 The second insertion film 132 may contain oxides of group IV metal elements having a rutile crystalline phase. For example, the second insertion film 132 may contain at least one oxide of germanium (Ge), silicon (Si), and tin (Sn). Germanium oxide (GeO2), silicon oxide (SiO2), and tin oxide (SnO2) can have thermodynamically stable properties in the rutile crystalline phase. In particular, germanium oxide (GeO2) can have the largest band gap (e.g., about 4.63 eV) among oxides having a rutile crystalline phase, and can compensate for the relatively small band gap of titanium oxide (TiO2). Such a second insertion film 132 can help the dielectric layer 130 grow into the rutile crystalline phase. The second insertion film 132 can also capture oxygen vacancies present in the dielectric layer 130, reducing the number of oxygen vacancies in the dielectric layer 130. Therefore, by suppressing Fermi-level pinning that occurs at the interface between the conductive interface layer 120 and the dielectric layer 130 through the numerous oxygen vacancies distributed within the dielectric layer 130, leakage current can be further reduced. 【0059】 The first insertion film 131 and the second insertion film 132 can be grown by atomic layer deposition (ALD) during the process of growing the dielectric layer 130. For example, the lower part of the dielectric layer 130 can be grown by atomic layer deposition (ALD), and the second insertion film 132 can be grown by atomic layer deposition (ALD). Subsequently, the dielectric layer 130 can be partially grown again on the second insertion film 132, the first insertion film 131 can be grown on the dielectric layer 130 by atomic layer deposition (ALD), and then the upper part of the dielectric layer 130 can be grown on the first insertion film 131. The thicknesses of the first insertion film 131 and the second insertion film 132 can vary depending on the content of the first insertion film 131 and the second insertion film 132 within the dielectric layer 130. 【0060】 Figure 8 illustrates GI-XRD (grazing incidence X-Ray diffraction) measurement results comparing the crystallinity of dielectric layers grown with diverse layer structures. Referring to Figure 8, it can be seen that titanium oxide (TiO2) grown on titanium nitride (TiN) mainly has an anatase crystalline phase. On the other hand, when a conductive interface layer containing molybdenum oxide (MoO2) is present between the titanium nitride (TiN) and the dielectric layer 130, titanium oxide (TiO2) having a rutile crystalline phase can grow well, even if the dielectric layer 130 includes a first insertion film 131 and a second insertion film 132. In particular, when tin oxide (SnO2) is further added as a conductive interface layer on top of the molybdenum oxide (MoO2), it can be confirmed that the orientation in the c-axis direction, which has a relatively high dielectric constant, increases. 【0061】 Figure 9 is a graph comparing the leakage current characteristics of the capacitor with various material content for the first insertion layer 131 and the second insertion layer 132. The dielectric layer 130 uses titanium oxide (TiO2) with a thickness of 5 nm, the first insertion layer 131 uses aluminum oxide (Al2O3), and the second insertion layer 132 uses germanium oxide (GeO2). The first electrode 110 uses titanium nitride (TiN), the first conductive interface layer 121 uses tin (Sn)-doped molybdenum oxide (MoO2), and the second conductive interface layer 122 uses tin oxide (SnO2). In Figure 9, "A" shows the characteristics when the dielectric layer 130 contains only the second insertion film 132 and no first insertion film 131; "B1", "B2", "B3", "B4", "B5", and "B6" show the characteristics when the dielectric layer 130 contains only the first insertion film 131 and no second insertion film 132; and "C1", "C2", "C3", and "C4" show the characteristics when the dielectric layer 130 contains both the first insertion film 131 and the second insertion film 132. Furthermore, the content of the first insertion film 131 increases from "B1" to "B6", and the content of the second insertion film 132 increases from "C1" to "C4". The content of the first insertion film 131 in the dielectric layers 130 of "B1", "B2", "B3", "B4", "B5", and "B6" is 0 at%, 2.5 at%, 5 at%, 7.5 at%, 10 at%, and 12.5 at%, respectively. In dielectric layers 130 of "C1", "C2", "C3", and "C4", the content of the first insertion film 131 is 10 at%, and in dielectric layers 130 of "C1", "C2", "C3", and "C4", the content of the second insertion film 132 is 3 at%, 4.5 at%, 6 at%, and 7.5 at%, respectively. Furthermore, the distance between the conductive interface layer 120 and the first insertion film 131 is 50% of the thickness of the dielectric layer 130, and the distance between the conductive interface layer 120 and the second insertion film 132 is 25% of the thickness of the dielectric layer 130. 【0062】 Referring to Figure 9, even when germanium oxide (GeO2) is inserted alone in the dielectric layer 130, an improvement in leakage current (LKG) can be observed. However, when aluminum oxide (Al2O3) is inserted alone in the dielectric layer 130, the leakage current can become even lower compared to when germanium oxide (GeO2) is inserted alone, as the content of aluminum oxide (Al2O3) increases. However, when aluminum oxide (Al2O3) is inserted alone in the dielectric layer 130, the leakage current characteristics improve with increasing aluminum oxide (Al2O3) content, but the equivalent oxide thickness (T oxeq The properties of the equivalent oxide may be degraded. On the other hand, when both aluminum oxide (Al2O3) and germanium oxide (GeO2) are inserted in the dielectric layer 130, the leakage current characteristics may be further improved. Also, when both aluminum oxide (Al2O3) and germanium oxide (GeO2) are inserted in the dielectric layer 130, the slope at which the thickness characteristics of the equivalent oxide are degraded may be relatively mitigated compared to the slope at which the leakage current characteristics are improved. 【0063】 Figure 10 is a graph comparing the leakage current characteristics of the capacitor depending on the thickness of the second insertion film 132. Figure 11 is a graph comparing the leakage current characteristics of the capacitor depending on the position of the second insertion film 132. Similar to Figure 9, in Figures 10 and 11, the dielectric layer 130 is made of 5 nm thick titanium oxide (TiO2), the first insertion film 131 is made of aluminum oxide (Al2O3), and the second insertion film 132 is made of germanium oxide (GeO2). The first electrode 110 is made of titanium nitride (TiN), the first conductive interface layer 121 is made of tin (Sn) doped molybdenum oxide (MoO2), and the second conductive interface layer 122 is made of tin oxide (SnO2). 【0064】 In Figure 10, "Ref" indicates the characteristics when the first insertion film 131 is inserted alone without the second insertion film 132. Referring to Figure 10, when the thickness of the second insertion film 132 is 0.2 nm (2 Å), the leakage current characteristics are improved compared to when the first insertion film 131 is inserted alone. Furthermore, as the thickness of the second insertion film 132 increases from 0.2 nm (2 Å) to 0.3 nm (3 Å), the leakage current characteristics may improve further. When the thickness of the second insertion film 132 is 0.4 nm (4 Å), a slight improvement in leakage current is observed compared to when the thickness of the second insertion film 132 is 0.3 nm (3 Å), but the equivalent oxide thickness characteristics may deteriorate. When the thickness of the second insertion film 132 is 0.4 nm (4 Å), the leakage current characteristics are similar to when the thickness of the second insertion film 132 is 0.2 nm (2 Å), and the equivalent oxide thickness characteristics may deteriorate further. 【0065】 Considering these characteristics, the thickness of the second insertion film 132 is also approximately 0.1 nm (1 Å) or more and approximately 0.5 nm (5 Å) or less, or approximately 0.1 nm (1 Å) or more and approximately 0.4 nm (4 Å) or less, or approximately 0.1 nm (1 Å) or more and approximately 0.3 nm (3 Å) or less, or approximately 0.2 nm (2 Å) or more and approximately 0.5 nm (5 Å) or less, or approximately 0.2 nm (2 Å) or more and approximately 0.4 nm (4 Å) or less, or approximately 0.2 nm (2 Å) or more and approximately 0.3 nm (3 Å) or less. The thickness of the second insertion film 132 is thinner than the thickness of the first insertion film 131. For example, the thickness of the first insertion film 131 is also approximately 1 nm (10 Å) or less. 【0066】 Furthermore, the metal content of the second insertion film 132 having the aforementioned thickness within the dielectric layer 130 is approximately 0.1 at% to approximately 10 at%. Here, the metal content of the second insertion film 132 is also the ratio of the number of metal atoms in the second insertion film 132 to the total number of metal atoms in the dielectric layer 130 containing the dopant metal of the first insertion film 131. 【0067】 Referring to Figure 11, changes in the equivalent oxide thickness characteristics were observed depending on the position of the second insertion film 132 or the distance g between the conductive interface layer 120 and the second insertion film 132 (see Figure 1). The second insertion film 132 was made of germanium oxide (GeO2) with a thickness of 0.2 nm. For example, when the distance g between the conductive interface layer 120 and the second insertion film 132 is 20% and 25% of the thickness of the dielectric layer 130, almost the same characteristics are observed. However, if the second insertion film 132 is too close to the conductive interface layer 120, the equivalent oxide thickness characteristics may deteriorate. For example, when the distance g between the conductive interface layer 120 and the second insertion film 132 is 12.5% ​​of the thickness of the dielectric layer 130, the leakage current characteristics are similar to when the distance g between the conductive interface layer 120 and the second insertion film 132 is 20% or more of the thickness of the dielectric layer 130, but the equivalent oxide thickness may increase. Taking these points into consideration, the distance g between the conductive interface layer 120 and the second insertion film 132 is 20% or more of the thickness of the dielectric layer 130, or 25% or more of the thickness of the dielectric layer 130. For example, the distance g between the conductive interface layer 120 and the second insertion film 132 is approximately 0.5 nm (5 Å) or more. As long as the distance g between the conductive interface layer 120 and the second insertion film 132 is approximately 0.5 nm (5 Å) or more, the second insertion film 132 can be provided at any position within the dielectric layer 130. 【0068】 Figure 12 is a cross-sectional view showing a schematic structure of a capacitor according to another embodiment. In Figure 1, the second insertion film 132 is shown to be provided between the first insertion film 131 and the conductive interface layer 120 within the dielectric layer 130, but the position of the second insertion film 132 is not limited thereto. Referring to Figure 12, in the case of capacitor 100a according to another embodiment, the first insertion film 131 may be provided between the second insertion film 132 and the conductive interface layer 120 within the dielectric layer 130. In this case, the distance g between the conductive interface layer 120 and the second insertion film 132 is greater than the distance g' between the conductive interface layer 120 and the first insertion film 131. 【0069】 Alternatively, although not shown, the first insertion film 131 and the second insertion film 132 may be superimposed within the dielectric layer 130. In this case, the distance g between the conductive interface layer 120 and the second insertion film 132 is the same as the distance g' between the conductive interface layer 120 and the first insertion film 131. 【0070】 Furthermore, although Figures 1 and 12 show, for convenience, the dielectric layer 130 and the first insertion film 131 and second insertion film 132 inserted within the dielectric layer 130 are clearly distinguishable, in the actually fabricated capacitors 100 and 100a, the materials of the dielectric layer 130 and the materials of the first insertion film 131 and second insertion film 132 are mixed within the dielectric layer 130 and are not clearly distinguishable. In this respect, the dielectric layer 130 can also be considered to contain the first metal oxide, the second metal oxide, and the third metal oxide. 【0071】 The first metal oxide is, for example, titanium oxide (TiO2) having a rutile crystalline phase. The second metal oxide is also the material for the first insertion film 131. For example, the second metal oxide may include an oxide of at least one metal from among aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc). The third metal oxide is also the material for the second insertion film 132. For example, the third metal oxide may include an oxide of a group IV metal element. For example, the third metal oxide may include an oxide of at least one metal from among germanium (Ge), silicon (Si), and tin (Sn). 【0072】 Within the dielectric layer 130, the metal content of the first metal oxide is the highest, and the metal content of the second metal oxide and the third metal oxide may differ from each other. For example, the ratio of metal atoms of the first metal oxide to the total number of metal atoms in the dielectric layer 130 is approximately 70 at% or more. Also, the ratio of metal atoms of the second metal oxide to the total number of metal atoms in the dielectric layer 130 is greater than 0 at% and approximately 20 at% or less. The ratio of metal atoms of the third metal oxide to the total number of metal atoms in the dielectric layer 130 is approximately 0.1 at% or more and approximately 10 at% or less. Furthermore, the above-mentioned explanation regarding the configuration, such as the thickness and position of the first insertion film 131 and the second insertion film 132, can also be applied to the second and third metal oxides. 【0073】 When forming the dielectric layer 130 on the second conductive interface layer 122 after the process shown in Figure 3D, the first metal oxide, titanium oxide (TiO2), can be partially deposited first using the ALD method, followed by the second metal oxide and the third metal oxide in that order, or the third metal oxide and the second metal oxide in that order, or simultaneously using the ALD method. Furthermore, when depositing the second or third metal oxide, the first metal oxide can be deposited together. After depositing the second and third metal oxides, the first metal oxide can be further deposited as needed. In this manner, a dielectric layer 130 containing the first metal oxide, the second metal oxide, and the third metal oxide can be formed on the second conductive interface layer 122. 【0074】 On the other hand, the tin (Sn) doping concentration in the first conductive interface layer 121 described in Figures 5 to 7 does not take into account the leakage current reduction effect of the first insertion film 131 and the second insertion film 132. When both the first insertion film 131 and the second insertion film 132 are provided within the dielectric layer 130, the range of tin (Sn) doping concentration in the first conductive interface layer 121 can be further widened. For example, the tin (Sn) doping concentration in the first conductive interface layer 121 is approximately 0.1 at% to approximately 10 at%. Alternatively, the tin (Sn) doping concentration in the first conductive interface layer 121 is approximately 0.1 at% to approximately 8 at% or approximately 0.1 at% to approximately 6 at%. 【0075】 As described above, in the case of capacitors 100 and 100a according to the embodiment, by utilizing a first conductive interface layer 121 doped with tin (Sn), a dielectric layer 130 containing a rutile crystalline dielectric material can be formed by atomic layer deposition (ALD). Therefore, the disclosed capacitors 100 and 100a can be miniaturized and have high capacitance. Furthermore, since the material of the first electrode 110 is chemically stable, there is a low possibility of it being reduced to metal in subsequent processes. In addition, by utilizing a second conductive interface layer 122 with a sufficiently large conduction band offset from the dielectric layer 130, leakage current can be reduced. Furthermore, by further inserting the first insertion film 131 and the second insertion film 132 into the dielectric layer 130, leakage current can be further reduced. 【0076】 The aforementioned capacitors can be used in a variety of electronic devices. These capacitors, along with transistors, can be used in DRAM elements. Furthermore, they can form part of the electronic circuits that constitute electronic devices, along with other circuit elements. 【0077】 Figure 13 is a circuit diagram illustrating the schematic circuit configuration and operation of an electronic device employing a capacitor according to an embodiment. 【0078】 The circuit diagram of the electronic device 1000 relates to one cell of a DRAM (Dynamic Random Access Memory) element and includes one transistor TR, one capacitor CA, a word line WL, and a bit line BL. Capacitor CA is also the capacitor 100 and 100a described in Figures 1 to 12. 【0079】 The method for writing data to DRAM is as follows: A gate voltage (high) is applied to the gate electrode of the transistor TR via the word line WL to turn it "ON," and then the data voltage value to be input, VDD (hereinafter referred to as "high voltage") or 0 (hereinafter referred to as "low voltage"), is applied to the bit line BL. If a high voltage is applied to both the word line and the bit line, the capacitor CA is charged and the data "1" is recorded. If a high voltage is applied to the word line and a low voltage is applied to the bit line, the capacitor CA is discharged and the data "0" is recorded. 【0080】 When reading data, a high voltage is applied to the word line WL to turn on the DRAM transistor TR, and then a voltage of VDD / 2 is applied to the bit line BL. If the DRAM data is "1", that is, if the capacitor CA voltage is VDD, the charge in capacitor CA gradually moves to the bit line BL, and the voltage of the bit line BL becomes slightly higher than VDD / 2. Conversely, if the data in capacitor CA is "0", the charge in the bit line BL moves to capacitor CA, and the voltage of the bit line BL becomes slightly lower than VDD / 2. The potential difference across the bit line that occurs in this way can be sensed by a sense amplifier, and the value can be amplified to determine whether the data is "0" or "1". 【0081】 Figure 14 is a schematic diagram showing an electronic device according to an exemplary embodiment. 【0082】 Referring to Figure 14, the electronic device 1001 may include a structure in which a capacitor CA1 and a transistor TR are electrically connected by a contact 20. Capacitor CA1 may include a first electrode 110, a second electrode 140, a dielectric layer 130 provided between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 provided between the first electrode 110 and the dielectric layer 130. Capacitor CA1 is the same as capacitors 100 and 100a described in Figures 1 to 12, and as previously mentioned, a redundant explanation will be omitted. 【0083】 A transistor TR is also a field-effect transistor. A transistor TR includes a semiconductor substrate SU having a source region SR, a drain region DR, and a channel region CH, and a gate stack GS disposed on the semiconductor substrate SU facing the channel region CH, and comprising a gate insulating layer GI and a gate electrode GA. 【0084】 The channel region CH is the region between the source region SR and the drain region DR, and is electrically connected to both the source region SR and the drain region DR. The source region SR is electrically connected to or in contact with one end of the channel region CH, and the drain region DR may be electrically connected to or in contact with the other end of the channel region CH. The channel region CH can be defined as the substrate region between the source region SR and the drain region DR within the semiconductor substrate SU. 【0085】 The semiconductor substrate SU may contain semiconductor materials. For example, the semiconductor substrate SU may contain semiconductor materials such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In addition, the semiconductor substrate SU may contain SOI (silicon on insulator) substrates. 【0086】 The source region SR, drain region DR, and channel region CH are each formed independently by implanting impurities into different regions of the semiconductor substrate SU. In this case, the source region SR, channel region CH, and drain region DR may contain the substrate material as a base material. The source region SR and drain region DR are made of a conductive material, and in this case, the source region SR and drain region DR may include, for example, a metal, a metal compound, or a conductive polymer. 【0087】 The channel region CH may be embodied by a separate material layer (thin film), contrary to what is shown in the illustration. In this case, for example, the channel region CH may include at least one of the following: Si, Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional material (2D material), quantum dots, and organic semiconductors. For example, oxide semiconductors include InGaZnO, two-dimensional materials include TMD (transition metal dichalcogenide) or graphene, and quantum dots may include colloidal quantum dots (QD) or nanocrystal structures. 【0088】 The gate electrode GA may be positioned on a semiconductor substrate SU, spaced apart from the semiconductor substrate SU and facing the channel region CH. The gate electrode GA may include at least one of metals, metal nitrides, metal carbides, and polysilicon. For example, the metal may include at least one of aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and the metal nitride film may include at least one of titanium nitride film (TiN film) and tantalum nitride film (TaN film). The metal carbide may include at least one of aluminum and silicon-doped (or silicon-containing) metal carbides, specifically including TiAlC, TaAlC, TiSiC, or TaSiC. 【0089】 The gate electrode GA has a structure in which multiple materials are stacked, and may have a stacked structure of metal nitride layer / metal layer, such as TiN / Al, or a stacked structure of metal nitride layer / metal carbide layer / metal layer, such as TiN / TiAlC / W. However, the materials mentioned above are merely examples. 【0090】 A gate insulating layer GI may be further disposed between the semiconductor substrate SU and the gate electrode GA. The gate insulating layer GI may contain a paraelectric material or a high-k dielectric material and may have a dielectric constant of about 20 to 70. 【0091】 The gate insulating layer GI may contain silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or a two-dimensional insulator such as h-BN (hexagonal boron nitride). For example, the gate insulating layer GI may contain silicon oxide (SiO2), silicon nitride (SiN x ) and others, including hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), scandium tantalum lead oxide (PbSc 0.5 Ta 0.5 The gate insulating layer GI may contain materials such as O3, zinc lead niobate (PbZnNbO3), etc. The gate insulating layer GI may also contain metal nitride oxides such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), and yttrium oxynitride (YON), silicates such as ZrSiON, HfSiON, YSiON, and LaSiON, or aluminates such as ZrAlON and HfAlON. The gate insulating layer GI may also form a gate stack together with the gate electrode GA. 【0092】 One of the electrodes 110 and 140 of capacitor CA1 and one of the source region SR and drain region DR of transistor TR may be electrically connected by a contact 20. Here, the contact 20 may include a suitable conductive material, such as tungsten, copper, aluminum, or polysilicon. 【0093】 The arrangement of capacitor CA1 and transistor TR can be varied in many ways. For example, capacitor CA1 can be placed on a semiconductor substrate SU and embedded within the semiconductor substrate SU. 【0094】 Figure 14 shows an electronic device 1001 containing one capacitor CA1 and one transistor TR, but this is illustrative, and the electronic device 1001 may contain multiple capacitors and multiple transistors. 【0095】 Figure 15 is a drawing showing an electronic device according to another exemplary embodiment. 【0096】 Referring to Figure 15, the electronic device 1002 may include a structure in which a capacitor CA2 and a transistor TR are electrically connected by a contact 21. The transistor TR includes a semiconductor substrate SU having a source region SR, a drain region DR, and a channel region CH, and a gate stack GS disposed on the semiconductor substrate SU facing the channel region CH, and comprising a gate insulating layer GI and a gate electrode GA. 【0097】 The interlayer insulating film 25 may be provided on the semiconductor substrate SU in a manner that covers the gate stack GS. The interlayer insulating film 25 may contain an insulating material. For example, the interlayer insulating film 25 may contain a Si oxide (e.g., SiO2), an Al oxide (e.g., Al2O3), or a high dielectric material (e.g., HfO2). The contact 21 penetrates the interlayer insulating film 25 and electrically connects the transistor TR and the capacitor CA2. 【0098】 Capacitor CA2 includes a first electrode 110, a second electrode 140, a dielectric layer 130 provided between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 provided between the first electrode 110 and the dielectric layer 130. The first electrode 110 and the second electrode 140 are presented in a shape that maximizes the contact area with the dielectric layer 130, and the material of capacitor CA2 is substantially the same as that of capacitors 100 and 100a as described in Figures 1 to 12. 【0099】 Figure 16 is a plan view showing an electronic device according to yet another exemplary embodiment. 【0100】 Referring to Figure 16, the electronic device 1003 may include a structure in which multiple capacitors and multiple field-effect transistors are arranged in a repeating pattern. The electronic device 1003 may further include a semiconductor substrate 11' including a source, drain, and channel, a field-effect transistor including a gate stack 12, a contact structure 20' positioned on the semiconductor substrate 11' so as not to overlap with the gate stack 12, and a capacitor CA3 positioned on the contact structure 20', and a bit line structure 13 that electrically connects the multiple field-effect transistors. 【0101】 Figure 16 illustrates, but is not limited to, a configuration in which both the contact structure 20' and the capacitor CA3 are arranged repeatedly along the X and Y directions. For example, the contact structure 20' may be arranged along the X and Y directions, and the capacitor CA3 may be arranged in a hexagonal shape, such as a honeycomb structure. 【0102】 Figure 17 is a cross-sectional view along the line A-A' in Figure 16. 【0103】 Referring to Figure 17, the semiconductor substrate 11' may have an STI (shallow trench isolation) structure including an element isolation film 14. The element isolation film 14 may be a single layer made of one type of insulating film, or a multilayer made of a combination of two or more types of insulating films. The element isolation film 14 contains an element isolation trench 14T within the semiconductor substrate 11', and the element isolation trench 14T may be filled with an insulating material. The insulating material may include, but is not limited to, at least one of FSG (fluoride silicate glass), USG (undoped silicate glass), BPSG (boro-phospho-silicate glass), PSG (phospho-silicate glass), FOX (flowable oxide), PE-TEOS (plasma-enhanced tetra-ethyl-ortho-silicate), and TOSZ (tonen silazene). 【0104】 The semiconductor substrate 11' may further include a channel region CH defined by the element isolation film 14 and gate line trenches 12T that are parallel to the upper surface of the semiconductor substrate 11' and extend along the X direction. The channel region CH may have a relatively long island shape with a short axis and a long axis. The long axis of the channel region CH may be aligned along the D3 direction parallel to the upper surface of the semiconductor substrate 11', as illustrated in Figure 16. 【0105】 The gate line trench 12T may be positioned so as to intersect the channel region CH at a predetermined depth from the upper surface of the semiconductor substrate 11', or within the channel region CH. The gate line trench 12T may also be positioned inside the element isolation trench 14T, and the gate line trench 12T inside the element isolation trench 14T may have a lower bottom surface than the gate line trench 12T of the channel region CH. The first source / drain 11'ab and the second source / drain 11"ab may be positioned in the upper portion of the channel region CH located on both sides of the gate line trench 12T. 【0106】 A gate stack 12 may be arranged inside the gate line trench 12T. Specifically, a gate insulating layer 12a, a gate electrode 12b, and a gate capping layer 12c may be arranged sequentially inside the gate line trench 12T. Based on the above, the gate insulating layer 12a and the gate electrode 12b may include at least one of silicon oxide, silicon oxynitride, and silicon nitride. The gate capping layer 12c may be arranged on the gate electrode GA to fill the remaining portion of the gate line trench 12T. 【0107】 A bit line structure 13 may be positioned on the first source / drain 11'ab. The bit line structure 13 may be positioned parallel to the upper surface of the semiconductor substrate 11' and extending along the Y direction. The bit line structure 13 may be electrically connected to the first source / drain 11'ab and may sequentially include a bit line contact 13a, a bit line 13b, and a bit line capping layer 13c on the substrate. For example, the bit line contact 13a may contain polysilicon, the bit line 13b may contain a metallic material, and the bit line capping layer 13c may contain an insulating material such as silicon nitride or silicon oxynitride. 【0108】 Figure 17 shows an example where the bit line contact 13a has a bottom surface at the same level as the top surface of the semiconductor substrate 11', but this is illustrative and not limited thereto. For example, in another embodiment, a recess formed to a predetermined depth from the top surface of the semiconductor substrate 11' may be further provided, and the bit line contact 13a may extend into the recess, with the bottom surface of the bit line contact 13a being formed lower than the top surface of the semiconductor substrate 11'. 【0109】 The bit line structure 13 may further include a bit line intermediate layer (not shown) between the bit line contact 13a and the bit line 13b. The bit line intermediate layer may include a metal silicide such as tungsten silicide, or a metal nitride such as tungsten nitride. A bit line spacer (not shown) may also be formed on the side wall of the bit line structure 13. The bit line spacer may have a single-layer or multi-layer structure and may include an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. The bit line spacer may also further include an air space (not shown). 【0110】 The contact structure 20' may be positioned on the second source / drain 11"ab. The contact structure 20' and the bit line structure 13 may be positioned on different sources / drains on the substrate. The contact structure 20' is also a structure in which a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) are sequentially stacked on the second source / drain 11"ab. The contact structure 20' may further include a barrier layer (not shown) surrounding the sides and bottom of the upper contact pattern. For example, the lower contact pattern may contain polysilicon, the upper contact pattern may contain a metallic material, and the barrier layer may contain a conductive metal nitride. 【0111】 The capacitor CA3 may be electrically connected to the contact structure 20' and disposed on the semiconductor substrate 11'. Specifically, the capacitor CA3 includes a first electrode 110 electrically connected to the contact structure 20', a second electrode 140 spaced apart from the first electrode 110, a dielectric layer 130 disposed between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 provided between the first electrode 110 and the dielectric layer 130. The first electrode 110 may have a bottomed cylindrical or cup shape with an internal space. The second electrode 140 may have a comb shape with comb teeth extending into the internal space formed by the first electrode 110 and the region between adjacent first electrodes 110. The dielectric layer 130 may be disposed between the first electrode 110 and the second electrode 140 so as to be parallel to their surfaces. The conductive interface layer 120 may be disposed between the first electrode 110 and the dielectric layer 130 so as to be parallel to their surfaces. The materials of the first electrode 110, conductive interface layer 120, dielectric layer 130, and second electrode 140 that make up capacitor CA3 are substantially the same as those of capacitors 100 and 100a described in Figures 1 to 12, so no explanation of them will be provided. 【0112】 An interlayer insulating film 15 may be further disposed between the capacitor CA3 and the semiconductor substrate 11'. The interlayer insulating film 15 may be disposed in the space between the capacitor CA3 and the semiconductor substrate 11' where no other structures are placed. Specifically, the interlayer insulating film 15 may be disposed to cover wiring and / or electrode structures such as the bit line structure 13, contact structure 20', and gate stack 12 on the substrate. For example, the interlayer insulating film 15 may surround the wall of the contact structure 20'. The interlayer insulating film 15 may include a first interlayer insulating film 15a surrounding the bit line contact 13a and a second interlayer insulating film 15b covering the sides and / or top surfaces of the bit line 13b and the bit line capping layer 13c. 【0113】 The first electrode 110 of the capacitor CA3 may be placed on the interlayer insulating film 15, specifically on the second interlayer insulating film 15b. Furthermore, when multiple capacitors CA3 are arranged, the bottom surfaces of the multiple first electrodes 110 may be separated by an etching stop layer 16. That is, the etching stop layer 16 includes an opening 16T, within which the bottom surfaces of the first electrodes 110 of the capacitor CA3 may be placed. The first electrode 110 may have a bottomed cylindrical or cup shape with an internal space, as shown. The capacitor CA3 further includes a support (not shown) to prevent the first electrode 110 from tilting or tipping over, and the support may be placed on the side wall of the first electrode 110. 【0114】 Figure 18 is a cross-sectional view showing an electronic device according to yet another exemplary embodiment. 【0115】 The electronic device 1004 of this embodiment is shown as a cross-sectional view corresponding to the A-A' cross-sectional view in Figure 16, and differs from Figure 17 only in the shape of the capacitor CA4. The capacitor CA4 is electrically connected to the contact structure 20' and placed on the semiconductor substrate 11', and includes a first electrode 110 electrically connected to the contact structure 20', a second electrode 140 spaced apart from the first electrode 110, a dielectric layer 130 placed between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 placed between the first electrode 110 and the dielectric layer 130. The materials of the first electrode 110, the conductive interface layer 120, the dielectric layer 130, and the second electrode 140 are substantially the same as those of the capacitors 100 and 100a described in Figures 1 to 12. 【0116】 The first electrode 110 may have a pillar-like shape, such as a cylinder, rectangular prism, or polygonal prism, extending along the vertical direction (Z direction). The second electrode 140 may have a comb-like shape with comb teeth extending into the region between adjacent first electrodes 110. The dielectric layer 130 may be arranged between the first electrode 110 and the second electrode 140 so as to be parallel to their surfaces. The conductive interface layer 120 may be arranged between the first electrode 110 and the dielectric layer 130 so as to be parallel to their surfaces. 【0117】 The capacitors and electronic devices according to the embodiments described above can be applied to a variety of application fields. For example, the electronic devices according to the embodiments can be applied as logic elements or memory elements. The electronic devices according to the embodiments can be used in devices such as mobile devices, computers, notebook computers, sensors, network devices, and neuromorphic devices for arithmetic operations, program execution, and temporary data storage. Furthermore, the electronic elements and electronic devices according to the embodiments are useful in devices where the amount of data transmitted is large and data transmission is continuous. 【0118】 Figures 19 and 20 are conceptual diagrams illustrating a schematic element architecture that may be applied to an apparatus according to an exemplary embodiment. 【0119】 Referring to Figure 19, the electronic device architecture 1100 may include a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory unit 1010, ALU 1020, and control unit 1030 may be electrically connected. For example, the electronic device architecture 1100 may be embodied as a single chip including the memory unit 1010, ALU 1020, and control unit 1030. 【0120】 The memory unit 1010, ALU 1020, and control unit 1030 can be interconnected on-chip via metal lines and communicate directly with each other. The memory unit 1010, ALU 1020, and control unit 1030 can be monolithically integrated on a single substrate to form a single chip. Input / output elements 2000 can be connected to the electronic device architecture (chip) 1100. The memory unit 1010 may include both main memory and cache memory. Such an electronic device architecture (chip) 1100 is also an on-chip memory processing unit. The memory unit 1010 may include the aforementioned capacitors and electronic devices that utilize them. The ALU 1020 or control unit 1030 may also each include the aforementioned capacitors. 【0121】 Referring to Figure 20, the cache memory 1510, ALU 1520, and control unit 1530 constitute the CPU (Central Processing Unit) 1500, and the cache memory 1510 may consist of SRAM (Static Random Access Memory). Separately from the CPU 1500, main memory 1600 and auxiliary storage 1700 may be provided. The main memory 1600 is DRAM (Dynamic Random Access Memory) and may include the capacitors mentioned above. Depending on the case, the electronic device architecture may be realized on a single chip in a form where computing unit elements and memory unit elements are adjacent to each other, without the division of sub-units. 【0122】 The embodiments described above can be summarized as follows: 【0123】 (1) The capacitor according to the embodiment includes a first electrode; a second electrode provided opposite to the first electrode; a dielectric layer provided between the first electrode and the second electrode and containing a dielectric material in a rutile crystal phase; and a conductive interface layer provided between the first electrode and the dielectric layer, wherein the dielectric layer includes a first insertion film and a second insertion film inserted into the dielectric material, the first insertion film containing an oxide of a metal selected from at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc), and the second insertion film may contain an oxide of a group IV metal element having a rutile crystal phase. 【0124】 (2) The dielectric layer may include, for example, a rutile crystalline titanium oxide (TiO2). 【0125】 (3) The metal content of the first insertion film in the dielectric layer is, for example, greater than 0 at% and 20 at% or less. 【0126】 (4) The second insertion film may contain, for example, at least one oxide of germanium (Ge), silicon (Si), and tin (Sn). 【0127】 (5) The metal content of the second insertion film in the dielectric layer is, for example, 0.1 at% or more and 10 at% or less. 【0128】 (6) The thickness of the second insertion film is, for example, 0.1 nm or more and 0.5 nm or less. 【0129】 (7) The thickness of the second insertion film is thinner than the thickness of the first insertion film. 【0130】 (8) The distance between the conductive interface layer and the second insertion film is, for example, 0.5 nm or more. 【0131】 (9) In one example, the second insertion film may be provided within the dielectric layer between the first insertion film and the conductive interface layer. 【0132】 (10) In other examples, the first insertion film may be provided between the second insertion film and the conductive interface layer within the dielectric layer. 【0133】 (11) The conductive interface layer includes a first conductive interface layer provided between the first electrode and the dielectric layer and a second conductive interface layer provided between the first conductive interface layer and the dielectric layer. The first conductive interface layer includes a conductive metal oxide material having a crystal structure stable in a rutile crystal phase. The conduction band offset between the second conductive interface layer and the dielectric layer is larger than the conduction band offset between the first conductive interface layer and the dielectric layer. 【0134】 (12) The first conductive interface layer may include molybdenum oxide (MoO2) doped with tin (Sn). 【0135】 (13) The doping concentration of tin within the first conductive interface layer is, for example, 0.1 at% or more and 10 at% or less. 【0136】 (14) The thickness of the first conductive interface layer is, for example, also 0.3 nm or more and 4 nm or less. 【0137】 (15) The second conductive interface layer may include a conductive metal oxide material having a crystal structure stable in a rutile phase. 【0138】 (16) The second conductive interface layer includes tin oxide (SnO2), germanium oxide (GeO2), or a mixture of tin oxide and germanium oxide (Sn x Ge 1-x )O2, where 0 < x < 1). 【0139】 (17) The thickness of the second conductive interface layer is, for example, also 0.3 nm or more and 1 nm or less. 【0140】 (18) The first electrode may include, for example, at least one conductive metal nitride or a combination thereof, from among titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN), and cobalt nitride (CoN). 【0141】 (19) An electronic device according to an embodiment includes a transistor and a capacitor electrically connected to the transistor, wherein the capacitor includes: a first electrode; a second electrode provided opposite to the first electrode; a dielectric layer provided between the first electrode and the second electrode; and a conductive interface layer provided between the first electrode and the dielectric layer, wherein the dielectric layer includes a dielectric material in the rutile crystalline phase, and the dielectric layer includes a first insertion film and a second insertion film inserted within the dielectric layer, wherein the first insertion film includes an oxide of a metal selected from at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc), and the second insertion film may include an oxide of a group IV metal element having a rutile structure. 【0142】 (20) A memory element according to an embodiment includes a transistor and a capacitor electrically connected to the transistor, wherein the capacitor includes: a first electrode; a second electrode provided opposite to the first electrode; and a dielectric layer provided between the first electrode and the second electrode, the dielectric layer comprising a first metal oxide, a second metal oxide and a third metal oxide, wherein the first metal oxide is a titanium oxide having a rutile crystalline phase, and the second metal oxide comprises an oxide of a metal selected from at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc), and may also comprise an oxide of a metal selected from at least one of germanium (Ge), silicon (Si), and tin (Sn). 【0143】 (21) The content of the second metal oxide and the content of the third metal oxide may differ within the dielectric layer. 【0144】 (22) A method for manufacturing a capacitor according to an embodiment includes the steps of: forming a conductive interface layer on a first electrode; forming a dielectric layer on the conductive interface layer containing a first metal oxide, a second metal oxide, and a third metal oxide; and forming a second electrode on the dielectric layer, wherein the first metal oxide is a titanium oxide having a rutile crystalline phase, and the second metal oxide includes an oxide of a metal selected from at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc), and may include an oxide of a metal selected from at least one of germanium (Ge), silicon (Si), and tin (Sn). 【0145】 Although the description has been based on capacitors and electronic devices containing the same, which include dielectric layers made of the aforementioned high dielectric constant material, this is merely an example, and anyone with ordinary skill in the art will understand that a variety of modifications and equivalent other embodiments are possible. Therefore, the disclosed embodiments should be considered in a descriptive rather than restrictive manner. The scope of the rights is set forth in the claims, not in the description above, and all differences within an equivalent scope should be interpreted as being included within the scope of the rights. [Explanation of Symbols] 【0146】 100 Capacitors 110 1st electrode 120 Conductive interface layer 121 First conductive interface layer 122 Second conductive interface layer 130 Dielectric layer 131 First insertion membrane 132 Second insertion membrane 140 2nd electrode 1000, 1001, 1002, 1003, 1004 Electronic equipment

Claims

[Claim 1] First electrode and A second electrode is provided opposite to the first electrode, A dielectric layer is provided between the first electrode and the second electrode, and includes a dielectric material in the rutile crystal phase. The first electrode and the dielectric layer are provided together, and the conductive interface layer is provided between them. The dielectric layer includes a first insertion film and a second insertion film inserted within the dielectric material. The first insertion film contains an oxide of a metal selected from at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc). The second insertion film is a capacitor comprising an oxide of a group IV metal element having a rutile crystalline phase. [Claim 2] The dielectric layer is a titanium oxide (TiO) in the rutile crystalline phase. ２ The capacitor according to claim 1, including ). [Claim 3] The capacitor according to claim 1, wherein the metal content of the first insertion film in the dielectric layer is greater than 0 at% and less than or equal to 20 at%. [Claim 4] The capacitor according to claim 1, wherein the second insertion film comprises at least one oxide of germanium (Ge), silicon (Si), and tin (Sn). [Claim 5] The capacitor according to claim 4, wherein the metal content of the second insertion film in the dielectric layer is 0.1 at% or more and 10 at% or less. [Claim 6] The capacitor according to claim 4, wherein the thickness of the second insertion film is 0.1 nm or more and 0.5 nm or less. [Claim 7] The capacitor according to claim 4, wherein the thickness of the second insertion film is thinner than the thickness of the first insertion film. [Claim 8] The capacitor according to claim 4, wherein the distance between the conductive interface layer and the second insertion film is 0.5 nm or more. [Claim 9] The capacitor according to claim 1, wherein the second insertion film is provided between the first insertion film and the conductive interface layer within the dielectric layer. [Claim 10] The capacitor according to claim 1, wherein the first insertion film is provided between the second insertion film and the conductive interface layer within the dielectric layer. [Claim 11] The conductive interface layer includes a first conductive interface layer provided between the first electrode and the dielectric layer and a second conductive interface layer provided between the first conductive interface layer and the dielectric layer. The first conductive interface layer comprises a conductive metal oxide material having a stable crystalline structure in the rutile crystalline phase. The capacitor according to claim 1, wherein the conduction band offset between the second conductive interface layer and the dielectric layer is greater than the conduction band offset between the first conductive interface layer and the dielectric layer. [Claim 12] The first conductive interface layer is made of tin (Sn) doped molybdenum oxide (MoO ２ The capacitor according to claim 11, including ). [Claim 13] The capacitor according to claim 11, wherein the tin doping concentration in the first conductive interface layer is 0.1 at% or more and 10 at% or less. [Claim 14] The capacitor according to claim 11, wherein the thickness of the first conductive interface layer is 0.3 nm or more and 4 nm or less. [Claim 15] The second conductive interface layer is made of tin oxide (SnO ２ ), germanium oxide (GeO ２ ), or a mixture of tin oxide and germanium oxide ((Sn ｘ Ge １－ｘ ) O ２ The capacitor according to claim 11, including , 0 < x < 1. [Claim 16] The capacitor according to claim 11, wherein the thickness of the second conductive interface layer is 0.3 nm or more and 1 nm or less. [Claim 17] The capacitor according to claim 1, wherein the first electrode comprises at least one conductive metal nitride or a combination thereof, selected from titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN), and cobalt nitride (CoN). [Claim 18] Transistors and The transistor and a capacitor electrically connected thereto, The aforementioned capacitor is First electrode and A second electrode is provided opposite to the first electrode, A dielectric layer provided between the first electrode and the second electrode, The dielectric layer comprises a first metal oxide, a second metal oxide, and a third metal oxide. The first metal oxide is a titanium oxide having a rutile crystalline phase. The second metal oxide includes an oxide of a metal selected from at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc). A memory element comprising an oxide of a metal selected from at least one of germanium (Ge), silicon (Si), and tin (Sn). [Claim 19] The memory element according to claim 18, wherein the content of the second metal oxide and the content of the third metal oxide in the dielectric layer are different from each other. [Claim 20] The steps include forming a conductive interface layer on the first electrode, The steps include forming a dielectric layer containing a first metal oxide, a second metal oxide, and a third metal oxide on the conductive interface layer, The step of forming a second electrode on the dielectric layer is included, The first metal oxide is a titanium oxide having a rutile crystalline phase. The second metal oxide includes an oxide of a metal selected from at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc). A method for manufacturing a capacitor, comprising an oxide of a metal selected from at least one of germanium (Ge), silicon (Si), and tin (Sn).

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