Photoelectric converter

Abstract

To provide a photoelectric converter capable of acquiring signals under various illumination conditions. [Solution] The system includes an avalanche photodiode, an output holding circuit that holds a light-receiving signal based on the output of the avalanche photodiode, a first logic circuit to which the light-receiving signal held in the output holding circuit and a first reference signal indicating a first weighting amount are input, and a first integration circuit that holds a first count value obtained by integrating the outputs of the first logic circuit, wherein the first integration circuit resets the first count value every first period, the first period is divided into a plurality of second periods, the first weighting amount changes every second period, and the output holding circuit resets the light-receiving signal every second period.

Description

Technical Field

[0001] The present disclosure relates to a photoelectric conversion device.

Background Art

[0002] Non-Patent Document 1 discloses a time-correlated image sensor. The pixel circuit of the time-correlated image sensor of Non-Patent Document 1 includes a photodiode that generates a photocurrent and a plurality of capacitors that each accumulate optical carriers. Thereby, the time-correlated image sensor of Non-Patent Document 1 can realize time-correlated imaging.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a time-correlated image sensor as exemplified in Non-Patent Document 1, signal acquisition under various illuminance levels may be required. Therefore, an object of the present invention is to provide a photoelectric conversion device capable of performing signal acquisition under various illuminance levels.

Means for Solving the Problems

[0005] According to one disclosure of this specification, a photoelectric converter is provided, comprising: an avalanche photodiode; an output holding circuit for holding a light-receiving signal based on the output of the avalanche photodiode; a first logic circuit to which the light-receiving signal held in the output holding circuit and a first reference signal indicating a first weighting amount are input; and a first integration circuit for holding a first count value obtained by integrating the outputs of the first logic circuit, wherein the first integration circuit resets the first count value every first period, the first period is divided into a plurality of second periods, the first weighting amount changes every second period, and the output holding circuit resets the light-receiving signal every second period.

[0006] According to one disclosure of this specification, a photoelectric converter is provided, comprising: an avalanche photodiode; a memory that holds two or more bits of light intensity values ​​generated by a light-receiving signal based on the output of the avalanche photodiode; a conversion unit that receives the light intensity values ​​held in the memory and a first reference signal indicating a first weighting amount, and outputs a conversion signal based on calculations using the light intensity values ​​and the first weighting amount; and a first integration circuit that holds a first count value obtained by integrating the conversion signals, wherein the first period in which the first integration circuit performs the integration of the first count value is divided into a plurality of second periods, the first weighting amount changes with each second period, and the light intensity value is generated based on the light-receiving signal input in one of the second periods. [Effects of the Invention]

[0007] According to this disclosure, a photoelectric converter capable of acquiring signals under various illumination conditions is provided. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic diagram showing the overall configuration of the photoelectric conversion device according to the first embodiment. [Figure 2] This is a schematic block diagram showing an example of the configuration of a sensor substrate according to the first embodiment. [Figure 3]It is a schematic block diagram showing a configuration example of a circuit board according to the first embodiment. [Figure 4] It is a diagram showing the relationship between the main frame period and the sub-frame period, and the time change of the weighting amount according to the first embodiment. [Figure 5] It is a schematic block diagram showing a configuration example of one pixel of a photoelectric conversion unit and a pixel signal processing unit according to the first embodiment. [Figure 6] It is a diagram for explaining the operation of an avalanche photodiode according to the first embodiment. [Figure 7] It is a diagram showing the configuration of a pixel according to the first embodiment. [Figure 8] It is a timing diagram showing a pixel driving method according to the first embodiment. [Figure 9] It is a timing diagram showing a pixel driving method according to the first embodiment. [Figure 10] It is a timing diagram showing a pixel driving method according to the first embodiment. [Figure 11] It is a diagram showing the configuration of a pixel according to the second embodiment. [Figure 12] It is a timing diagram showing a pixel driving method according to the second embodiment. [Figure 13] It is a diagram showing the configuration of a pixel according to the third embodiment. [Figure 14] It is a diagram showing the configuration of a pixel according to the fourth embodiment. [Figure 15] It is a timing diagram showing a pixel driving method according to the fourth embodiment. [Figure 16] It is a block diagram showing a schematic configuration of a device according to the fifth embodiment. [Figure 17] It is a block diagram showing a schematic configuration of a device according to the sixth embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the embodiments described below, as an example of a photoelectric conversion device, an imaging device will be mainly described. However, the photoelectric conversion device to which the technology of each embodiment is applicable is not limited to an imaging device, and may be other devices. For example, the technology of each embodiment is also applicable to a distance measuring device (for example, a focus detection device or a device that measures distance using ToF (Time of Flight)), and a photometric device (a device that measures the amount of incident light).

[0010] Note that the conductivity type of the transistor described in the embodiments below is an example, and is not limited to only the conductivity type described in the embodiments. The conductivity type described in the embodiments may be appropriately changed, and accordingly, the potential of the gate, source, or drain of the transistor may be appropriately changed. For example, in a transistor that operates as a switch, when the conductivity type is changed, the low level and high level of the potential supplied to the gate are reversed with respect to the description in the embodiments.

[0011] Also, in the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, unless otherwise specified, the elements of interest are treated as being connected. For example, assume that element A is connected to one node of a capacitive element C having a plurality of nodes, and element B is connected to another node of the capacitive element C. Even in such a case, unless otherwise specified, element A and element B are treated as being connected.

[0012] [First Embodiment] Prior to the description of the photoelectric conversion device of this embodiment, the principles of a time-correlated image sensor and an event-based sensor will be outlined.

[0013] The time-correlated image sensor includes a photodiode and a configuration that divides and acquires the signals output from the photodiode into a plurality. The signal for each pixel that generates an image is represented by the following formula (1). [Equation] Here, f(x,y,t) is the brightness of pixel (x,y) at time t. Also, v is the velocity of pixel (x,y) (the time derivative of pixel (x,y)). ∇ is the nabla operator (vector differential operator).

[0014] Let T be the exposure time for acquiring one frame of image. Also, image g n (x,y) is expressed by the following equation (2).

number

[0015] As shown in equation (2), image g n (x,y) is a complex number e with lightness f(x,y,t) -inΔwt The image g is obtained by multiplying the reference signal represented by by and integrating over the duration of one frame. n Let (x,y) satisfy the following equation (3).

number

[0016] The second term on the left side of equation (3) represents the boundary value of the integral. Equation (3) is a system of simultaneous equations because it consists of multiple equations that differ depending on the value of n. Therefore, the boundary value of the integral can be eliminated by solving the system of simultaneous equations using, for example, two images g0(x,y) and g1(x,y). The time-correlated image sensor consists of an intensity image g0(x,y) consisting only of the real part and a correlation image g of a complex number. n The real and imaginary parts of (x,y) can be output (hereinafter, the complex correlation image will also be called the time-correlated signal). Therefore, by substituting the output signal of the time-correlated image sensor into the system of equations in equation (3) and solving it, the velocity v at each pixel (x,y), i.e., the optical flow, can be obtained.

[0017] In the signal processing of a time-correlated image sensor, it is necessary to calculate an integral over the range of one frame period, as shown in equation (2). Therefore, the output timing of the correlated image is limited to one frame period. In a time-correlated image sensor, the period of the reference signal and the period of the shutter opening period are matched. Therefore, the correlated image is output at a frequency corresponding to the period of the shutter opening period.

[0018] Here, we will provide an overview of event-based sensors. An event-based sensor detects changes in brightness within the shooting range and outputs an event signal each time a change in brightness is detected. An event-based sensor includes, for example, multiple pixels arranged in a matrix. That is, an event signal is a signal associated with an event, and an event is a change in the brightness of a pixel. An event signal may include, for example, the time when the event was detected, the position of the pixel where the event was detected, and the change in the pixel value. The time when the event was detected can be measured relative to the time indicated by the internal clock of the event-based sensor (event camera time).

[0019] The time reference for event detection can be reset as needed. A change in pixel value is, for example, a change in brightness. A change in pixel value may be the amount of change itself, or it may be information indicating whether the brightness change is positive or negative.

[0020] An event-based sensor outputs an event signal when a change in brightness occurs, and does not output an event signal when no change in brightness occurs. In other words, an event-based sensor outputs event signals asynchronously. Asynchronous output means that signals are output on a pixel-by-pixel basis, independently of time.

[0021] The operation of the event-based sensor can be expressed mathematically as follows: Equation (4).

number

[0022] An event-based sensor can be equipped with the functionality to output a time-correlated signal, similar to that of a time-correlated image sensor. When time t is the end time of the frame period, the output signal of the time-correlated image sensor can be expressed using the angular velocity ω (ω = 2π / T) as shown in equations (5) to (7) below.

number

[0023] In a time-correlated image sensor, charge based on the current output from the photodiode is accumulated in a capacitor. The accumulated charge corresponds to brightness. On the other hand, in an event-based sensor, a signal is output that is a quantized version of the change in current output from the photodiode. Therefore, in an event-based sensor, the output from the photodiode at time s can be divided into a localization term f(x,y,tT) which is constant within the measurement period, and a displacement term δf(x,y,s) which corresponds to the difference with respect to the localization term. Thus, f(x,y,s) is expressed as shown in equation (8) below.

number

[0024] Furthermore, considering the properties of the reference signal, equations (9) and (10) below are satisfied.

number

[0025] Using the relationship between equations (9) and (10), equations (5) through (7) can be rewritten using a local term and a displacement term. This yields equations (11) through (13) below.

number

[0026] In the event-based sensor, the current output by the photodiode of the time-correlated image sensor is converted into an event signal for the event-based sensor, as shown in equation (14) below.

number

[0027] As a result, equations (11) through (13) can be transformed into equations (15) through (17) below.

number

[0028] Next, the configuration of the photoelectric converter according to this embodiment will be described. Figure 1 is a schematic diagram showing the overall configuration of the photoelectric converter 100 according to this embodiment. The photoelectric converter 100 has a sensor substrate 11 (first substrate) and a circuit board 21 (second substrate) stacked on top of each other. The sensor substrate 11 and the circuit board 21 are electrically interconnected. The sensor substrate 11 has a pixel region 12 on which a plurality of pixel circuits 101 are arranged in a plurality of rows and a plurality of columns. The circuit board 21 has a first circuit region 22 on which a plurality of pixel signal processing units 103 are arranged in a plurality of rows and a plurality of columns, and a second circuit region 23 arranged on the outer periphery of the first circuit region 22. The second circuit region 23 may include circuits for controlling the plurality of pixel signal processing units 103. The sensor substrate 11 has a light incident surface that receives incident light and a connection surface that faces the light incident surface. The sensor substrate 11 is connected to the circuit board 21 on the connection surface side. In other words, the photoelectric converter 100 is a so-called back-illuminated type.

[0029] In this specification, "plan view" refers to viewing from a direction perpendicular to the surface opposite to the light incidence surface. Similarly, "cross-section" refers to the surface of the sensor substrate 11 perpendicular to the surface opposite to the light incidence surface. While the light incidence surface may appear rough at a microscopic level, in such cases, the plan view is defined based on the light incidence surface as viewed macroscopically.

[0030] In the following description, the sensor substrate 11 and the circuit board 21 are assumed to be diced chips, but the sensor substrate 11 and the circuit board 21 are not limited to chips. For example, the sensor substrate 11 and the circuit board 21 may be wafers. Furthermore, if the sensor substrate 11 and the circuit board 21 are diced chips, the photoelectric converter 100 may be manufactured by stacking wafers and then dicing them, or by stacking wafers after dicing them.

[0031] Figure 2 is a schematic block diagram showing an example of the arrangement of the sensor substrate 11. Multiple pixel circuits 101 are arranged in multiple rows and multiple columns in the pixel region 12. Each of the multiple pixel circuits 101 has a photoelectric conversion unit 102 on the substrate, which includes an avalanche photodiode (hereinafter referred to as APD) as a photoelectric conversion element.

[0032] In an APD (Automated Precipitator), the conductivity type corresponding to the charge used as the signal charge is called the first conductivity type. The first conductivity type refers to a conductivity type in which the majority carriers are charges of the same polarity as the signal charge. Conversely, the conductivity type opposite to the first conductivity type, i.e., a conductivity type in which the majority carriers are charges of a different polarity than the signal charge, is called the second conductivity type. In the APD described below, the anode of the APD is at a fixed potential, and the signal is extracted from the cathode of the APD. Therefore, the semiconductor region of the first conductivity type is the N-type semiconductor region, and the semiconductor region of the second conductivity type is the P-type semiconductor region. Alternatively, the cathode of the APD may be at a fixed potential, and the signal may be extracted from the anode of the APD. In this case, the semiconductor region of the first conductivity type is the P-type semiconductor region, and the semiconductor region of the second conductivity type is the N-type semiconductor region. Furthermore, the following description focuses on the case where one node of the APD is at a fixed potential, but a configuration in which the potentials of both nodes fluctuate is also possible.

[0033] Figure 3 is a schematic block diagram showing an example of the configuration of the circuit board 21. The circuit board 21 has a first circuit region 22 in which a plurality of pixel signal processing units 103 are arranged in a plurality of rows and a plurality of columns.

[0034] Furthermore, the circuit board 21 includes a vertical scanning circuit 110, a horizontal scanning circuit 111, a readout circuit 112, a pixel output signal line 113, an output circuit 114, a control signal generation unit 115, and a weight control unit 116. The multiple photoelectric conversion units 102 shown in Figure 2 and the multiple pixel signal processing units 103 shown in Figure 3 are electrically connected via connecting wiring provided for each pixel circuit 101.

[0035] The control signal generation unit 115 is a control circuit that generates and supplies control signals to drive the vertical scanning circuit 110, the horizontal scanning circuit 111, the readout circuit 112, and the weight control unit 116. In this way, the control signal generation unit 115 controls the drive timing and other aspects of each component.

[0036] The vertical scanning circuit 110 supplies control signals to each of the multiple pixel signal processing units 103 based on the control signals supplied from the control signal generation unit 115. The vertical scanning circuit 110 supplies control signals to each pixel signal processing unit 103 row by row via drive lines provided for each row of the first circuit region 22. As will be described later, there may be multiple drive lines for each row. Logic circuits such as shift registers and address decoders may be used in the vertical scanning circuit 110. This allows the vertical scanning circuit 110 to select the row from which the pixel signal processing unit 103 will output a signal.

[0037] The signal output from the photoelectric conversion unit 102 of the pixel circuit 101 is processed by the pixel signal processing unit 103. The pixel signal processing unit 103 acquires and stores a digital signal based on the pulse output from the APD included in the photoelectric conversion unit 102.

[0038] The weight control unit 116 controls the weighting coefficient (weighting amount) applied to the output signal from the APD in the pixel signal processing unit 103. A reference signal containing information about the weighting amount is supplied from the weight control unit 116 to each of the multiple pixel signal processing units 103.

[0039] The horizontal scanning circuit 111 supplies control signals to the readout circuit 112 based on control signals supplied from the control signal generation unit 115. The pixel signal processing unit 103 is connected to the readout circuit 112 via pixel output signal lines 113, which are provided for each column of the first circuit region 22. The pixel output signal line 113 of one column is shared by multiple pixel signal processing units 103 of the corresponding column. The pixel output signal line 113 includes multiple wires and has at least the function of outputting a digital signal from each pixel signal processing unit 103 to the readout circuit 112, and the function of supplying a control signal to the pixel signal processing unit 103 for selecting the column from which to output a signal. The readout circuit 112 outputs a signal to the processing unit 400 via the output circuit 114 based on control signals supplied from the control signal generation unit 115.

[0040] The processing unit 400 performs signal processing on the signal output from the photoelectric converter 100. The processing unit 400 can use the signal output from the photoelectric converter 100 to perform processing related to time-correlated imaging, such as calculating optical flow. This processing may be based, for example, on equations (1) to (17) described above. The processing unit 400 may be located inside the photoelectric converter 100, or it may be located in the equipment on which the photoelectric converter 100 is mounted.

[0041] The photoelectric conversion units 102 in the pixel region 12 may be arranged in a one-dimensional manner. Furthermore, the pixel signal processing unit 103 does not necessarily have to be provided for every pixel circuit 101. For example, one pixel signal processing unit 103 may be shared by multiple pixel circuits 101. In this case, the pixel signal processing unit 103 provides signal processing functionality to each pixel circuit 101 by sequentially processing the signals output from each photoelectric conversion unit 102.

[0042] As shown in Figures 2 and 3, a first circuit region 22, in which multiple pixel signal processing units 103 are arranged, is located in a region that overlaps with the pixel region 12 in a plan view. A vertical scanning circuit 110, a horizontal scanning circuit 111, a readout circuit 112, an output circuit 114, a control signal generation unit 115, and a weight control unit 116 are arranged so as to overlap between the edge of the sensor substrate 11 and the edge of the pixel region 12 in a plan view. In other words, the sensor substrate 11 has a pixel region 12 and a non-pixel region arranged around the pixel region 12. A second circuit region 23 is located in the circuit substrate 21, in a region that overlaps with the non-pixel region in a plan view, and in which the vertical scanning circuit 110, a horizontal scanning circuit 111, a readout circuit 112, an output circuit 114, a control signal generation unit 115, and a weight control unit 116 are arranged.

[0043] Note that the arrangement of the pixel output signal lines 113, the readout circuit 112, and the output circuit 114 is not limited to those shown in Figure 3. For example, the pixel output signal lines 113 may be arranged to extend in the row direction and be shared by multiple pixel signal processing units 103 in the corresponding row. The readout circuit 112 may be arranged so that the pixel output signal lines 113 of each row are connected.

[0044] Figure 4 shows the relationship between the mainframe period and the subframe period, and the time change of the weighting amount, according to the first embodiment. In the graph shown in Figure 4, the horizontal axis represents time, and the vertical axis represents the weighting amount set by the weighting control unit 116. As shown in Figure 4, the mainframe period (first period), which is the exposure period for generating one frame, is divided into multiple subframe periods (second period). The weighting control unit 116 sets the weighting amount so that the weighting amount changes each time a subframe period has elapsed. The weighting amount can be set based on a periodic function in which time is a variable and the mainframe period is one period. In other words, this periodic function has a different phase for each subframe period. The periodic function used to set the weighting amount may be a sine function. By performing weighting with a weighting amount based on a sine function, a signal corresponding to equation (17) can be generated. Alternatively, the periodic function used to set the weighting amount may be a cosine function. By performing weighting with a weighting amount based on a cosine function, a signal corresponding to equation (16) can be generated. As will be discussed later, a single subframe period can be further divided into multiple microframe periods (third periods).

[0045] Figure 5 is a schematic block diagram showing an example of the configuration of one pixel of the photoelectric conversion unit 102 and the pixel signal processing unit 103 according to this embodiment. Figure 5 schematically shows a more specific configuration example, including the connection relationship between the photoelectric conversion unit 102 arranged on the sensor substrate 11 and the pixel signal processing unit 103 arranged on the circuit board 21. In Figure 5, the drive lines between the vertical scanning circuit 110 and the pixel signal processing unit 103 in Figure 3 are shown as drive lines 213 and 214.

[0046] The photoelectric conversion unit 102 has an APD 201. The pixel signal processing unit 103 has a quench element 202, a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212. Note that the pixel signal processing unit 103 only needs to have at least one of the waveform shaping unit 210, the counter circuit 211, and the selection circuit 212.

[0047] The APD201 generates charge pairs corresponding to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD201. The cathode of the APD201 is connected to the first terminal of the quench element 202 and the input terminal of the waveform shaping unit 210. A voltage VH (second voltage), which is higher than the voltage VL supplied to the anode, is supplied to the cathode of the APD201. As a result, a reverse bias voltage is supplied to the anode and cathode of the APD201, causing the APD201 to perform avalanche multiplication. When a charge is generated by incident light in the APD201 with the reverse bias voltage supplied, this charge undergoes avalanche multiplication, generating an avalanche current.

[0048] When a reverse bias voltage is supplied to the APD201, there are two operating modes: Geiger mode and linear mode. Geiger mode is a mode in which the anode and cathode potential difference is greater than the breakdown voltage, while linear mode is a mode in which the anode and cathode potential difference is near or below the breakdown voltage.

[0049] An APD operating in Geiger mode is called a SPAD (Single Photon Avalanche Diode). In this case, for example, the voltage VL (first voltage) is -30V and the voltage VH (second voltage) is 1V. The APD201 may operate in linear mode or Geiger mode. In the case of a SPAD, the potential difference is larger compared to a linear-mode APD, and the avalanche multiplication effect is more pronounced, so it is preferable to use a SPAD.

[0050] The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication. The quench element 202 suppresses the voltage supplied to the APD201, thereby suppressing avalanche multiplication (quench operation). The quench element 202 also restores the voltage supplied to the APD201 to voltage VH by supplying a current corresponding to the voltage drop caused by the quench operation (recharge operation). The quench element 202 may be, for example, a transistor.

[0051] The waveform shaping unit 210 shapes the cathode potential change of the APD201 obtained during photon detection and outputs a pulse signal. For example, an inverter circuit can be used as the waveform shaping unit 210. Figure 5 shows an example in which one inverter is used as the waveform shaping unit 210, but the waveform shaping unit 210 may also be a circuit in which multiple inverters are connected in series, or it may be any other circuit that has a waveform shaping effect.

[0052] The counter circuit 211 counts the pulse signals output from the waveform shaping unit 210 and holds a digital signal indicating the count value. When a control signal is supplied from the vertical scanning circuit 110 via the drive line 213, the counter circuit 211 resets the signal it is holding.

[0053] The selection circuit 212 receives a control signal from the vertical scanning circuit 110 shown in Figure 3 via the drive line 214 shown in Figure 5. In response to this control signal, the selection circuit 212 switches between electrically connecting and disconnecting the counter circuit 211 and the pixel output signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting a signal corresponding to the value held in the counter circuit 211.

[0054] In the example shown in Figure 5, the selection circuit 212 switches between the electrical connection and disconnection of the counter circuit 211 and the pixel output signal line 113. However, the method for controlling the signal output to the pixel output signal line 113 is not limited to this. For example, switches such as transistors may be placed at nodes such as between the quench element 202 and the APD 201, or between the photoelectric conversion unit 102 and the pixel signal processing unit 103, to switch between electrical connection and disconnection and control the signal output to the pixel output signal line 113. Alternatively, the signal output to the pixel output signal line 113 may be controlled by changing the value of the voltage VH or voltage VL supplied to the photoelectric conversion unit 102 using a switch such as a transistor.

[0055] Figures 6(a), 6(b), and 6(c) illustrate the operation of the APD201 according to this embodiment. Figure 6(a) is a diagram showing the APD201, quench element 202, and waveform shaping unit 210 extracted from Figure 5. As shown in Figure 6(a), the connection node of the input terminals of the APD201, quench element 202, and waveform shaping unit 210 is designated as nodeA. Also, as shown in Figure 6(a), the output side of the waveform shaping unit 210 is designated as nodeB.

[0056] Figure 6(b) is a graph showing the time evolution of the potential of node A in Figure 6(a). Figure 6(c) is a graph showing the time evolution of the potential of node B in Figure 6(a). During the period from time t0 to time t1, a voltage of VH-VL is applied to APD201 in Figure 6(a). When a photon is incident on APD201 at time t1, avalanche multiplication occurs in APD201. This causes an avalanche current to flow in the quench element 202, and the potential of node A drops. Subsequently, the amount of potential drop increases further, and the voltage applied to APD201 gradually decreases. Then, at time t2, avalanche multiplication in APD201 stops. As a result, the voltage level of node A no longer drops below a certain value. Subsequently, during the period from time t2 to time t3, a current flows from the node with voltage VH to node A to compensate for the voltage drop, and at time t3, node A settles back to its original potential.

[0057] In the process described above, the potential of node B becomes high during the period when the potential of node A is below a certain threshold. In this way, the waveform of the potential drop at node A caused by the photon incidence is shaped by the waveform shaping unit 210 and output as a pulse to node B.

[0058] Figure 7 shows the pixel configuration according to this embodiment. Figure 7 shows the photoelectric conversion unit 102 and the pixel signal processing unit 103 in Figure 5 in more detail. Hereinafter, the combined element of the photoelectric conversion unit 102 and the pixel signal processing unit 103 may be referred to as pixel 200. In Figure 7, elements having the same function as those shown in Figure 5 are denoted by the same reference numerals as in Figure 5, and the explanation of those elements may be omitted or simplified.

[0059] Pixel 200 includes an APD 201, a quench element 202, a waveform shaping unit 210, a counter circuit 211, a NAND circuit 221, and a logic circuit 222. The quench element 202 has a P-type MOS transistor 202a. The counter circuit 211 includes an output holding circuit 230, an AND circuit 241 (first logic circuit), and an integration circuit 251 (first integration circuit). The output holding circuit 230 is a circuit that holds the received signal based on the output of the APD 201, and includes a selector circuit 231, a NOT circuit 232, and a flip-flop circuit 233.

[0060] The signal P_DECI_CLK is input to pixel 200 from the weight control unit 116. In addition, the signals P_RCH_TRG, P_RCH_TRG2, P_RCH_TRG3, and P_RES are input to pixel 200 from the vertical scanning circuit 110.

[0061] The signal P_DECI_CLK is, for example, a pulse signal with a frequency of 1MHz to 200MHz, and indicates the weighting amount (first weighting amount) set by the weight control unit 116. As described above, this weighting amount is determined by a periodic function in which the mainframe period is one period. This periodic function is, for example, a sine function or a cosine function. The weight control unit 116 is generated by decimating some pulses from the clock signal input to the weight control unit 116. The number of pulses within one mainframe period can be set appropriately according to the number of bits in the counter circuit 211. When the counter circuit 211 performs counting with 11 bits, the number of pulses within one mainframe period is less than 2048.

[0062] The signal P_DECI_CLK is input to the first input terminal of the NAND circuit 221, and the signal P_RCH_TRG is input to the second input terminal of the NAND circuit 221. The signal P_RCH_TRG is a signal that indicates the start of a subframe period. The signal P_RCH_TRG becomes high at the start of the subframe period, and then becomes low. The signal P_RCH_TRG is then maintained at a low level until the end of the subframe. The NAND circuit 221 outputs a signal PCLKB which is the inverted logical AND of the signals P_DECI_CLK and P_RCH_TRG. The output terminal of the NAND circuit 221 is connected to the gate of the MOS transistor 202a. A voltage VH is supplied to the source of the MOS transistor 202a. The drain of the MOS transistor 202a is connected to the cathode of the APD201 and the input terminal of the waveform shaping unit 210.

[0063] The signal PCLKB controls the timing of the recharge operation in APD201. When both signals P_DECI_CLK and P_RCH_TRG are at a high level, PCLKB goes to a low level. At this time, MOS transistor 202a turns on, and the recharge operation is performed in APD201. The recharge operation is performed once per subframe period.

[0064] The output terminal of the waveform shaping unit 210 is connected to the first input terminal of the selector circuit 231. The output terminal of the selector circuit 231 is connected to the input terminal D of the flip-flop circuit 233. The signal P_RCH_TRG2 is input to the reset terminal R of the flip-flop circuit 233. The signal P_RCH_TRG2 controls the reset of the signal held in the flip-flop circuit 233. The signal P_RCH_TRG3 is input to the clock input terminal of the flip-flop circuit 233. The signal P_RCH_TRG3 controls the timing of the signal held in the flip-flop circuit 233. The output terminal Q of the flip-flop circuit 233 is connected to the second input terminal of the selector circuit 231, the input terminal of the NOT circuit 232, and the second input terminal of the AND circuit 241. The output terminal of the NOT circuit 232 is connected to the control terminal of the selector circuit 231.

[0065] The selector circuit 231 selects and outputs the signal input to the first input terminal when the output signal of the flip-flop circuit 233 is at a low level. That is, the output signal of the waveform shaping unit 210 is input to input terminal D of the flip-flop circuit 233. Also, the selector circuit 231 selects and outputs the signal input to the second input terminal when the output signal of the flip-flop circuit 233 is at a high level. That is, the output signal of the flip-flop circuit 233 is fed back and input to input terminal D of the flip-flop circuit 233.

[0066] Logic circuit 222 is a circuit that outputs the logical AND of the inverted value of the input signal at the first input terminal and the input signal at the second input terminal. The signal P_DECI_CLK is input to the first input terminal of logic circuit 222, and the signal P_RCH_TRG is input to the second input terminal of logic circuit 222. Logic circuit 222 outputs the logical AND of the inverted value of signal P_DECI_CLK and signal P_RCH_TRG as the signal TCLK (first reference signal). The output terminal of logic circuit 222 is connected to the first input terminal of AND circuit 241. That is, the signal TCLK is input to the first input terminal of AND circuit 241.

[0067] The AND gate 241 outputs the logical AND of the signal TCLK and the output signal of the flip-flop gate 233 to the integrator gate 251. The integrator gate 251 counts the number of pulses by integrating the pulses of the input signal. The integrator gate 251 stores the count value obtained in this way. The signal P_RES is also input to the integrator gate 251. The signal P_RES goes high at the start of a main frame. This resets the count value held in the integrator gate 251.

[0068] The method for driving the pixel 200 will be explained with reference to Figures 8 to 10. Figure 8 is a timing diagram showing the method for driving the pixel 200 according to this embodiment. Figure 8 schematically shows the configuration of the imaging period, main frame period, and subframe period, as well as the timing of each signal, the photon detection timing, and the transition of the count value.

[0069] The imaging period is the operating period of the photoelectric converter 100, and mainframes are repeatedly captured within this period. The imaging period includes multiple mainframe periods F1, F2, etc. Each mainframe period is one exposure period, and one frame is captured for each mainframe period. The signal P_RES becomes high at the start of each mainframe period, and then becomes low.

[0070] Each mainframe period is divided into multiple subframe periods. In Figure 8, "Mainframe Period" indicates that the initial mainframe period F1 is divided into multiple subframe periods SF11, SF12, etc. Signals P_RCH_TRG and P_RCH_TRG2 become high at the start of each subframe period and then become low. The times when signals P_RES, P_RCH_TRG, and P_RCH_TRG2 become low can be set appropriately within a range that does not affect the operation of signal counting, etc.

[0071] Each subframe period is divided into multiple microframe periods. In Figure 8, the "subframe period" shows that the initial subframe period SF11 is divided into multiple microframe periods MF11, MF12, etc. Although the lengths of the multiple microframe periods MF11, MF12, etc. are shown to be different in Figure 8, it is not necessary for the lengths of the multiple microframe periods MF11, MF12, etc. to be different. The lengths of the multiple microframe periods MF11, MF12, etc. may be the same. The same applies to the microframe periods in other timing diagrams.

[0072] The pulse AP1 shown in "Photon Detection" in Figure 8 indicates the timing of photon detection within the subframe period SF11. In the example in Figure 8, the photon is detected within the microframe period MF11.

[0073] The signal P_RCH_TRG3 becomes high at the start of each microframe period, and then becomes low. The time at which the signal P_RCH_TRG3 becomes low can be set appropriately, as long as it does not affect the operation of the signal count or other functions.

[0074] Figure 8 shows "P_DECI_CLK," which represents multiple pulses of the signal P_DECI_CLK during microframe periods MF11 and MF12. Within microframe period MF11, the signal P_DECI_CLK becomes high at times t11, t12, t13, t14, ... t1x, and then becomes low. Similarly, within microframe period MF12, the signal P_DECI_CLK becomes high at times t21, t22, t23, t24, ... t2x, and then becomes low. The number of pulses, or pulse density, input to a single microframe period is associated with a weighting amount. This weighting amount changes with each passing subframe period.

[0075] The "count value" in Figure 8 shows the time change of the count value (first count value) held in the integration circuit 251 during microframe periods MF11 and MF12. The pulse resulting from photon detection is held in the flip-flop circuit 233 when a high-level signal P_RCH_TRG3 is input to the clock input terminal of the flip-flop circuit 233. The timing when the signal P_RCH_TRG3 becomes high is at the start of the next microframe period MF12 following the microframe period MF11 in which the photon was detected. Therefore, the increase in the count value due to photon detection begins from the microframe period MF12 following the microframe period MF11 in which the photon was detected. In other words, the count value does not change during the microframe period MF11 in which the photon is detected. Then, in the next microframe period MF12, the count value increases by 1 each time the signal P_DECI_CLK becomes high at times t21, t22, t23, t24, ... t2x.

[0076] Figure 8 shows an example where the weighting amount is set as a periodic function containing the sine function sin(t). Since the weighting amount is expressed as the number of pulse signals, the function of the weighting amount is set so that the range of the weighting amount is non-negative. Here, we assume that the function of the weighting amount is (sin(t)+1) and the range of the weighting amount is from 0 to 2. Also, we assume that the bit width of the digital value representing (sin(t)+1) is 4 bits. That is, the number of pulses of the signal P_DECI_CLK within one microframe period is from 0 to 15. In this case, if we assume that the phase of the sine function is 0 in the first subframe period SF11, the weighting amount is (sin(0)+1), which is 1. Since the number of pulses corresponding to this weighting amount is 8, the count at time t2x in microframe period MF12 is 8.

[0077] The count value continues to increase even in microframe periods after microframe period MF12. When the signal P_RCH_TRG2 becomes high at the start of the next subframe period SF12, the flip-flop circuit 233 is reset and the count value stops increasing. In this way, the integrator circuit 251 counts pulses based on the signal P_DECI_CLK from the microframe period following the microframe period in which a photon was detected until the end of the subframe period within a single subframe period.

[0078] When a photon is detected within a subframe period, higher illuminance results in the photon being detected in a microframe period closer to the beginning of the subframe period. In this case, the pulse count based on the signal P_DECI_CLK continues for a longer period, resulting in a larger count value. Conversely, lower illuminance results in the photon being detected in a microframe period closer to the end of the subframe period. In this case, the pulse count based on the signal P_DECI_CLK continues for a shorter period, resulting in a smaller count value. Therefore, count values ​​of a magnitude corresponding to the illuminance can be obtained.

[0079] Figure 9 is a timing diagram showing the driving method of the pixel 200 according to this embodiment. Figure 8 mainly shows the operation during subframe period SF11. In contrast, Figure 9 mainly shows the operation during the subframe period SF12 following subframe period SF11. The explanation of operations common to Figure 8 will be omitted or simplified.

[0080] The "Subframe Period" in Figure 9 indicates that the subframe period SF12 following subframe period SF11 is divided into multiple microframe periods MF21, MF22, etc. The pulse AP2 illustrated in "Photon Detection" in Figure 9 indicates the timing when a photon was detected within subframe period SF12. In the example in Figure 9, a photon is detected within microframe period MF21. Therefore, the count value begins to increase from the next microframe period MF22.

[0081] Figure 9 shows "P_DECI_CLK," which represents multiple pulses of the signal P_DECI_CLK during microframe periods MF21 and MF22. Within microframe period MF21, the signal P_DECI_CLK becomes high at times t31, t32, t33, t34, t35, ... t3y, and then becomes low. Within microframe period MF22, the signal P_DECI_CLK becomes high at times t41, t42, t43, t44, ... t4y, and then becomes low.

[0082] During the microframe period MF21 in which photons are detected, the count value does not change. Then, in the next microframe period MF22, the count value increases by 1 each time at times t41, t42, t43, t44, t45, ... t4y as the signal P_DECI_CLK becomes high.

[0083] The phase of the periodic function of the weighting amount in subframe period SF12 is different from the phase of the periodic function of the weighting amount in subframe period SF11. Therefore, the number of pulses of the signal P_DECI_CLK in microframe periods MF21 and MF22 shown in Figure 9 is different from the number of pulses of the signal P_DECI_CLK in microframe periods MF11 and MF12 shown in Figure 8.

[0084] For example, similar to Figure 8, let's assume the weighting function is (sin(t)+1) and the number of subframes is 50. In this case, the phase of the sine function during subframe period SF12 is 2π / 50. The weighting is (sin(2π / 50)+1), which is approximately 1.115. Since the number of pulses corresponding to this weighting is 9, the count at time t4y during microframe period MF22 is 9.

[0085] Figure 10 is a timing diagram showing the driving method of the pixel 200 according to this embodiment. Figures 8 and 9 mainly show the operation during mainframe period F1. In contrast, Figure 10 mainly shows the operation during mainframe period F2, which follows mainframe period F1. The explanation of operations common to Figure 8 or Figure 9 will be omitted or simplified.

[0086] The "Mainframe Period" in Figure 10 indicates that the mainframe period F2 following mainframe period F1 is divided into multiple subframe periods SF21, SF22, etc. The "Subframe Period" in Figure 10 indicates that the first subframe period SF21 of mainframe period F2 is divided into multiple microframe periods MF31, MF32, MF33, MF34, etc.

[0087] The pulse AP3 shown in "Photon Detection" in Figure 10 indicates the timing of photon detection within the subframe period SF21. In the example in Figure 10, the photon is detected within the microframe period MF32. Therefore, the count value begins to increase from the next microframe period MF33, and continues to increase in the following microframe period MF34.

[0088] Figure 10 shows multiple pulses of the signal P_DECI_CLK in "P_DECI_CLK" during microframe periods MF32, MF33, and MF34. Within microframe period MF32, the signal P_DECI_CLK becomes high at times t51, t52, t53, t54, ... t5x, and then becomes low. Within microframe period MF33, the signal P_DECI_CLK becomes high at times t61, t62, t63, t64, ... t6x, and then becomes low. Within microframe period MF34, the signal P_DECI_CLK becomes high at times t71, t72, t73, t74, ... t7x, and then becomes low.

[0089] During the microframe period MF32 in which photons are detected, the count value does not change. Then, in the next microframe period MF33, the count value increases by 1 each time at times t61, t62, t63, t64, ... t6x as the signal P_DECI_CLK becomes high. Furthermore, in the following microframe period MF33, the count value increases by 1 each time at times t71, t72, t73, t74, ... t7x as the signal P_DECI_CLK becomes high.

[0090] Similar to Figure 8, the function of the weighting amount is (sin(t)+1), and the phase of the sine function in the first subframe period SF21 is assumed to be 0. The weighting amount is (sin(0)+1), which is 1. Since the number of pulses corresponding to this weighting amount is 8, the count at time t6x in microframe period MF33 is 8. Then, the count value at time t7x in the next microframe period MF34 is 16.

[0091] As described above, in this embodiment, a count value is generated corresponding to the microframe in which a photon is detected within the subframe period. Generally, the greater the amount of incident light, the earlier the photon is detected, so the generated count value has a value corresponding to the amount of incident light. In addition, in this embodiment, the received signal held in the output holding circuit 230 is reset each subframe period, and photon detection is performed each subframe period, so saturation is less likely to occur. Therefore, this embodiment can handle various light intensities. Accordingly, this embodiment provides a photoelectric conversion device that can acquire signals under various illuminance conditions.

[0092] Furthermore, in the photoelectric converter of this embodiment, the output signal can be weighted based on a periodic function such as a trigonometric function. Therefore, the photoelectric converter of this embodiment is applicable to acquiring signals for time-correlated imaging, such as calculating optical flow.

[0093] In the explanation of the operation of pixel 200, specific examples of weighting, such as the formula for the weighting function, the bit width of the weighting, and the value of the weighting, may be shown, but these are not particularly limited and can be changed as appropriate. Also, the number of divisions of the subframe period and microframe period can be set as appropriate.

[0094] [Second Embodiment] This embodiment describes a modified version of the pixel 200 circuit of the first embodiment. In this embodiment, elements common to the first embodiment may be omitted or simplified in their description.

[0095] Figure 11 shows the configuration of the pixel 200 according to this embodiment. The difference between Figure 11 and Figure 7 is that the signal P_DECI_CLK is input to the clock input terminal of the flip-flop circuit 233. The other circuit configurations are the same as in Figure 7, so their explanation is omitted.

[0096] Figure 12 is a timing diagram showing the driving method of the pixel 200 according to this embodiment. The mainframe period, subframe period, and microframe period are the same as in Figure 8.

[0097] Figure 12 shows "P_DECI_CLK," which represents multiple pulses of the signal P_DECI_CLK during microframe periods MF11 and MF12. Within microframe period MF11, the signal P_DECI_CLK becomes high at times t81, t82, t83, t84, ... t8x, and then becomes low. Within microframe period MF12, the signal P_DECI_CLK becomes high at times t91, t92, t93, t94, ... t9x, and then becomes low.

[0098] The pulse AP4 shown in "Photon Detection" in Figure 12 indicates the timing of photon detection. In the example in Figure 12, the photon is detected between time t82 and time t83 within the microframe period MF11.

[0099] The "count value" in Figure 12 shows the time change of the count value held in the integration circuit 251 during microframe periods MF11 and MF12. The pulse resulting from photon detection is held in the flip-flop circuit 233 when a high-level signal P_DECI_CLK is input to the clock input terminal of the flip-flop circuit 233. Therefore, after the photon is detected, the increase in the count value due to photon detection begins from time t83, when the first high-level signal P_DECI_CLK is input. That is, during the microframe period MF11 in which the photon is detected, the count value increases by 1 each time the signal P_DECI_CLK becomes high at times t83, t84, ... t8x. As a result, the count at time t8x in the microframe period MF11 is 6. Then, during the next microframe period MF12, the count value increases by 1 each time the signal P_DECI_CLK becomes high at times t91, t92, t93, t94, ... t9x. As a result, the count at time t9x in microframe period MF12 is 14.

[0100] In the first embodiment, the flip-flop circuit 233 holds the pulse resulting from the detection of a photon during the microframe period following the microframe period in which the photon was detected. Therefore, in the first embodiment, the count value starts increasing from the microframe period following the microframe period in which the photon was detected. In contrast, in this embodiment, the flip-flop circuit 233 holds the pulse resulting from the detection of a photon when the next signal P_DECI_CLK pulse is input after the photon has been detected during a certain microframe period. Therefore, in this embodiment, the count value may start increasing within the microframe period in which the photon was detected. As a result, in this embodiment, the same effects as in the first embodiment can be obtained, and the illuminance can be reflected more appropriately in the count value compared to the first embodiment.

[0101] [Third Embodiment] This embodiment describes a modified version of the pixel 200 circuit of the first embodiment. In this embodiment, elements common to the first embodiment may be omitted or simplified in their description.

[0102] Figure 13 shows the configuration of the pixel 200 according to this embodiment. The difference between Figure 13 and Figure 7 is that Figure 13 can generate multiple signals with different weighting amounts. In addition to the elements shown in Figure 7, the pixel 200 further includes logic circuits 223 and 224. The counter circuit 211 further includes AND circuits 242 and 243 and integration circuits 252 and 253. The pixel 200 is also further input to the signals P_DECI_CLK1 and P_DECI_CLK2 from the weight control unit 116.

[0103] Signals P_DECI_CLK1 and P_DECI_CLK2 are pulse signals similar to signal P_DECI_CLK. However, signals P_DECI_CLK, P_DECI_CLK1, and P_DECI_CLK2 may be signals that exhibit different weightings from each other.

[0104] Logic circuits 223 and 224 are both circuits that output a logical AND of the inverted value of the input signal at the first input terminal and the input signal at the second input terminal. The first input terminal of logic circuit 223 is input to signal P_DECI_CLK1 (second reference signal), which indicates a weighting amount different from that of signal P_DECI_CLK (second weighting amount), and the second input terminal of logic circuit 223 is input to signal P_RCH_TRG. Logic circuit 223 outputs the logical AND of the inverted value of signal P_DECI_CLK1 and signal P_RCH_TRG to the first input terminal of AND circuit 242 (second logic circuit). The first input terminal of logic circuit 224 is input to signal P_DECI_CLK and signal P_DECI_CLK2, which indicates a weighting amount different from that of P_DECI_CLK1, and the second input terminal of logic circuit 224 is input to signal P_RCH_TRG. Logic circuit 224 outputs the logical AND of the signal P_DECI_CLK2 and the inverted value of the signal P_RCH_TRG to the first input terminal of AND circuit 243. The output signals of flip-flop circuit 233 are input to the second input terminal of AND circuit 242 and the second input terminal of AND circuit 243.

[0105] AND gate 241 outputs the logical AND of the output signal of logic gate 222 and the output signal of flip-flop gate 233 to the integrator gate 251. AND gate 242 outputs the logical AND of the output signal of logic gate 223 and the output signal of flip-flop gate 233 to the integrator gate 252 (second integrator gate). AND gate 243 outputs the logical AND of the output signal of logic gate 224 and the output signal of flip-flop gate 233 to the integrator gate 253. Each of the integrator gates 251, 252, and 253 counts the number of pulses by integrating the pulses of the input signal. The integrator gates 251, 252, and 253 each hold the first count value, second count value, and third count value obtained in this way. Due to differences in weighting, the first count value, second count value, and third count value may be different from each other. In addition, the signal P_RES is input to the integrator gates 251, 252, and 253. The signal P_RES goes high at the start of a mainframe. This resets the count values ​​held in the integrators 251, 252, and 253.

[0106] As described above, in this embodiment, in addition to obtaining the same effects as in the first embodiment, it is possible to acquire three signals weighted based on three types of signals P_DECI_CLK, P_DECI_CLK1, and P_DECI_CLK2 in parallel. For example, the three types of signals P_DECI_CLK, P_DECI_CLK1, and P_DECI_CLK2 mentioned above may be signals indicating a weighting amount based on a sine function, a weighting amount based on a cosine function, and a weighting amount that does not change with each subframe period. In this case, a correlation image based on sine function weighting, a correlation image based on cosine function weighting, and a normal image can be acquired in parallel, making it possible to acquire signals applicable to time correlation imaging such as optical flow calculation more efficiently.

[0107] [Fourth Embodiment] This embodiment describes an example configuration of a photoelectric converter 100 that achieves signal acquisition under various illumination conditions using a circuit configuration and operating method different from those of the first to third embodiments. In this embodiment, elements common to the first to third embodiments may be omitted or simplified in their explanation. In this embodiment, as in the third embodiment, an example is given in which weighting is performed based on three types of signals P_DECI_CLK, P_DECI_CLK1, and P_DECI_CLK2, but the number of types of pulse signals used for weighting is not limited to these.

[0108] Figure 14 shows the configuration of the pixel 200 according to this embodiment. The difference between Figure 14 and Figure 13 is that Figure 14 has a memory that holds the count value within one subframe period and a multiplier that multiplies the count value. The counter circuit 211 has AND circuits 241, 242, 243, integration circuits 251, 252, 253, 254, memory 261 and multipliers 271, 272. Also, unlike Figure 13, the output holding circuit 230 is not provided in this embodiment.

[0109] The signal TCLK from the logic circuit 222 is input to the first input terminal of the AND circuit 241, and the output signal from the waveform shaping unit 210 is input to the second input terminal of the AND circuit 241. The AND circuit 241 outputs the logical AND of the signal TCLK and the output signal (received light signal) from the waveform shaping unit 210 to the integration circuits 251 and 254.

[0110] The integration circuits 251 and 254 count the number of pulses by integrating the pulses of the input signal. The integration circuits 251 and 254 store the count value obtained in this way. The memory 261 receives the count value output from the integration circuit 254 as input. The signal P_RCH_TRG is input to the integration circuits 251 and 254 and the memory 261. Based on the signal P_RCH_TRG, the memory 261 stores the count value output from the integration circuit 254 at the start of one subframe period. After the count value has been stored in the memory 261, the integration circuit 254 resets the stored count value based on the signal P_RCH_TRG. In other words, the integration circuit 254 resets the count value for each subframe period. The memory 261 then stores the count value (light intensity value) obtained in the previous subframe period for each subframe period and updates the stored count value at the start of the next subframe period. Since this count value is 2 bits or more, the memory 261 has a storage capacity of 2 bits or more. On the other hand, the integration circuit 251 is not reset at the time of the subframe period switch and continues to integrate the count value from the detection of the photon until the end of the mainframe period.

[0111] The output signal of the logic circuit 223 is input to the first input terminal of the AND circuit 242, and the output signal of the waveform shaping unit 210 is input to the second input terminal of the AND circuit 242. The AND circuit 242 outputs the logical AND of the output signal of the logic circuit 223 and the output signal of the waveform shaping unit 210 to the multiplier 271 (conversion unit).

[0112] The output signal of the logic circuit 224 is input to the first input terminal of the AND circuit 243, and the output signal of the waveform shaping unit 210 is input to the second input terminal of the AND circuit 243. The AND circuit 243 outputs the logical AND of the output signal of the logic circuit 224 and the output signal of the waveform shaping unit 210 to the multiplier 272.

[0113] Multiplier 271 multiplies the count value held in memory 261 by the output signal of AND circuit 242. Multiplier 271 outputs a signal (converted signal) indicating the value obtained by this multiplication operation to the integrator circuit 252 (first integrator circuit). Multiplier 272 multiplies the count value held in memory 261 by the output signal of AND circuit 243. Multiplier 272 outputs a signal indicating the value obtained by this multiplication operation to the integrator circuit 253.

[0114] The integrator circuit 252 generates and holds a count value (first count value) by integrating the signal values ​​input from the multiplier 271. The integrator circuit 253 generates and holds a count value by integrating the signal values ​​input from the multiplier 272. Due to differences in weighting, the count values ​​held by integrator circuits 252 and 253 may be different from each other. The signal P_RES is input to integrator circuits 251, 252, and 253. The signal P_RES goes high at the start of a mainframe. This resets the count values ​​held by integrator circuits 251, 252, and 253.

[0115] Figure 15 is a timing diagram showing the driving method of the pixel 200 according to this embodiment. Figure 15 mainly shows the operation during subframe periods SF11 and SF12. The explanation of operations common to any of Figures 8 to 10 and Figure 12 will be omitted or simplified.

[0116] In Figure 15, the "mainframe period" indicates that the mainframe period F1 is divided into multiple subframe periods SF11, SF12, etc. In this embodiment, unlike the first to third embodiments, the subframe period is not divided into multiple microframe periods.

[0117] Pulse AP5, shown in "Photon Detection" in Figure 15, indicates the timing of photon detection within subframe period SF11. Similarly, pulse AP6, also shown in "Photon Detection" in Figure 15, indicates the timing of photon detection within subframe period SF12.

[0118] In Figure 15, "P_DECI_CLK" shows multiple pulses of the signal P_DECI_CLK during subframe periods SF11 and SF12. In Figure 15, "P_DECI_CLK1" shows multiple pulses of the signal P_DECI_CLK1 during subframe periods SF11 and SF12. Within subframe period SF11, signals P_DECI_CLK and P_DECI_CLK1 become high at times t111, t112, t113, t114, ... t11x, and then become low. Within subframe period SF12, signals P_DECI_CLK and P_DECI_CLK1 become high at times t121, t122, t123, t124, t125, ... t12y, and then become low.

[0119] In this embodiment as well, the weighting amounts in the signals P_DECI_CLK and P_DECI_CLK1 can be set using periodic functions such as sine functions, as in the first embodiment. In the example in Figure 15, during subframe period SF11, the number of pulses in the signals P_DECI_CLK and P_DECI_CLK1 corresponding to the weighting amounts is 8. During subframe period SF12, the number of pulses in the signals P_DECI_CLK and P_DECI_CLK1 corresponding to the weighting amounts is 9.

[0120] The "Count Value of Integration Circuit 254" and "Count Value of Integration Circuit 251" in Figure 15 show the time evolution of the count values ​​held in integration circuits 254 and 251, respectively. In integration circuits 254 and 251, the increase in the count value due to photon detection begins from the time when the first high-level signal P_DECI_CLK is input after the photon is detected. That is, in the subframe period SF11 in which photons are detected, the count values ​​of integration circuits 254 and 251 increase by 1 each time the signal P_DECI_CLK becomes high at times t112, t113, ... t11x. As a result, the count value of integration circuits 254 and 251 at time t11x in the subframe period SF11 is 7.

[0121] As described above, the count value of the integration circuit 254 is reset at the start of each subframe period. Therefore, the count value of the integration circuit 254 is reset to 0 at the start of subframe period SF12. Subsequently, during subframe period SF12, the count value of the integration circuit 254 increases by 1 each time at times t123, t124, ... t12y after photon detection, due to the signal P_DECI_CLK becoming high level. As a result, the count of the integration circuit 254 at time t12y in subframe period SF12 is 7.

[0122] On the other hand, in the integration circuit 251, the count value is not reset at the time of subframe period switching. Therefore, the count value of the integration circuit 254 is maintained at 7 at the start of subframe period SF12. Subsequently, in subframe period SF12, the count value of the integration circuit 251 increases by 1 each time at times t123, t124, ... t12y after photon detection due to the signal P_DECI_CLK becoming high level. As a result, the count of the integration circuit 251 at time t12y in subframe period SF12 is 14.

[0123] The "memory value" in Figure 15 shows the time change of the count value held in memory 261. As described above, memory 261 holds the count value output from the integration circuit 254 at the start of one subframe period. Therefore, at the start of subframe period SF12, memory 261 acquires and holds the count value 7 obtained by the integration circuit 254 in subframe period SF11. In this way, memory 261 has the function of holding the count value acquired by the integration circuit 254 in the previous subframe period.

[0124] Figure 15, "Integration Circuit 252 Count Value," shows the time change of the count value held in integration circuit 252. In integration circuit 252, after a photon is detected, the count value due to photon detection begins to increase from the time the first high-level signal P_DECI_CLK1 is input. When a pulse of signal P_DECI_CLK1 is input to multiplier 271, this input value "1" is multiplied by the value held in memory 261 and output to integration circuit 252. That is, in subframe period SF12, when the signal P_DECI_CLK1 becomes high level at time t123 after photon detection, multiplier 271 multiplies the input value "1" by 7 held in memory 261 and outputs the resulting value to integration circuit 252. As a result, the count value of integration circuit 252 increases from 0 to 7. Similarly thereafter, the count value of integration circuit 252 increases by 7 at times t124, ... t12y. As a result, the count of the integrator circuit 252 at time t12y of subframe period SF12 is 49. Note that the change in the count value of the integrator circuit 253 is the same as that of the integrator circuit 252, except that the input signal is P_DECI_CLK2, so the explanation is omitted.

[0125] As described above, in this embodiment, a memory 261 that holds the count value acquired in the immediately preceding subframe period is provided in the pixel 200. The multipliers 271, 272 and the integrating circuits 252, 253 generate a count value by multiplying the count value of a certain subframe period by the count value of the immediately preceding subframe period. Therefore, the generated count value has an amplified value based on the amount of incident light in past subframe periods. Thus, compared to the case where the count value is generated by considering only the amount of incident light in one subframe period, this embodiment can handle various light intensities. Therefore, according to this embodiment, a photoelectric conversion device capable of acquiring signals under various illumination conditions is provided.

[0126] Furthermore, in the photoelectric converter of this embodiment, the output signal can be weighted based on a periodic function such as a trigonometric function. Therefore, the photoelectric converter of this embodiment is applicable to acquiring signals for time-correlated imaging, such as calculating optical flow.

[0127] In the explanation of the operation of pixel 200, specific examples of weighting, such as the formula for the weighting function, the bit width of the weighting, and the weighting value, may be shown, but these are not particularly limited and can be changed as appropriate. Furthermore, the number of divisions in the subframe period can also be set as appropriate.

[0128] The conversion process performed using the count value held in memory 261 is not limited to multiplication. For example, each of the multipliers 271 and 272 shown in Figure 14 may be replaced with a shift arithmetic circuit. In this case, the shift arithmetic circuit performs a bit shift on the input value by an amount corresponding to the count value held in memory 261, thereby performing a process that is essentially equivalent to multiplying the input value by the count value. This can lead to faster multiplication processing. The shift arithmetic circuit may include, for example, a demultiplexer.

[0129] [Fifth Embodiment] The device according to the third embodiment will be described with reference to Figure 16. Figure 16 is a block diagram showing the schematic configuration of the device according to this embodiment.

[0130] Figure 16 is a schematic diagram showing an instrument EQP including a photoelectric converter APR. The photoelectric converter APR has the functions of the photoelectric converter 100 of the first to fourth embodiments. All or part of the photoelectric converter APR is a semiconductor device IC. The photoelectric converter APR in this example can be used as, for example, an image sensor, an AF (Auto Focus) sensor, a photometering sensor, a distance measuring sensor, etc. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including a photoelectric conversion unit are arranged in a matrix. The semiconductor device IC may have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0131] The photoelectric converter APR may have a stacked structure (chip stacking structure) comprising a first semiconductor chip provided with multiple photoelectric conversion units and a second semiconductor chip provided with peripheral circuits. The peripheral circuits on the second semiconductor chip can each be a column circuit corresponding to a pixel row of the first semiconductor chip. Alternatively, the peripheral circuits on the second semiconductor chip can each be a matrix circuit corresponding to a pixel or pixel block of the first semiconductor chip. For connecting the first and second semiconductor chips, through-swivel electrodes (TSVs), direct bonding of conductors such as copper for inter-chip wiring, connection by microbumps between chips, or connection by wire bonding can be employed.

[0132] The photoelectric converter APR may include a semiconductor device IC as well as a package PKG that houses the semiconductor device IC. The package PKG may include a substrate on which the semiconductor device IC is fixed, a lid made of glass or the like that faces the semiconductor device IC, and connecting members such as bonding wires and bumps that connect terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0133] The EQP device may further comprise at least one of the following: an optical device OPT, a control unit CTRL, a processing unit PRCS, a display unit DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric converter APR as a photoelectric converter, and is, for example, a lens, shutter, or mirror. The control unit CTRL controls the photoelectric converter APR and is, for example, a semiconductor device such as an ASIC.

[0134] The processing unit PRCS processes the signals output from the photoelectric converter APR and constitutes either the AFE (analog front end) or DFE (digital front end). The processing unit PRCS is a semiconductor device such as a CPU (central processing unit) or ASIC (application-specific integrated circuit). The display device DSPL is an EL display device, liquid crystal display device, etc., that displays the information (image) obtained from the photoelectric converter APR. The memory device MMRY is a magnetic device, semiconductor device, etc., that stores the information (image) obtained from the photoelectric converter APR. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or hard disk drive.

[0135] Furthermore, the processing unit PRCS may acquire optical flow using the signals output by the photoelectric converter 100 of the first to fourth embodiments. For example, the processing unit PRCS may generate a correlation image weighted based on a sine function, a correlation image weighted based on a cosine function, and a normal image, and acquire optical flow from these three images.

[0136] The mechanical device MCHN has moving parts or propulsion parts such as motors and engines. The equipment EQP displays the signals output from the photoelectric converter APR on the display device DSPL, or transmits them to the outside using a communication device (not shown) provided by the equipment EQP. For this purpose, it is preferable that the equipment EQP further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the photoelectric converter APR. The mechanical device MCHN may be controlled based on the signals output from the photoelectric converter APR.

[0137] The EQP (Equipment Equipped Device) shown in Figure 16 can be electronic devices such as information terminals with imaging capabilities (e.g., smartphones and wearable devices), cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In cameras, the mechanical device MCHN can drive components of the optical device OPT for zooming, focusing, and shutter operation. The EQP can also be transportation equipment (mobile devices) such as vehicles, ships, drones, and airplanes. Furthermore, the EQP can be medical equipment such as endoscopes and CT scanners. Additionally, the EQP can be measuring instruments such as distance sensors, analytical instruments such as electron microscopes, office equipment such as photocopiers, and industrial equipment such as robots.

[0138] The mechanical device MCHN in transport equipment can be used as a mobile device. The device EQP as transport equipment is suitable for transporting the photoelectric converter APR, assisting and / or automating driving (operation) through its imaging function, etc. The processing device PRCS for assisting and / or automating driving (operation) can perform processing to operate the mechanical device MCHN as a mobile device based on information obtained from the photoelectric converter APR.

[0139] According to the first to fourth embodiments, good signal acquisition is possible. Therefore, the photoelectric converter APR according to the first to fourth embodiments can provide high value to its designers, manufacturers, distributors, buyers, and / or users. Thus, by installing the photoelectric converter APR in the EQP, the value of the EQP can also be increased. Therefore, when manufacturing and selling the EQP, deciding to install the photoelectric converter APR of this embodiment in the EQP is advantageous in increasing the value of the EQP. Increasing value here includes at least one of the following: addition of functions, improvement of performance, improvement of characteristics, improvement of reliability, improvement of manufacturing yield, reduction of environmental impact, cost reduction, miniaturization, and weight reduction.

[0140] For example, by installing the APR (Photoelectric Converter) in transportation equipment, superior performance can be obtained when photographing the outside of the transportation equipment or measuring the external environment. Therefore, when manufacturing and selling transportation equipment, deciding to install the APR (Photoelectric Converter) according to this embodiment in the transportation equipment is advantageous in improving the performance of the transportation equipment itself. In particular, the APR (Photoelectric Converter) is suitable for transportation equipment that uses information obtained from the APR to provide driving assistance and / or automatic driving.

[0141] [Fourth Embodiment] Figures 17(a) and 17(b) are block diagrams of the equipment related to the in-vehicle camera in this embodiment. Figures 17(a) and 17(b) show an example of applying the photoelectric converter to a moving object such as a vehicle. Equipment 80 includes an imaging device 800 (an example of a photoelectric converter) and a signal processing device (processing device) that processes signals from the imaging device 800. Equipment 80 includes an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 800, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by equipment 80.

[0142] Here, the device 80 may include an optical system (not shown) that guides light to the imaging device 800. The optical system may include, for example, lenses, shutters, and mirrors. In addition, multiple photoelectric conversion units that are substantially conjugate to the pupil of the optical system may be arranged in pixels of the imaging device 800. For example, the multiple photoelectric conversion units may be arranged corresponding to one microlens. The multiple photoelectric conversion units receive light beams that have passed through different positions in the pupil of the optical system. As a result, the imaging device 800 outputs multiple image data corresponding to the light beams that have passed through different positions in the pupil of the optical system. The disparity calculation unit 802 may then calculate the disparity using the output multiple image data.

[0143] Furthermore, the device 80 includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. Note that the distance information may be acquired using ToF (Time of Flight) technology. The distance information acquisition means may be implemented by specially designed hardware or by a software module. It may also be implemented by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0144] Device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the collision determination result of the collision determination unit 804. Furthermore, device 80 is connected to a warning device 830 that issues a warning to the driver based on the collision determination result of the collision determination unit 804. For example, if the collision determination result of the collision determination unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seatbelt or steering wheel. As described above, device 80 functions as a control means that controls the actions that control the vehicle.

[0145] In this embodiment, the equipment 80 images the area around the vehicle, for example, in front of or behind it. Figure 17(b) shows the equipment when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810, acting as an imaging control means, sends instructions to the equipment 80 or imaging device 800 to perform the imaging operation. This configuration can further improve the accuracy of distance measurement.

[0146] The above example described controlling a vehicle to avoid collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles, or control systems that automatically stay within their lane. Furthermore, the equipment is not limited to vehicles such as automobiles, but can be applied to mobile objects (mobile devices) such as ships, aircraft, satellites, industrial robots, and consumer robots. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition or biometric recognition, such as intelligent transportation systems (ITS) and surveillance systems.

[0147] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or an example in which a part of the configuration of one embodiment is replaced with a part of the configuration of another embodiment, is also an embodiment of the present invention.

[0148] The embodiments described above can be modified as appropriate without departing from the technical concept. Furthermore, the disclosures in this specification include not only what is described herein, but also all matters that can be understood from this specification and the drawings attached thereto. In addition, the disclosures in this specification include the complement of the concepts described herein. That is, if this specification states, for example, "A is greater than B," then even if the statement "A is not greater than B" is omitted, this specification can be said to disclose that "A is not greater than B." This is because the statement "A is greater than B" presupposes that the case where "A is not greater than B" is being considered.

[0149] The disclosures in this specification include the following components: (Composition 1) Avalanche photodiode and An output holding circuit that holds a light-receiving signal based on the output of the avalanche photodiode, A first logic circuit to which the light-receiving signal held in the output holding circuit and a first reference signal indicating a first weighting amount are input, A first integrating circuit that holds a first count value obtained by integrating the outputs of the first logic circuit, It has, The first integration circuit resets the first count value at the beginning of each first period. The aforementioned first period is divided into multiple second periods, The first weighting amount changes with each second period, The output holding circuit resets the received light signal every second period. A photoelectric conversion device characterized by the following features. (Configuration 2) The output holding circuit holds the received signal after the first photon is detected in the avalanche photodiode within the second period. A photoelectric conversion device according to configuration 1, characterized in that it is a photoelectric conversion device. (Composition 3) The aforementioned second period is divided into several third periods. The output holding circuit holds the received signal from the third period following the third period in which the first photon was detected among the plurality of third periods. The photoelectric conversion device according to configuration 2, characterized in that it is a photoelectric conversion device. (Composition 4) The aforementioned second period is divided into several third periods. The output holding circuit holds the photon signal from the third period in which the first photon was detected among the plurality of third periods. The photoelectric conversion device according to configuration 2, characterized in that it is a photoelectric conversion device. (Composition 5) The output holding circuit holds the received signal at a time corresponding to the first reference signal after the first photon is detected in the second period. The photoelectric conversion device according to configuration 2, characterized in that it is a photoelectric conversion device. (Composition 6) A second logic circuit to which the light-receiving signal held in the output holding circuit and a second reference signal indicating a second weighting amount are input, A second integrating circuit that holds a second count value obtained by integrating the outputs of the second logic circuit, A photoelectric conversion device according to any one of configurations 1 to 5, further comprising the above. (Composition 7) The first weighting amount is determined by a periodic function having a different phase for each of the second periods. A photoelectric conversion device according to any one of configurations 1 to 6, characterized by the above. (Composition 8) The aforementioned periodic function includes a sine function or a cosine function. The photoelectric conversion device according to configuration 7, characterized by the features described above. (Composition 9) The length of the period of the aforementioned periodic function is equal to the length of the first period. The photoelectric conversion device according to configuration 8, characterized by the above. (Composition 10) The first logic circuit is an AND gate. A photoelectric conversion device according to any one of configurations 1 to 9, characterized by the above. (Composition 11) The first reference signal includes a plurality of pulses, and the number of these pulses is associated with the first weighting amount. A photoelectric conversion device according to any one of configurations 1 to 10, characterized by the above. (Composition 12) Avalanche photodiode and A memory that stores two or more light intensity values ​​generated by a light-receiving signal based on the output of the avalanche photodiode, A conversion unit receives the light intensity value held in the memory and a first reference signal indicating a first weighting amount, and outputs a converted signal based on calculations using the light intensity value and the first weighting amount. A first integration circuit that holds a first count value obtained by integrating the aforementioned conversion signals, It has, The first period in which the first integration circuit performs the integration of the first count value is divided into a plurality of second periods. The first weighting amount changes with each second period, The light intensity value is generated based on the light received signal input during one of the second periods. A photoelectric conversion device characterized by the following features. (Composition 13) The conversion signal has a value obtained by multiplying the first weighting amount by the light intensity value. The photoelectric conversion device according to configuration 12, characterized in that it is a photoelectric conversion device. (Composition 14) The conversion signal has a value obtained by performing a shift operation on the first weighting amount by a shift amount corresponding to the light intensity value. The photoelectric conversion device according to configuration 12, characterized in that it is a photoelectric conversion device. (Composition 15) The memory updates the light intensity value each time a plurality of second periods begin. A photoelectric conversion device according to any one of configurations 12 to 14, characterized by the above. (Composition 16) A logic circuit to which the aforementioned light-receiving signal and a second reference signal indicating a second weighting amount are input, A second integration circuit that stores a second count value obtained by integrating the outputs of the aforementioned logic circuit, A photoelectric conversion device according to any one of configurations 12 to 15, further comprising the above. (Composition 17) The aforementioned logic circuit is an AND gate. The photoelectric conversion device according to configuration 16, characterized by the above. (Composition 18) The first weighting amount is determined by a periodic function having a different phase for each of the second periods. A photoelectric conversion device according to any one of configurations 12 to 17, characterized by the above. (Composition 19) The aforementioned periodic function includes a sine function or a cosine function. A photoelectric conversion device according to configuration 18, characterized by the above. (Composition 20) The length of the period of the aforementioned periodic function is equal to the length of the first period. A photoelectric conversion device according to configuration 19, characterized by the features described above. (Composition 21) The first reference signal includes a plurality of pulses, and the number of these pulses is associated with the first weighting amount. A photoelectric conversion device according to any one of the configurations 12 to 20, characterized by the above. (Composition 22) The system further comprises a processing unit that acquires optical flow based on the first count value. A photoelectric conversion device according to any one of configurations 1 to 21. (Composition 23) A photoelectric conversion device according to any one of configurations 1 to 21, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the aforementioned photoelectric converter, and A device characterized by comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter. (Composition 24) The processing unit acquires optical flow based on the signal output from the photoelectric converter. The apparatus according to configuration 23, characterized by the features described above. (Composition 25) The processing device acquires distance information from the photoelectric converter to the object. The apparatus according to configuration 23, characterized by the features described above.

[0150] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by a process in which one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0151] It should be noted that the embodiments described above are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various ways without departing from its technical concept or its main features. [Explanation of symbols]

[0152] 201 Avalanche Photodiode (APD) 230 Output holding circuit 241 AND circuit 251 Integration Circuit

Claims

1. Avalanche photodiode and An output holding circuit that holds a light-receiving signal based on the output of the avalanche photodiode, A first logic circuit to which the light-receiving signal held in the output holding circuit and a first reference signal indicating a first weighting amount are input, A first integrating circuit that holds a first count value obtained by integrating the outputs of the first logic circuit, It has, The first integration circuit resets the first count value at the beginning of each first period. The aforementioned first period is divided into multiple second periods, The first weighting amount changes with each second period. The output holding circuit resets the received light signal every second period. A photoelectric conversion device characterized by the following features.

2. The output holding circuit holds the received signal after the first photon is detected in the avalanche photodiode within the second period. The photoelectric conversion device according to feature 1.

3. The aforementioned second period is divided into several third periods. The output holding circuit holds the photon signal from the third period following the third period in which the first photon was detected among the plurality of third periods. The photoelectric conversion device according to feature 2.

4. The aforementioned second period is divided into several third periods. The output holding circuit holds the received signal from the third period in which the first photon was detected among the plurality of third periods. The photoelectric conversion device according to feature 2.

5. The output holding circuit holds the received signal at a time corresponding to the first reference signal after the first photon is detected in the second period. The photoelectric conversion device according to feature 2.

6. A second logic circuit to which the light-receiving signal held in the output holding circuit and a second reference signal indicating a second weighting amount are input, A second integrating circuit that holds a second count value obtained by integrating the outputs of the second logic circuit, The photoelectric conversion device according to claim 1, further comprising the following:

7. The first weighting amount is determined by a periodic function having a different phase for each of the second periods. The photoelectric conversion device according to feature 1.

8. The aforementioned periodic function includes a sine function or a cosine function. The photoelectric conversion device according to feature 7.

9. The length of the period of the periodic function is equal to the length of the first period. The photoelectric conversion device according to feature 8.

10. The first logic circuit is an AND circuit. The photoelectric conversion device according to feature 1.

11. The first reference signal includes a plurality of pulses, and the number of the plurality of pulses is associated with the first weighting amount. The photoelectric conversion device according to feature 1.

12. Avalanche photodiode and A memory that stores two or more light intensity values ​​generated by a light-receiving signal based on the output of the avalanche photodiode, A conversion unit receives the light intensity value held in the memory and a first reference signal indicating a first weighting amount, and outputs a converted signal based on calculations using the light intensity value and the first weighting amount. A first integration circuit that holds a first count value obtained by integrating the aforementioned conversion signals, It has, The first period in which the first integration circuit performs the integration of the first count value is divided into a plurality of second periods. The first weighting amount changes with each second period. The light intensity value is generated based on the light received signal input during one of the second periods. A photoelectric conversion device characterized by the following features.

13. The conversion signal has a value obtained by multiplying the first weighting amount by the light intensity value. The photoelectric conversion device according to feature 12.

14. The conversion signal has a value obtained by performing a shift operation on the first weighting amount by a shift amount corresponding to the light intensity value. The photoelectric conversion device according to feature 12.

15. The memory updates the light intensity value each time a plurality of second periods begin. The photoelectric conversion device according to feature 12.

16. A logic circuit to which the aforementioned light-receiving signal and a second reference signal indicating a second weighting amount are input, A second integration circuit that stores a second count value obtained by integrating the outputs of the aforementioned logic circuit, The photoelectric conversion device according to claim 12, further comprising the above.

17. The logic circuit is an AND circuit. The photoelectric conversion device according to feature 16.

18. The first weighting amount is determined by a periodic function having a different phase for each of the second periods. The photoelectric conversion device according to feature 12.

19. The aforementioned periodic function includes a sine function or a cosine function. The photoelectric conversion device according to feature 18.

20. The length of the period of the periodic function is equal to the length of the first period. The photoelectric conversion device according to feature 19.

21. The first reference signal includes a plurality of pulses, and the number of the plurality of pulses is associated with the first weighting amount. The photoelectric conversion device according to feature 12.

22. The system further comprises a processing unit that acquires optical flow based on the first count value. A photoelectric conversion device according to any one of claims 1 to 21.

23. A photoelectric conversion device according to any one of claims 1 to 21, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the aforementioned photoelectric converter, and A device characterized by comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter.

24. The processing unit acquires optical flow based on the signal output from the photoelectric converter. The apparatus according to claim 23.

25. The processing device acquires distance information from the photoelectric converter to the object. The apparatus according to claim 23.

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