Semiconductor equipment

Abstract

The present invention provides a semiconductor device that includes an RC-IGBT having an IGBT and a diode, enabling improved performance. [Solution] The semiconductor device of the embodiment comprises a transistor region, a diode region, and a termination region. The diode region includes a first group of trenches extending in a first direction and repeatedly arranged in a second direction, and the termination region includes the first group of trenches. The first group of trenches includes a first trench, a second trench, a third trench, and a fourth trench, the first and second trenches being connected in the termination region, and the third and fourth trenches being connected in the termination region. The second and third trenches are adjacent in a second direction, and the first minimum distance in the second direction between the second and third trenches in the termination region is less than the second minimum distance in the second direction between the second and third trenches in the diode region.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] An example of a power semiconductor device is an Insulated Gate Bipolar Transistor (IGBT). In an IGBT, for example, a p-type collector region, an n-type drift region, and a p-type base region are provided on the collector electrode. A gate electrode is provided in a trench that penetrates the p-type base region and reaches the n-type drift region, with a gate insulating film in between. Furthermore, an n-type emitter region, connected to the emitter electrode, is provided in a region adjacent to the trench on the surface of the p-type base region.

[0003] In recent years, reverse-conducting IGBTs (RC-IGBTs), which integrate IGBTs and free-wheeling diodes (Free Wheeling Diodes) on the same semiconductor chip, have been widely developed and commercialized. RC-IGBTs are used, for example, as switching elements in inverter circuits. The free-wheeling diode has the function of allowing current to flow in the opposite direction to the IGBT's on-current. Integrating IGBTs and free-wheeling diodes on the same semiconductor chip offers many advantages, such as simplified assembly processes and dispersion of heat-generating points.

[0004] Because the freewheel diode is formed on the same semiconductor chip as the IGBT, the structure and process of the freewheel diode cannot always be optimized, which may result in a decrease in the freewheel diode's characteristics. Improvement of the freewheel diode characteristics in RC-IGBTs is desirable. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2024-13911 [Overview of the project] [Problems that the invention aims to solve]

[0006] The problem that this invention aims to solve is to provide a semiconductor device that includes an RC-IGBT having an IGBT and a diode, and that enables improved characteristics. [Means for solving the problem]

[0007] The semiconductor device of the embodiment comprises a transistor region, a diode region, and a termination region surrounding the transistor region and the diode region, wherein the diode region comprises a semiconductor layer having a first surface and a second surface facing the first surface, a first semiconductor region of a first conductivity type provided within the semiconductor layer, a second semiconductor region of a first conductivity type provided within the semiconductor layer and between the first semiconductor region and the first surface, having a first conductivity type impurity concentration lower than that of the first semiconductor region, a third semiconductor region of a second conductivity type provided within the semiconductor layer and between the second semiconductor region and the first surface, a first group of trenches provided on the side of the first surface within the semiconductor layer, extending in a first direction parallel to the first surface, arranged in a second direction parallel to the first surface and perpendicular to the first direction, and in contact with the second and third semiconductor regions, a first electrode electrically connected to the third semiconductor region, and a portion in contact with the first semiconductor region The terminal region includes the semiconductor layer, the second semiconductor region, a fourth semiconductor region of a second conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface, electrically connected to the first electrode, and having a depth greater than the depth of the third semiconductor region, the first group of trenches, and the second electrode, wherein the first group of trenches includes a first trench, a second trench, a third trench, and a fourth trench, the first trench and the second trench are physically connected in the terminal region, the third trench and the fourth trench are physically connected in the terminal region, the second trench and the third trench are adjacent in the second direction, and the first minimum distance in the second direction between the second trench and the third trench in the terminal region is less than the second minimum distance in the second direction between the second trench and the third trench in the diode region. [Brief explanation of the drawing]

[0008] [Figure 1] A schematic diagram of the semiconductor device according to the first embodiment. [Figure 2]Schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. [Figure 3] Schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 4] Schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 5] Schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. [Figure 6] Schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 7] Schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 8] Schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. [Figure 9] Schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. [Figure 10] Schematic cross-sectional view of a part of the semiconductor device of the comparative example. [Figure 11] Explanation diagram of the operation and effect of the semiconductor device according to the first embodiment. [Figure 12] Explanation diagram of the operation and effect of the semiconductor device according to the first embodiment. [Figure 13] Explanation diagram of the operation and effect of the semiconductor device according to the first embodiment. [Figure 14] Explanation diagram of the operation and effect of the semiconductor device according to the first embodiment. [Figure 15] Explanation diagram of the operation and effect of the semiconductor device according to the first embodiment. [Figure 16] Schematic cross-sectional view of a part of the semiconductor device of the first modification of the first embodiment. [Figure 17] Explanation diagram of the operation and effect of the semiconductor device of the first modification of the first embodiment. [Figure 18] Schematic cross-sectional view of a part of the semiconductor device of the second modification of the first embodiment. [Figure 19] Explanation diagram of the operation and effect of the semiconductor device of the second modification of the first embodiment. [Figure 20] Schematic top view of a part of the semiconductor device according to the second embodiment. [Figure 21] Schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. [Figure 22] A schematic cross-sectional view of a part of the semiconductor device of the second embodiment. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described will be omitted from the description as appropriate.

[0010] In this specification, n + shape, n shape, n - When the notation "shape" is used, n + shape, n shape, n - This means that the concentration of n-type impurities decreases in the order of their shapes. Also, p + shape, p shape, p - If there is a notation for the shape, p + shape, p shape, p - This means that the concentration of p-type impurities decreases in the order of their shapes.

[0011] In this specification, the n-type impurity concentration refers to the effective n-type impurity concentration after compensation, not the actual n-type impurity concentration. Similarly, the p-type impurity concentration refers to the effective p-type impurity concentration after compensation, not the actual p-type impurity concentration. For example, if the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the n-type impurity concentration is calculated by subtracting the p-type impurity concentration from the actual n-type impurity concentration. The same applies to the p-type impurity concentration.

[0012] In this specification, the distribution and absolute value of impurity concentrations in semiconductor regions can be measured, for example, using secondary ion mass spectrometry (SIMS). Furthermore, the relative magnitudes of impurity concentrations in two semiconductor regions can be determined, for example, using scanning capacitance microscopy (SCM). Additionally, the distribution and absolute value of impurity concentrations can be measured, for example, using spreading resistance analysis (SRA). SCM and SRA provide the relative magnitudes and absolute values ​​of carrier concentrations in the semiconductor regions. By assuming an activation rate for impurities, the relative magnitudes, distribution, and absolute values ​​of impurity concentrations between two semiconductor regions can be determined from the measurement results of SCM and SRA.

[0013] Unless otherwise specified in the specification, the impurity concentration in the semiconductor region shall be represented by the maximum concentration in that semiconductor region.

[0014] (First embodiment) The semiconductor device of the first embodiment includes a transistor region, a diode region, and a termination region surrounding the transistor region and the diode region. The diode region includes a semiconductor layer having a first surface and a second surface facing the first surface, a first semiconductor region of a first conductivity type provided within the semiconductor layer, a second semiconductor region of a first conductivity type provided within the semiconductor layer and between the first semiconductor region and the first surface, having a first conductivity type impurity concentration lower than that of the first semiconductor region, a third semiconductor region of a second conductivity type provided within the semiconductor layer and between the second semiconductor region and the first surface, a first group of trenches provided on the side of the first surface within the semiconductor layer, extending in a first direction parallel to the first surface, arranged in a second direction parallel to the first surface and perpendicular to the first direction, and in contact with the second and third semiconductor regions, a first electrode electrically connected to the third semiconductor region, and a second electrode in contact with the first semiconductor region. The termination region includes a semiconductor layer, a second semiconductor region, a fourth semiconductor region of a second conductivity type provided within the semiconductor layer and between the second semiconductor region and the first surface, electrically connected to the first electrode, and having a depth greater than that of the third semiconductor region, a first group of trenches, and a second electrode. The first group of trenches includes a first trench, a second trench, a third trench, and a fourth trench. The first and second trenches are physically connected in the termination region, the third and fourth trenches are physically connected in the termination region, and the second and third trenches are adjacent in a second direction. The first minimum distance in the second direction between the second and third trenches in the termination region is less than the second minimum distance in the second direction between the second and third trenches in the diode region.

[0015] The semiconductor device of the first embodiment is an RC-IGBT100 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The RC-IGBT100 has a trench-gate type IGBT with a gate electrode located in a trench formed in the semiconductor layer. The following explanation will be given using the case where the first conductivity type is n-type and the second conductivity type is p-type as an example.

[0016] FIG. 1 is a schematic diagram of a semiconductor device according to the first embodiment.

[0017] As shown in FIG. 1, the RC-IGBT 100 has a transistor region 101, a diode region 102, and a termination region 103. The transistor region 101 and the diode region 102 are alternately arranged in a second direction perpendicular to the first direction. The termination region 103 surrounds the transistor region 101 and the diode region 102.

[0018] The transistor region 101 operates as an IGBT. The diode region 102 operates as a freewheeling diode. The freewheeling diode is, for example, a Fast Recovery Diode (FRD).

[0019] When the RC-IGBT 100 is in the off state, the termination region 103 relaxes the strength of the electric field applied to the end portions of the pn junctions of the transistor region 101 and the diode region 102. The termination region 103 has a function of improving the breakdown voltage of the RC-IGBT 100.

[0020] A gate electrode pad 104 is provided in the termination region 103. Specifically, it is provided via an insulating film on the upper portion of the diffusion layer of the p-type guard ring region 34, which will be described in detail later.

[0021] The RC-IGBT 100 of the first embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate insulating film 41, a dummy gate insulating film 42, a trench insulating film 43, a gate electrode 51, a dummy gate electrode 52, a conductive layer 53, an interlayer insulating layer 60, and a gate electrode pad 104.

[0022] In the semiconductor layer 10, there are a first group of trenches 21, a second group of trenches 22, a p + -type collector region 26 (sixth semiconductor region), an n - -type drift region 27 (second semiconductor region), a p-type cell base region 28 (seventh semiconductor region), an n + -type cell emitter region 29 (eighth semiconductor region), a p +Shaped cell contact area 30, n + The cathode region 31 (first semiconductor region) of the p-type, the anode region 32 (third semiconductor region) of the p-type, p + P-shaped diode contact region 33, p-shaped guard ring region 34 (fourth semiconductor region), p + A terminal back surface p region 35 (fifth semiconductor region) is provided.

[0023] The first group of trenches 21 includes trenches A 21a, B 21b, C 21c, D 21d, E 21e, F 21f, G 21g, H 21h, I 21i, and J 21j.

[0024] The second group of trenches 22 includes gate trenches 22x and dummy gate trenches 22y.

[0025] In this specification, "trench" means a groove provided in the semiconductor layer 10. The "trench" is part of the semiconductor layer 10. The "trench" is filled with, for example, a conductor or an insulator.

[0026] The semiconductor layer 10 has a first surface F1 and a second surface F2 facing the first surface F1. The semiconductor layer 10 is, for example, single-crystal silicon. The thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0027] In this specification, a direction parallel to the first surface F1 is referred to as the first direction. A direction parallel to the first surface F1 and perpendicular to the first direction is referred to as the second direction. In this specification, "depth" is defined as the distance in the direction toward the second surface F2 with respect to the first surface F1.

[0028] Figure 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 2 is a schematic cross-sectional view of the transistor region. Figure 2 is a cross-sectional view AA' of Figure 1.

[0029] Figure 3 is a schematic top view of a part of the semiconductor device of the first embodiment. Figure 3 is a top view of the first surface F1 of the transistor region. Figure 2 is a cross-section AA' of Figure 3.

[0030] The transistor region 101 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate insulating film 41, a dummy gate insulating film 42, a gate electrode 51, a dummy gate electrode 52, and an interlayer insulating layer 60.

[0031] Within the semiconductor layer 10 of the transistor region 101, there are a second group of trenches 22, a collector region 26 (sixth semiconductor region), a drift region 27 (second semiconductor region), a cell base region 28 (seventh semiconductor region), a cell emitter region 29 (eighth semiconductor region), and a cell contact region 30.

[0032] The upper electrode 12 is provided on the side of the first surface F1 of the semiconductor layer 10. At least a portion of the upper electrode 12 is in contact with the first surface F1 of the semiconductor layer 10.

[0033] The upper electrode 12 functions as the emitter electrode of the IGBT in the transistor region 101. The upper electrode 12 is made of, for example, metal.

[0034] The upper electrode 12 is in contact with the cell emitter region 29 and the cell contact region 30. The upper electrode 12 is electrically connected to the cell emitter region 29. Hereinafter, the portion of the upper electrode 12 that is in contact with the cell emitter region 29 and the cell contact region 30 will be referred to as the cell contact CC.

[0035] The upper electrode 12 is in contact with the cell contact area 30. The upper electrode 12 is electrically connected to the cell contact area 30. The upper electrode 12 is electrically connected to the cell base area 28 via the cell contact area 30.

[0036] The lower electrode 14 is provided on the side of the second surface F2 of the semiconductor layer 10. At least a portion of the lower electrode 14 is in contact with the second surface F2 of the semiconductor layer 10.

[0037] The lower electrode 14 functions as the collector electrode of the IGBT in the transistor region 101. The lower electrode 14 is made of, for example, metal.

[0038] The lower electrode 14 is in contact with the collector region 26 in the transistor region 101. The lower electrode 14 is electrically connected to the collector region 26 in the transistor region 101.

[0039] The collector area 26 is p + This is a semiconductor region of a certain shape. The collector region 26 is in contact with the second surface F2. The collector region 26 is electrically connected to the lower electrode 14. The collector region 26 is in contact with the lower electrode 14. The collector region 26 is a source of holes when the IGBT is ON.

[0040] The drift region 27 is n - This is a semiconductor region of a certain shape. The drift region 27 is provided between the collector region 26 and the first surface F1.

[0041] The drift region 27 serves as the path for the on-current when the IGBT is on. The drift region 27 also functions to deplete when the IGBT is off, thus maintaining the IGBT's breakdown voltage.

[0042] The cell base region 28 is a p-type semiconductor region. The cell base region 28 is located between the drift region 27 and the first surface F1. The cell base region 28 has the drift region 27 between it and the collector region 26.

[0043] In the cell base region 28, an n-type inversion layer is formed in the region opposite the gate electrode 51 to which the gate voltage Vg is applied when the IGBT is in the ON state. The cell base region 28 functions as the channel region of the transistor.

[0044] The cell emitter region 29 is n +This is a semiconductor region of a certain shape. The cell emitter region 29 is provided between the cell base region 28 and the first surface F1. The cell emitter region 29 is in contact with the gate insulating film 41.

[0045] The n-type impurity concentration in the cell emitter region 29 is higher than the n-type impurity concentration in the drift region 27.

[0046] The cell emitter region 29 is in contact with the upper electrode 12. The cell emitter region 29 is electrically connected to the upper electrode 12. The cell emitter region 29 serves as an electron source when the transistor is in the ON state.

[0047] The cell contact area 30 is p + This is a semiconductor region of a certain shape. The cell contact region 30 is provided between the cell base region 28 and the first surface F1. The cell contact region 30 is in contact with the upper electrode 12. The cell contact region 30 is electrically connected to the upper electrode 12.

[0048] The concentration of p-type impurities in the cell contact region 30 is higher than the concentration of p-type impurities in the cell base region 28.

[0049] The second group of trenches 22 is provided on the side of the first surface F1 of the semiconductor layer 10. The second group of trenches 22 is a groove provided in the semiconductor layer 10. The second group of trenches 22 is a part of the semiconductor layer 10.

[0050] As shown in Figure 3, the second group of trenches 22 extends in a first direction parallel to the first surface F1 on the first surface F1. The second group of trenches 22 has a stripe shape. Ten or more trenches in the second group 22 are repeatedly arranged in a second direction perpendicular to the first direction.

[0051] The second group of trenches 22 are in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The second group of trenches 22 penetrate the cell base region 28 and reach the drift region 27.

[0052] The second group of trenches 22 includes gate trenches 22x and dummy gate trenches 22y. The gate trenches 22x and dummy gate trenches 22y are arranged alternately, for example, one at a time, in a second direction.

[0053] The gate electrode 51 is provided in the gate trench 22x. The gate electrode 51 is, for example, a semiconductor or a metal. The gate electrode 51 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0054] The gate electrode 51 is electrically connected to the gate electrode pad 104.

[0055] The gate insulating film 41 is provided between the gate electrode 51 and the semiconductor layer 10. The gate insulating film 41 is provided between the gate electrode 51 and the drift region 27, between the gate electrode 51 and the cell base region 28, and between the gate electrode 51 and the cell emitter region 29. The gate electrode 51 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The gate insulating film 41 is, for example, silicon oxide.

[0056] The dummy gate electrode 52 is provided in the dummy gate trench 22y. The dummy gate electrode 52 is, for example, a semiconductor or a metal. The dummy gate electrode 52 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0057] The dummy gate electrode 52 is electrically connected, for example, to the upper electrode 12.

[0058] The dummy gate insulating film 42 is provided between the dummy gate electrode 52 and the semiconductor layer 10. The dummy gate insulating film 42 is provided between the dummy gate electrode 52 and the drift region 27, between the dummy gate electrode 52 and the cell base region 28, and between the dummy gate electrode 52 and the cell emitter region 29. The dummy gate insulating film 42 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The dummy gate insulating film 42 is, for example, silicon oxide.

[0059] Furthermore, a dummy gate trench 22y is not required to be provided in the transistor region 101. Also, in the transistor region 101, the ratio of gate trenches 22x to the second group of trenches 22 and the ratio of dummy gate trenches 22y to the second group of trenches 22 do not have to be the same.

[0060] The interlayer insulating layer 60 is provided between the gate electrode 51 and the upper electrode 12, and between the dummy gate electrode 52 and the upper electrode 12. The interlayer insulating layer 60 electrically isolates the gate electrode 51 and the upper electrode 12, and between the dummy gate electrode 52 and the upper electrode 12. The interlayer insulating layer 60 is, for example, silicon oxide.

[0061] Figure 4 is a schematic top view of a part of the semiconductor device of the first embodiment. Figure 4 is a top view of the first surface F1, which includes the boundary between the transistor region and the termination region. Figure 4 is a top view of the region R1 enclosed by the dotted line in Figure 1.

[0062] Figure 4 shows the layout pattern of the second group of trenches 22. Also, Figure 4 shows the layout patterns of the drift region 27, guard ring region 34, cell base region 28, cell emitter region 29, and cell contact region 30.

[0063] The terminal region 103 includes the second group of trenches 22. As shown in Figure 4, in the terminal region 103, the minimum distance in the second direction between any two adjacent trenches in the second group of trenches 22 is approximately the same. In other words, in the terminal region 103, the second group of trenches 22 are arranged at approximately equal intervals in the second direction.

[0064] Furthermore, in the terminal region 103, the trenches 22 of the second group are not physically connected to each other. The trenches 22 of the second group are each physically independent.

[0065] For example, in the gate contact CG shown in Figure 4, the gate electrode 51 in the gate trench 22x is connected to a gate wiring (not shown). The gate wiring is electrically connected to the gate electrode pad 104.

[0066] For example, in the dummy gate contact CDG shown in Figure 4, the dummy gate electrode 52 in the dummy gate trench 22y is connected to an upper electrode 12 (not shown).

[0067] Figure 4 also illustrates the pattern of cell contact CCs provided between two adjacent second-group trenches 22.

[0068] Figure 5 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 2 is a schematic cross-sectional view of the diode region 102. Figure 5 is a cross-section of BB' in Figure 1.

[0069] Figure 6 is a schematic top view of a part of the semiconductor device of the first embodiment. Figure 6 is a top view of the first surface F1 of the diode region. Figure 5 is a cross-section of BB' in Figure 6.

[0070] The diode region 102 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a trench insulating film 43, a conductive layer 53, and an interlayer insulating layer 60.

[0071] Within the semiconductor layer 10 of the diode region 102, there are a first group of trenches 21, a cathode region 31 (first semiconductor region), a drift region 27 (second semiconductor region), an anode region 32 (third semiconductor region), and a diode contact region 33.

[0072] The first group of trenches 21 includes trenches A 21a, B 21b, C 21c, D 21d, E 21e, F 21f, G 21g, H 21h, I 21i, and J 21j.

[0073] The upper electrode 12 functions as the anode electrode of the diode in the diode region 102. The upper electrode 12 is in contact with the diode contact region 33. The upper electrode 12 is electrically connected to the diode contact region 33. The upper electrode 12 is electrically connected to the anode region 32 via the diode contact region 33. The upper electrode 12 is also in contact with the anode region 32, for example. Hereinafter, the portion of the upper electrode 12 that is in contact with the diode contact region 33 and the anode region 32 will be referred to as the diode contact CD.

[0074] The lower electrode 14 functions as the cathode electrode of the diode in the diode region 102. The lower electrode 14 is in contact with the cathode region 31.

[0075] The cathode region 31 is n + This is a semiconductor region of a certain shape. The cathode region 31 is in contact with the second surface F2. The cathode region 31 is an electron source when the diode is in the ON state. The cathode region 31 is in contact with the lower electrode 14.

[0076] The drift region 27 is n - This is a semiconductor region of a certain shape. The drift region 27 is located between the cathode region 31 and the first surface F1. The n-type impurity concentration in the drift region 27 is lower than the n-type impurity concentration in the cathode region 31.

[0077] The drift region 27 is the path of the on-current when the diode is in the ON state.

[0078] The anode region 32 is a p-type semiconductor region. The anode region 32 is located between the drift region 27 and the first surface F1. The anode region 32 has the drift region 27 between it and the cathode region 31.

[0079] The anode region 32 serves as a hole source when the diode is in the ON state.

[0080] The p-type impurity concentration in the anode region 32 is lower than, for example, the p-type impurity concentration in the guard ring region 34. The depth of the anode region 32 is, for example, the same as the depth of the cell base region 28. In some cases, an n-type layer with a higher impurity concentration than the drift region 27 may be formed directly below the cell base region 28. In that case, the depth of the anode region 32 may be greater than that of the cell base region 28.

[0081] The diode contact region 33 is p + This is a semiconductor region of a certain shape. The diode contact region 33 is provided between the anode region 32 and the first surface F1.

[0082] The diode contact region 33 is in contact with the upper electrode 12. The diode contact region 33 is electrically connected to the upper electrode 12.

[0083] The p-type impurity concentration in the diode contact region 33 is higher than that in the anode region 32.

[0084] The first group of trenches 21 is provided on the side of the first surface F1 of the semiconductor layer 10. The first group of trenches 21 is a groove provided in the semiconductor layer 10. The first group of trenches 21 is a part of the semiconductor layer 10.

[0085] As shown in Figure 6, the first group of trenches 21 extends in a first direction parallel to the first surface F1 on the first surface F1. The first group of trenches 21 has a stripe shape. The first group of trenches 21 are repeatedly arranged in a second direction perpendicular to the first direction.

[0086] For example, trenches A 21a, B 21b, C 21c, D 21d, E 21e, F 21f, G 21g, H 21h, I 21i, and J 21j are arranged in this order in the second direction.

[0087] The first group of trenches 21 are in contact with the drift region 27 and the anode region 32. The first group of trenches 21 penetrate the anode region 32 and reach the drift region 27.

[0088] The conductive layer 53 is provided in each of the first group of trenches 21. The conductive layer 53 is, for example, a semiconductor or a metal. The conductive layer 53 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0089] The conductive layer 53 is electrically connected to, for example, the upper electrode 12.

[0090] The trench insulating film 43 is provided between the conductive layer 53 and the semiconductor layer 10. The trench insulating film 43 is provided between the conductive layer 53 and the drift region 27, and between the conductive layer 53 and the anode region 32. The conductive layer 53 is in contact with the drift region 27 and the anode region 32. The conductive layer 53 is, for example, silicon oxide.

[0091] The interlayer insulating layer 60 is provided between the conductive layer 53 and the upper electrode 12. The interlayer insulating layer 60 electrically isolates the conductive layer 53 and the upper electrode 12.

[0092] Figure 7 is a schematic top view of a part of the semiconductor device of the first embodiment. Figure 7 is a top view of the first surface F1, which includes the boundary between the diode region and the termination region. Figure 7 is a top view of the region R2 enclosed by the dotted line in Figure 1.

[0093] Figure 7 shows the layout pattern of the first group of trenches 21. Figure 7 also shows the layout patterns of the drift region 27, guard ring region 34, anode region 32, and diode contact region 33.

[0094] The terminal region 103 includes the first group of trenches 21. The terminal region 103 includes trenches A 21a, B 21b, C 21c, D 21d, E 21e, F 21f, G 21g, H 21h, I 21i, and J 21j.

[0095] In the termination region 103, the first group of trenches 21 includes a first trench, a second trench, a third trench, and a fourth trench. The first and second trenches are physically connected in the termination region 103, and the third and fourth trenches are also physically connected in the termination region 103. The second and third trenches are adjacent in a second direction, and the first minimum distance in the second direction between the second and third trenches in the termination region 103 is smaller than the second minimum distance in the second direction between the second and third trenches in the diode region 102.

[0096] Trench B 21b is an example of the first trench. Trench C 21c is an example of the second trench. Trench D 21d is an example of the third trench. Trench E 21e is an example of the fourth trench.

[0097] Trench B 21b and Trench C 21c are physically connected in the terminal region 103. Trench D 21d and Trench E 21e are physically connected in the terminal region 103. Trench C 21c and Trench D 21d are adjacent in the second direction.

[0098] The first minimum distance in the second direction between the C trench 21c and the D trench 21d in the terminal region 103 (d1 in Figure 7) is smaller than the second minimum distance in the second direction between the C trench 21c and the D trench 21d in the diode region 102 (d2 in Figure 7).

[0099] The first minimum distance d1 is, for example, between 1 / 10 and 1 / 2 of the second minimum distance d2.

[0100] Furthermore, for example, in the terminal region 103, the length in the first direction (L in Figure 7) of the portion where the distance in the second direction between trench C 21c and trench D 21d is less than or equal to the second minimum distance d2 is longer than the second minimum distance d2 and less than or equal to 100 times the second minimum distance d2.

[0101] For example, in the conductive layer contact CCN shown in Figure 7, the conductive layer 53 in the first group of trenches 21 is connected to an upper electrode 12 (not shown).

[0102] Figure 7 also shows the pattern of the diode contact CD provided between two adjacent first-group trenches 21.

[0103] Figure 8 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 8 is a schematic cross-sectional view including the boundary between the diode region 102 and the termination region 103. Figure 8 is a cross-section CC' of Figure 7.

[0104] Figure 9 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 9 is a schematic cross-sectional view including the boundary between the diode region 102 and the termination region 103. Figure 9 is a cross-sectional view of DD' in Figure 7.

[0105] The termination region 103 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate insulating film 41, a dummy gate insulating film 42, a trench insulating film 43, a gate electrode 51, a dummy gate electrode 52, a conductive layer 53, and an interlayer insulating layer 60.

[0106] Within the semiconductor layer 10 of the termination region 103, there are a first group of trenches 21, a second group of trenches 22, a drift region 27, a guard ring region 34 (fourth semiconductor region), and a termination back surface p region 35 (fifth semiconductor region).

[0107] In the termination region 103, a parasitic diode is formed, including a pn junction between the guard ring region 34 and the drift region 27.

[0108] The terminal back surface p region 35 is p + This is a semiconductor region of a certain shape. The terminal back surface p region 35 is in contact with the second surface F2. The terminal back surface p region 35 is in contact with the lower electrode 14.

[0109] The boundary between the terminal back surface p region 35 and the cathode region 31 is, for example, located within the diode region 102. The distance in the first direction between the guard ring region 34 and the cathode region 31 (d3 in Figure 8) is, for example, between 100 μm and 300 μm.

[0110] It should be noted that providing the terminal back surface p region 35 is not mandatory. For example, it is also possible to provide the cathode region 31 below the guard ring region 34 of the terminal region 103.

[0111] The drift region 27 is n - This is a semiconductor region of a certain shape. The drift region 27 is provided between the terminal back surface p region 35 and the first surface F1.

[0112] The drift region 27 becomes the path for the on-current when the parasitic diode is in the ON state.

[0113] The guard ring region 34 is a p-type semiconductor region. The guard ring region 34 is provided between the drift region 27 and the first surface F1. The guard ring region 34 sandwiches the drift region 27 between itself and the terminal back surface p region 35.

[0114] The depth of the guard ring region 34 is greater than the depth of the anode region 32. Furthermore, it is desirable that the depth of the guard ring region 34 be greater than the depth of the first group of trenches 21. Also, it is desirable that the depth of the guard ring region 34 be greater than the depth of the second group of trenches 22.

[0115] The guard ring region 34 surrounds the transistor region 101 and the diode region 102. The guard ring region 34 is provided in a ring shape on the first surface F1. The guard ring region 34 has the function of mitigating the intensity of the electric field applied to the termination of the pn junction of the transistor region 101 and the diode region 102.

[0116] Furthermore, the guard ring region 34 becomes a source of holes when the parasitic diode is ON.

[0117] For example, it is also possible to provide an additional annular p-shaped region as a guard ring outside the guard ring region 34 of the terminal region 103, so as to surround the guard ring region 34.

[0118] The p-type impurity concentration in the guard ring region 34 is, for example, higher than the p-type impurity concentration in the anode region 32. The p-type impurity concentration in the guard ring region 34 is, for example, 5 times or more but 100 times or less than the p-type impurity concentration in the anode region 32.

[0119] The interlayer insulating layer 60 is provided between the semiconductor layer 10 and the upper electrode 12. For example, the interlayer insulating layer 60 is provided between the guard ring region 34 and the upper electrode 12.

[0120] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0121] Figure 10 is a schematic cross-sectional view of a part of a comparative example semiconductor device. Figure 10 corresponds to Figure 7 of the first embodiment.

[0122] The comparative example semiconductor device is an RC-IGBT900, in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The comparative example RC-IGBT900 differs from the RC-IGBT100 of the first embodiment in that, in the termination region, the minimum distance in the second direction between any two adjacent trenches in the second group of trenches is approximately the same, and each of the trenches in the second group is not physically connected to one another.

[0123] As shown in Figure 10, in the terminal region 103, the minimum distance in the second direction between any two adjacent trenches in the first group of trenches 21 is approximately the same. In other words, in the terminal region 103, the first group of trenches 21 are arranged at approximately equal intervals in the second direction.

[0124] Furthermore, in the terminal region 103, the trenches 22 of the second group are not physically connected to each other. The trenches 22 of the second group are independent of each other.

[0125] Figures 11 and 12 are explanatory diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Figures 11 and 12 are diagrams showing the current flow when the diode in the diode region 102 of the comparative example RC-IGBT900 is in a conducting state. Figure 11 is a diagram corresponding to Figure 10. Figure 12 is a cross-section of EE' in Figure 10.

[0126] In Figures 11 and 12, the flow of current is indicated by arrows.

[0127] As shown in Figure 11, when the diode in diode region 102 is in a conductive state, current flows from the anode region 32 to the guard ring region 34. The current flows from the diode contact CD through the first group of trenches 21 to the guard ring region 34.

[0128] As shown in Figure 12, the current that flows into the guard ring region 34 further flows into the drift region 27. In other words, holes are injected into the drift region 27. In other words, when the diode in the diode region 102 is conducting, the parasitic diode in the termination region 103 also becomes conducting, and holes are injected from the guard ring region 34 into the drift region 27. As a result, there is an excess of holes in the drift region 27 near the termination region 103.

[0129] In the drift region 27 near the termination region 103 of the diode region 102, an excess of holes occurs, delaying the discharge of holes to the upper electrode 12. Consequently, the reverse recovery current (Irr) during the reverse recovery of the diode increases, and the reverse recovery loss (Err) of the diode increases.

[0130] For example, when carriers accumulated in the drift region 27 of the termination region in the ON state are discharged to the emitter electrode or anode electrode in the OFF state, current may concentrate in the guard ring region. In this case, the concentration of p-type impurities in the guard ring region is increased to mitigate the current concentration. If this is done, when the diode in the diode region 102 is conducting, the amount of hole injection in the drift region 27 near the termination region 103 adjacent to the diode region 102 will increase further, resulting in an even greater hole excess. Consequently, the reverse recovery loss (Err) of the diode will increase further.

[0131] Figures 13, 14, and 15 are explanatory diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Figures 13, 14, and 15 are diagrams illustrating the current flow when the diode in the diode region 102 of the RC-IGBT 100 of the first embodiment is in a conductive state. Figure 13 corresponds to Figure 7. Figure 14 corresponds to Figure 8. Figure 15 corresponds to Figure 9.

[0132] In Figures 13, 14, and 15, the flow of current is indicated by arrows.

[0133] As is clear from Figures 13 and 14, when the diode is conducting, the current flowing from the anode region 32 to the guard ring region 34 between the two first group of trenches 21 that are physically connected in the termination region 103, for example, trench B 21b and trench C 21c, is interrupted by the first group of trenches 21. By making the depth of the guard ring region 34 approximately the same as the depth of the first group of trenches 21, the diffusion layer is completely divided by the trenches, thus increasing the current interruption effect. However, even if the depth of the guard ring region 34 is greater than the depth of the first group of trenches 21, the impurity concentration of the guard ring region 34 decreases from the surface towards the bottom, so even if the guard ring region 34 is not completely divided by the trenches, the bottom of the guard ring region 34 becomes highly resistive, thus providing a current interruption effect. Therefore, as shown in Figure 14, the number of holes injected from the guard ring region 34 outside the trench 21 of the first group into the drift region 27 is reduced compared to the comparative example RC-IGBT900.

[0134] Furthermore, as is clear from Figures 13 and 15, when the diode is in a conducting state, the current flowing from the anode region 32 to the guard ring region 34 between two adjacent, physically unconnected trenches 21 of the first group, for example, trench C 21c and trench D 21d, is reduced compared to the comparative example RC-IGBT900 because the space between trench C 21c and trench D 21d narrows and the electrical resistance increases. Consequently, the number of holes injected from the guard ring region 34 into the drift region 27 is reduced compared to the comparative example RC-IGBT900.

[0135] When the diode is conducting, the number of holes injected from the guard ring region 34 into the drift region 27 is reduced, which decreases the reverse recovery current (Irr) during the reverse recovery of the diode and reduces the reverse recovery loss (Err) of the diode. Therefore, according to the first embodiment, the reverse recovery loss (Err) of the RC-IGBT100 is reduced.

[0136] In the RC-IGBT100, the first minimum distance d1 is preferably, more preferably, one-third or less, and even more preferably one-fifth or less of the second minimum distance d2. This further increases the electrical resistance between the two trenches 21 of the first group, further reduces the number of holes injected from the guard ring region 34 into the drift region 27, and further reduces the reverse recovery loss (Err) of the RC-IGBT100.

[0137] In the RC-IGBT100, the length in the first direction (L in Figure 7) of the portion where the distance in the second direction between trench C 21c and trench D 21d in the termination region 103 is less than or equal to the second minimum distance d2 is preferably longer than the second minimum distance d2, more preferably twice or more than the second minimum distance d2, even more preferably five times or more, and most preferably ten times or more. This further increases the electrical resistance between the two trenches 21 of the first group, further reduces the number of holes injected from the guard ring region 34 into the drift region 27, and further reduces the reverse recovery loss (Err) of the RC-IGBT100.

[0138] The distance in the first direction between the guard ring region 34 and the cathode region 31 (d3 in Figure 8) is preferably 100 μm or more. A larger distance d3 in the first direction between the guard ring region 34 and the cathode region 31 further reduces the number of holes injected from the guard ring region 34 into the drift region 27, thereby further reducing the reverse recovery loss (Err) of the RC-IGBT 100.

[0139] (First variation) The semiconductor device of the first modification of the first embodiment differs from the semiconductor device of the first embodiment in that the first group of trenches further includes a fifth trench and a sixth trench, the fifth trench is provided between the first trench and the second trench, and the sixth trench is provided between the third trench and the fourth trench.

[0140] The first modified semiconductor device of the first embodiment is the RC-IGBT110.

[0141] Figure 16 is a schematic cross-sectional view of a part of a semiconductor device of a first modification of the first embodiment. Figure 16 corresponds to Figure 7 of the first embodiment.

[0142] Trench B 21b is an example of the first trench. Trench D 21d is an example of the second trench. Trench E 21e is an example of the third trench. Trench G 21g is an example of the fourth trench. Trench C 21c is an example of the fifth trench. Trench F 21f is an example of the sixth trench.

[0143] Trench B 21b and trench D 21d are physically connected in the terminal region 103. Trench E 21e and trench G 21g are physically connected in the terminal region 103. Trench D 21d and trench E 21e are adjacent in the second direction.

[0144] Trench C 21c is located between trench B 21b and trench D 21d. Trench F 21f is located between trench E 21e and trench G 21g.

[0145] The first minimum distance in the second direction between the D trench 21d and the E trench 21e in the termination region 103 (d1 in Figure 16) is smaller than the second minimum distance in the second direction between the D trench 21d and the E trench 21e in the diode region 102 (d2 in Figure 16).

[0146] Furthermore, for example, the length in the first direction (L in Figure 16) of the portion where the distance in the second direction between trench D 21d and trench E 21e in the terminal region 103 is less than or equal to the second minimum distance d2 is longer than the second minimum distance d2 and less than or equal to 100 times the second minimum distance d2.

[0147] Figure 17 is an explanatory diagram of the operation and effect of the semiconductor device of the first modified example of the first embodiment. Figure 17 is a diagram showing the current flow when the diode in the diode region 102 of the RC-IGBT110 of the first modified example of the first embodiment is in a conducting state. Figure 17 is a diagram corresponding to Figure 13 of the first embodiment.

[0148] In Figure 17, the flow of current is indicated by arrows.

[0149] As is clear from Figure 17, when the diode is conducting, the proportion of the current flowing from the anode region 32 to the guard ring region 34 that is interrupted by the physically connected first group of trenches 21 increases. Also, the number of paths passing between two adjacent, physically unconnected first group of trenches 21 decreases. As a result, the current flowing from the anode region 32 to the guard ring region 34 decreases further.

[0150] Therefore, the number of holes injected from the guard ring region 34 into the drift region 27 is further reduced. Thus, the reverse recovery loss (Err) of the RC-IGBT 110 is further reduced.

[0151] According to the first modification of the first embodiment, the reverse recovery loss (Err) of the RC-IGBT is reduced, similar to the first embodiment.

[0152] (Second variation) The semiconductor device of the second modification of the first embodiment differs from the semiconductor device of the first modification of the first embodiment in that the first group of trenches further includes a seventh trench and an eighth trench, the seventh trench is provided between the fifth trench and the second trench, and the eighth trench is provided between the sixth trench and the fourth trench.

[0153] A semiconductor device of the second modification of the first embodiment is the RC-IGBT120.

[0154] Figure 18 is a schematic cross-sectional view of a part of a semiconductor device of a second modification of the first embodiment. Figure 18 corresponds to Figure 7 of the first embodiment.

[0155] Trench B 21b is an example of the first trench. Trench E 21e is an example of the second trench. Trench F 21f is an example of the third trench. Trench I 21i is an example of the fourth trench. Trench C 21c is an example of the fifth trench. Trench G 21g is an example of the sixth trench. Trench D 21d is an example of the seventh trench. Trench H 21h is an example of the eighth trench.

[0156] Trench B 21b and Trench E 21e are physically connected in the terminal region 103. Trench F 21f and Trench I 21i are physically connected in the terminal region 103. Trench E 21e and Trench F 21f are adjacent in the second direction.

[0157] Trench C 21c is provided between trench B 21b and trench E 21e. Trench G 21g is provided between trench F 21f and trench I 21i.

[0158] Trench D 21d is provided between trench C 21c and trench E 21e. Trench H 21h is provided between trench G 21g and trench I 21i.

[0159] The first minimum distance in the second direction between the E trench 21e and the F trench 21f in the termination region 103 (d1 in Figure 18) is smaller than the second minimum distance in the second direction between the E trench 21e and the F trench 21f in the diode region 102 (d2 in Figure 18).

[0160] Furthermore, for example, the length in the first direction (L in Figure 18) of the portion where the distance in the second direction between trench E 21e and trench F 21f in the terminal region 103 is less than or equal to the second minimum distance d2 is longer than the second minimum distance d2 and less than or equal to 100 times the second minimum distance d2.

[0161] Figure 19 is an explanatory diagram of the operation and effect of the semiconductor device of a second modified example of the first embodiment. Figure 19 is a diagram showing the current flow when the diode in the diode region 102 of the RC-IGBT120 of the second modified example of the first embodiment is in a conductive state. Figure 19 corresponds to Figure 13 of the first embodiment.

[0162] In Figure 19, the flow of current is indicated by arrows.

[0163] As is clear from Figure 19, when the diode is conducting, the proportion of the current flowing from the anode region 32 to the guard ring region 34 that is interrupted by the physically connected first group of trenches 21 becomes even larger. Also, the number of paths passing between two adjacent, physically unconnected first group of trenches 21 decreases further. As a result, the current flowing from the anode region 32 to the guard ring region 34 decreases even further.

[0164] Therefore, the number of holes injected from the guard ring region 34 into the drift region 27 is further reduced. Thus, the reverse recovery loss (Err) of the RC-IGBT 120 is further reduced.

[0165] According to the second modification of the first embodiment, the reverse recovery loss (Err) of the RC-IGBT is reduced, similar to the first embodiment.

[0166] As described above, according to the first embodiment and its modifications, a semiconductor device can be realized that includes an RC-IGBT having an IGBT and a diode, and that improves performance by reducing the reverse recovery loss (Err).

[0167] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the fourth semiconductor region includes the first region and a second region located between the first region and the third semiconductor region, the second conductivity type impurity concentration being lower than that of the first region. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0168] The semiconductor device of the second embodiment is an RC-IGBT200 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip.

[0169] Figure 20 is a schematic top view of a part of the semiconductor device of the second embodiment. Figure 20 corresponds to Figure 7 of the first embodiment.

[0170] Figure 21 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment. Figure 21 is a schematic cross-sectional view including the boundary between the diode region and the termination region. Figure 21 is a cross-section of the FF' of Figure 20.

[0171] Figure 22 is a schematic cross-sectional view of a portion of the semiconductor device of the second embodiment. Figure 22 is a schematic cross-sectional view including the boundary between the diode region and the termination region. Figure 22 is the GG' section of Figure 20.

[0172] The guard ring region 34 (the fourth semiconductor region) includes a high-concentration region 34a (the first region) and a low-concentration region 34b (the second region).

[0173] The low-concentration region 34b is located between the high-concentration region 34a and the anode region 32 (third semiconductor region).

[0174] The p-type impurity concentration in the low-concentration region 34b is lower than the p-type impurity concentration in the high-concentration region 34a. For example, the p-type impurity concentration in the low-concentration region 34b is between one-tenth and one-half of the p-type impurity concentration in the high-concentration region 34a.

[0175] The concentration of p-type impurities in the high-concentration region 34a is higher than, for example, the concentration of p-type impurities in the anode region 32. The concentration of p-type impurities in the low-concentration region 34b is higher than, for example, the concentration of p-type impurities in the anode region 32.

[0176] In the RC-IGBT200 of the second embodiment, a low-concentration region 34b is provided between the high-concentration region 34a and the anode region 32 (third semiconductor region). This increases the electrical resistance of the path from the anode region 32 to the guard ring region 34 when the diode is conducting. As a result, the current flowing from the anode region 32 to the guard ring region 34 is further reduced compared to the RC-IGBT100 of the first embodiment.

[0177] Therefore, the number of holes injected from the guard ring region 34 into the drift region 27 is further reduced. Thus, the reverse recovery loss (Err) of the RC-IGBT200 is further reduced.

[0178] The p-type impurity concentration in the low-concentration region 34b is preferably half or less of the p-type impurity concentration in the high-concentration region 34a, and more preferably one-fifth or less. The electrical resistance of the path from the anode region 32 to the guard ring region 34 increases, further reducing the current flowing from the anode region 32 to the guard ring region 34.

[0179] As described above, according to the second embodiment, a semiconductor device can be realized that includes an RC-IGBT having an IGBT and a diode, and that improves characteristics by reducing the reverse recovery loss (Err).

[0180] In the first and second embodiments, the case where the semiconductor layer is single-crystal silicon was described as an example, but the semiconductor layer is not limited to single-crystal silicon. For example, it may be other single-crystal semiconductors such as single-crystal silicon carbide.

[0181] In the first and second embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was described as an example, but it is also possible to have the first conductivity type be p-type and the second conductivity type be n-type.

[0182] The layout pattern in the termination region of the second group of trenches included in the transistor region is not necessarily limited to the pattern shown in Figure 4 in the first embodiment. For example, it is also possible to physically connect a portion of the second group of trenches in the termination region.

[0183] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0184] 10 Semiconductor Layers 12 Upper electrode (first electrode) 14. Lower electrode (second electrode) 21 Trench Group 1 21b Trench B (First Trench) 21c C trench (second trench, fifth trench) 21d D Trench (Third Trench, Second Trench, Seventh Trench) 21e E Trench (4th Trench, 3rd Trench, 2nd Trench) 21f F Trench (6th Trench, 3rd Trench) 21g G Trench (4th Trench, 6th Trench) 21h H Trench (Trench No. 8) 21i I Trench (The Fourth Trench) 22 Trench of Group 2 26. Collector region (sixth semiconductor region) 27. Drift region (second semiconductor region) 28. Cell-based region (7th semiconductor region) 29. Cell emitter region (8th semiconductor region) 31. Cathode region (first semiconductor region) 32. Anode region (third semiconductor region) 34. Guard Ring Region (Fourth Semiconductor Region) 34a High concentration region (first region) 34b Low concentration region (second region) 35 Termination backside p-region (5th semiconductor region) 100 RC-IGBT (Semiconductor Device) 101 Transistor Region 102 Diode region 103 Termination area 110 RC-IGBT (Semiconductor Device) 120 RC-IGBT (Semiconductor Equipment) 200 RC-IGBT (Semiconductor Device) d1 First minimum distance d2 Second minimum distance F1 First Side F2 Second side

Claims

1. The transistor region and Diode region and The system comprises a termination region surrounding the transistor region and the diode region, The diode region is A semiconductor layer having a first surface and a second surface facing the first surface, A first semiconductor region of a first conductivity type provided within the semiconductor layer, A second semiconductor region of a first conductivity type is provided within the semiconductor layer, between the first semiconductor region and the first surface, and having a first conductivity type impurity concentration lower than the first conductivity type impurity concentration of the first semiconductor region. A third semiconductor region of a second conductivity type is provided within the semiconductor layer and between the second semiconductor region and the first surface, A first group of trenches is provided on the side of the first surface within the semiconductor layer, extending in a first direction parallel to the first surface, and arranged in a second direction parallel to the first surface and perpendicular to the first direction, and in contact with the second semiconductor region and the third semiconductor region. A first electrode electrically connected to the third semiconductor region, A second electrode in contact with the first semiconductor region, Includes, The aforementioned termination region is The semiconductor layer and, The second semiconductor region described above, A fourth semiconductor region of a second conductivity type is provided within the semiconductor layer, between the second semiconductor region and the first surface, electrically connected to the first electrode, and having a depth greater than the depth of the third semiconductor region. The trench of the first group, The first electrode 2, Includes, The trenches in the first group include a first trench, a second trench, a third trench, and a fourth trench. The first trench and the second trench are physically connected in the terminal region. The third trench and the fourth trench are physically connected in the terminal region. The second trench and the third trench are adjacent in the second direction, A semiconductor device wherein the first minimum distance in the second direction between the second trench and the third trench in the termination region is smaller than the second minimum distance in the second direction between the second trench and the third trench in the diode region.

2. The semiconductor device according to claim 1, wherein the first minimum distance is less than or equal to half of the second minimum distance.

3. The trenches of the first group further include a fifth trench and a sixth trench, The fifth trench is provided between the first trench and the second trench. The semiconductor device according to claim 1, wherein the sixth trench is provided between the third trench and the fourth trench.

4. The trenches of the first group further include a seventh trench and an eighth trench. The seventh trench is provided between the fifth trench and the second trench. The semiconductor device according to claim 3, wherein the eighth trench is provided between the sixth trench and the fourth trench.

5. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in the fourth semiconductor region is higher than the concentration of the second conductivity type impurity in the third semiconductor region.

6. The semiconductor device according to claim 1, wherein the fourth semiconductor region includes a first region and a second region provided between the first region and the third semiconductor region, the second region having a lower concentration of second conductivity type impurities than the second conductivity type impurities concentration in the first region.

7. The semiconductor device according to claim 1, wherein the semiconductor layer of the terminal region further comprises a fifth semiconductor region of a second conductivity type provided between the second semiconductor region and the second surface and in contact with the second electrode.

8. The semiconductor device according to claim 7, wherein the boundary between the fifth semiconductor region and the first semiconductor region lies within the diode region, and the distance between the fourth semiconductor region and the first semiconductor region in the first direction is 100 μm or more.

9. The semiconductor device according to claim 1, wherein the length in the first direction of the portion where the distance in the second direction between the second trench and the third trench in the terminal region is less than or equal to the second minimum distance is longer than the second minimum distance.

10. The aforementioned transistor region is The semiconductor layer and, The second semiconductor region described above, A sixth semiconductor region of a second conductivity type is provided within the semiconductor layer and between the second semiconductor region and the second surface, A seventh semiconductor region of a second conductivity type is provided within the semiconductor layer and between the second semiconductor region and the first surface, An eighth semiconductor region of a first conductivity type is provided within the semiconductor layer and is located between the seventh semiconductor region and the first surface, A second group of trenches is provided on the side of the first surface within the semiconductor layer, extending in the first direction, and arranged repeatedly in the second direction in 10 or more locations, and is in contact with the second semiconductor region, the seventh semiconductor region, and the eighth semiconductor region. The first electrode in contact with the eighth semiconductor region, The second electrode in contact with the sixth semiconductor region, The terminal region further includes the trenches of the second group, In the terminal region, the minimum distance in the second direction between any two adjacent trenches in the second group of trenches is substantially the same. The semiconductor device according to claim 1, wherein each of the trenches in the second group is not physically connected to one another.

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